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gerrit-public.fairphone.software / toolchain / llvm-project / 7684e055b34935b29e4fb355fde9630c55a88bb2 / . / llvm / lib / Target / X86 / X86SchedSkylakeClient.td
blob: 6826347ad7767abb7ef6eb8474bc52f82b67e28b [file] [log] [blame]
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Skylake Client to support
11// instruction scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15def SkylakeClientModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SKylake can
17 // decode 6 instructions per cycle.
18 let IssueWidth = 6;
19 let MicroOpBufferSize = 224; // Based on the reorder buffer.
20 let LoadLatency = 5;
21 let MispredictPenalty = 14;
22
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
25
26 // This flag is set to allow the scheduler to assign a default model to
27 // unrecognized opcodes.
28 let CompleteModel = 0;
29}
30
31let SchedModel = SkylakeClientModel in {
32
33// Skylake Client can issue micro-ops to 8 different ports in one cycle.
34
35// Ports 0, 1, 5, and 6 handle all computation.
36// Port 4 gets the data half of stores. Store data can be available later than
37// the store address, but since we don't model the latency of stores, we can
38// ignore that.
39// Ports 2 and 3 are identical. They handle loads and the address half of
40// stores. Port 7 can handle address calculations.
41def SKLPort0 : ProcResource<1>;
42def SKLPort1 : ProcResource<1>;
43def SKLPort2 : ProcResource<1>;
44def SKLPort3 : ProcResource<1>;
45def SKLPort4 : ProcResource<1>;
46def SKLPort5 : ProcResource<1>;
47def SKLPort6 : ProcResource<1>;
48def SKLPort7 : ProcResource<1>;
49
50// Many micro-ops are capable of issuing on multiple ports.
51def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>;
52def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>;
53def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
54def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>;
55def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>;
56def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>;
57def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>;
58def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>;
59def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>;
60def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
61def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
62def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
63
64// 60 Entry Unified Scheduler
65def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
66 SKLPort5, SKLPort6, SKLPort7]> {
67 let BufferSize=60;
68}
69
70// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
71// cycles after the memory operand.
72def : ReadAdvance<ReadAfterLd, 5>;
73
74// Many SchedWrites are defined in pairs with and without a folded load.
75// Instructions with folded loads are usually micro-fused, so they only appear
76// as two micro-ops when queued in the reservation station.
77// This multiclass defines the resource usage for variants with and without
78// folded loads.
79multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]80 list<ProcResourceKind> ExePorts,
81 int Lat, list<int> Res = [1], int UOps = 1> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]82 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]83 def : WriteRes<SchedRW, ExePorts> {
84 let Latency = Lat;
85 let ResourceCycles = Res;
86 let NumMicroOps = UOps;
87 }
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]88
89 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
90 // latency.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]91 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
92 let Latency = !add(Lat, 5);
93 let ResourceCycles = !listconcat([1], Res);
94 let NumMicroOps = UOps;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]95 }
96}
97
98// A folded store needs a cycle on port 4 for the store data, but it does not
99// need an extra port 2/3 cycle to recompute the address.
100def : WriteRes<WriteRMW, [SKLPort4]>;
101
102// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]103defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
104defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]105def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
106def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
107def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.
108 let Latency = 25;
109 let ResourceCycles = [1, 10];
110}
111def : WriteRes<WriteIDivLd, [SKLPort23, SKLPort0, SKLDivider]> {
112 let Latency = 29;
113 let ResourceCycles = [1, 1, 10];
114}
115
116def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
117
118// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]119defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]120
121// Loads, stores, and moves, not folded with other operations.
122def : WriteRes<WriteLoad, [SKLPort23]> { let Latency = 5; }
123def : WriteRes<WriteStore, [SKLPort237, SKLPort4]>;
124def : WriteRes<WriteMove, [SKLPort0156]>;
125
126// Idioms that clear a register, like xorps %xmm0, %xmm0.
127// These can often bypass execution ports completely.
128def : WriteRes<WriteZero, []>;
129
130// Branches don't produce values, so they have no latency, but they still
131// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]132defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]133
134// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]135def : WriteRes<WriteFLoad, [SKLPort23]> { let Latency = 6; }
136def : WriteRes<WriteFStore, [SKLPort237, SKLPort4]>;
137def : WriteRes<WriteFMove, [SKLPort015]>;
138
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]139defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3>; // Floating point add/sub/compare.
140defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication.
141defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12>; // 10-14 cycles. // Floating point division.
142defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square root.
143defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate.
144defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate.
145defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add.
146defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles.
147defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends.
148defm : SKLWriteResPair<WriteFVarBlend, [SKLPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]149
150// FMA Scheduling helper class.
151// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
152
153// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]154def : WriteRes<WriteVecLoad, [SKLPort23]> { let Latency = 6; }
155def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>;
156def : WriteRes<WriteVecMove, [SKLPort015]>;
157
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]158defm : SKLWriteResPair<WriteVecALU, [SKLPort15], 1>; // Vector integer ALU op, no logicals.
159defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1>; // Vector integer shifts.
160defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply.
161defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1>; // Vector shuffles.
162defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends.
163defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable blends.
164defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]165
166// Vector bitwise operations.
167// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]168defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1>; // Vector and/or/xor.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]169
170// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]171defm : SKLWriteResPair<WriteCvtF2I, [SKLPort1], 3>; // Float -> Integer.
172defm : SKLWriteResPair<WriteCvtI2F, [SKLPort1], 4>; // Integer -> Float.
173defm : SKLWriteResPair<WriteCvtF2F, [SKLPort1], 3>; // Float -> Float size conversion.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]174
175// Strings instructions.
176// Packed Compare Implicit Length Strings, Return Mask
177// String instructions.
178def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
179 let Latency = 10;
180 let ResourceCycles = [3];
181}
182def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
183 let Latency = 10;
184 let ResourceCycles = [3, 1];
185}
186// Packed Compare Explicit Length Strings, Return Mask
187def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort16, SKLPort5]> {
188 let Latency = 10;
189 let ResourceCycles = [3, 2, 4];
190}
191def : WriteRes<WritePCmpEStrMLd, [SKLPort05, SKLPort16, SKLPort23]> {
192 let Latency = 10;
193 let ResourceCycles = [6, 2, 1];
194}
195 // Packed Compare Implicit Length Strings, Return Index
196def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
197 let Latency = 11;
198 let ResourceCycles = [3];
199}
200def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
201 let Latency = 11;
202 let ResourceCycles = [3, 1];
203}
204// Packed Compare Explicit Length Strings, Return Index
205def : WriteRes<WritePCmpEStrI, [SKLPort05, SKLPort16]> {
206 let Latency = 11;
207 let ResourceCycles = [6, 2];
208}
209def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort16, SKLPort5, SKLPort23]> {
210 let Latency = 11;
211 let ResourceCycles = [3, 2, 2, 1];
212}
213
214// AES instructions.
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]215def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
216 let Latency = 4;
217 let NumMicroOps = 1;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]218 let ResourceCycles = [1];
219}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]220def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
221 let Latency = 10;
222 let NumMicroOps = 2;
223 let ResourceCycles = [1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]224}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]225
226def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
227 let Latency = 8;
228 let NumMicroOps = 2;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]229 let ResourceCycles = [2];
230}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]231def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]232 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]233 let NumMicroOps = 3;
234 let ResourceCycles = [2,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]235}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]236
237def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
238 let Latency = 20;
239 let NumMicroOps = 11;
240 let ResourceCycles = [3,6,2];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]241}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]242def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
243 let Latency = 25;
244 let NumMicroOps = 11;
245 let ResourceCycles = [3,6,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]246}
247
248// Carry-less multiplication instructions.
249def : WriteRes<WriteCLMul, [SKLPort0, SKLPort5]> {
250 let Latency = 7;
251 let ResourceCycles = [2, 1];
252}
253def : WriteRes<WriteCLMulLd, [SKLPort0, SKLPort5, SKLPort23]> {
254 let Latency = 7;
255 let ResourceCycles = [2, 1, 1];
256}
257
258// Catch-all for expensive system instructions.
259def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
260
261// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]262defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3>; // Fp 256-bit width vector shuffles.
263defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3>; // 256-bit width vector shuffles.
264defm : SKLWriteResPair<WriteVarVecShift, [SKLPort0, SKLPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]265
266// Old microcoded instructions that nobody use.
267def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
268
269// Fence instructions.
270def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
271
272// Nop, not very useful expect it provides a model for nops!
273def : WriteRes<WriteNop, []>;
274
275////////////////////////////////////////////////////////////////////////////////
276// Horizontal add/sub instructions.
277////////////////////////////////////////////////////////////////////////////////
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]278
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]279defm : SKLWriteResPair<WriteFHAdd, [SKLPort1], 3>;
280defm : SKLWriteResPair<WritePHAdd, [SKLPort15], 1>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]281
282// Remaining instrs.
283
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]284def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]285 let Latency = 1;
286 let NumMicroOps = 1;
287 let ResourceCycles = [1];
288}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]289def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr",
290 "MMX_PADDSWirr",
291 "MMX_PADDUSBirr",
292 "MMX_PADDUSWirr",
293 "MMX_PAVGBirr",
294 "MMX_PAVGWirr",
295 "MMX_PCMPEQBirr",
296 "MMX_PCMPEQDirr",
297 "MMX_PCMPEQWirr",
298 "MMX_PCMPGTBirr",
299 "MMX_PCMPGTDirr",
300 "MMX_PCMPGTWirr",
301 "MMX_PMAXSWirr",
302 "MMX_PMAXUBirr",
303 "MMX_PMINSWirr",
304 "MMX_PMINUBirr",
305 "MMX_PSLLDri",
306 "MMX_PSLLDrr",
307 "MMX_PSLLQri",
308 "MMX_PSLLQrr",
309 "MMX_PSLLWri",
310 "MMX_PSLLWrr",
311 "MMX_PSRADri",
312 "MMX_PSRADrr",
313 "MMX_PSRAWri",
314 "MMX_PSRAWrr",
315 "MMX_PSRLDri",
316 "MMX_PSRLDrr",
317 "MMX_PSRLQri",
318 "MMX_PSRLQrr",
319 "MMX_PSRLWri",
320 "MMX_PSRLWrr",
321 "MMX_PSUBSBirr",
322 "MMX_PSUBSWirr",
323 "MMX_PSUBUSBirr",
324 "MMX_PSUBUSWirr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]325
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]326def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]327 let Latency = 1;
328 let NumMicroOps = 1;
329 let ResourceCycles = [1];
330}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]331def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
332 "COM_FST0r",
333 "INSERTPSrr",
334 "MMX_MOVD64rr",
335 "MMX_MOVD64to64rr",
336 "MMX_PALIGNRrri",
337 "MMX_PSHUFBrr",
338 "MMX_PSHUFWri",
339 "MMX_PUNPCKHBWirr",
340 "MMX_PUNPCKHDQirr",
341 "MMX_PUNPCKHWDirr",
342 "MMX_PUNPCKLBWirr",
343 "MMX_PUNPCKLDQirr",
344 "MMX_PUNPCKLWDirr",
345 "MOV64toPQIrr",
346 "MOVDDUPrr",
347 "MOVDI2PDIrr",
348 "MOVHLPSrr",
349 "MOVLHPSrr",
350 "MOVSDrr",
351 "MOVSHDUPrr",
352 "MOVSLDUPrr",
353 "MOVUPDrr",
354 "MOVUPSrr",
355 "PACKSSDWrr",
356 "PACKSSWBrr",
357 "PACKUSDWrr",
358 "PACKUSWBrr",
359 "PALIGNRrri",
360 "PBLENDWrri",
361 "PMOVSXBDrr",
362 "PMOVSXBQrr",
363 "PMOVSXBWrr",
364 "PMOVSXDQrr",
365 "PMOVSXWDrr",
366 "PMOVSXWQrr",
367 "PMOVZXBDrr",
368 "PMOVZXBQrr",
369 "PMOVZXBWrr",
370 "PMOVZXDQrr",
371 "PMOVZXWDrr",
372 "PMOVZXWQrr",
373 "PSHUFBrr",
374 "PSHUFDri",
375 "PSHUFHWri",
376 "PSHUFLWri",
377 "PSLLDQri",
378 "PSRLDQri",
379 "PUNPCKHBWrr",
380 "PUNPCKHDQrr",
381 "PUNPCKHQDQrr",
382 "PUNPCKHWDrr",
383 "PUNPCKLBWrr",
384 "PUNPCKLDQrr",
385 "PUNPCKLQDQrr",
386 "PUNPCKLWDrr",
387 "SHUFPDrri",
388 "SHUFPSrri",
389 "UCOM_FPr",
390 "UCOM_Fr",
391 "UNPCKHPDrr",
392 "UNPCKHPSrr",
393 "UNPCKLPDrr",
394 "UNPCKLPSrr",
395 "VBROADCASTSSrr",
396 "VINSERTPSrr",
397 "VMOV64toPQIrr",
398 "VMOVDDUPYrr",
399 "VMOVDDUPrr",
400 "VMOVDI2PDIrr",
401 "VMOVHLPSrr",
402 "VMOVLHPSrr",
403 "VMOVSDrr",
404 "VMOVSHDUPYrr",
405 "VMOVSHDUPrr",
406 "VMOVSLDUPYrr",
407 "VMOVSLDUPrr",
408 "VMOVUPDYrr",
409 "VMOVUPDrr",
410 "VMOVUPSYrr",
411 "VMOVUPSrr",
412 "VPACKSSDWYrr",
413 "VPACKSSDWrr",
414 "VPACKSSWBYrr",
415 "VPACKSSWBrr",
416 "VPACKUSDWYrr",
417 "VPACKUSDWrr",
418 "VPACKUSWBYrr",
419 "VPACKUSWBrr",
420 "VPALIGNRYrri",
421 "VPALIGNRrri",
422 "VPBLENDWYrri",
423 "VPBLENDWrri",
424 "VPBROADCASTDrr",
425 "VPBROADCASTQrr",
426 "VPERMILPDYri",
427 "VPERMILPDYrr",
428 "VPERMILPDri",
429 "VPERMILPDrr",
430 "VPERMILPSYri",
431 "VPERMILPSYrr",
432 "VPERMILPSri",
433 "VPERMILPSrr",
434 "VPMOVSXBDrr",
435 "VPMOVSXBQrr",
436 "VPMOVSXBWrr",
437 "VPMOVSXDQrr",
438 "VPMOVSXWDrr",
439 "VPMOVSXWQrr",
440 "VPMOVZXBDrr",
441 "VPMOVZXBQrr",
442 "VPMOVZXBWrr",
443 "VPMOVZXDQrr",
444 "VPMOVZXWDrr",
445 "VPMOVZXWQrr",
446 "VPSHUFBYrr",
447 "VPSHUFBrr",
448 "VPSHUFDYri",
449 "VPSHUFDri",
450 "VPSHUFHWYri",
451 "VPSHUFHWri",
452 "VPSHUFLWYri",
453 "VPSHUFLWri",
454 "VPSLLDQYri",
455 "VPSLLDQri",
456 "VPSRLDQYri",
457 "VPSRLDQri",
458 "VPUNPCKHBWYrr",
459 "VPUNPCKHBWrr",
460 "VPUNPCKHDQYrr",
461 "VPUNPCKHDQrr",
462 "VPUNPCKHQDQYrr",
463 "VPUNPCKHQDQrr",
464 "VPUNPCKHWDYrr",
465 "VPUNPCKHWDrr",
466 "VPUNPCKLBWYrr",
467 "VPUNPCKLBWrr",
468 "VPUNPCKLDQYrr",
469 "VPUNPCKLDQrr",
470 "VPUNPCKLQDQYrr",
471 "VPUNPCKLQDQrr",
472 "VPUNPCKLWDYrr",
473 "VPUNPCKLWDrr",
474 "VSHUFPDYrri",
475 "VSHUFPDrri",
476 "VSHUFPSYrri",
477 "VSHUFPSrri",
478 "VUNPCKHPDYrr",
479 "VUNPCKHPDrr",
480 "VUNPCKHPSYrr",
481 "VUNPCKHPSrr",
482 "VUNPCKLPDYrr",
483 "VUNPCKLPDrr",
484 "VUNPCKLPSYrr",
485 "VUNPCKLPSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]486
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]487def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]488 let Latency = 1;
489 let NumMicroOps = 1;
490 let ResourceCycles = [1];
491}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]492def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]493
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]494def SKLWriteResGroup5 : SchedWriteRes<[SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]495 let Latency = 1;
496 let NumMicroOps = 1;
497 let ResourceCycles = [1];
498}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]499def: InstRW<[SKLWriteResGroup5], (instregex "PABSBrr",
500 "PABSDrr",
501 "PABSWrr",
502 "PADDSBrr",
503 "PADDSWrr",
504 "PADDUSBrr",
505 "PADDUSWrr",
506 "PAVGBrr",
507 "PAVGWrr",
508 "PCMPEQBrr",
509 "PCMPEQDrr",
510 "PCMPEQQrr",
511 "PCMPEQWrr",
512 "PCMPGTBrr",
513 "PCMPGTDrr",
514 "PCMPGTWrr",
515 "PMAXSBrr",
516 "PMAXSDrr",
517 "PMAXSWrr",
518 "PMAXUBrr",
519 "PMAXUDrr",
520 "PMAXUWrr",
521 "PMINSBrr",
522 "PMINSDrr",
523 "PMINSWrr",
524 "PMINUBrr",
525 "PMINUDrr",
526 "PMINUWrr",
527 "PSIGNBrr",
528 "PSIGNDrr",
529 "PSIGNWrr",
530 "PSLLDri",
531 "PSLLQri",
532 "PSLLWri",
533 "PSRADri",
534 "PSRAWri",
535 "PSRLDri",
536 "PSRLQri",
537 "PSRLWri",
538 "PSUBSBrr",
539 "PSUBSWrr",
540 "PSUBUSBrr",
541 "PSUBUSWrr",
542 "VPABSBYrr",
543 "VPABSBrr",
544 "VPABSDYrr",
545 "VPABSDrr",
546 "VPABSWYrr",
547 "VPABSWrr",
548 "VPADDSBYrr",
549 "VPADDSBrr",
550 "VPADDSWYrr",
551 "VPADDSWrr",
552 "VPADDUSBYrr",
553 "VPADDUSBrr",
554 "VPADDUSWYrr",
555 "VPADDUSWrr",
556 "VPAVGBYrr",
557 "VPAVGBrr",
558 "VPAVGWYrr",
559 "VPAVGWrr",
560 "VPCMPEQBYrr",
561 "VPCMPEQBrr",
562 "VPCMPEQDYrr",
563 "VPCMPEQDrr",
564 "VPCMPEQQYrr",
565 "VPCMPEQQrr",
566 "VPCMPEQWYrr",
567 "VPCMPEQWrr",
568 "VPCMPGTBYrr",
569 "VPCMPGTBrr",
570 "VPCMPGTDYrr",
571 "VPCMPGTDrr",
572 "VPCMPGTWYrr",
573 "VPCMPGTWrr",
574 "VPMAXSBYrr",
575 "VPMAXSBrr",
576 "VPMAXSDYrr",
577 "VPMAXSDrr",
578 "VPMAXSWYrr",
579 "VPMAXSWrr",
580 "VPMAXUBYrr",
581 "VPMAXUBrr",
582 "VPMAXUDYrr",
583 "VPMAXUDrr",
584 "VPMAXUWYrr",
585 "VPMAXUWrr",
586 "VPMINSBYrr",
587 "VPMINSBrr",
588 "VPMINSDYrr",
589 "VPMINSDrr",
590 "VPMINSWYrr",
591 "VPMINSWrr",
592 "VPMINUBYrr",
593 "VPMINUBrr",
594 "VPMINUDYrr",
595 "VPMINUDrr",
596 "VPMINUWYrr",
597 "VPMINUWrr",
598 "VPSIGNBYrr",
599 "VPSIGNBrr",
600 "VPSIGNDYrr",
601 "VPSIGNDrr",
602 "VPSIGNWYrr",
603 "VPSIGNWrr",
604 "VPSLLDYri",
605 "VPSLLDri",
606 "VPSLLQYri",
607 "VPSLLQri",
608 "VPSLLVDYrr",
609 "VPSLLVDrr",
610 "VPSLLVQYrr",
611 "VPSLLVQrr",
612 "VPSLLWYri",
613 "VPSLLWri",
614 "VPSRADYri",
615 "VPSRADri",
616 "VPSRAVDYrr",
617 "VPSRAVDrr",
618 "VPSRAWYri",
619 "VPSRAWri",
620 "VPSRLDYri",
621 "VPSRLDri",
622 "VPSRLQYri",
623 "VPSRLQri",
624 "VPSRLVDYrr",
625 "VPSRLVDrr",
626 "VPSRLVQYrr",
627 "VPSRLVQrr",
628 "VPSRLWYri",
629 "VPSRLWri",
630 "VPSUBSBYrr",
631 "VPSUBSBrr",
632 "VPSUBSWYrr",
633 "VPSUBSWrr",
634 "VPSUBUSBYrr",
635 "VPSUBUSBrr",
636 "VPSUBUSWYrr",
637 "VPSUBUSWrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]638
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]639def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]640 let Latency = 1;
641 let NumMicroOps = 1;
642 let ResourceCycles = [1];
643}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]644def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP",
645 "FNOP",
646 "MMX_MOVQ64rr",
647 "MMX_PABSBrr",
648 "MMX_PABSDrr",
649 "MMX_PABSWrr",
650 "MMX_PADDBirr",
651 "MMX_PADDDirr",
652 "MMX_PADDQirr",
653 "MMX_PADDWirr",
654 "MMX_PANDNirr",
655 "MMX_PANDirr",
656 "MMX_PORirr",
657 "MMX_PSIGNBrr",
658 "MMX_PSIGNDrr",
659 "MMX_PSIGNWrr",
660 "MMX_PSUBBirr",
661 "MMX_PSUBDirr",
662 "MMX_PSUBQirr",
663 "MMX_PSUBWirr",
664 "MMX_PXORirr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]665
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]666def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]667 let Latency = 1;
668 let NumMicroOps = 1;
669 let ResourceCycles = [1];
670}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]671def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
672 "ADC(16|32|64)i",
673 "ADC(8|16|32|64)rr",
674 "ADCX(32|64)rr",
675 "ADOX(32|64)rr",
676 "BT(16|32|64)ri8",
677 "BT(16|32|64)rr",
678 "BTC(16|32|64)ri8",
679 "BTC(16|32|64)rr",
680 "BTR(16|32|64)ri8",
681 "BTR(16|32|64)rr",
682 "BTS(16|32|64)ri8",
683 "BTS(16|32|64)rr",
684 "CDQ",
685 "CLAC",
686 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
687 "CQO",
688 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
689 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
690 "JMP_1",
691 "JMP_4",
692 "RORX(32|64)ri",
693 "SAR(8|16|32|64)r1",
694 "SAR(8|16|32|64)ri",
695 "SARX(32|64)rr",
696 "SBB(16|32|64)ri",
697 "SBB(16|32|64)i",
698 "SBB(8|16|32|64)rr",
699 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
700 "SHL(8|16|32|64)r1",
701 "SHL(8|16|32|64)ri",
702 "SHLX(32|64)rr",
703 "SHR(8|16|32|64)r1",
704 "SHR(8|16|32|64)ri",
705 "SHRX(32|64)rr",
706 "STAC")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]707
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]708def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
709 let Latency = 1;
710 let NumMicroOps = 1;
711 let ResourceCycles = [1];
712}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]713def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
714 "BLSI(32|64)rr",
715 "BLSMSK(32|64)rr",
716 "BLSR(32|64)rr",
717 "BZHI(32|64)rr",
718 "LEA(16|32|64)(_32)?r")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]719
720def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
721 let Latency = 1;
722 let NumMicroOps = 1;
723 let ResourceCycles = [1];
724}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]725def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPDrr",
726 "ANDNPSrr",
727 "ANDPDrr",
728 "ANDPSrr",
729 "BLENDPDrri",
730 "BLENDPSrri",
731 "MOVAPDrr",
732 "MOVAPSrr",
733 "MOVDQArr",
734 "MOVDQUrr",
735 "MOVPQI2QIrr",
736 "MOVSSrr",
737 "ORPDrr",
738 "ORPSrr",
739 "PADDBrr",
740 "PADDDrr",
741 "PADDQrr",
742 "PADDWrr",
743 "PANDNrr",
744 "PANDrr",
745 "PORrr",
746 "PSUBBrr",
747 "PSUBDrr",
748 "PSUBQrr",
749 "PSUBWrr",
750 "PXORrr",
751 "VANDNPDYrr",
752 "VANDNPDrr",
753 "VANDNPSYrr",
754 "VANDNPSrr",
755 "VANDPDYrr",
756 "VANDPDrr",
757 "VANDPSYrr",
758 "VANDPSrr",
759 "VBLENDPDYrri",
760 "VBLENDPDrri",
761 "VBLENDPSYrri",
762 "VBLENDPSrri",
763 "VMOVAPDYrr",
764 "VMOVAPDrr",
765 "VMOVAPSYrr",
766 "VMOVAPSrr",
767 "VMOVDQAYrr",
768 "VMOVDQArr",
769 "VMOVDQUYrr",
770 "VMOVDQUrr",
771 "VMOVPQI2QIrr",
772 "VMOVSSrr",
773 "VMOVZPQILo2PQIrr",
774 "VORPDYrr",
775 "VORPDrr",
776 "VORPSYrr",
777 "VORPSrr",
778 "VPADDBYrr",
779 "VPADDBrr",
780 "VPADDDYrr",
781 "VPADDDrr",
782 "VPADDQYrr",
783 "VPADDQrr",
784 "VPADDWYrr",
785 "VPADDWrr",
786 "VPANDNYrr",
787 "VPANDNrr",
788 "VPANDYrr",
789 "VPANDrr",
790 "VPBLENDDYrri",
791 "VPBLENDDrri",
792 "VPORYrr",
793 "VPORrr",
794 "VPSUBBYrr",
795 "VPSUBBrr",
796 "VPSUBDYrr",
797 "VPSUBDrr",
798 "VPSUBQYrr",
799 "VPSUBQrr",
800 "VPSUBWYrr",
801 "VPSUBWrr",
802 "VPXORYrr",
803 "VPXORrr",
804 "VXORPDYrr",
805 "VXORPDrr",
806 "VXORPSYrr",
807 "VXORPSrr",
808 "XORPDrr",
809 "XORPSrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]810
811def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
812 let Latency = 1;
813 let NumMicroOps = 1;
814 let ResourceCycles = [1];
815}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]816def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]817def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
818 "ADD(8|16|32|64)rr",
819 "ADD(8|16|32|64)i",
820 "AND(8|16|32|64)ri",
821 "AND(8|16|32|64)rr",
822 "AND(8|16|32|64)i",
823 "CBW",
824 "CLC",
825 "CMC",
826 "CMP(8|16|32|64)ri",
827 "CMP(8|16|32|64)rr",
828 "CMP(8|16|32|64)i",
829 "DEC(8|16|32|64)r",
830 "INC(8|16|32|64)r",
831 "LAHF",
832 "MOV(8|16|32|64)rr",
833 "MOV(8|16|32|64)ri",
834 "MOVSX(16|32|64)rr16",
835 "MOVSX(16|32|64)rr32",
836 "MOVSX(16|32|64)rr8",
837 "MOVZX(16|32|64)rr16",
838 "MOVZX(16|32|64)rr8",
839 "NEG(8|16|32|64)r",
840 "NOOP",
841 "NOT(8|16|32|64)r",
842 "OR(8|16|32|64)ri",
843 "OR(8|16|32|64)rr",
844 "OR(8|16|32|64)i",
845 "SAHF",
846 "SGDT64m",
847 "SIDT64m",
848 "SLDT64m",
849 "SMSW16m",
850 "STC",
851 "STRm",
852 "SUB(8|16|32|64)ri",
853 "SUB(8|16|32|64)rr",
854 "SUB(8|16|32|64)i",
855 "SYSCALL",
856 "TEST(8|16|32|64)rr",
857 "TEST(8|16|32|64)i",
858 "TEST(8|16|32|64)ri",
859 "XCHG(16|32|64)rr",
860 "XOR(8|16|32|64)ri",
861 "XOR(8|16|32|64)rr",
862 "XOR(8|16|32|64)i")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]863
864def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]865 let Latency = 1;
866 let NumMicroOps = 2;
867 let ResourceCycles = [1,1];
868}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]869def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
870 "MMX_MOVD64from64rm",
871 "MMX_MOVD64mr",
872 "MMX_MOVNTQmr",
873 "MMX_MOVQ64mr",
874 "MOV(8|16|32|64)mr",
875 "MOV8mi",
876 "MOVAPDmr",
877 "MOVAPSmr",
878 "MOVDQAmr",
879 "MOVDQUmr",
880 "MOVHPDmr",
881 "MOVHPSmr",
882 "MOVLPDmr",
883 "MOVLPSmr",
884 "MOVNTDQmr",
885 "MOVNTI_64mr",
886 "MOVNTImr",
887 "MOVNTPDmr",
888 "MOVNTPSmr",
889 "MOVPDI2DImr",
890 "MOVPQI2QImr",
891 "MOVPQIto64mr",
892 "MOVSDmr",
893 "MOVSSmr",
894 "MOVUPDmr",
895 "MOVUPSmr",
896 "ST_FP32m",
897 "ST_FP64m",
898 "ST_FP80m",
899 "VEXTRACTF128mr",
900 "VEXTRACTI128mr",
901 "VMOVAPDYmr",
902 "VMOVAPDmr",
903 "VMOVAPSYmr",
904 "VMOVAPSmr",
905 "VMOVDQAYmr",
906 "VMOVDQAmr",
907 "VMOVDQUYmr",
908 "VMOVDQUmr",
909 "VMOVHPDmr",
910 "VMOVHPSmr",
911 "VMOVLPDmr",
912 "VMOVLPSmr",
913 "VMOVNTDQYmr",
914 "VMOVNTDQmr",
915 "VMOVNTPDYmr",
916 "VMOVNTPDmr",
917 "VMOVNTPSYmr",
918 "VMOVNTPSmr",
919 "VMOVPDI2DImr",
920 "VMOVPQI2QImr",
921 "VMOVPQIto64mr",
922 "VMOVSDmr",
923 "VMOVSSmr",
924 "VMOVUPDYmr",
925 "VMOVUPDmr",
926 "VMOVUPSYmr",
927 "VMOVUPSmr",
928 "VMPTRSTm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]929
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]930def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]931 let Latency = 2;
932 let NumMicroOps = 1;
933 let ResourceCycles = [1];
934}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]935def: InstRW<[SKLWriteResGroup12], (instregex "COMISDrr",
936 "COMISSrr",
937 "MMX_MOVD64from64rr",
938 "MMX_MOVD64grr",
939 "MMX_PMOVMSKBrr",
940 "MOVMSKPDrr",
941 "MOVMSKPSrr",
942 "MOVPDI2DIrr",
943 "MOVPQIto64rr",
944 "PMOVMSKBrr",
945 "UCOMISDrr",
946 "UCOMISSrr",
947 "VCOMISDrr",
948 "VCOMISSrr",
949 "VMOVMSKPDYrr",
950 "VMOVMSKPDrr",
951 "VMOVMSKPSYrr",
952 "VMOVMSKPSrr",
953 "VMOVPDI2DIrr",
954 "VMOVPQIto64rr",
955 "VPMOVMSKBYrr",
956 "VPMOVMSKBrr",
957 "VTESTPDYrr",
958 "VTESTPDrr",
959 "VTESTPSYrr",
960 "VTESTPSrr",
961 "VUCOMISDrr",
962 "VUCOMISSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]963
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]964def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]965 let Latency = 2;
966 let NumMicroOps = 2;
967 let ResourceCycles = [2];
968}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]969def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr",
970 "MMX_PINSRWrr",
971 "PINSRBrr",
972 "PINSRDrr",
973 "PINSRQrr",
974 "PINSRWrr",
975 "VPINSRBrr",
976 "VPINSRDrr",
977 "VPINSRQrr",
978 "VPINSRWrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]979
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]980def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]981 let Latency = 2;
982 let NumMicroOps = 2;
983 let ResourceCycles = [2];
984}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]985def: InstRW<[SKLWriteResGroup14], (instregex "FDECSTP",
986 "MMX_MOVDQ2Qrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]987
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]988def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]989 let Latency = 2;
990 let NumMicroOps = 2;
991 let ResourceCycles = [2];
992}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]993def: InstRW<[SKLWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr",
994 "ROL(8|16|32|64)r1",
995 "ROL(8|16|32|64)ri",
996 "ROR(8|16|32|64)r1",
997 "ROR(8|16|32|64)ri",
998 "SET(A|BE)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]999
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1000def SKLWriteResGroup16 : SchedWriteRes<[SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1001 let Latency = 2;
1002 let NumMicroOps = 2;
1003 let ResourceCycles = [2];
1004}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1005def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPDrr0",
1006 "BLENDVPSrr0",
1007 "PBLENDVBrr0",
1008 "VBLENDVPDYrr",
1009 "VBLENDVPDrr",
1010 "VBLENDVPSYrr",
1011 "VBLENDVPSrr",
1012 "VPBLENDVBYrr",
1013 "VPBLENDVBrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1014
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1015def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1016 let Latency = 2;
1017 let NumMicroOps = 2;
1018 let ResourceCycles = [2];
1019}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1020def: InstRW<[SKLWriteResGroup17], (instregex "LFENCE",
1021 "WAIT",
1022 "XGETBV")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1023
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1024def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,SKLPort237]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1025 let Latency = 2;
1026 let NumMicroOps = 2;
1027 let ResourceCycles = [1,1];
1028}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1029def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr",
1030 "VMASKMOVPDmr",
1031 "VMASKMOVPSYmr",
1032 "VMASKMOVPSmr",
1033 "VPMASKMOVDYmr",
1034 "VPMASKMOVDmr",
1035 "VPMASKMOVQYmr",
1036 "VPMASKMOVQmr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1037
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1038def SKLWriteResGroup19 : SchedWriteRes<[SKLPort5,SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1039 let Latency = 2;
1040 let NumMicroOps = 2;
1041 let ResourceCycles = [1,1];
1042}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1043def: InstRW<[SKLWriteResGroup19], (instregex "PSLLDrr",
1044 "PSLLQrr",
1045 "PSLLWrr",
1046 "PSRADrr",
1047 "PSRAWrr",
1048 "PSRLDrr",
1049 "PSRLQrr",
1050 "PSRLWrr",
1051 "VPSLLDrr",
1052 "VPSLLQrr",
1053 "VPSLLWrr",
1054 "VPSRADrr",
1055 "VPSRAWrr",
1056 "VPSRLDrr",
1057 "VPSRLQrr",
1058 "VPSRLWrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1059
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1060def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1061 let Latency = 2;
1062 let NumMicroOps = 2;
1063 let ResourceCycles = [1,1];
1064}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1065def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1066
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1067def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1068 let Latency = 2;
1069 let NumMicroOps = 2;
1070 let ResourceCycles = [1,1];
1071}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1072def: InstRW<[SKLWriteResGroup21], (instregex "SFENCE")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1073
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1074def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,SKLPort15]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1075 let Latency = 2;
1076 let NumMicroOps = 2;
1077 let ResourceCycles = [1,1];
1078}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1079def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR(32|64)rr",
1080 "BSWAP(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1081
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1082def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1083 let Latency = 2;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1084 let NumMicroOps = 2;
1085 let ResourceCycles = [1,1];
1086}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1087def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]1088def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1089def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8",
1090 "ADC8ri",
1091 "SBB8i8",
1092 "SBB8ri")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1093
1094def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
1095 let Latency = 2;
1096 let NumMicroOps = 3;
1097 let ResourceCycles = [1,1,1];
1098}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1099def: InstRW<[SKLWriteResGroup24], (instregex "EXTRACTPSmr",
1100 "PEXTRBmr",
1101 "PEXTRDmr",
1102 "PEXTRQmr",
1103 "PEXTRWmr",
1104 "STMXCSR",
1105 "VEXTRACTPSmr",
1106 "VPEXTRBmr",
1107 "VPEXTRDmr",
1108 "VPEXTRQmr",
1109 "VPEXTRWmr",
1110 "VSTMXCSR")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1111
1112def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
1113 let Latency = 2;
1114 let NumMicroOps = 3;
1115 let ResourceCycles = [1,1,1];
1116}
1117def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;
1118
1119def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1120 let Latency = 2;
1121 let NumMicroOps = 3;
1122 let ResourceCycles = [1,1,1];
1123}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1124def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1125
1126def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
1127 let Latency = 2;
1128 let NumMicroOps = 3;
1129 let ResourceCycles = [1,1,1];
1130}
1131def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
1132
1133def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
1134 let Latency = 2;
1135 let NumMicroOps = 3;
1136 let ResourceCycles = [1,1,1];
1137}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1138def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1139def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
1140 "PUSH64i8",
1141 "STOSB",
1142 "STOSL",
1143 "STOSQ",
1144 "STOSW")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1145
1146def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
1147 let Latency = 3;
1148 let NumMicroOps = 1;
1149 let ResourceCycles = [1];
1150}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1151def: InstRW<[SKLWriteResGroup29], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1152def: InstRW<[SKLWriteResGroup29], (instrs IMUL8r, MUL8r)>;
1153def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr",
1154 "BSR(16|32|64)rr",
1155 "LZCNT(16|32|64)rr",
1156 "PDEP(32|64)rr",
1157 "PEXT(32|64)rr",
1158 "POPCNT(16|32|64)rr",
1159 "SHLD(16|32|64)rri8",
1160 "SHRD(16|32|64)rri8",
1161 "TZCNT(16|32|64)rr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1162
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1163def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> {
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1164 let Latency = 3;
1165 let NumMicroOps = 2;
1166 let ResourceCycles = [1,1];
1167}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1168def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1169
1170def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
1171 let Latency = 3;
1172 let NumMicroOps = 1;
1173 let ResourceCycles = [1];
1174}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1175def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0",
1176 "ADD_FST0r",
1177 "ADD_FrST0",
1178 "MMX_PSADBWirr",
1179 "PCMPGTQrr",
1180 "PSADBWrr",
1181 "SUBR_FPrST0",
1182 "SUBR_FST0r",
1183 "SUBR_FrST0",
1184 "SUB_FPrST0",
1185 "SUB_FST0r",
1186 "SUB_FrST0",
1187 "VBROADCASTSDYrr",
1188 "VBROADCASTSSYrr",
1189 "VEXTRACTF128rr",
1190 "VEXTRACTI128rr",
1191 "VINSERTF128rr",
1192 "VINSERTI128rr",
1193 "VPBROADCASTBYrr",
1194 "VPBROADCASTBrr",
1195 "VPBROADCASTDYrr",
1196 "VPBROADCASTQYrr",
1197 "VPBROADCASTWYrr",
1198 "VPBROADCASTWrr",
1199 "VPCMPGTQYrr",
1200 "VPCMPGTQrr",
1201 "VPERM2F128rr",
1202 "VPERM2I128rr",
1203 "VPERMDYrr",
1204 "VPERMPDYri",
1205 "VPERMPSYrr",
1206 "VPERMQYri",
1207 "VPMOVSXBDYrr",
1208 "VPMOVSXBQYrr",
1209 "VPMOVSXBWYrr",
1210 "VPMOVSXDQYrr",
1211 "VPMOVSXWDYrr",
1212 "VPMOVSXWQYrr",
1213 "VPMOVZXBDYrr",
1214 "VPMOVZXBQYrr",
1215 "VPMOVZXBWYrr",
1216 "VPMOVZXDQYrr",
1217 "VPMOVZXWDYrr",
1218 "VPMOVZXWQYrr",
1219 "VPSADBWYrr",
1220 "VPSADBWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1221
1222def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1223 let Latency = 3;
1224 let NumMicroOps = 2;
1225 let ResourceCycles = [1,1];
1226}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1227def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr",
1228 "MMX_PEXTRWrr",
1229 "PEXTRBrr",
1230 "PEXTRDrr",
1231 "PEXTRQrr",
1232 "PEXTRWrr",
1233 "PTESTrr",
1234 "VEXTRACTPSrr",
1235 "VPEXTRBrr",
1236 "VPEXTRDrr",
1237 "VPEXTRQrr",
1238 "VPEXTRWrr",
1239 "VPTESTYrr",
1240 "VPTESTrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1241
1242def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
1243 let Latency = 3;
1244 let NumMicroOps = 2;
1245 let ResourceCycles = [1,1];
1246}
1247def: InstRW<[SKLWriteResGroup32], (instregex "FNSTSW16r")>;
1248
1249def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
1250 let Latency = 3;
1251 let NumMicroOps = 3;
1252 let ResourceCycles = [3];
1253}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1254def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL",
1255 "ROR(8|16|32|64)rCL",
1256 "SAR(8|16|32|64)rCL",
1257 "SHL(8|16|32|64)rCL",
1258 "SHR(8|16|32|64)rCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1259
1260def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
1261 let Latency = 3;
1262 let NumMicroOps = 3;
1263 let ResourceCycles = [3];
1264}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1265def: InstRW<[SKLWriteResGroup34], (instregex "XADD(8|16|32|64)rr",
1266 "XCHG8rr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1267
1268def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1269 let Latency = 3;
1270 let NumMicroOps = 3;
1271 let ResourceCycles = [1,2];
1272}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1273def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr",
1274 "MMX_PHSUBSWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1275
1276def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1277 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1278 let NumMicroOps = 3;
1279 let ResourceCycles = [2,1];
1280}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1281def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr",
1282 "PHSUBSWrr",
1283 "VPHADDSWrr",
1284 "VPHADDSWYrr",
1285 "VPHSUBSWrr",
1286 "VPHSUBSWYrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1287
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1288def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
1289 let Latency = 3;
1290 let NumMicroOps = 3;
1291 let ResourceCycles = [2,1];
1292}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1293def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDDrr",
1294 "MMX_PHADDWrr",
1295 "MMX_PHSUBDrr",
1296 "MMX_PHSUBWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1297
1298def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort015]> {
1299 let Latency = 3;
1300 let NumMicroOps = 3;
1301 let ResourceCycles = [2,1];
1302}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1303def: InstRW<[SKLWriteResGroup38], (instregex "PHADDDrr",
1304 "PHADDWrr",
1305 "PHSUBDrr",
1306 "PHSUBWrr",
1307 "VPHADDDYrr",
1308 "VPHADDDrr",
1309 "VPHADDWYrr",
1310 "VPHADDWrr",
1311 "VPHSUBDYrr",
1312 "VPHSUBDrr",
1313 "VPHSUBWYrr",
1314 "VPHSUBWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1315
1316def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1317 let Latency = 3;
1318 let NumMicroOps = 3;
1319 let ResourceCycles = [2,1];
1320}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1321def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr",
1322 "MMX_PACKSSWBirr",
1323 "MMX_PACKUSWBirr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1324
1325def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1326 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1327 let NumMicroOps = 3;
1328 let ResourceCycles = [1,2];
1329}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1330def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1331
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1332def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
1333 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1334 let NumMicroOps = 3;
1335 let ResourceCycles = [1,2];
1336}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1337def: InstRW<[SKLWriteResGroup41], (instregex "MFENCE")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1338
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1339def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1340 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1341 let NumMicroOps = 3;
1342 let ResourceCycles = [1,2];
1343}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1344def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",
1345 "RCL(8|16|32|64)ri",
1346 "RCR(8|16|32|64)r1",
1347 "RCR(8|16|32|64)ri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1348
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1349def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
1350 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1351 let NumMicroOps = 3;
1352 let ResourceCycles = [1,1,1];
1353}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1354def: InstRW<[SKLWriteResGroup43], (instregex "FNSTSWm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1355
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1356def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1357 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1358 let NumMicroOps = 4;
1359 let ResourceCycles = [1,1,2];
1360}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1361def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1362
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1363def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
1364 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1365 let NumMicroOps = 4;
1366 let ResourceCycles = [1,1,1,1];
1367}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1368def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1369
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1370def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
1371 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1372 let NumMicroOps = 4;
1373 let ResourceCycles = [1,1,1,1];
1374}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1375def: InstRW<[SKLWriteResGroup46], (instregex "CALL64pcrel32")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1376
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1377def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1378 let Latency = 4;
1379 let NumMicroOps = 1;
1380 let ResourceCycles = [1];
1381}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]1382def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1383 "MMX_PMADDWDirr",
1384 "MMX_PMULHRSWrr",
1385 "MMX_PMULHUWirr",
1386 "MMX_PMULHWirr",
1387 "MMX_PMULLWirr",
1388 "MMX_PMULUDQirr",
1389 "MUL_FPrST0",
1390 "MUL_FST0r",
1391 "MUL_FrST0",
1392 "RCPPSr",
1393 "RCPSSr",
1394 "RSQRTPSr",
1395 "RSQRTSSr",
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1396 "VRCPPSYr",
1397 "VRCPPSr",
1398 "VRCPSSr",
1399 "VRSQRTPSYr",
1400 "VRSQRTPSr",
1401 "VRSQRTSSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1402
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1403def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1404 let Latency = 4;
1405 let NumMicroOps = 1;
1406 let ResourceCycles = [1];
1407}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1408def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr",
1409 "ADDPSrr",
1410 "ADDSDrr",
1411 "ADDSSrr",
1412 "ADDSUBPDrr",
1413 "ADDSUBPSrr",
1414 "MULPDrr",
1415 "MULPSrr",
1416 "MULSDrr",
1417 "MULSSrr",
1418 "SUBPDrr",
1419 "SUBPSrr",
1420 "SUBSDrr",
1421 "SUBSSrr",
1422 "VADDPDYrr",
1423 "VADDPDrr",
1424 "VADDPSYrr",
1425 "VADDPSrr",
1426 "VADDSDrr",
1427 "VADDSSrr",
1428 "VADDSUBPDYrr",
1429 "VADDSUBPDrr",
1430 "VADDSUBPSYrr",
1431 "VADDSUBPSrr",
1432 "VMULPDYrr",
1433 "VMULPDrr",
1434 "VMULPSYrr",
1435 "VMULPSrr",
1436 "VMULSDrr",
1437 "VMULSSrr",
1438 "VSUBPDYrr",
1439 "VSUBPDrr",
1440 "VSUBPSYrr",
1441 "VSUBPSrr",
1442 "VSUBSDrr",
1443 "VSUBSSrr")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1444def: InstRW<[SKLWriteResGroup48],
1445 (instregex
1446 "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1447 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1448
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1449def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1450 let Latency = 4;
1451 let NumMicroOps = 1;
1452 let ResourceCycles = [1];
1453}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1454def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
1455 "CMPPSrri",
1456 "CMPSDrr",
1457 "CMPSSrr",
1458 "CVTDQ2PSrr",
1459 "CVTPS2DQrr",
1460 "CVTTPS2DQrr",
1461 "MAX(C?)PDrr",
1462 "MAX(C?)PSrr",
1463 "MAX(C?)SDrr",
1464 "MAX(C?)SSrr",
1465 "MIN(C?)PDrr",
1466 "MIN(C?)PSrr",
1467 "MIN(C?)SDrr",
1468 "MIN(C?)SSrr",
1469 "PHMINPOSUWrr",
1470 "PMADDUBSWrr",
1471 "PMADDWDrr",
1472 "PMULDQrr",
1473 "PMULHRSWrr",
1474 "PMULHUWrr",
1475 "PMULHWrr",
1476 "PMULLWrr",
1477 "PMULUDQrr",
1478 "VCMPPDYrri",
1479 "VCMPPDrri",
1480 "VCMPPSYrri",
1481 "VCMPPSrri",
1482 "VCMPSDrr",
1483 "VCMPSSrr",
1484 "VCVTDQ2PSYrr",
1485 "VCVTDQ2PSrr",
1486 "VCVTPS2DQYrr",
1487 "VCVTPS2DQrr",
1488 "VCVTTPS2DQYrr",
1489 "VCVTTPS2DQrr",
1490 "VMAX(C?)PDYrr",
1491 "VMAX(C?)PDrr",
1492 "VMAX(C?)PSYrr",
1493 "VMAX(C?)PSrr",
1494 "VMAX(C?)SDrr",
1495 "VMAX(C?)SSrr",
1496 "VMIN(C?)PDYrr",
1497 "VMIN(C?)PDrr",
1498 "VMIN(C?)PSYrr",
1499 "VMIN(C?)PSrr",
1500 "VMIN(C?)SDrr",
1501 "VMIN(C?)SSrr",
1502 "VPHMINPOSUWrr",
1503 "VPMADDUBSWYrr",
1504 "VPMADDUBSWrr",
1505 "VPMADDWDYrr",
1506 "VPMADDWDrr",
1507 "VPMULDQYrr",
1508 "VPMULDQrr",
1509 "VPMULHRSWYrr",
1510 "VPMULHRSWrr",
1511 "VPMULHUWYrr",
1512 "VPMULHUWrr",
1513 "VPMULHWYrr",
1514 "VPMULHWrr",
1515 "VPMULLWYrr",
1516 "VPMULLWrr",
1517 "VPMULUDQYrr",
1518 "VPMULUDQrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1519
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1520def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1521 let Latency = 4;
1522 let NumMicroOps = 2;
1523 let ResourceCycles = [2];
1524}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1525def: InstRW<[SKLWriteResGroup50], (instregex "MPSADBWrri",
1526 "VMPSADBWYrri",
1527 "VMPSADBWrri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1528
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1529def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1530 let Latency = 4;
1531 let NumMicroOps = 2;
1532 let ResourceCycles = [1,1];
1533}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1534def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r,
1535 MULX64rr)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1536
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1537def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1538 let Latency = 4;
1539 let NumMicroOps = 4;
1540}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1541def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1542
1543def SKLWriteResGroup52 : SchedWriteRes<[SKLPort5,SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1544 let Latency = 4;
1545 let NumMicroOps = 2;
1546 let ResourceCycles = [1,1];
1547}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1548def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLDYrr",
1549 "VPSLLQYrr",
1550 "VPSLLWYrr",
1551 "VPSRADYrr",
1552 "VPSRAWYrr",
1553 "VPSRLDYrr",
1554 "VPSRLQYrr",
1555 "VPSRLWYrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1556
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1557def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1558 let Latency = 4;
1559 let NumMicroOps = 3;
1560 let ResourceCycles = [1,1,1];
1561}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1562def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP16m",
1563 "ISTT_FP32m",
1564 "ISTT_FP64m",
1565 "IST_F16m",
1566 "IST_F32m",
1567 "IST_FP16m",
1568 "IST_FP32m",
1569 "IST_FP64m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1570
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1571def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1572 let Latency = 4;
1573 let NumMicroOps = 4;
1574 let ResourceCycles = [4];
1575}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1576def: InstRW<[SKLWriteResGroup54], (instregex "FNCLEX")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1577
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1578def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1579 let Latency = 4;
1580 let NumMicroOps = 4;
1581 let ResourceCycles = [1,3];
1582}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1583def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1584
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1585def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1586 let Latency = 4;
1587 let NumMicroOps = 4;
1588 let ResourceCycles = [1,3];
1589}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1590def: InstRW<[SKLWriteResGroup56], (instregex "VZEROUPPER")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1591
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1592def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1593 let Latency = 4;
1594 let NumMicroOps = 4;
1595 let ResourceCycles = [1,1,2];
1596}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1597def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1598
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1599def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
1600 let Latency = 5;
1601 let NumMicroOps = 1;
1602 let ResourceCycles = [1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1603}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1604def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm",
1605 "MMX_MOVD64to64rm",
1606 "MMX_MOVQ64rm",
1607 "MOV(8|16|32|64)rm",
1608 "MOV64toPQIrm",
1609 "MOVDDUPrm",
1610 "MOVDI2PDIrm",
1611 "MOVQI2PQIrm",
1612 "MOVSDrm",
1613 "MOVSSrm",
1614 "MOVSX(16|32|64)rm16",
1615 "MOVSX(16|32|64)rm32",
1616 "MOVSX(16|32|64)rm8",
1617 "MOVZX(16|32|64)rm16",
1618 "MOVZX(16|32|64)rm8",
1619 "PREFETCHNTA",
1620 "PREFETCHT0",
1621 "PREFETCHT1",
1622 "PREFETCHT2",
1623 "VMOV64toPQIrm",
1624 "VMOVDDUPrm",
1625 "VMOVDI2PDIrm",
1626 "VMOVQI2PQIrm",
1627 "VMOVSDrm",
1628 "VMOVSSrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1629
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1630def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1631 let Latency = 5;
1632 let NumMicroOps = 2;
1633 let ResourceCycles = [1,1];
1634}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1635def: InstRW<[SKLWriteResGroup59], (instregex "CVTDQ2PDrr",
1636 "MMX_CVTPI2PDirr",
1637 "VCVTDQ2PDrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1638
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1639def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1640 let Latency = 5;
1641 let NumMicroOps = 2;
1642 let ResourceCycles = [1,1];
1643}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1644def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2DQrr",
1645 "CVTPD2PSrr",
1646 "CVTPS2PDrr",
1647 "CVTSD2SSrr",
1648 "CVTSI642SDrr",
1649 "CVTSI2SDrr",
1650 "CVTSI2SSrr",
1651 "CVTSS2SDrr",
1652 "CVTTPD2DQrr",
1653 "MMX_CVTPD2PIirr",
1654 "MMX_CVTPS2PIirr",
1655 "MMX_CVTTPD2PIirr",
1656 "MMX_CVTTPS2PIirr",
1657 "VCVTPD2DQrr",
1658 "VCVTPD2PSrr",
1659 "VCVTPH2PSrr",
1660 "VCVTPS2PDrr",
1661 "VCVTPS2PHrr",
1662 "VCVTSD2SSrr",
1663 "VCVTSI642SDrr",
1664 "VCVTSI2SDrr",
1665 "VCVTSI2SSrr",
1666 "VCVTSS2SDrr",
1667 "VCVTTPD2DQrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1668
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1669def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1670 let Latency = 5;
1671 let NumMicroOps = 3;
1672 let ResourceCycles = [1,1,1];
1673}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1674def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1675
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1676def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1677 let Latency = 5;
1678 let NumMicroOps = 3;
1679 let ResourceCycles = [1,1,1];
1680}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1681def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1682def: InstRW<[SKLWriteResGroup62], (instrs MULX32rr)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1683
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1684def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1685 let Latency = 5;
1686 let NumMicroOps = 5;
1687 let ResourceCycles = [1,4];
1688}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1689def: InstRW<[SKLWriteResGroup63], (instregex "XSETBV")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1690
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1691def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1692 let Latency = 5;
1693 let NumMicroOps = 5;
1694 let ResourceCycles = [2,3];
1695}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]1696def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1697
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1698def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1699 let Latency = 5;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1700 let NumMicroOps = 6;
1701 let ResourceCycles = [1,1,4];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1702}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1703def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF16",
1704 "PUSHF64")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1705
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1706def SKLWriteResGroup66 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1707 let Latency = 6;
1708 let NumMicroOps = 1;
1709 let ResourceCycles = [1];
1710}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1711def: InstRW<[SKLWriteResGroup66], (instregex "(V?)PCLMULQDQrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1712
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1713def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
1714 let Latency = 6;
1715 let NumMicroOps = 1;
1716 let ResourceCycles = [1];
1717}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1718def: InstRW<[SKLWriteResGroup67], (instregex "LDDQUrm",
1719 "MOVAPDrm",
1720 "MOVAPSrm",
1721 "MOVDQArm",
1722 "MOVDQUrm",
1723 "MOVNTDQArm",
1724 "MOVSHDUPrm",
1725 "MOVSLDUPrm",
1726 "MOVUPDrm",
1727 "MOVUPSrm",
1728 "VBROADCASTSSrm",
1729 "VLDDQUrm",
1730 "VMOVAPDrm",
1731 "VMOVAPSrm",
1732 "VMOVDQArm",
1733 "VMOVDQUrm",
1734 "VMOVNTDQArm",
1735 "VMOVSHDUPrm",
1736 "VMOVSLDUPrm",
1737 "VMOVUPDrm",
1738 "VMOVUPSrm",
1739 "VPBROADCASTDrm",
1740 "VPBROADCASTQrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1741
1742def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1743 let Latency = 6;
1744 let NumMicroOps = 2;
1745 let ResourceCycles = [2];
1746}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1747def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1748
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1749def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1750 let Latency = 6;
1751 let NumMicroOps = 2;
1752 let ResourceCycles = [1,1];
1753}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1754def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
1755 "MMX_PADDSWirm",
1756 "MMX_PADDUSBirm",
1757 "MMX_PADDUSWirm",
1758 "MMX_PAVGBirm",
1759 "MMX_PAVGWirm",
1760 "MMX_PCMPEQBirm",
1761 "MMX_PCMPEQDirm",
1762 "MMX_PCMPEQWirm",
1763 "MMX_PCMPGTBirm",
1764 "MMX_PCMPGTDirm",
1765 "MMX_PCMPGTWirm",
1766 "MMX_PMAXSWirm",
1767 "MMX_PMAXUBirm",
1768 "MMX_PMINSWirm",
1769 "MMX_PMINUBirm",
1770 "MMX_PSLLDrm",
1771 "MMX_PSLLQrm",
1772 "MMX_PSLLWrm",
1773 "MMX_PSRADrm",
1774 "MMX_PSRAWrm",
1775 "MMX_PSRLDrm",
1776 "MMX_PSRLQrm",
1777 "MMX_PSRLWrm",
1778 "MMX_PSUBSBirm",
1779 "MMX_PSUBSWirm",
1780 "MMX_PSUBUSBirm",
1781 "MMX_PSUBUSWirm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1782
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1783def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1784 let Latency = 6;
1785 let NumMicroOps = 2;
1786 let ResourceCycles = [1,1];
1787}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1788def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SI64rr",
1789 "CVTSD2SIrr",
1790 "CVTSS2SI64rr",
1791 "CVTSS2SIrr",
1792 "CVTTSD2SI64rr",
1793 "CVTTSD2SIrr",
1794 "VCVTSD2SI64rr",
1795 "VCVTSD2SIrr",
1796 "VCVTSS2SI64rr",
1797 "VCVTSS2SIrr",
1798 "VCVTTSD2SI64rr",
1799 "VCVTTSD2SIrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1800
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1801def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1802 let Latency = 6;
1803 let NumMicroOps = 2;
1804 let ResourceCycles = [1,1];
1805}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1806def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi",
1807 "MMX_PINSRWrm",
1808 "MMX_PSHUFBrm",
1809 "MMX_PSHUFWmi",
1810 "MMX_PUNPCKHBWirm",
1811 "MMX_PUNPCKHDQirm",
1812 "MMX_PUNPCKHWDirm",
1813 "MMX_PUNPCKLBWirm",
1814 "MMX_PUNPCKLDQirm",
1815 "MMX_PUNPCKLWDirm",
1816 "MOVHPDrm",
1817 "MOVHPSrm",
1818 "MOVLPDrm",
1819 "MOVLPSrm",
1820 "PINSRBrm",
1821 "PINSRDrm",
1822 "PINSRQrm",
1823 "PINSRWrm",
1824 "PMOVSXBDrm",
1825 "PMOVSXBQrm",
1826 "PMOVSXBWrm",
1827 "PMOVSXDQrm",
1828 "PMOVSXWDrm",
1829 "PMOVSXWQrm",
1830 "PMOVZXBDrm",
1831 "PMOVZXBQrm",
1832 "PMOVZXBWrm",
1833 "PMOVZXDQrm",
1834 "PMOVZXWDrm",
1835 "PMOVZXWQrm",
1836 "VMOVHPDrm",
1837 "VMOVHPSrm",
1838 "VMOVLPDrm",
1839 "VMOVLPSrm",
1840 "VPINSRBrm",
1841 "VPINSRDrm",
1842 "VPINSRQrm",
1843 "VPINSRWrm",
1844 "VPMOVSXBDrm",
1845 "VPMOVSXBQrm",
1846 "VPMOVSXBWrm",
1847 "VPMOVSXDQrm",
1848 "VPMOVSXWDrm",
1849 "VPMOVSXWQrm",
1850 "VPMOVZXBDrm",
1851 "VPMOVZXBQrm",
1852 "VPMOVZXBWrm",
1853 "VPMOVZXDQrm",
1854 "VPMOVZXWDrm",
1855 "VPMOVZXWQrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1856
1857def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1858 let Latency = 6;
1859 let NumMicroOps = 2;
1860 let ResourceCycles = [1,1];
1861}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1862def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64",
1863 "JMP(16|32|64)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1864
1865def SKLWriteResGroup73 : SchedWriteRes<[SKLPort23,SKLPort05]> {
1866 let Latency = 6;
1867 let NumMicroOps = 2;
1868 let ResourceCycles = [1,1];
1869}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1870def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm",
1871 "MMX_PABSDrm",
1872 "MMX_PABSWrm",
1873 "MMX_PADDBirm",
1874 "MMX_PADDDirm",
1875 "MMX_PADDQirm",
1876 "MMX_PADDWirm",
1877 "MMX_PANDNirm",
1878 "MMX_PANDirm",
1879 "MMX_PORirm",
1880 "MMX_PSIGNBrm",
1881 "MMX_PSIGNDrm",
1882 "MMX_PSIGNWrm",
1883 "MMX_PSUBBirm",
1884 "MMX_PSUBDirm",
1885 "MMX_PSUBQirm",
1886 "MMX_PSUBWirm",
1887 "MMX_PXORirm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1888
1889def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
1890 let Latency = 6;
1891 let NumMicroOps = 2;
1892 let ResourceCycles = [1,1];
1893}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1894def: InstRW<[SKLWriteResGroup74], (instregex "ADC(8|16|32|64)rm",
1895 "ADCX(32|64)rm",
1896 "ADOX(32|64)rm",
1897 "BT(16|32|64)mi8",
1898 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1899 "RORX(32|64)mi",
1900 "SARX(32|64)rm",
1901 "SBB(8|16|32|64)rm",
1902 "SHLX(32|64)rm",
1903 "SHRX(32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1904
1905def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1906 let Latency = 6;
1907 let NumMicroOps = 2;
1908 let ResourceCycles = [1,1];
1909}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1910def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1911 "BLSI(32|64)rm",
1912 "BLSMSK(32|64)rm",
1913 "BLSR(32|64)rm",
1914 "BZHI(32|64)rm",
1915 "MOVBE(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1916
1917def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1918 let Latency = 6;
1919 let NumMicroOps = 2;
1920 let ResourceCycles = [1,1];
1921}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1922def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1923def: InstRW<[SKLWriteResGroup76], (instregex "ADD(8|16|32|64)rm",
1924 "AND(8|16|32|64)rm",
1925 "CMP(8|16|32|64)mi",
1926 "CMP(8|16|32|64)mr",
1927 "CMP(8|16|32|64)rm",
1928 "OR(8|16|32|64)rm",
1929 "POP(16|32|64)rmr",
1930 "SUB(8|16|32|64)rm",
1931 "TEST(8|16|32|64)mr",
1932 "TEST(8|16|32|64)mi",
1933 "XOR(8|16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1934
1935def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1936 let Latency = 6;
1937 let NumMicroOps = 3;
1938 let ResourceCycles = [2,1];
1939}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1940def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr",
1941 "HADDPSrr",
1942 "HSUBPDrr",
1943 "HSUBPSrr",
1944 "VHADDPDYrr",
1945 "VHADDPDrr",
1946 "VHADDPSYrr",
1947 "VHADDPSrr",
1948 "VHSUBPDYrr",
1949 "VHSUBPDrr",
1950 "VHSUBPSYrr",
1951 "VHSUBPSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1952
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1953def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1954 let Latency = 6;
1955 let NumMicroOps = 3;
1956 let ResourceCycles = [2,1];
1957}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1958def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1959
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1960def SKLWriteResGroup79 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1961 let Latency = 6;
1962 let NumMicroOps = 4;
1963 let ResourceCycles = [1,2,1];
1964}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1965def: InstRW<[SKLWriteResGroup79], (instregex "SHLD(16|32|64)rrCL",
1966 "SHRD(16|32|64)rrCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1967
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1968def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1969 let Latency = 6;
1970 let NumMicroOps = 4;
1971 let ResourceCycles = [1,1,1,1];
1972}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1973def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1974
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1975def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
1976 let Latency = 6;
1977 let NumMicroOps = 4;
1978 let ResourceCycles = [1,1,1,1];
1979}
1980def: InstRW<[SKLWriteResGroup81], (instregex "VCVTPS2PHmr")>;
1981
1982def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1983 let Latency = 6;
1984 let NumMicroOps = 4;
1985 let ResourceCycles = [1,1,1,1];
1986}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1987def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",
1988 "BTR(16|32|64)mi8",
1989 "BTS(16|32|64)mi8",
1990 "SAR(8|16|32|64)m1",
1991 "SAR(8|16|32|64)mi",
1992 "SHL(8|16|32|64)m1",
1993 "SHL(8|16|32|64)mi",
1994 "SHR(8|16|32|64)m1",
1995 "SHR(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1996
1997def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1998 let Latency = 6;
1999 let NumMicroOps = 4;
2000 let ResourceCycles = [1,1,1,1];
2001}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2002def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mi",
2003 "ADD(8|16|32|64)mr",
2004 "AND(8|16|32|64)mi",
2005 "AND(8|16|32|64)mr",
2006 "DEC(8|16|32|64)m",
2007 "INC(8|16|32|64)m",
2008 "NEG(8|16|32|64)m",
2009 "NOT(8|16|32|64)m",
2010 "OR(8|16|32|64)mi",
2011 "OR(8|16|32|64)mr",
2012 "POP(16|32|64)rmm",
2013 "PUSH(16|32|64)rmm",
2014 "SUB(8|16|32|64)mi",
2015 "SUB(8|16|32|64)mr",
2016 "XOR(8|16|32|64)mi",
2017 "XOR(8|16|32|64)mr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2018
2019def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2020 let Latency = 6;
2021 let NumMicroOps = 6;
2022 let ResourceCycles = [1,5];
2023}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2024def: InstRW<[SKLWriteResGroup84], (instregex "STD")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2025
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2026def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
2027 let Latency = 7;
2028 let NumMicroOps = 1;
2029 let ResourceCycles = [1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2030}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2031def: InstRW<[SKLWriteResGroup85], (instregex "LD_F32m",
2032 "LD_F64m",
2033 "LD_F80m",
2034 "VBROADCASTF128",
2035 "VBROADCASTI128",
2036 "VBROADCASTSDYrm",
2037 "VBROADCASTSSYrm",
2038 "VLDDQUYrm",
2039 "VMOVAPDYrm",
2040 "VMOVAPSYrm",
2041 "VMOVDDUPYrm",
2042 "VMOVDQAYrm",
2043 "VMOVDQUYrm",
2044 "VMOVNTDQAYrm",
2045 "VMOVSHDUPYrm",
2046 "VMOVSLDUPYrm",
2047 "VMOVUPDYrm",
2048 "VMOVUPSYrm",
2049 "VPBROADCASTDYrm",
2050 "VPBROADCASTQYrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2051
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2052def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2053 let Latency = 7;
2054 let NumMicroOps = 2;
2055 let ResourceCycles = [1,1];
2056}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2057def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2058
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2059def SKLWriteResGroup87 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2060 let Latency = 7;
2061 let NumMicroOps = 2;
2062 let ResourceCycles = [1,1];
2063}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2064def: InstRW<[SKLWriteResGroup87], (instregex "COMISDrm",
2065 "COMISSrm",
2066 "UCOMISDrm",
2067 "UCOMISSrm",
2068 "VCOMISDrm",
2069 "VCOMISSrm",
2070 "VUCOMISDrm",
2071 "VUCOMISSrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2072
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2073def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2074 let Latency = 7;
2075 let NumMicroOps = 2;
2076 let ResourceCycles = [1,1];
2077}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2078def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm",
2079 "PACKSSDWrm",
2080 "PACKSSWBrm",
2081 "PACKUSDWrm",
2082 "PACKUSWBrm",
2083 "PALIGNRrmi",
2084 "PBLENDWrmi",
2085 "PSHUFBrm",
2086 "PSHUFDmi",
2087 "PSHUFHWmi",
2088 "PSHUFLWmi",
2089 "PUNPCKHBWrm",
2090 "PUNPCKHDQrm",
2091 "PUNPCKHQDQrm",
2092 "PUNPCKHWDrm",
2093 "PUNPCKLBWrm",
2094 "PUNPCKLDQrm",
2095 "PUNPCKLQDQrm",
2096 "PUNPCKLWDrm",
2097 "SHUFPDrmi",
2098 "SHUFPSrmi",
2099 "UNPCKHPDrm",
2100 "UNPCKHPSrm",
2101 "UNPCKLPDrm",
2102 "UNPCKLPSrm",
2103 "VINSERTPSrm",
2104 "VPACKSSDWrm",
2105 "VPACKSSWBrm",
2106 "VPACKUSDWrm",
2107 "VPACKUSWBrm",
2108 "VPALIGNRrmi",
2109 "VPBLENDWrmi",
2110 "VPBROADCASTBrm",
2111 "VPBROADCASTWrm",
2112 "VPERMILPDmi",
2113 "VPERMILPDrm",
2114 "VPERMILPSmi",
2115 "VPERMILPSrm",
2116 "VPSHUFBrm",
2117 "VPSHUFDmi",
2118 "VPSHUFHWmi",
2119 "VPSHUFLWmi",
2120 "VPUNPCKHBWrm",
2121 "VPUNPCKHDQrm",
2122 "VPUNPCKHQDQrm",
2123 "VPUNPCKHWDrm",
2124 "VPUNPCKLBWrm",
2125 "VPUNPCKLDQrm",
2126 "VPUNPCKLQDQrm",
2127 "VPUNPCKLWDrm",
2128 "VSHUFPDrmi",
2129 "VSHUFPSrmi",
2130 "VUNPCKHPDrm",
2131 "VUNPCKHPSrm",
2132 "VUNPCKLPDrm",
2133 "VUNPCKLPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2134
2135def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort015]> {
2136 let Latency = 7;
2137 let NumMicroOps = 2;
2138 let ResourceCycles = [1,1];
2139}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2140def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr",
2141 "VCVTPD2PSYrr",
2142 "VCVTPH2PSYrr",
2143 "VCVTPS2PDYrr",
2144 "VCVTPS2PHYrr",
2145 "VCVTTPD2DQYrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2146
2147def SKLWriteResGroup90 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2148 let Latency = 7;
2149 let NumMicroOps = 2;
2150 let ResourceCycles = [1,1];
2151}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2152def: InstRW<[SKLWriteResGroup90], (instregex "PABSBrm",
2153 "PABSDrm",
2154 "PABSWrm",
2155 "PADDSBrm",
2156 "PADDSWrm",
2157 "PADDUSBrm",
2158 "PADDUSWrm",
2159 "PAVGBrm",
2160 "PAVGWrm",
2161 "PCMPEQBrm",
2162 "PCMPEQDrm",
2163 "PCMPEQQrm",
2164 "PCMPEQWrm",
2165 "PCMPGTBrm",
2166 "PCMPGTDrm",
2167 "PCMPGTWrm",
2168 "PMAXSBrm",
2169 "PMAXSDrm",
2170 "PMAXSWrm",
2171 "PMAXUBrm",
2172 "PMAXUDrm",
2173 "PMAXUWrm",
2174 "PMINSBrm",
2175 "PMINSDrm",
2176 "PMINSWrm",
2177 "PMINUBrm",
2178 "PMINUDrm",
2179 "PMINUWrm",
2180 "PSIGNBrm",
2181 "PSIGNDrm",
2182 "PSIGNWrm",
2183 "PSLLDrm",
2184 "PSLLQrm",
2185 "PSLLWrm",
2186 "PSRADrm",
2187 "PSRAWrm",
2188 "PSRLDrm",
2189 "PSRLQrm",
2190 "PSRLWrm",
2191 "PSUBSBrm",
2192 "PSUBSWrm",
2193 "PSUBUSBrm",
2194 "PSUBUSWrm",
2195 "VPABSBrm",
2196 "VPABSDrm",
2197 "VPABSWrm",
2198 "VPADDSBrm",
2199 "VPADDSWrm",
2200 "VPADDUSBrm",
2201 "VPADDUSWrm",
2202 "VPAVGBrm",
2203 "VPAVGWrm",
2204 "VPCMPEQBrm",
2205 "VPCMPEQDrm",
2206 "VPCMPEQQrm",
2207 "VPCMPEQWrm",
2208 "VPCMPGTBrm",
2209 "VPCMPGTDrm",
2210 "VPCMPGTWrm",
2211 "VPMAXSBrm",
2212 "VPMAXSDrm",
2213 "VPMAXSWrm",
2214 "VPMAXUBrm",
2215 "VPMAXUDrm",
2216 "VPMAXUWrm",
2217 "VPMINSBrm",
2218 "VPMINSDrm",
2219 "VPMINSWrm",
2220 "VPMINUBrm",
2221 "VPMINUDrm",
2222 "VPMINUWrm",
2223 "VPSIGNBrm",
2224 "VPSIGNDrm",
2225 "VPSIGNWrm",
2226 "VPSLLDrm",
2227 "VPSLLQrm",
2228 "VPSLLVDrm",
2229 "VPSLLVQrm",
2230 "VPSLLWrm",
2231 "VPSRADrm",
2232 "VPSRAVDrm",
2233 "VPSRAWrm",
2234 "VPSRLDrm",
2235 "VPSRLQrm",
2236 "VPSRLVDrm",
2237 "VPSRLVQrm",
2238 "VPSRLWrm",
2239 "VPSUBSBrm",
2240 "VPSUBSWrm",
2241 "VPSUBUSBrm",
2242 "VPSUBUSWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2243
2244def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2245 let Latency = 7;
2246 let NumMicroOps = 2;
2247 let ResourceCycles = [1,1];
2248}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2249def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPDrm",
2250 "ANDNPSrm",
2251 "ANDPDrm",
2252 "ANDPSrm",
2253 "BLENDPDrmi",
2254 "BLENDPSrmi",
2255 "ORPDrm",
2256 "ORPSrm",
2257 "PADDBrm",
2258 "PADDDrm",
2259 "PADDQrm",
2260 "PADDWrm",
2261 "PANDNrm",
2262 "PANDrm",
2263 "PORrm",
2264 "PSUBBrm",
2265 "PSUBDrm",
2266 "PSUBQrm",
2267 "PSUBWrm",
2268 "PXORrm",
2269 "VANDNPDrm",
2270 "VANDNPSrm",
2271 "VANDPDrm",
2272 "VANDPSrm",
2273 "VBLENDPDrmi",
2274 "VBLENDPSrmi",
2275 "VINSERTF128rm",
2276 "VINSERTI128rm",
2277 "VMASKMOVPDrm",
2278 "VMASKMOVPSrm",
2279 "VORPDrm",
2280 "VORPSrm",
2281 "VPADDBrm",
2282 "VPADDDrm",
2283 "VPADDQrm",
2284 "VPADDWrm",
2285 "VPANDNrm",
2286 "VPANDrm",
2287 "VPBLENDDrmi",
2288 "VPMASKMOVDrm",
2289 "VPMASKMOVQrm",
2290 "VPORrm",
2291 "VPSUBBrm",
2292 "VPSUBDrm",
2293 "VPSUBQrm",
2294 "VPSUBWrm",
2295 "VPXORrm",
2296 "VXORPDrm",
2297 "VXORPSrm",
2298 "XORPDrm",
2299 "XORPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2300
2301def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2302 let Latency = 7;
2303 let NumMicroOps = 3;
2304 let ResourceCycles = [2,1];
2305}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2306def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm",
2307 "MMX_PACKSSWBirm",
2308 "MMX_PACKUSWBirm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2309
2310def SKLWriteResGroup93 : SchedWriteRes<[SKLPort23,SKLPort06]> {
2311 let Latency = 7;
2312 let NumMicroOps = 3;
2313 let ResourceCycles = [1,2];
2314}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]2315def: InstRW<[SKLWriteResGroup93], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2316
2317def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
2318 let Latency = 7;
2319 let NumMicroOps = 3;
2320 let ResourceCycles = [1,2];
2321}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2322def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64",
2323 "SCASB",
2324 "SCASL",
2325 "SCASQ",
2326 "SCASW")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2327
2328def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2329 let Latency = 7;
2330 let NumMicroOps = 3;
2331 let ResourceCycles = [1,1,1];
2332}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2333def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI64rr",
2334 "(V?)CVTTSS2SIrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2335
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2336def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2337 let Latency = 7;
2338 let NumMicroOps = 3;
2339 let ResourceCycles = [1,1,1];
2340}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2341def: InstRW<[SKLWriteResGroup96], (instregex "FLDCW16m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2342
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2343def SKLWriteResGroup97 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2344 let Latency = 7;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2345 let NumMicroOps = 3;
2346 let ResourceCycles = [1,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2347}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2348def: InstRW<[SKLWriteResGroup97], (instregex "(V?)LDMXCSR")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2349
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2350def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2351 let Latency = 7;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2352 let NumMicroOps = 3;
2353 let ResourceCycles = [1,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2354}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2355def: InstRW<[SKLWriteResGroup98], (instregex "LRETQ",
2356 "RETQ")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2357
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2358def SKLWriteResGroup99 : SchedWriteRes<[SKLPort23,SKLPort06,SKLPort15]> {
2359 let Latency = 7;
2360 let NumMicroOps = 3;
2361 let ResourceCycles = [1,1,1];
2362}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]2363def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR(32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2364
2365def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
2366 let Latency = 7;
2367 let NumMicroOps = 5;
2368 let ResourceCycles = [1,1,1,2];
2369}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2370def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",
2371 "ROL(8|16|32|64)mi",
2372 "ROR(8|16|32|64)m1",
2373 "ROR(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2374
2375def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
2376 let Latency = 7;
2377 let NumMicroOps = 5;
2378 let ResourceCycles = [1,1,1,2];
2379}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2380def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2381
2382def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
2383 let Latency = 7;
2384 let NumMicroOps = 5;
2385 let ResourceCycles = [1,1,1,1,1];
2386}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2387def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m",
2388 "FARCALL64")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2389
2390def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2391 let Latency = 7;
2392 let NumMicroOps = 7;
2393 let ResourceCycles = [1,3,1,2];
2394}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2395def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2396
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2397def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2398 let Latency = 8;
2399 let NumMicroOps = 2;
2400 let ResourceCycles = [2];
2401}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2402def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr",
2403 "ROUNDPSr",
2404 "ROUNDSDr",
2405 "ROUNDSSr",
2406 "VROUNDPDr",
2407 "VROUNDPSr",
2408 "VROUNDSDr",
2409 "VROUNDSSr",
2410 "VROUNDYPDr",
2411 "VROUNDYPSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2412
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]2413def SKLWriteResGroup105_2 : SchedWriteRes<[SKLPort01]> {
2414 let Latency = 10;
2415 let NumMicroOps = 2;
2416 let ResourceCycles = [2];
2417}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2418def: InstRW<[SKLWriteResGroup105_2], (instregex "PMULLDrr",
2419 "VPMULLDYrr",
2420 "VPMULLDrr")>;
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]2421
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2422def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2423 let Latency = 8;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2424 let NumMicroOps = 2;
2425 let ResourceCycles = [1,1];
2426}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2427def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPDrm",
2428 "VTESTPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2429
2430def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
2431 let Latency = 8;
2432 let NumMicroOps = 2;
2433 let ResourceCycles = [1,1];
2434}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2435def: InstRW<[SKLWriteResGroup107], (instrs IMUL64m, MUL64m)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2436def: InstRW<[SKLWriteResGroup107], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2437def: InstRW<[SKLWriteResGroup107], (instrs IMUL8m, MUL8m)>;
2438def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm",
2439 "BSR(16|32|64)rm",
2440 "LZCNT(16|32|64)rm",
2441 "PDEP(32|64)rm",
2442 "PEXT(32|64)rm",
2443 "POPCNT(16|32|64)rm",
2444 "TZCNT(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2445
2446def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2447 let Latency = 8;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2448 let NumMicroOps = 3;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2449 let ResourceCycles = [1,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2450}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2451def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2452
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2453def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2454 let Latency = 8;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2455 let NumMicroOps = 5;
2456}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2457def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2458
2459def SKLWriteResGroup107_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2460 let Latency = 8;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2461 let NumMicroOps = 3;
2462 let ResourceCycles = [1,1,1];
2463}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2464def: InstRW<[SKLWriteResGroup107_32], (instrs IMUL32m, MUL32m)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2465
2466def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2467 let Latency = 8;
2468 let NumMicroOps = 2;
2469 let ResourceCycles = [1,1];
2470}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2471def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m",
2472 "FCOM64m",
2473 "FCOMP32m",
2474 "FCOMP64m",
2475 "MMX_PSADBWirm",
2476 "VPACKSSDWYrm",
2477 "VPACKSSWBYrm",
2478 "VPACKUSDWYrm",
2479 "VPACKUSWBYrm",
2480 "VPALIGNRYrmi",
2481 "VPBLENDWYrmi",
2482 "VPBROADCASTBYrm",
2483 "VPBROADCASTWYrm",
2484 "VPERMILPDYmi",
2485 "VPERMILPDYrm",
2486 "VPERMILPSYmi",
2487 "VPERMILPSYrm",
2488 "VPMOVSXBDYrm",
2489 "VPMOVSXBQYrm",
2490 "VPMOVSXWQYrm",
2491 "VPSHUFBYrm",
2492 "VPSHUFDYmi",
2493 "VPSHUFHWYmi",
2494 "VPSHUFLWYmi",
2495 "VPUNPCKHBWYrm",
2496 "VPUNPCKHDQYrm",
2497 "VPUNPCKHQDQYrm",
2498 "VPUNPCKHWDYrm",
2499 "VPUNPCKLBWYrm",
2500 "VPUNPCKLDQYrm",
2501 "VPUNPCKLQDQYrm",
2502 "VPUNPCKLWDYrm",
2503 "VSHUFPDYrmi",
2504 "VSHUFPSYrmi",
2505 "VUNPCKHPDYrm",
2506 "VUNPCKHPSYrm",
2507 "VUNPCKLPDYrm",
2508 "VUNPCKLPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2509
2510def SKLWriteResGroup109 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2511 let Latency = 8;
2512 let NumMicroOps = 2;
2513 let ResourceCycles = [1,1];
2514}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2515def: InstRW<[SKLWriteResGroup109], (instregex "VPABSBYrm",
2516 "VPABSDYrm",
2517 "VPABSWYrm",
2518 "VPADDSBYrm",
2519 "VPADDSWYrm",
2520 "VPADDUSBYrm",
2521 "VPADDUSWYrm",
2522 "VPAVGBYrm",
2523 "VPAVGWYrm",
2524 "VPCMPEQBYrm",
2525 "VPCMPEQDYrm",
2526 "VPCMPEQQYrm",
2527 "VPCMPEQWYrm",
2528 "VPCMPGTBYrm",
2529 "VPCMPGTDYrm",
2530 "VPCMPGTWYrm",
2531 "VPMAXSBYrm",
2532 "VPMAXSDYrm",
2533 "VPMAXSWYrm",
2534 "VPMAXUBYrm",
2535 "VPMAXUDYrm",
2536 "VPMAXUWYrm",
2537 "VPMINSBYrm",
2538 "VPMINSDYrm",
2539 "VPMINSWYrm",
2540 "VPMINUBYrm",
2541 "VPMINUDYrm",
2542 "VPMINUWYrm",
2543 "VPSIGNBYrm",
2544 "VPSIGNDYrm",
2545 "VPSIGNWYrm",
2546 "VPSLLDYrm",
2547 "VPSLLQYrm",
2548 "VPSLLVDYrm",
2549 "VPSLLVQYrm",
2550 "VPSLLWYrm",
2551 "VPSRADYrm",
2552 "VPSRAVDYrm",
2553 "VPSRAWYrm",
2554 "VPSRLDYrm",
2555 "VPSRLQYrm",
2556 "VPSRLVDYrm",
2557 "VPSRLVQYrm",
2558 "VPSRLWYrm",
2559 "VPSUBSBYrm",
2560 "VPSUBSWYrm",
2561 "VPSUBUSBYrm",
2562 "VPSUBUSWYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2563
2564def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2565 let Latency = 8;
2566 let NumMicroOps = 2;
2567 let ResourceCycles = [1,1];
2568}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2569def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPDYrm",
2570 "VANDNPSYrm",
2571 "VANDPDYrm",
2572 "VANDPSYrm",
2573 "VBLENDPDYrmi",
2574 "VBLENDPSYrmi",
2575 "VMASKMOVPDYrm",
2576 "VMASKMOVPSYrm",
2577 "VORPDYrm",
2578 "VORPSYrm",
2579 "VPADDBYrm",
2580 "VPADDDYrm",
2581 "VPADDQYrm",
2582 "VPADDWYrm",
2583 "VPANDNYrm",
2584 "VPANDYrm",
2585 "VPBLENDDYrmi",
2586 "VPMASKMOVDYrm",
2587 "VPMASKMOVQYrm",
2588 "VPORYrm",
2589 "VPSUBBYrm",
2590 "VPSUBDYrm",
2591 "VPSUBQYrm",
2592 "VPSUBWYrm",
2593 "VPXORYrm",
2594 "VXORPDYrm",
2595 "VXORPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2596
2597def SKLWriteResGroup111 : SchedWriteRes<[SKLPort23,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2598 let Latency = 8;
2599 let NumMicroOps = 3;
2600 let ResourceCycles = [1,2];
2601}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2602def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPDrm0",
2603 "BLENDVPSrm0",
2604 "PBLENDVBrm0",
2605 "VBLENDVPDrm",
2606 "VBLENDVPSrm",
2607 "VPBLENDVBYrm",
2608 "VPBLENDVBrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2609
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2610def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
2611 let Latency = 8;
2612 let NumMicroOps = 4;
2613 let ResourceCycles = [1,2,1];
2614}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2615def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm",
2616 "MMX_PHSUBSWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2617
2618def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
2619 let Latency = 8;
2620 let NumMicroOps = 4;
2621 let ResourceCycles = [2,1,1];
2622}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2623def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm",
2624 "MMX_PHADDWrm",
2625 "MMX_PHSUBDrm",
2626 "MMX_PHSUBWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2627
2628def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
2629 let Latency = 8;
2630 let NumMicroOps = 4;
2631 let ResourceCycles = [1,1,1,1];
2632}
2633def: InstRW<[SKLWriteResGroup114], (instregex "VCVTPS2PHYmr")>;
2634
2635def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
2636 let Latency = 8;
2637 let NumMicroOps = 5;
2638 let ResourceCycles = [1,1,3];
2639}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2640def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2641
2642def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
2643 let Latency = 8;
2644 let NumMicroOps = 5;
2645 let ResourceCycles = [1,1,1,2];
2646}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2647def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",
2648 "RCL(8|16|32|64)mi",
2649 "RCR(8|16|32|64)m1",
2650 "RCR(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2651
2652def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
2653 let Latency = 8;
2654 let NumMicroOps = 6;
2655 let ResourceCycles = [1,1,1,3];
2656}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2657def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
2658 "SAR(8|16|32|64)mCL",
2659 "SHL(8|16|32|64)mCL",
2660 "SHR(8|16|32|64)mCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2661
2662def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
2663 let Latency = 8;
2664 let NumMicroOps = 6;
2665 let ResourceCycles = [1,1,1,3];
2666}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2667def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2668
2669def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
2670 let Latency = 8;
2671 let NumMicroOps = 6;
2672 let ResourceCycles = [1,1,1,2,1];
2673}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2674def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr",
2675 "CMPXCHG(8|16|32|64)rm",
2676 "SBB(8|16|32|64)mi",
2677 "SBB(8|16|32|64)mr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2678
2679def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
2680 let Latency = 9;
2681 let NumMicroOps = 2;
2682 let ResourceCycles = [1,1];
2683}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2684def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm",
2685 "MMX_PMADDUBSWrm",
2686 "MMX_PMADDWDirm",
2687 "MMX_PMULHRSWrm",
2688 "MMX_PMULHUWirm",
2689 "MMX_PMULHWirm",
2690 "MMX_PMULLWirm",
2691 "MMX_PMULUDQirm",
2692 "RCPSSm",
2693 "RSQRTSSm",
2694 "VRCPSSm",
2695 "VRSQRTSSm",
2696 "VTESTPDYrm",
2697 "VTESTPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2698
2699def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2700 let Latency = 9;
2701 let NumMicroOps = 2;
2702 let ResourceCycles = [1,1];
2703}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2704def: InstRW<[SKLWriteResGroup121], (instregex "PCMPGTQrm",
2705 "PSADBWrm",
2706 "VPCMPGTQrm",
2707 "VPMOVSXBWYrm",
2708 "VPMOVSXDQYrm",
2709 "VPMOVSXWDYrm",
2710 "VPMOVZXWDYrm",
2711 "VPSADBWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2712
2713def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2714 let Latency = 9;
2715 let NumMicroOps = 2;
2716 let ResourceCycles = [1,1];
2717}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2718def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm",
2719 "ADDSSrm",
2720 "MULSDrm",
2721 "MULSSrm",
2722 "SUBSDrm",
2723 "SUBSSrm",
2724 "VADDSDrm",
2725 "VADDSSrm",
2726 "VMULSDrm",
2727 "VMULSSrm",
2728 "VSUBSDrm",
2729 "VSUBSSrm")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2730def: InstRW<[SKLWriteResGroup122],
2731 (instregex "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2732
2733def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2734 let Latency = 9;
2735 let NumMicroOps = 2;
2736 let ResourceCycles = [1,1];
2737}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2738def: InstRW<[SKLWriteResGroup123], (instregex "CMPSDrm",
2739 "CMPSSrm",
2740 "CVTPS2PDrm",
2741 "MAX(C?)SDrm",
2742 "MAX(C?)SSrm",
2743 "MIN(C?)SDrm",
2744 "MIN(C?)SSrm",
2745 "MMX_CVTPS2PIirm",
2746 "MMX_CVTTPS2PIirm",
2747 "VCMPSDrm",
2748 "VCMPSSrm",
2749 "VCVTPH2PSrm",
2750 "VCVTPS2PDrm",
2751 "VMAX(C?)SDrm",
2752 "VMAX(C?)SSrm",
2753 "VMIN(C?)SDrm",
2754 "VMIN(C?)SSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2755
2756def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2757 let Latency = 9;
2758 let NumMicroOps = 3;
2759 let ResourceCycles = [1,2];
2760}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2761def: InstRW<[SKLWriteResGroup124], (instregex "(V?)DPPDrri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2762
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2763def SKLWriteResGroup125 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2764 let Latency = 9;
2765 let NumMicroOps = 3;
2766 let ResourceCycles = [1,2];
2767}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2768def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPDYrm",
2769 "VBLENDVPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2770
2771def SKLWriteResGroup126 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
2772 let Latency = 9;
2773 let NumMicroOps = 3;
2774 let ResourceCycles = [1,1,1];
2775}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2776def: InstRW<[SKLWriteResGroup126], (instregex "(V?)PTESTrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2777
2778def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
2779 let Latency = 9;
2780 let NumMicroOps = 3;
2781 let ResourceCycles = [1,1,1];
2782}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2783def: InstRW<[SKLWriteResGroup127], (instrs MULX64rm)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2784
2785def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2786 let Latency = 9;
2787 let NumMicroOps = 4;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2788 let ResourceCycles = [2,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2789}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2790def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
2791 "(V?)PHSUBSWrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2792
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2793def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
2794 let Latency = 9;
2795 let NumMicroOps = 4;
2796 let ResourceCycles = [2,1,1];
2797}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2798def: InstRW<[SKLWriteResGroup129], (instregex "(V?)PHADDDrm",
2799 "(V?)PHADDWrm",
2800 "(V?)PHSUBDrm",
2801 "(V?)PHSUBWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2802
2803def SKLWriteResGroup130 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort0156]> {
2804 let Latency = 9;
2805 let NumMicroOps = 4;
2806 let ResourceCycles = [1,1,1,1];
2807}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2808def: InstRW<[SKLWriteResGroup130], (instregex "SHLD(16|32|64)mri8",
2809 "SHRD(16|32|64)mri8")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2810
2811def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
2812 let Latency = 9;
2813 let NumMicroOps = 5;
2814 let ResourceCycles = [1,2,1,1];
2815}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2816def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
2817 "LSL(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2818
2819def SKLWriteResGroup132 : SchedWriteRes<[SKLPort0,SKLPort23]> {
2820 let Latency = 10;
2821 let NumMicroOps = 2;
2822 let ResourceCycles = [1,1];
2823}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame^]2824def: InstRW<[SKLWriteResGroup132], (instregex "(V?)RCPPSm",
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2825 "(V?)RSQRTPSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2826
2827def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2828 let Latency = 10;
2829 let NumMicroOps = 2;
2830 let ResourceCycles = [1,1];
2831}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2832def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F32m",
2833 "ADD_F64m",
2834 "ILD_F16m",
2835 "ILD_F32m",
2836 "ILD_F64m",
2837 "SUBR_F32m",
2838 "SUBR_F64m",
2839 "SUB_F32m",
2840 "SUB_F64m",
2841 "VPCMPGTQYrm",
2842 "VPERM2F128rm",
2843 "VPERM2I128rm",
2844 "VPERMDYrm",
2845 "VPERMPDYmi",
2846 "VPERMPSYrm",
2847 "VPERMQYmi",
2848 "VPMOVZXBDYrm",
2849 "VPMOVZXBQYrm",
2850 "VPMOVZXBWYrm",
2851 "VPMOVZXDQYrm",
2852 "VPMOVZXWQYrm",
2853 "VPSADBWYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2854
2855def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2856 let Latency = 10;
2857 let NumMicroOps = 2;
2858 let ResourceCycles = [1,1];
2859}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2860def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm",
2861 "ADDPSrm",
2862 "ADDSUBPDrm",
2863 "ADDSUBPSrm",
2864 "MULPDrm",
2865 "MULPSrm",
2866 "SUBPDrm",
2867 "SUBPSrm",
2868 "VADDPDrm",
2869 "VADDPSrm",
2870 "VADDSUBPDrm",
2871 "VADDSUBPSrm",
2872 "VMULPDrm",
2873 "VMULPSrm",
2874 "VSUBPDrm",
2875 "VSUBPSrm")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2876def: InstRW<[SKLWriteResGroup134],
2877 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2878
2879def SKLWriteResGroup135 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2880 let Latency = 10;
2881 let NumMicroOps = 2;
2882 let ResourceCycles = [1,1];
2883}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2884def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
2885 "CMPPSrmi",
2886 "CVTDQ2PSrm",
2887 "CVTPS2DQrm",
2888 "CVTSS2SDrm",
2889 "CVTTPS2DQrm",
2890 "MAX(C?)PDrm",
2891 "MAX(C?)PSrm",
2892 "MIN(C?)PDrm",
2893 "MIN(C?)PSrm",
2894 "PHMINPOSUWrm",
2895 "PMADDUBSWrm",
2896 "PMADDWDrm",
2897 "PMULDQrm",
2898 "PMULHRSWrm",
2899 "PMULHUWrm",
2900 "PMULHWrm",
2901 "PMULLWrm",
2902 "PMULUDQrm",
2903 "VCMPPDrmi",
2904 "VCMPPSrmi",
2905 "VCVTDQ2PSrm",
2906 "VCVTPH2PSYrm",
2907 "VCVTPS2DQrm",
2908 "VCVTSS2SDrm",
2909 "VCVTTPS2DQrm",
2910 "VMAX(C?)PDrm",
2911 "VMAX(C?)PSrm",
2912 "VMIN(C?)PDrm",
2913 "VMIN(C?)PSrm",
2914 "VPHMINPOSUWrm",
2915 "VPMADDUBSWrm",
2916 "VPMADDWDrm",
2917 "VPMULDQrm",
2918 "VPMULHRSWrm",
2919 "VPMULHUWrm",
2920 "VPMULHWrm",
2921 "VPMULLWrm",
2922 "VPMULUDQrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2923
2924def SKLWriteResGroup136 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2925 let Latency = 10;
2926 let NumMicroOps = 3;
2927 let ResourceCycles = [3];
2928}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2929def: InstRW<[SKLWriteResGroup136], (instregex "(V?)PCMPISTRIrr",
2930 "(V?)PCMPISTRM128rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2931
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2932def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2933 let Latency = 10;
2934 let NumMicroOps = 3;
2935 let ResourceCycles = [2,1];
2936}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2937def: InstRW<[SKLWriteResGroup137], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2938
2939def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
2940 let Latency = 10;
2941 let NumMicroOps = 3;
2942 let ResourceCycles = [1,1,1];
2943}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2944def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm",
2945 "VPTESTYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2946
2947def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
2948 let Latency = 10;
2949 let NumMicroOps = 3;
2950 let ResourceCycles = [1,1,1];
2951}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2952def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2953
2954def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2955 let Latency = 10;
2956 let NumMicroOps = 4;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2957 let ResourceCycles = [2,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2958}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2959def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm",
2960 "VPHSUBSWYrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2961
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2962def SKLWriteResGroup141 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
2963 let Latency = 10;
2964 let NumMicroOps = 4;
2965 let ResourceCycles = [2,1,1];
2966}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2967def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDDYrm",
2968 "VPHADDWYrm",
2969 "VPHSUBDYrm",
2970 "VPHSUBWYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2971
2972def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
2973 let Latency = 10;
2974 let NumMicroOps = 4;
2975 let ResourceCycles = [1,1,1,1];
2976}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2977def: InstRW<[SKLWriteResGroup142], (instrs MULX32rm)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2978
2979def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
2980 let Latency = 10;
2981 let NumMicroOps = 8;
2982 let ResourceCycles = [1,1,1,1,1,3];
2983}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2984def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2985
2986def SKLWriteResGroup144 : SchedWriteRes<[SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2987 let Latency = 10;
2988 let NumMicroOps = 10;
2989 let ResourceCycles = [9,1];
2990}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2991def: InstRW<[SKLWriteResGroup144], (instregex "MMX_EMMS")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2992
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2993def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2994 let Latency = 11;
2995 let NumMicroOps = 1;
2996 let ResourceCycles = [1];
2997}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2998def: InstRW<[SKLWriteResGroup145], (instregex "DIVPSrr",
2999 "DIVSSrr",
3000 "VDIVPSYrr",
3001 "VDIVPSrr",
3002 "VDIVSSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3003
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3004def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3005 let Latency = 11;
3006 let NumMicroOps = 2;
3007 let ResourceCycles = [1,1];
3008}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3009def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F32m",
3010 "MUL_F64m",
3011 "VRCPPSYm",
3012 "VRSQRTPSYm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3013
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3014def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
3015 let Latency = 11;
3016 let NumMicroOps = 2;
3017 let ResourceCycles = [1,1];
3018}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3019def: InstRW<[SKLWriteResGroup147], (instregex "VADDPDYrm",
3020 "VADDPSYrm",
3021 "VADDSUBPDYrm",
3022 "VADDSUBPSYrm",
3023 "VMULPDYrm",
3024 "VMULPSYrm",
3025 "VSUBPDYrm",
3026 "VSUBPSYrm")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]3027def: InstRW<[SKLWriteResGroup147],
3028 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3029
3030def SKLWriteResGroup148 : SchedWriteRes<[SKLPort23,SKLPort015]> {
3031 let Latency = 11;
3032 let NumMicroOps = 2;
3033 let ResourceCycles = [1,1];
3034}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3035def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi",
3036 "VCMPPSYrmi",
3037 "VCVTDQ2PSYrm",
3038 "VCVTPS2DQYrm",
3039 "VCVTPS2PDYrm",
3040 "VCVTTPS2DQYrm",
3041 "VMAX(C?)PDYrm",
3042 "VMAX(C?)PSYrm",
3043 "VMIN(C?)PDYrm",
3044 "VMIN(C?)PSYrm",
3045 "VPMADDUBSWYrm",
3046 "VPMADDWDYrm",
3047 "VPMULDQYrm",
3048 "VPMULHRSWYrm",
3049 "VPMULHUWYrm",
3050 "VPMULHWYrm",
3051 "VPMULLWYrm",
3052 "VPMULUDQYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3053
3054def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
3055 let Latency = 11;
3056 let NumMicroOps = 3;
3057 let ResourceCycles = [2,1];
3058}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3059def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m",
3060 "FICOM32m",
3061 "FICOMP16m",
3062 "FICOMP32m",
3063 "VMPSADBWYrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3064
3065def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3066 let Latency = 11;
3067 let NumMicroOps = 3;
3068 let ResourceCycles = [1,1,1];
3069}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3070def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3071
3072def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {
3073 let Latency = 11;
3074 let NumMicroOps = 3;
3075 let ResourceCycles = [1,1,1];
3076}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3077def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm",
3078 "CVTSD2SIrm",
3079 "CVTSS2SI64rm",
3080 "CVTSS2SIrm",
3081 "CVTTSD2SI64rm",
3082 "CVTTSD2SIrm",
3083 "CVTTSS2SIrm",
3084 "VCVTSD2SI64rm",
3085 "VCVTSD2SIrm",
3086 "VCVTSS2SI64rm",
3087 "VCVTSS2SIrm",
3088 "VCVTTSD2SI64rm",
3089 "VCVTTSD2SIrm",
3090 "VCVTTSS2SI64rm",
3091 "VCVTTSS2SIrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3092
3093def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3094 let Latency = 11;
3095 let NumMicroOps = 3;
3096 let ResourceCycles = [1,1,1];
3097}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3098def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm",
3099 "CVTPD2PSrm",
3100 "CVTTPD2DQrm",
3101 "MMX_CVTPD2PIirm",
3102 "MMX_CVTTPD2PIirm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3103
3104def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3105 let Latency = 11;
3106 let NumMicroOps = 6;
3107 let ResourceCycles = [1,1,1,2,1];
3108}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3109def: InstRW<[SKLWriteResGroup153], (instregex "SHLD(16|32|64)mrCL",
3110 "SHRD(16|32|64)mrCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3111
3112def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3113 let Latency = 11;
3114 let NumMicroOps = 7;
3115 let ResourceCycles = [2,3,2];
3116}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3117def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
3118 "RCR(16|32|64)rCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3119
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3120def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3121 let Latency = 11;
3122 let NumMicroOps = 9;
3123 let ResourceCycles = [1,5,1,2];
3124}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3125def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3126
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3127def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3128 let Latency = 11;
3129 let NumMicroOps = 11;
3130 let ResourceCycles = [2,9];
3131}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3132def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3133
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3134def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3135 let Latency = 12;
3136 let NumMicroOps = 1;
3137 let ResourceCycles = [1];
3138}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3139def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr",
3140 "VSQRTPSr",
3141 "VSQRTSSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3142
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3143def SKLWriteResGroup158 : SchedWriteRes<[SKLPort5,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3144 let Latency = 12;
3145 let NumMicroOps = 2;
3146 let ResourceCycles = [1,1];
3147}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3148def: InstRW<[SKLWriteResGroup158], (instregex "(V?)PCLMULQDQrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3149
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3150def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
3151 let Latency = 12;
3152 let NumMicroOps = 4;
3153 let ResourceCycles = [2,1,1];
3154}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3155def: InstRW<[SKLWriteResGroup159], (instregex "(V?)HADDPDrm",
3156 "(V?)HADDPSrm",
3157 "(V?)HSUBPDrm",
3158 "(V?)HSUBPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3159
3160def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
3161 let Latency = 12;
3162 let NumMicroOps = 4;
3163 let ResourceCycles = [1,1,1,1];
3164}
3165def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
3166
3167def SKLWriteResGroup161 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3168 let Latency = 13;
3169 let NumMicroOps = 1;
3170 let ResourceCycles = [1];
3171}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3172def: InstRW<[SKLWriteResGroup161], (instregex "SQRTPSr",
3173 "SQRTSSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3174
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3175def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3176 let Latency = 13;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3177 let NumMicroOps = 3;
3178 let ResourceCycles = [2,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3179}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3180def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI16m",
3181 "ADD_FI32m",
3182 "SUBR_FI16m",
3183 "SUBR_FI32m",
3184 "SUB_FI16m",
3185 "SUB_FI32m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3186
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3187def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3188 let Latency = 13;
3189 let NumMicroOps = 3;
3190 let ResourceCycles = [1,1,1];
3191}
3192def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
3193
3194def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3195 let Latency = 13;
3196 let NumMicroOps = 4;
3197 let ResourceCycles = [1,3];
3198}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3199def: InstRW<[SKLWriteResGroup164], (instregex "DPPSrri",
3200 "VDPPSYrri",
3201 "VDPPSrri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3202
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3203def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3204 let Latency = 13;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3205 let NumMicroOps = 4;
3206 let ResourceCycles = [2,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3207}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3208def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPDYrm",
3209 "VHADDPSYrm",
3210 "VHSUBPDYrm",
3211 "VHSUBPSYrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3212
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3213def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3214 let Latency = 14;
3215 let NumMicroOps = 1;
3216 let ResourceCycles = [1];
3217}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3218def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr",
3219 "DIVSDrr",
3220 "VDIVPDYrr",
3221 "VDIVPDrr",
3222 "VDIVSDrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3223
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3224def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> {
3225 let Latency = 14;
3226 let NumMicroOps = 3;
3227 let ResourceCycles = [1,2];
3228}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3229def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDPDm")>;
3230def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDPSm")>;
3231def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDSDm")>;
3232def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDSSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3233
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]3234def SKLWriteResGroup168_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {
3235 let Latency = 16;
3236 let NumMicroOps = 3;
3237 let ResourceCycles = [1,2];
3238}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3239def: InstRW<[SKLWriteResGroup168_2], (instregex "(V?)PMULLDrm")>;
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]3240
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3241def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3242 let Latency = 14;
3243 let NumMicroOps = 3;
3244 let ResourceCycles = [1,1,1];
3245}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3246def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI16m",
3247 "MUL_FI32m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3248
3249def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3250 let Latency = 14;
3251 let NumMicroOps = 10;
3252 let ResourceCycles = [2,4,1,3];
3253}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3254def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3255
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3256def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3257 let Latency = 15;
3258 let NumMicroOps = 1;
3259 let ResourceCycles = [1];
3260}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3261def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FPrST0",
3262 "DIVR_FST0r",
3263 "DIVR_FrST0")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3264
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3265def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3266 let Latency = 15;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3267 let NumMicroOps = 3;
3268 let ResourceCycles = [1,2];
3269}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3270def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm",
3271 "VROUNDYPSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3272
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]3273def SKLWriteResGroup172_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {
3274 let Latency = 17;
3275 let NumMicroOps = 3;
3276 let ResourceCycles = [1,2];
3277}
3278def: InstRW<[SKLWriteResGroup172_2], (instregex "VPMULLDYrm")>;
3279
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3280def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3281 let Latency = 15;
3282 let NumMicroOps = 4;
3283 let ResourceCycles = [1,1,2];
3284}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3285def: InstRW<[SKLWriteResGroup173], (instregex "(V?)DPPDrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3286
3287def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
3288 let Latency = 15;
3289 let NumMicroOps = 10;
3290 let ResourceCycles = [1,1,1,5,1,1];
3291}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3292def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3293
3294def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3295 let Latency = 16;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3296 let NumMicroOps = 2;
3297 let ResourceCycles = [1,1];
3298}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3299def: InstRW<[SKLWriteResGroup175], (instregex "(V?)DIVSSrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3300
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3301def SKLWriteResGroup176 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3302 let Latency = 16;
3303 let NumMicroOps = 4;
3304 let ResourceCycles = [3,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3305}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3306def: InstRW<[SKLWriteResGroup176], (instregex "(V?)PCMPISTRIrm",
3307 "(V?)PCMPISTRM128rm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3308
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3309def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
3310 let Latency = 16;
3311 let NumMicroOps = 14;
3312 let ResourceCycles = [1,1,1,4,2,5];
3313}
3314def: InstRW<[SKLWriteResGroup177], (instregex "CMPXCHG8B")>;
3315
3316def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3317 let Latency = 16;
3318 let NumMicroOps = 16;
3319 let ResourceCycles = [16];
3320}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3321def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3322
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3323def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3324 let Latency = 17;
3325 let NumMicroOps = 2;
3326 let ResourceCycles = [1,1];
3327}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3328def: InstRW<[SKLWriteResGroup179], (instregex "(V?)DIVPSrm",
3329 "VSQRTSSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3330
3331def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3332 let Latency = 17;
3333 let NumMicroOps = 15;
3334 let ResourceCycles = [2,1,2,4,2,4];
3335}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3336def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3337
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3338def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3339 let Latency = 18;
3340 let NumMicroOps = 1;
3341 let ResourceCycles = [1];
3342}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3343def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDYr",
3344 "VSQRTPDr",
3345 "VSQRTSDr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3346
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3347def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3348 let Latency = 18;
3349 let NumMicroOps = 2;
3350 let ResourceCycles = [1,1];
3351}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3352def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm",
3353 "VDIVPSYrm",
3354 "VSQRTPSm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3355
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3356def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3357 let Latency = 18;
3358 let NumMicroOps = 8;
3359 let ResourceCycles = [4,3,1];
3360}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3361def: InstRW<[SKLWriteResGroup183], (instregex "(V?)PCMPESTRIrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3362
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3363def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3364 let Latency = 18;
3365 let NumMicroOps = 8;
3366 let ResourceCycles = [1,1,1,5];
3367}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3368def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3369
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3370def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3371 let Latency = 18;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3372 let NumMicroOps = 11;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3373 let ResourceCycles = [2,1,1,4,1,2];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3374}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3375def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3376
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3377def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3378 let Latency = 19;
3379 let NumMicroOps = 2;
3380 let ResourceCycles = [1,1];
3381}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3382def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm",
3383 "SQRTPSm",
3384 "VDIVSDrm",
3385 "VSQRTPSYm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3386
3387def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3388 let Latency = 19;
3389 let NumMicroOps = 5;
3390 let ResourceCycles = [1,1,3];
3391}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3392def: InstRW<[SKLWriteResGroup187], (instregex "(V?)DPPSrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3393
3394def SKLWriteResGroup188 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {
3395 let Latency = 19;
3396 let NumMicroOps = 9;
3397 let ResourceCycles = [4,3,1,1];
3398}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3399def: InstRW<[SKLWriteResGroup188], (instregex "(V?)PCMPESTRM128rr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3400
3401def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3402 let Latency = 20;
3403 let NumMicroOps = 1;
3404 let ResourceCycles = [1];
3405}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3406def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FPrST0",
3407 "DIV_FST0r",
3408 "DIV_FrST0",
3409 "SQRTPDr",
3410 "SQRTSDr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3411
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3412def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3413 let Latency = 20;
3414 let NumMicroOps = 2;
3415 let ResourceCycles = [1,1];
3416}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3417def: InstRW<[SKLWriteResGroup190], (instregex "(V?)DIVPDrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3418
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3419def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3420 let Latency = 20;
3421 let NumMicroOps = 5;
3422 let ResourceCycles = [1,1,3];
3423}
3424def: InstRW<[SKLWriteResGroup191], (instregex "VDPPSYrmi")>;
3425
3426def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3427 let Latency = 20;
3428 let NumMicroOps = 8;
3429 let ResourceCycles = [1,1,1,1,1,1,2];
3430}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3431def: InstRW<[SKLWriteResGroup192], (instregex "INSB",
3432 "INSL",
3433 "INSW")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3434
3435def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3436 let Latency = 20;
3437 let NumMicroOps = 10;
3438 let ResourceCycles = [1,2,7];
3439}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3440def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3441
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3442def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3443 let Latency = 21;
3444 let NumMicroOps = 2;
3445 let ResourceCycles = [1,1];
3446}
3447def: InstRW<[SKLWriteResGroup195], (instregex "VDIVPDYrm")>;
3448
3449def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3450 let Latency = 22;
3451 let NumMicroOps = 2;
3452 let ResourceCycles = [1,1];
3453}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3454def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F32m",
3455 "DIV_F64m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3456
3457def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
3458 let Latency = 22;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3459 let NumMicroOps = 5;
3460 let ResourceCycles = [1,2,1,1];
3461}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3462def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
3463 VGATHERDPDrm,
3464 VGATHERQPDrm,
3465 VGATHERQPSrm,
3466 VPGATHERDDrm,
3467 VPGATHERDQrm,
3468 VPGATHERQDrm,
3469 VPGATHERQQrm)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3470
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3471def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
3472 let Latency = 25;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3473 let NumMicroOps = 5;
3474 let ResourceCycles = [1,2,1,1];
3475}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3476def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
3477 VGATHERQPDYrm,
3478 VGATHERQPSYrm,
3479 VPGATHERDDYrm,
3480 VPGATHERDQYrm,
3481 VPGATHERQDYrm,
3482 VPGATHERQQYrm,
3483 VGATHERDPDYrm)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3484
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3485def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3486 let Latency = 23;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3487 let NumMicroOps = 2;
3488 let ResourceCycles = [1,1];
3489}
3490def: InstRW<[SKLWriteResGroup197], (instregex "VSQRTSDm")>;
3491
3492def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3493 let Latency = 23;
3494 let NumMicroOps = 19;
3495 let ResourceCycles = [2,1,4,1,1,4,6];
3496}
3497def: InstRW<[SKLWriteResGroup198], (instregex "CMPXCHG16B")>;
3498
3499def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3500 let Latency = 24;
3501 let NumMicroOps = 2;
3502 let ResourceCycles = [1,1];
3503}
3504def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;
3505
3506def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
3507 let Latency = 24;
3508 let NumMicroOps = 9;
3509 let ResourceCycles = [4,3,1,1];
3510}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3511def: InstRW<[SKLWriteResGroup200], (instregex "(V?)PCMPESTRIrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3512
3513def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3514 let Latency = 25;
3515 let NumMicroOps = 2;
3516 let ResourceCycles = [1,1];
3517}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3518def: InstRW<[SKLWriteResGroup201], (instregex "SQRTSDm",
3519 "VSQRTPDYm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3520
3521def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3522 let Latency = 25;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3523 let NumMicroOps = 3;
3524 let ResourceCycles = [1,1,1];
3525}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3526def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m",
3527 "DIV_FI32m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3528
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3529def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {
3530 let Latency = 25;
3531 let NumMicroOps = 10;
3532 let ResourceCycles = [4,3,1,1,1];
3533}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3534def: InstRW<[SKLWriteResGroup203], (instregex "(V?)PCMPESTRM128rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3535
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3536def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3537 let Latency = 26;
3538 let NumMicroOps = 2;
3539 let ResourceCycles = [1,1];
3540}
3541def: InstRW<[SKLWriteResGroup205], (instregex "SQRTPDm")>;
3542
3543def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3544 let Latency = 27;
3545 let NumMicroOps = 2;
3546 let ResourceCycles = [1,1];
3547}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3548def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F32m",
3549 "DIVR_F64m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3550
3551def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
3552 let Latency = 28;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3553 let NumMicroOps = 8;
3554 let ResourceCycles = [2,4,1,1];
3555}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3556def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3557
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3558def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3559 let Latency = 30;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3560 let NumMicroOps = 3;
3561 let ResourceCycles = [1,1,1];
3562}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3563def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI16m",
3564 "DIVR_FI32m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3565
3566def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
3567 let Latency = 35;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3568 let NumMicroOps = 23;
3569 let ResourceCycles = [1,5,3,4,10];
3570}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3571def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
3572 "IN(8|16|32)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3573
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3574def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3575 let Latency = 35;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3576 let NumMicroOps = 23;
3577 let ResourceCycles = [1,5,2,1,4,10];
3578}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3579def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
3580 "OUT(8|16|32)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3581
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3582def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
3583 let Latency = 37;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3584 let NumMicroOps = 31;
3585 let ResourceCycles = [1,8,1,21];
3586}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3587def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3588
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3589def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
3590 let Latency = 40;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3591 let NumMicroOps = 18;
3592 let ResourceCycles = [1,1,2,3,1,1,1,8];
3593}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3594def: InstRW<[SKLWriteResGroup212], (instregex "VMCLEARm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3595
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3596def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
3597 let Latency = 41;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3598 let NumMicroOps = 39;
3599 let ResourceCycles = [1,10,1,1,26];
3600}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3601def: InstRW<[SKLWriteResGroup213], (instregex "XSAVE64")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3602
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3603def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3604 let Latency = 42;
3605 let NumMicroOps = 22;
3606 let ResourceCycles = [2,20];
3607}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3608def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3609
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3610def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
3611 let Latency = 42;
3612 let NumMicroOps = 40;
3613 let ResourceCycles = [1,11,1,1,26];
3614}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3615def: InstRW<[SKLWriteResGroup215], (instregex "^XSAVE$", "XSAVEC", "XSAVES")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3616
3617def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
3618 let Latency = 46;
3619 let NumMicroOps = 44;
3620 let ResourceCycles = [1,11,1,1,30];
3621}
3622def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
3623
3624def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
3625 let Latency = 62;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3626 let NumMicroOps = 64;
3627 let ResourceCycles = [2,8,5,10,39];
3628}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3629def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3630
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3631def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
3632 let Latency = 63;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3633 let NumMicroOps = 88;
3634 let ResourceCycles = [4,4,31,1,2,1,45];
3635}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3636def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3637
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3638def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
3639 let Latency = 63;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3640 let NumMicroOps = 90;
3641 let ResourceCycles = [4,2,33,1,2,1,47];
3642}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3643def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3644
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3645def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3646 let Latency = 75;
3647 let NumMicroOps = 15;
3648 let ResourceCycles = [6,3,6];
3649}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3650def: InstRW<[SKLWriteResGroup220], (instregex "FNINIT")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3651
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3652def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3653 let Latency = 76;
3654 let NumMicroOps = 32;
3655 let ResourceCycles = [7,2,8,3,1,11];
3656}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3657def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3658
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3659def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3660 let Latency = 102;
3661 let NumMicroOps = 66;
3662 let ResourceCycles = [4,2,4,8,14,34];
3663}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3664def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3665
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3666def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
3667 let Latency = 106;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3668 let NumMicroOps = 100;
3669 let ResourceCycles = [9,1,11,16,1,11,21,30];
3670}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3671def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3672
3673} // SchedModel