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gerrit-public.fairphone.software / toolchain / llvm-project / c976e8eef4a1ca6ab758f5aa414bf85e8e05ba52 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 8a6684cef0c7966dad9a70835c6ede3a49b6acae [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]27#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]28#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]29#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]31#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]32#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]33#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]35#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]38#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]39#include <limits>
40
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]41using namespace llvm;
42
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]43#define DEBUG_TYPE "x86-instr-info"
44
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]45#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]46#include "X86GenInstrInfo.inc"
47
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]48static cl::opt<bool>
49NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
51static cl::opt<bool>
52PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
55 cl::Hidden);
56static cl::opt<bool>
57ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]60
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]61enum {
62 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]63 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]64 TB_INDEX_0 = 0,
65 TB_INDEX_1 = 1,
66 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]67 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]68 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]69 TB_INDEX_MASK = 0xf,
70
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
74
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
79
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]82
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
86 TB_ALIGN_SHIFT = 8,
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]92};
93
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]94struct X86OpTblEntry {
95 uint16_t RegOp;
96 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]97 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]98};
99
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]100// Pin the vtable to this file.
101void X86InstrInfo::anchor() {}
102
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]103X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104 : X86GenInstrInfo(
Pavel Chupinbe9f1212014-09-22 13:11:35 +0000[diff] [blame]105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]107 Subtarget(STI), RI(STI) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]108
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]109 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]153 { X86::INC64r, X86::INC64m, 0 },
154 { X86::INC8r, X86::INC8m, 0 },
155 { X86::NEG16r, X86::NEG16m, 0 },
156 { X86::NEG32r, X86::NEG32m, 0 },
157 { X86::NEG64r, X86::NEG64m, 0 },
158 { X86::NEG8r, X86::NEG8m, 0 },
159 { X86::NOT16r, X86::NOT16m, 0 },
160 { X86::NOT32r, X86::NOT32m, 0 },
161 { X86::NOT64r, X86::NOT64m, 0 },
162 { X86::NOT8r, X86::NOT8m, 0 },
163 { X86::OR16ri, X86::OR16mi, 0 },
164 { X86::OR16ri8, X86::OR16mi8, 0 },
165 { X86::OR16rr, X86::OR16mr, 0 },
166 { X86::OR32ri, X86::OR32mi, 0 },
167 { X86::OR32ri8, X86::OR32mi8, 0 },
168 { X86::OR32rr, X86::OR32mr, 0 },
169 { X86::OR64ri32, X86::OR64mi32, 0 },
170 { X86::OR64ri8, X86::OR64mi8, 0 },
171 { X86::OR64rr, X86::OR64mr, 0 },
172 { X86::OR8ri, X86::OR8mi, 0 },
173 { X86::OR8rr, X86::OR8mr, 0 },
174 { X86::ROL16r1, X86::ROL16m1, 0 },
175 { X86::ROL16rCL, X86::ROL16mCL, 0 },
176 { X86::ROL16ri, X86::ROL16mi, 0 },
177 { X86::ROL32r1, X86::ROL32m1, 0 },
178 { X86::ROL32rCL, X86::ROL32mCL, 0 },
179 { X86::ROL32ri, X86::ROL32mi, 0 },
180 { X86::ROL64r1, X86::ROL64m1, 0 },
181 { X86::ROL64rCL, X86::ROL64mCL, 0 },
182 { X86::ROL64ri, X86::ROL64mi, 0 },
183 { X86::ROL8r1, X86::ROL8m1, 0 },
184 { X86::ROL8rCL, X86::ROL8mCL, 0 },
185 { X86::ROL8ri, X86::ROL8mi, 0 },
186 { X86::ROR16r1, X86::ROR16m1, 0 },
187 { X86::ROR16rCL, X86::ROR16mCL, 0 },
188 { X86::ROR16ri, X86::ROR16mi, 0 },
189 { X86::ROR32r1, X86::ROR32m1, 0 },
190 { X86::ROR32rCL, X86::ROR32mCL, 0 },
191 { X86::ROR32ri, X86::ROR32mi, 0 },
192 { X86::ROR64r1, X86::ROR64m1, 0 },
193 { X86::ROR64rCL, X86::ROR64mCL, 0 },
194 { X86::ROR64ri, X86::ROR64mi, 0 },
195 { X86::ROR8r1, X86::ROR8m1, 0 },
196 { X86::ROR8rCL, X86::ROR8mCL, 0 },
197 { X86::ROR8ri, X86::ROR8mi, 0 },
198 { X86::SAR16r1, X86::SAR16m1, 0 },
199 { X86::SAR16rCL, X86::SAR16mCL, 0 },
200 { X86::SAR16ri, X86::SAR16mi, 0 },
201 { X86::SAR32r1, X86::SAR32m1, 0 },
202 { X86::SAR32rCL, X86::SAR32mCL, 0 },
203 { X86::SAR32ri, X86::SAR32mi, 0 },
204 { X86::SAR64r1, X86::SAR64m1, 0 },
205 { X86::SAR64rCL, X86::SAR64mCL, 0 },
206 { X86::SAR64ri, X86::SAR64mi, 0 },
207 { X86::SAR8r1, X86::SAR8m1, 0 },
208 { X86::SAR8rCL, X86::SAR8mCL, 0 },
209 { X86::SAR8ri, X86::SAR8mi, 0 },
210 { X86::SBB32ri, X86::SBB32mi, 0 },
211 { X86::SBB32ri8, X86::SBB32mi8, 0 },
212 { X86::SBB32rr, X86::SBB32mr, 0 },
213 { X86::SBB64ri32, X86::SBB64mi32, 0 },
214 { X86::SBB64ri8, X86::SBB64mi8, 0 },
215 { X86::SBB64rr, X86::SBB64mr, 0 },
216 { X86::SHL16rCL, X86::SHL16mCL, 0 },
217 { X86::SHL16ri, X86::SHL16mi, 0 },
218 { X86::SHL32rCL, X86::SHL32mCL, 0 },
219 { X86::SHL32ri, X86::SHL32mi, 0 },
220 { X86::SHL64rCL, X86::SHL64mCL, 0 },
221 { X86::SHL64ri, X86::SHL64mi, 0 },
222 { X86::SHL8rCL, X86::SHL8mCL, 0 },
223 { X86::SHL8ri, X86::SHL8mi, 0 },
224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
230 { X86::SHR16r1, X86::SHR16m1, 0 },
231 { X86::SHR16rCL, X86::SHR16mCL, 0 },
232 { X86::SHR16ri, X86::SHR16mi, 0 },
233 { X86::SHR32r1, X86::SHR32m1, 0 },
234 { X86::SHR32rCL, X86::SHR32mCL, 0 },
235 { X86::SHR32ri, X86::SHR32mi, 0 },
236 { X86::SHR64r1, X86::SHR64m1, 0 },
237 { X86::SHR64rCL, X86::SHR64mCL, 0 },
238 { X86::SHR64ri, X86::SHR64mi, 0 },
239 { X86::SHR8r1, X86::SHR8m1, 0 },
240 { X86::SHR8rCL, X86::SHR8mCL, 0 },
241 { X86::SHR8ri, X86::SHR8mi, 0 },
242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
248 { X86::SUB16ri, X86::SUB16mi, 0 },
249 { X86::SUB16ri8, X86::SUB16mi8, 0 },
250 { X86::SUB16rr, X86::SUB16mr, 0 },
251 { X86::SUB32ri, X86::SUB32mi, 0 },
252 { X86::SUB32ri8, X86::SUB32mi8, 0 },
253 { X86::SUB32rr, X86::SUB32mr, 0 },
254 { X86::SUB64ri32, X86::SUB64mi32, 0 },
255 { X86::SUB64ri8, X86::SUB64mi8, 0 },
256 { X86::SUB64rr, X86::SUB64mr, 0 },
257 { X86::SUB8ri, X86::SUB8mi, 0 },
258 { X86::SUB8rr, X86::SUB8mr, 0 },
259 { X86::XOR16ri, X86::XOR16mi, 0 },
260 { X86::XOR16ri8, X86::XOR16mi8, 0 },
261 { X86::XOR16rr, X86::XOR16mr, 0 },
262 { X86::XOR32ri, X86::XOR32mi, 0 },
263 { X86::XOR32ri8, X86::XOR32mi8, 0 },
264 { X86::XOR32rr, X86::XOR32mr, 0 },
265 { X86::XOR64ri32, X86::XOR64mi32, 0 },
266 { X86::XOR64ri8, X86::XOR64mi8, 0 },
267 { X86::XOR64rr, X86::XOR64mr, 0 },
268 { X86::XOR8ri, X86::XOR8mi, 0 },
269 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]270 };
271
272 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]273 unsigned RegOp = OpTbl2Addr[i].RegOp;
274 unsigned MemOp = OpTbl2Addr[i].MemOp;
275 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277 RegOp, MemOp,
278 // Index 0, folded load and store, no alignment requirement.
279 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]280 }
281
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]282 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]336 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
337 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
356 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
357 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
358 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]359 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
360 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]361 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]362 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]363 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
367 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
368 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
369 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
370 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
371 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]372 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
373 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]374 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]375 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]376 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
378 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
379 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]380 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
381 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]382 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
383 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
384 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
385 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
386 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
387 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]389 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
390 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]391 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]392 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
393 // AVX-512 foldable instructions (256-bit versions)
394 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
398 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
399 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
400 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
401 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
402 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
403 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
404 // AVX-512 foldable instructions (128-bit versions)
405 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
406 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
407 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
408 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
409 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
410 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
411 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
412 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
413 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]414 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
415 // F16C foldable instructions
416 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
417 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]418 };
419
420 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]421 unsigned RegOp = OpTbl0[i].RegOp;
422 unsigned MemOp = OpTbl0[i].MemOp;
423 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]424 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
425 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]426 }
427
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]428 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]429 { X86::CMP16rr, X86::CMP16rm, 0 },
430 { X86::CMP32rr, X86::CMP32rm, 0 },
431 { X86::CMP64rr, X86::CMP64rm, 0 },
432 { X86::CMP8rr, X86::CMP8rm, 0 },
433 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
434 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
435 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
436 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
437 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
438 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
439 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
440 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
441 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
442 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
444 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
445 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
446 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
447 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
448 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
449 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
450 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]451 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
452 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]453 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
454 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]455 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]456 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]457 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]458 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]459 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]460 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]461 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
462 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
463 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
464 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
465 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
466 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
467 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
468 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]469 { X86::MOV16rr, X86::MOV16rm, 0 },
470 { X86::MOV32rr, X86::MOV32rm, 0 },
471 { X86::MOV64rr, X86::MOV64rm, 0 },
472 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
473 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
474 { X86::MOV8rr, X86::MOV8rm, 0 },
475 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
476 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]477 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
478 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
479 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
480 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]481 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
482 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
483 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
484 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
485 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
486 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
487 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
488 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
489 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
490 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]491 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
492 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
493 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
494 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
495 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
496 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]497 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
498 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
499 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]500 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
501 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
502 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
503 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
504 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
505 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
506 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
507 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
508 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
509 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
510 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
511 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
512 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
513 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
514 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
515 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
516 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]517 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
518 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
519 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]520 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]521 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
522 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]523 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
524 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]525 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
526 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
527 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
528 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
529 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]530 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]531 { X86::SQRTSDr, X86::SQRTSDm, 0 },
532 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
533 { X86::SQRTSSr, X86::SQRTSSm, 0 },
534 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
535 { X86::TEST16rr, X86::TEST16rm, 0 },
536 { X86::TEST32rr, X86::TEST32rm, 0 },
537 { X86::TEST64rr, X86::TEST64rm, 0 },
538 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]539 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]540 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
541 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]542 // AVX 128-bit versions of foldable instructions
543 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
544 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]545 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
546 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]547 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
548 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]549 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]550 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
551 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
552 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
553 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
554 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
555 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
556 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
557 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
558 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]559 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]560 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]561 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]562 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]563 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]564 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]565 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
566 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]567 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
568 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
569 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
570 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
571 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
572 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
573 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
574 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
575 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
576 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]577 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]578 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]579 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
580 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]581 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
582 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
583 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]584 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
585 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
586 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
587 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
588 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]589 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
590 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]591 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
592 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
593 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
594 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
595 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
596 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
597 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
598 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
599 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
600 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
601 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
602 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]603 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
604 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
605 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]606 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]607 { X86::VRCPPSr, X86::VRCPPSm, 0 },
608 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]609 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
610 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]611 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
612 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
613 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]614 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]615 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
616 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]617 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]618 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]619 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
620
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]621 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]622 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]623 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]624 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]625 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]626 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]627 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]628 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
629 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]630 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
631 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]632 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]633 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]634 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]635 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
636 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]637 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
638 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]639 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
640 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]641 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]642 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]643 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
644 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]645 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
646 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]647 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
648 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]649
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]650 // AVX2 foldable instructions
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]651 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
652 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
653 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
654 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
655 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
656 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]657
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]658 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]659 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
660 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]661 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
662 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
663 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
664 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
665 { X86::BLCI32rr, X86::BLCI32rm, 0 },
666 { X86::BLCI64rr, X86::BLCI64rm, 0 },
667 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
668 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
669 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
670 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
671 { X86::BLCS32rr, X86::BLCS32rm, 0 },
672 { X86::BLCS64rr, X86::BLCS64rm, 0 },
673 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
674 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]675 { X86::BLSI32rr, X86::BLSI32rm, 0 },
676 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]677 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
678 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]679 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
680 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
681 { X86::BLSR32rr, X86::BLSR32rm, 0 },
682 { X86::BLSR64rr, X86::BLSR64rm, 0 },
683 { X86::BZHI32rr, X86::BZHI32rm, 0 },
684 { X86::BZHI64rr, X86::BZHI64rm, 0 },
685 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
686 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
687 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
688 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
689 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
690 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]691 { X86::RORX32ri, X86::RORX32mi, 0 },
692 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]693 { X86::SARX32rr, X86::SARX32rm, 0 },
694 { X86::SARX64rr, X86::SARX64rm, 0 },
695 { X86::SHRX32rr, X86::SHRX32rm, 0 },
696 { X86::SHRX64rr, X86::SHRX64rm, 0 },
697 { X86::SHLX32rr, X86::SHLX32rm, 0 },
698 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]699 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
700 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]701 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
702 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
703 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]704 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
705 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]706
707 // AVX-512 foldable instructions
708 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
709 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]710 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
711 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]712 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
713 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]714 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
715 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]716 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
717 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]718 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
719 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]720 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
721 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]722 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
723 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]724 // AVX-512 foldable instructions (256-bit versions)
725 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
726 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
727 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
728 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
729 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
730 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
731 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
732 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
733 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
734 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]735 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
736 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]737 // AVX-512 foldable instructions (256-bit versions)
738 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
739 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
740 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
741 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
742 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
743 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
744 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
745 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
746 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
747 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]748 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]749 // F16C foldable instructions
750 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
751 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]752 // AES foldable instructions
753 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
754 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
755 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]756 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]757 };
758
759 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]760 unsigned RegOp = OpTbl1[i].RegOp;
761 unsigned MemOp = OpTbl1[i].MemOp;
762 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]763 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
764 RegOp, MemOp,
765 // Index 1, folded load
766 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]767 }
768
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]769 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]770 { X86::ADC32rr, X86::ADC32rm, 0 },
771 { X86::ADC64rr, X86::ADC64rm, 0 },
772 { X86::ADD16rr, X86::ADD16rm, 0 },
773 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
774 { X86::ADD32rr, X86::ADD32rm, 0 },
775 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
776 { X86::ADD64rr, X86::ADD64rm, 0 },
777 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
778 { X86::ADD8rr, X86::ADD8rm, 0 },
779 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
780 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
781 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]782 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]783 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]784 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]785 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
786 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
787 { X86::AND16rr, X86::AND16rm, 0 },
788 { X86::AND32rr, X86::AND32rm, 0 },
789 { X86::AND64rr, X86::AND64rm, 0 },
790 { X86::AND8rr, X86::AND8rm, 0 },
791 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
792 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
793 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
794 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]795 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
796 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
797 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
798 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]799 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
800 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
801 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
802 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
803 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
804 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
805 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
806 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
807 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
808 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
809 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
810 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
811 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
812 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
813 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
814 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
815 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
816 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
817 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
818 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
819 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
820 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
821 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
822 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
823 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
824 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
825 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
826 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
827 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
828 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
829 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
830 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
831 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
832 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
833 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
834 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
835 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
836 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
837 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
838 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
839 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
840 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
841 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
842 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
843 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
844 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
845 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
846 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
847 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
848 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
849 { X86::CMPSDrr, X86::CMPSDrm, 0 },
850 { X86::CMPSSrr, X86::CMPSSrm, 0 },
851 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
852 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
853 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]854 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]855 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]856 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
857 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
858 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]859 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
860 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
861 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
862 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
863 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
864 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
865 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
866 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
867 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
868 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
869 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
870 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
871 { X86::IMUL16rr, X86::IMUL16rm, 0 },
872 { X86::IMUL32rr, X86::IMUL32rm, 0 },
873 { X86::IMUL64rr, X86::IMUL64rm, 0 },
874 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
875 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]876 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
877 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
878 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
879 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
880 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
881 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]882 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]883 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]884 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]885 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]886 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]887 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]888 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]889 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]890 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]891 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]892 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]893 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]894 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]895 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
896 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
897 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]898 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]899 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]900 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]901 { X86::OR16rr, X86::OR16rm, 0 },
902 { X86::OR32rr, X86::OR32rm, 0 },
903 { X86::OR64rr, X86::OR64rm, 0 },
904 { X86::OR8rr, X86::OR8rm, 0 },
905 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
906 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
907 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
908 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]909 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]910 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
911 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
912 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
913 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
914 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
915 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]916 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
917 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]918 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]919 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]920 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
921 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
922 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
923 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]924 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]925 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]926 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]927 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
928 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]929 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]930 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
931 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
932 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]933 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]934 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]935 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
936 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]937 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]938 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]939 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]940 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]941 { X86::PINSRBrr, X86::PINSRBrm, 0 },
942 { X86::PINSRDrr, X86::PINSRDrm, 0 },
943 { X86::PINSRQrr, X86::PINSRQrm, 0 },
944 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]945 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]946 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
947 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
948 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
949 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
950 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]951 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
952 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
953 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
954 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
955 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
956 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
957 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
958 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]959 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]960 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]961 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
962 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
963 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
964 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
965 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
966 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
967 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]968 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
969 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
970 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
971 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]972 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
973 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
974 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
975 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
976 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
977 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
978 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
979 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
980 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
981 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]982 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]983 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
984 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]985 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
986 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]987 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
988 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
989 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
990 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
991 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
992 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
993 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
994 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
995 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
996 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
997 { X86::SBB32rr, X86::SBB32rm, 0 },
998 { X86::SBB64rr, X86::SBB64rm, 0 },
999 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1000 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1001 { X86::SUB16rr, X86::SUB16rm, 0 },
1002 { X86::SUB32rr, X86::SUB32rm, 0 },
1003 { X86::SUB64rr, X86::SUB64rm, 0 },
1004 { X86::SUB8rr, X86::SUB8rm, 0 },
1005 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1006 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1007 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1008 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1009 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1010 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1011 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1012 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1013 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1014 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1015 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1016 { X86::XOR16rr, X86::XOR16rm, 0 },
1017 { X86::XOR32rr, X86::XOR32rm, 0 },
1018 { X86::XOR64rr, X86::XOR64rm, 0 },
1019 { X86::XOR8rr, X86::XOR8rm, 0 },
1020 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1021 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
1022 // AVX 128-bit versions of foldable instructions
1023 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1024 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1025 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1026 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1027 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1028 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1029 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1030 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1031 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1032 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1033 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1034 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1035 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1036 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1037 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1038 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1039 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1040 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1041 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1042 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1043 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1044 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1045 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1046 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1047 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1048 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1049 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1050 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1051 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1052 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1053 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1054 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1055 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1056 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1057 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1058 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1059 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1060 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1061 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1062 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1063 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1064 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1065 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1066 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1067 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
1068 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
1069 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
1070 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
1071 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
1072 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
1073 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
1074 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1075 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1076 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1077 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1078 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1079 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1080 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1081 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1082 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1083 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1084 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1085 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1086 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1087 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1088 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1089 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1090 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1091 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1092 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1093 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1094 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1095 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1096 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1097 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1098 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1099 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1100 { X86::VORPDrr, X86::VORPDrm, 0 },
1101 { X86::VORPSrr, X86::VORPSrm, 0 },
1102 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1103 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1104 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1105 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1106 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1107 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1108 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1109 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1110 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1111 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1112 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1113 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1114 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1115 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1116 { X86::VPANDrr, X86::VPANDrm, 0 },
1117 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1118 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1119 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1120 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1121 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1122 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1123 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1124 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1125 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1126 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1127 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1128 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1129 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1130 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1131 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1132 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1133 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1134 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1135 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1136 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1137 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1138 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1139 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1140 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1141 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1142 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1143 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1144 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1145 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1146 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1147 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1148 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1149 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1150 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1151 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1152 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1153 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1154 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1155 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1156 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1157 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1158 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1159 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1160 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1161 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1162 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1163 { X86::VPORrr, X86::VPORrm, 0 },
1164 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1165 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1166 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1167 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1168 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1169 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1170 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1171 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1172 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1173 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1174 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1175 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1176 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1177 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1178 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1179 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1180 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1181 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1182 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1183 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1184 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1185 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1186 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1187 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1188 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1189 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1190 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1191 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1192 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1193 { X86::VPXORrr, X86::VPXORrm, 0 },
1194 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1195 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1196 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1197 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1198 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1199 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1200 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1201 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1202 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1203 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1204 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1205 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1206 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1207 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1208 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1209 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1210 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1211 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1212 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1213 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1214 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1215 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1216 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1217 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1218 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1219 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1220 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1221 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1222 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1223 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1224 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1225 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1226 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1227 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1228 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1229 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1230 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1231 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1232 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1233 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1234 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1235 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1236 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1237 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1238 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1239 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1240 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1241 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1242 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1243 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1244 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1245 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1246 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1247 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1248 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1249 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1250 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1251 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1252 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1253 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1254 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1255 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1256 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1257 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1258 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1259 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1260 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1261 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1262 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1263 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1264 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1265 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1266 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1267 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1268 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1269 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1270 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1271 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1272 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1273 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1274 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1275 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1276 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1277 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1278 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1279 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1280 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1281 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1282 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1283 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1284 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1285 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1286 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1287 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1288 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1289 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1290 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1291 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1292 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1293 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1294 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1295 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1296 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1297 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1298 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1299 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1300 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1301 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1302 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1303 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1304 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1305 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1306 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1307 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1308 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1309 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1310 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1311 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1312 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1313 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1314 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1315 { X86::VPORYrr, X86::VPORYrm, 0 },
1316 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1317 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1318 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1319 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1320 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1321 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1322 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1323 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1324 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1325 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1326 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1327 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1328 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1329 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1330 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1331 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1332 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1333 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1334 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1335 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1336 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1337 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1338 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1339 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1340 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1341 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1342 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1343 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1344 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1345 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1346 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1347 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1348 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1349 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1350 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1351 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1352 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1353 // FIXME: add AVX 256-bit foldable instructions
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1354
1355 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1356 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1357 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1358 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1359 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1360 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1361 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1362 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1363 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1364 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1365 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1366 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1367 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1368 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1369 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1370 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1371 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1372 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1373 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1374 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1375 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1376 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1377 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1378 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1379 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1380 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1381 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1382 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1383 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1384 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1385 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1386 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1387 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1388
1389 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1390 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1391 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1392 { X86::MULX32rr, X86::MULX32rm, 0 },
1393 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1394 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1395 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1396 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1397 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1398
1399 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1400 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1401 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1402 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1403 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1404 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1405 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1406 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1407 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1408 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1409 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1410 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1411 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1412 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1413 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1414 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1415 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1416 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1417 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1418 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1419 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1420 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1421 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1422 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1423 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1424 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1425 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1426 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1427 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1428 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1429 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1430 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1431 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1432 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1433 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1434 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1435 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1436 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1437 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1438 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1439
1440 // AVX-512{F,VL} foldable instructions
1441 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1442 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1443 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1444
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1445 // AVX-512{F,VL} foldable instructions
1446 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1447 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1448 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1449 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1450
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1451 // AES foldable instructions
1452 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1453 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1454 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1455 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1456 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
1457 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
1458 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
1459 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
1460
1461 // SHA foldable instructions
1462 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1463 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1464 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1465 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1466 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1467 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1468 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1469 };
1470
1471 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1472 unsigned RegOp = OpTbl2[i].RegOp;
1473 unsigned MemOp = OpTbl2[i].MemOp;
1474 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1475 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1476 RegOp, MemOp,
1477 // Index 2, folded load
1478 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1479 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1480
1481 static const X86OpTblEntry OpTbl3[] = {
1482 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1483 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1484 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1485 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1486 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1487 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1488 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1489
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1490 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1491 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1492 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1493 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1494 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1495 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1496 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1497 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1498 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1499 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1500 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1501 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1502
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1503 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1504 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1505 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1506 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1507 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1508 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1509
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1510 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1511 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1512 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1513 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1514 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1515 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1516 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1517 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1518 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1519 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1520 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1521 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1522
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1523 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1524 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1525 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1526 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1527 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1528 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1529
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1530 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1531 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1532 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1533 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1534 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1535 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1536 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1537 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1538 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1539 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1540 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1541 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1542
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1543 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1544 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1545 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1546 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1547 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1548 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1549
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1550 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1551 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1552 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1553 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1554 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1555 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1556 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1557 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1558 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1559 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1560 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1561 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1562
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1563 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1564 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1565 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1566 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1567 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1568 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1569 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1570 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1571 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1572 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1573 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1574 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1575
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1576 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1577 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1578 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1579 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1580 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1581 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1582 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1583 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1584 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1585 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1586 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1587 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1588
1589 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1590 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1591 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1592 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1593 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1594 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1595 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1596 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1597 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1598 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1599 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1600 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1601 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1602 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1603 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1604 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1605 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1606 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1607 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1608 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1609 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1610 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1611 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1612 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1613 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1614 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1615 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1616 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1617 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1618 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1619 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1620 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1621 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1622 // AVX-512 VPERMI instructions with 3 source operands.
1623 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1624 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1625 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1626 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1627 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1628 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1629 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1630 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1631 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1632 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1633 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1634 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1635 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1636 // AVX-512 arithmetic instructions
1637 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1638 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1639 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1640 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1641 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1642 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1643 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1644 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1645 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1646 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1647 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1648 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1649 // AVX-512{F,VL} arithmetic instructions 256-bit
1650 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1651 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1652 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1653 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1654 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1655 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1656 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1657 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1658 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1659 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1660 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1661 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1662 // AVX-512{F,VL} arithmetic instructions 128-bit
1663 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1664 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1665 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1666 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1667 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1668 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1669 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1670 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1671 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1672 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1673 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1674 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1675 };
1676
1677 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1678 unsigned RegOp = OpTbl3[i].RegOp;
1679 unsigned MemOp = OpTbl3[i].MemOp;
1680 unsigned Flags = OpTbl3[i].Flags;
1681 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1682 RegOp, MemOp,
1683 // Index 3, folded load
1684 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1685 }
1686
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1687 static const X86OpTblEntry OpTbl4[] = {
1688 // AVX-512 foldable instructions
1689 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1690 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1691 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1692 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1693 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1694 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1695 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1696 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1697 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1698 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1699 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1700 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1701 // AVX-512{F,VL} foldable instructions 256-bit
1702 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1703 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1704 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1705 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1706 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1707 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1708 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1709 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1710 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1711 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1712 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1713 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1714 // AVX-512{F,VL} foldable instructions 128-bit
1715 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1716 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1717 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1718 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1719 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1720 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1721 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1722 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1723 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1724 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1725 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1726 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1727 };
1728
1729 for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1730 unsigned RegOp = OpTbl4[i].RegOp;
1731 unsigned MemOp = OpTbl4[i].MemOp;
1732 unsigned Flags = OpTbl4[i].Flags;
1733 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1734 RegOp, MemOp,
1735 // Index 4, folded load
1736 Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1737 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1738}
1739
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1740void
1741X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1742 MemOp2RegOpTableType &M2RTable,
1743 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1744 if ((Flags & TB_NO_FORWARD) == 0) {
1745 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1746 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1747 }
1748 if ((Flags & TB_NO_REVERSE) == 0) {
1749 assert(!M2RTable.count(MemOp) &&
1750 "Duplicated entries in unfolding maps?");
1751 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1752 }
1753}
1754
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1755bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1756X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1757 unsigned &SrcReg, unsigned &DstReg,
1758 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1759 switch (MI.getOpcode()) {
1760 default: break;
1761 case X86::MOVSX16rr8:
1762 case X86::MOVZX16rr8:
1763 case X86::MOVSX32rr8:
1764 case X86::MOVZX32rr8:
1765 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]1766 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1767 // It's not always legal to reference the low 8-bit of the larger
1768 // register in 32-bit mode.
1769 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1770 case X86::MOVSX32rr16:
1771 case X86::MOVZX32rr16:
1772 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]1773 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1774 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1775 // Be conservative.
1776 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1777 SrcReg = MI.getOperand(1).getReg();
1778 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1779 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1780 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1781 case X86::MOVSX16rr8:
1782 case X86::MOVZX16rr8:
1783 case X86::MOVSX32rr8:
1784 case X86::MOVZX32rr8:
1785 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1786 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1787 break;
1788 case X86::MOVSX32rr16:
1789 case X86::MOVZX32rr16:
1790 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1791 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1792 break;
1793 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1794 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1795 break;
1796 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1797 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1798 }
1799 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1800 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1801}
1802
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1803/// isFrameOperand - Return true and the FrameIndex if the specified
1804/// operand and follow operands form a reference to the stack frame.
1805bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1806 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1807 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1808 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1809 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1810 MI->getOperand(Op+X86::AddrDisp).isImm() &&
1811 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1812 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1813 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1814 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1815 return true;
1816 }
1817 return false;
1818}
1819
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1820static bool isFrameLoadOpcode(int Opcode) {
1821 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]1822 default:
1823 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1824 case X86::MOV8rm:
1825 case X86::MOV16rm:
1826 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]1827 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]1828 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1829 case X86::MOVSSrm:
1830 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]1831 case X86::MOVAPSrm:
1832 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]1833 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1834 case X86::VMOVSSrm:
1835 case X86::VMOVSDrm:
1836 case X86::VMOVAPSrm:
1837 case X86::VMOVAPDrm:
1838 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]1839 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1840 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]1841 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1842 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]1843 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1844 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]1845 case X86::MMX_MOVD64rm:
1846 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1847 case X86::VMOVAPSZrm:
1848 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1849 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1850 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1851}
1852
1853static bool isFrameStoreOpcode(int Opcode) {
1854 switch (Opcode) {
1855 default: break;
1856 case X86::MOV8mr:
1857 case X86::MOV16mr:
1858 case X86::MOV32mr:
1859 case X86::MOV64mr:
1860 case X86::ST_FpP64m:
1861 case X86::MOVSSmr:
1862 case X86::MOVSDmr:
1863 case X86::MOVAPSmr:
1864 case X86::MOVAPDmr:
1865 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1866 case X86::VMOVSSmr:
1867 case X86::VMOVSDmr:
1868 case X86::VMOVAPSmr:
1869 case X86::VMOVAPDmr:
1870 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]1871 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1872 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]1873 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1874 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]1875 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1876 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1877 case X86::VMOVUPSZmr:
1878 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1879 case X86::MMX_MOVD64mr:
1880 case X86::MMX_MOVQ64mr:
1881 case X86::MMX_MOVNTQmr:
1882 return true;
1883 }
1884 return false;
1885}
1886
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1887unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1888 int &FrameIndex) const {
1889 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1890 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1891 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1892 return 0;
1893}
1894
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1895unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1896 int &FrameIndex) const {
1897 if (isFrameLoadOpcode(MI->getOpcode())) {
1898 unsigned Reg;
1899 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1900 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1901 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1902 const MachineMemOperand *Dummy;
1903 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1904 }
1905 return 0;
1906}
1907
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]1908unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1909 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1910 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1911 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1912 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]1913 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1914 return 0;
1915}
1916
1917unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1918 int &FrameIndex) const {
1919 if (isFrameStoreOpcode(MI->getOpcode())) {
1920 unsigned Reg;
1921 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1922 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1923 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1924 const MachineMemOperand *Dummy;
1925 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1926 }
1927 return 0;
1928}
1929
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1930/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1931/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1932static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]1933 // Don't waste compile time scanning use-def chains of physregs.
1934 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1935 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1936 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]1937 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1938 E = MRI.def_instr_end(); I != E; ++I) {
1939 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1940 if (DefMI->getOpcode() != X86::MOVPC32r)
1941 return false;
1942 assert(!isPICBase && "More than one PIC base?");
1943 isPICBase = true;
1944 }
1945 return isPICBase;
1946}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]1947
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]1948bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]1949X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1950 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1951 switch (MI->getOpcode()) {
1952 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1953 case X86::MOV8rm:
1954 case X86::MOV16rm:
1955 case X86::MOV32rm:
1956 case X86::MOV64rm:
1957 case X86::LD_Fp64m:
1958 case X86::MOVSSrm:
1959 case X86::MOVSDrm:
1960 case X86::MOVAPSrm:
1961 case X86::MOVUPSrm:
1962 case X86::MOVAPDrm:
1963 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1964 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1965 case X86::VMOVSSrm:
1966 case X86::VMOVSDrm:
1967 case X86::VMOVAPSrm:
1968 case X86::VMOVUPSrm:
1969 case X86::VMOVAPDrm:
1970 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1971 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1972 case X86::VMOVAPSYrm:
1973 case X86::VMOVUPSYrm:
1974 case X86::VMOVAPDYrm:
1975 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]1976 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1977 case X86::MMX_MOVD64rm:
1978 case X86::MMX_MOVQ64rm:
1979 case X86::FsVMOVAPSrm:
1980 case X86::FsVMOVAPDrm:
1981 case X86::FsMOVAPSrm:
1982 case X86::FsMOVAPDrm: {
1983 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1984 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1985 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1986 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1987 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1988 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1989 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1990 if (BaseReg == 0 || BaseReg == X86::RIP)
1991 return true;
1992 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1993 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1994 return false;
1995 const MachineFunction &MF = *MI->getParent()->getParent();
1996 const MachineRegisterInfo &MRI = MF.getRegInfo();
1997 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]1998 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1999 return false;
2000 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2001
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2002 case X86::LEA32r:
2003 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2004 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2005 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2006 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2007 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2008 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2009 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2010 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2011 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2012 if (BaseReg == 0)
2013 return true;
2014 // Allow re-materialization of lea PICBase + x.
2015 const MachineFunction &MF = *MI->getParent()->getParent();
2016 const MachineRegisterInfo &MRI = MF.getRegInfo();
2017 return regIsPICBase(BaseReg, MRI);
2018 }
2019 return false;
2020 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2021 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2022
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2023 // All other instructions marked M_REMATERIALIZABLE are always trivially
2024 // rematerializable.
2025 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2026}
2027
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2028bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2029 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2030 MachineBasicBlock::iterator E = MBB.end();
2031
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2032 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2033 // safety after visiting 4 instructions in each direction, we will assume
2034 // it's not safe.
2035 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2036 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2037 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2038 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2039 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2040 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2041 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2042 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2043 continue;
2044 if (MO.getReg() == X86::EFLAGS) {
2045 if (MO.isUse())
2046 return false;
2047 SeenDef = true;
2048 }
2049 }
2050
2051 if (SeenDef)
2052 // This instruction defines EFLAGS, no need to look any further.
2053 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2054 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2055 // Skip over DBG_VALUE.
2056 while (Iter != E && Iter->isDebugValue())
2057 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2058 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2059
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2060 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2061 // live in.
2062 if (Iter == E) {
2063 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2064 SE = MBB.succ_end(); SI != SE; ++SI)
2065 if ((*SI)->isLiveIn(X86::EFLAGS))
2066 return false;
2067 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2068 }
2069
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2070 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2071 Iter = I;
2072 for (unsigned i = 0; i < 4; ++i) {
2073 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2074 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2075 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2076 return !MBB.isLiveIn(X86::EFLAGS);
2077
2078 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2079 // Skip over DBG_VALUE.
2080 while (Iter != B && Iter->isDebugValue())
2081 --Iter;
2082
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2083 bool SawKill = false;
2084 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2085 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2086 // A register mask may clobber EFLAGS, but we should still look for a
2087 // live EFLAGS def.
2088 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2089 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2090 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2091 if (MO.isDef()) return MO.isDead();
2092 if (MO.isKill()) SawKill = true;
2093 }
2094 }
2095
2096 if (SawKill)
2097 // This instruction kills EFLAGS and doesn't redefine it, so
2098 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2099 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2100 }
2101
2102 // Conservative answer.
2103 return false;
2104}
2105
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2106void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2107 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2108 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]2109 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2110 const TargetRegisterInfo &TRI) const {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2111 // MOV32r0 is implemented with a xor which clobbers condition code.
2112 // Re-materialize it as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2113 unsigned Opc = Orig->getOpcode();
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2114 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2115 DebugLoc DL = Orig->getDebugLoc();
2116 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2117 .addImm(0);
2118 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2119 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2120 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2121 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2122
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2123 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2124 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2125}
2126
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2127/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2128/// is not marked dead.
2129static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2130 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2131 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2132 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2133 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2134 return true;
2135 }
2136 }
2137 return false;
2138}
2139
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2140/// getTruncatedShiftCount - check whether the shift count for a machine operand
2141/// is non-zero.
2142inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2143 unsigned ShiftAmtOperandIdx) {
2144 // The shift count is six bits with the REX.W prefix and five bits without.
2145 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2146 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2147 return Imm & ShiftCountMask;
2148}
2149
2150/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2151/// can be represented by a LEA instruction.
2152inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2153 // Left shift instructions can be transformed into load-effective-address
2154 // instructions if we can encode them appropriately.
2155 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2156 // The SIB.scale field is two bits wide which means that we can encode any
2157 // shift amount less than 4.
2158 return ShAmt < 4 && ShAmt > 0;
2159}
2160
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2161bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2162 unsigned Opc, bool AllowSP,
2163 unsigned &NewSrc, bool &isKill, bool &isUndef,
2164 MachineOperand &ImplicitOp) const {
2165 MachineFunction &MF = *MI->getParent()->getParent();
2166 const TargetRegisterClass *RC;
2167 if (AllowSP) {
2168 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2169 } else {
2170 RC = Opc != X86::LEA32r ?
2171 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2172 }
2173 unsigned SrcReg = Src.getReg();
2174
2175 // For both LEA64 and LEA32 the register already has essentially the right
2176 // type (32-bit or 64-bit) we may just need to forbid SP.
2177 if (Opc != X86::LEA64_32r) {
2178 NewSrc = SrcReg;
2179 isKill = Src.isKill();
2180 isUndef = Src.isUndef();
2181
2182 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2183 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2184 return false;
2185
2186 return true;
2187 }
2188
2189 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2190 // another we need to add 64-bit registers to the final MI.
2191 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2192 ImplicitOp = Src;
2193 ImplicitOp.setImplicit();
2194
2195 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2196 MachineBasicBlock::LivenessQueryResult LQR =
2197 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2198
2199 switch (LQR) {
2200 case MachineBasicBlock::LQR_Unknown:
2201 // We can't give sane liveness flags to the instruction, abandon LEA
2202 // formation.
2203 return false;
2204 case MachineBasicBlock::LQR_Live:
2205 isKill = MI->killsRegister(SrcReg);
2206 isUndef = false;
2207 break;
2208 default:
2209 // The physreg itself is dead, so we have to use it as an <undef>.
2210 isKill = false;
2211 isUndef = true;
2212 break;
2213 }
2214 } else {
2215 // Virtual register of the wrong class, we have to create a temporary 64-bit
2216 // vreg to feed into the LEA.
2217 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2218 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2219 get(TargetOpcode::COPY))
2220 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2221 .addOperand(Src);
2222
2223 // Which is obviously going to be dead after we're done with it.
2224 isKill = true;
2225 isUndef = false;
2226 }
2227
2228 // We've set all the parameters without issue.
2229 return true;
2230}
2231
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2232/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2233/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2234/// to a 32-bit superregister and then truncating back down to a 16-bit
2235/// subregister.
2236MachineInstr *
2237X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2238 MachineFunction::iterator &MFI,
2239 MachineBasicBlock::iterator &MBBI,
2240 LiveVariables *LV) const {
2241 MachineInstr *MI = MBBI;
2242 unsigned Dest = MI->getOperand(0).getReg();
2243 unsigned Src = MI->getOperand(1).getReg();
2244 bool isDead = MI->getOperand(0).isDead();
2245 bool isKill = MI->getOperand(1).isKill();
2246
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2247 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2248 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2249 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2250 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2251 Opc = X86::LEA64_32r;
2252 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2253 } else {
2254 Opc = X86::LEA32r;
2255 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2256 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2257
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2258 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2259 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2260 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2261 // movw (%rbp,%rcx,2), %dx
2262 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2263 // But testing has shown this *does* help performance in 64-bit mode (at
2264 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2265 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2266 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2267 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2268 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2269 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2270
2271 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2272 get(Opc), leaOutReg);
2273 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2274 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2275 case X86::SHL16ri: {
2276 unsigned ShAmt = MI->getOperand(2).getImm();
2277 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2278 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2279 break;
2280 }
2281 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2282 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2283 break;
2284 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2285 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2286 break;
2287 case X86::ADD16ri:
2288 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2289 case X86::ADD16ri_DB:
2290 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2291 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2292 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2293 case X86::ADD16rr:
2294 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2295 unsigned Src2 = MI->getOperand(2).getReg();
2296 bool isKill2 = MI->getOperand(2).isKill();
2297 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2298 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2299 if (Src == Src2) {
2300 // ADD16rr %reg1028<kill>, %reg1028
2301 // just a single insert_subreg.
2302 addRegReg(MIB, leaInReg, true, leaInReg, false);
2303 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2304 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2305 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2306 else
2307 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2308 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2309 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2310 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2311 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2312 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2313 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2314 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2315 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2316 }
2317 if (LV && isKill2 && InsMI2)
2318 LV->replaceKillInstruction(Src2, MI, InsMI2);
2319 break;
2320 }
2321 }
2322
2323 MachineInstr *NewMI = MIB;
2324 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2325 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2326 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2327 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2328
2329 if (LV) {
2330 // Update live variables
2331 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2332 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2333 if (isKill)
2334 LV->replaceKillInstruction(Src, MI, InsMI);
2335 if (isDead)
2336 LV->replaceKillInstruction(Dest, MI, ExtMI);
2337 }
2338
2339 return ExtMI;
2340}
2341
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2342/// convertToThreeAddress - This method must be implemented by targets that
2343/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2344/// may be able to convert a two-address instruction into a true
2345/// three-address instruction on demand. This allows the X86 target (for
2346/// example) to convert ADD and SHL instructions into LEA instructions if they
2347/// would require register copies due to two-addressness.
2348///
2349/// This method returns a null pointer if the transformation cannot be
2350/// performed, otherwise it returns the new instruction.
2351///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2352MachineInstr *
2353X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2354 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2355 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2356 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2357
2358 // The following opcodes also sets the condition code register(s). Only
2359 // convert them to equivalent lea if the condition code register def's
2360 // are dead!
2361 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2362 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2363
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2364 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2365 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2366 const MachineOperand &Dest = MI->getOperand(0);
2367 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2368
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2369 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2370 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2371 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2372 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2373 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2374 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2375
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2376 unsigned MIOpc = MI->getOpcode();
2377 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2378 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2379 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2380 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2381 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2382 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2383
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2384 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2385 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2386 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2387 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2388 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2389
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2390 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2391 .addOperand(Dest)
2392 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2393 break;
2394 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2395 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2396 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2397 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2398 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2399
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2400 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2401
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2402 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2403 bool isKill, isUndef;
2404 unsigned SrcReg;
2405 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2406 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2407 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2408 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2409
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2410 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2411 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2412 .addReg(0).addImm(1 << ShAmt)
2413 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2414 .addImm(0).addReg(0);
2415 if (ImplicitOp.getReg() != 0)
2416 MIB.addOperand(ImplicitOp);
2417 NewMI = MIB;
2418
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2419 break;
2420 }
2421 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2422 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2423 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2424 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2425
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2426 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2427 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2428 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2429 .addOperand(Dest)
2430 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2431 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2432 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2433 case X86::INC64r:
2434 case X86::INC32r: {
2435 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2436 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2437 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2438 bool isKill, isUndef;
2439 unsigned SrcReg;
2440 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2441 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2442 SrcReg, isKill, isUndef, ImplicitOp))
2443 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2444
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2445 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2446 .addOperand(Dest)
2447 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2448 if (ImplicitOp.getReg() != 0)
2449 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2450
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2451 NewMI = addOffset(MIB, 1);
2452 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2453 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2454 case X86::INC16r:
2455 if (DisableLEA16)
2456 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2457 : nullptr;
2458 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2459 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2460 .addOperand(Dest).addOperand(Src), 1);
2461 break;
2462 case X86::DEC64r:
2463 case X86::DEC32r: {
2464 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2465 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2466 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2467
2468 bool isKill, isUndef;
2469 unsigned SrcReg;
2470 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2471 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2472 SrcReg, isKill, isUndef, ImplicitOp))
2473 return nullptr;
2474
2475 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2476 .addOperand(Dest)
2477 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2478 if (ImplicitOp.getReg() != 0)
2479 MIB.addOperand(ImplicitOp);
2480
2481 NewMI = addOffset(MIB, -1);
2482
2483 break;
2484 }
2485 case X86::DEC16r:
2486 if (DisableLEA16)
2487 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2488 : nullptr;
2489 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2490 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2491 .addOperand(Dest).addOperand(Src), -1);
2492 break;
2493 case X86::ADD64rr:
2494 case X86::ADD64rr_DB:
2495 case X86::ADD32rr:
2496 case X86::ADD32rr_DB: {
2497 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2498 unsigned Opc;
2499 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2500 Opc = X86::LEA64r;
2501 else
2502 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2503
2504 bool isKill, isUndef;
2505 unsigned SrcReg;
2506 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2507 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2508 SrcReg, isKill, isUndef, ImplicitOp))
2509 return nullptr;
2510
2511 const MachineOperand &Src2 = MI->getOperand(2);
2512 bool isKill2, isUndef2;
2513 unsigned SrcReg2;
2514 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2515 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2516 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2517 return nullptr;
2518
2519 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2520 .addOperand(Dest);
2521 if (ImplicitOp.getReg() != 0)
2522 MIB.addOperand(ImplicitOp);
2523 if (ImplicitOp2.getReg() != 0)
2524 MIB.addOperand(ImplicitOp2);
2525
2526 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2527
2528 // Preserve undefness of the operands.
2529 NewMI->getOperand(1).setIsUndef(isUndef);
2530 NewMI->getOperand(3).setIsUndef(isUndef2);
2531
2532 if (LV && Src2.isKill())
2533 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2534 break;
2535 }
2536 case X86::ADD16rr:
2537 case X86::ADD16rr_DB: {
2538 if (DisableLEA16)
2539 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2540 : nullptr;
2541 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2542 unsigned Src2 = MI->getOperand(2).getReg();
2543 bool isKill2 = MI->getOperand(2).isKill();
2544 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2545 .addOperand(Dest),
2546 Src.getReg(), Src.isKill(), Src2, isKill2);
2547
2548 // Preserve undefness of the operands.
2549 bool isUndef = MI->getOperand(1).isUndef();
2550 bool isUndef2 = MI->getOperand(2).isUndef();
2551 NewMI->getOperand(1).setIsUndef(isUndef);
2552 NewMI->getOperand(3).setIsUndef(isUndef2);
2553
2554 if (LV && isKill2)
2555 LV->replaceKillInstruction(Src2, MI, NewMI);
2556 break;
2557 }
2558 case X86::ADD64ri32:
2559 case X86::ADD64ri8:
2560 case X86::ADD64ri32_DB:
2561 case X86::ADD64ri8_DB:
2562 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2563 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2564 .addOperand(Dest).addOperand(Src),
2565 MI->getOperand(2).getImm());
2566 break;
2567 case X86::ADD32ri:
2568 case X86::ADD32ri8:
2569 case X86::ADD32ri_DB:
2570 case X86::ADD32ri8_DB: {
2571 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2572 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2573
2574 bool isKill, isUndef;
2575 unsigned SrcReg;
2576 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2577 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2578 SrcReg, isKill, isUndef, ImplicitOp))
2579 return nullptr;
2580
2581 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2582 .addOperand(Dest)
2583 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2584 if (ImplicitOp.getReg() != 0)
2585 MIB.addOperand(ImplicitOp);
2586
2587 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2588 break;
2589 }
2590 case X86::ADD16ri:
2591 case X86::ADD16ri8:
2592 case X86::ADD16ri_DB:
2593 case X86::ADD16ri8_DB:
2594 if (DisableLEA16)
2595 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2596 : nullptr;
2597 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2598 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2599 .addOperand(Dest).addOperand(Src),
2600 MI->getOperand(2).getImm());
2601 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2602 }
2603
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2604 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2605
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2606 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2607 if (Src.isKill())
2608 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2609 if (Dest.isDead())
2610 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2611 }
2612
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2613 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2614 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2615}
2616
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2617/// commuteInstruction - We have a few instructions that must be hacked on to
2618/// commute them.
2619///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2620MachineInstr *
2621X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2622 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2623 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2624 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2625 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2626 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2627 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2628 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2629 unsigned Opc;
2630 unsigned Size;
2631 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2632 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2633 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2634 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2635 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2636 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2637 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2638 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2639 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2640 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2641 if (NewMI) {
2642 MachineFunction &MF = *MI->getParent()->getParent();
2643 MI = MF.CloneMachineInstr(MI);
2644 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2645 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2646 MI->setDesc(get(Opc));
2647 MI->getOperand(3).setImm(Size-Amt);
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2648 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2649 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2650 case X86::BLENDPDrri:
2651 case X86::BLENDPSrri:
2652 case X86::PBLENDWrri:
2653 case X86::VBLENDPDrri:
2654 case X86::VBLENDPSrri:
2655 case X86::VBLENDPDYrri:
2656 case X86::VBLENDPSYrri:
2657 case X86::VPBLENDDrri:
2658 case X86::VPBLENDWrri:
2659 case X86::VPBLENDDYrri:
2660 case X86::VPBLENDWYrri:{
2661 unsigned Mask;
2662 switch (MI->getOpcode()) {
2663 default: llvm_unreachable("Unreachable!");
2664 case X86::BLENDPDrri: Mask = 0x03; break;
2665 case X86::BLENDPSrri: Mask = 0x0F; break;
2666 case X86::PBLENDWrri: Mask = 0xFF; break;
2667 case X86::VBLENDPDrri: Mask = 0x03; break;
2668 case X86::VBLENDPSrri: Mask = 0x0F; break;
2669 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2670 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2671 case X86::VPBLENDDrri: Mask = 0x0F; break;
2672 case X86::VPBLENDWrri: Mask = 0xFF; break;
2673 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2674 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2675 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]2676 // Only the least significant bits of Imm are used.
2677 unsigned Imm = MI->getOperand(3).getImm() & Mask;
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2678 if (NewMI) {
2679 MachineFunction &MF = *MI->getParent()->getParent();
2680 MI = MF.CloneMachineInstr(MI);
2681 NewMI = false;
2682 }
2683 MI->getOperand(3).setImm(Mask ^ Imm);
2684 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2685 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2686 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2687 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2688 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2689 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2690 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2691 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2692 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2693 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2694 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2695 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2696 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2697 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2698 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2699 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2700 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2701 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2702 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2703 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2704 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2705 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2706 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2707 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2708 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2709 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2710 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2711 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2712 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2713 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2714 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2715 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2716 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2717 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2718 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2719 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2720 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2721 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2722 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2723 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2724 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2725 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2726 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2727 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2728 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2729 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2730 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2731 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2732 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2733 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2734 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2735 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2736 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2737 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2738 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2739 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2740 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2741 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2742 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2743 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2744 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2745 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2746 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2747 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2748 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2749 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2750 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2751 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2752 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2753 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2754 if (NewMI) {
2755 MachineFunction &MF = *MI->getParent()->getParent();
2756 MI = MF.CloneMachineInstr(MI);
2757 NewMI = false;
2758 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]2759 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2760 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2761 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2762 default:
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2763 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2764 }
2765}
2766
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2767bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2768 unsigned &SrcOpIdx2) const {
2769 switch (MI->getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2770 case X86::BLENDPDrri:
2771 case X86::BLENDPSrri:
2772 case X86::PBLENDWrri:
2773 case X86::VBLENDPDrri:
2774 case X86::VBLENDPSrri:
2775 case X86::VBLENDPDYrri:
2776 case X86::VBLENDPSYrri:
2777 case X86::VPBLENDDrri:
2778 case X86::VPBLENDDYrri:
2779 case X86::VPBLENDWrri:
2780 case X86::VPBLENDWYrri:
2781 SrcOpIdx1 = 1;
2782 SrcOpIdx2 = 2;
2783 return true;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2784 case X86::VFMADDPDr231r:
2785 case X86::VFMADDPSr231r:
2786 case X86::VFMADDSDr231r:
2787 case X86::VFMADDSSr231r:
2788 case X86::VFMSUBPDr231r:
2789 case X86::VFMSUBPSr231r:
2790 case X86::VFMSUBSDr231r:
2791 case X86::VFMSUBSSr231r:
2792 case X86::VFNMADDPDr231r:
2793 case X86::VFNMADDPSr231r:
2794 case X86::VFNMADDSDr231r:
2795 case X86::VFNMADDSSr231r:
2796 case X86::VFNMSUBPDr231r:
2797 case X86::VFNMSUBPSr231r:
2798 case X86::VFNMSUBSDr231r:
2799 case X86::VFNMSUBSSr231r:
2800 case X86::VFMADDPDr231rY:
2801 case X86::VFMADDPSr231rY:
2802 case X86::VFMSUBPDr231rY:
2803 case X86::VFMSUBPSr231rY:
2804 case X86::VFNMADDPDr231rY:
2805 case X86::VFNMADDPSr231rY:
2806 case X86::VFNMSUBPDr231rY:
2807 case X86::VFNMSUBPSr231rY:
2808 SrcOpIdx1 = 2;
2809 SrcOpIdx2 = 3;
2810 return true;
2811 default:
2812 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2813 }
2814}
2815
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2816static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2817 switch (BrOpc) {
2818 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]2819 case X86::JE_1: return X86::COND_E;
2820 case X86::JNE_1: return X86::COND_NE;
2821 case X86::JL_1: return X86::COND_L;
2822 case X86::JLE_1: return X86::COND_LE;
2823 case X86::JG_1: return X86::COND_G;
2824 case X86::JGE_1: return X86::COND_GE;
2825 case X86::JB_1: return X86::COND_B;
2826 case X86::JBE_1: return X86::COND_BE;
2827 case X86::JA_1: return X86::COND_A;
2828 case X86::JAE_1: return X86::COND_AE;
2829 case X86::JS_1: return X86::COND_S;
2830 case X86::JNS_1: return X86::COND_NS;
2831 case X86::JP_1: return X86::COND_P;
2832 case X86::JNP_1: return X86::COND_NP;
2833 case X86::JO_1: return X86::COND_O;
2834 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2835 }
2836}
2837
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2838/// getCondFromSETOpc - return condition code of a SET opcode.
2839static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2840 switch (Opc) {
2841 default: return X86::COND_INVALID;
2842 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2843 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2844 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2845 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2846 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2847 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2848 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2849 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2850 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2851 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2852 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2853 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2854 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2855 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2856 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2857 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2858 }
2859}
2860
2861/// getCondFromCmovOpc - return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]2862X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2863 switch (Opc) {
2864 default: return X86::COND_INVALID;
2865 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2866 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2867 return X86::COND_A;
2868 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2869 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2870 return X86::COND_AE;
2871 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2872 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2873 return X86::COND_B;
2874 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2875 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2876 return X86::COND_BE;
2877 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2878 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2879 return X86::COND_E;
2880 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2881 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2882 return X86::COND_G;
2883 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2884 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2885 return X86::COND_GE;
2886 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2887 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2888 return X86::COND_L;
2889 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2890 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2891 return X86::COND_LE;
2892 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2893 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2894 return X86::COND_NE;
2895 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2896 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2897 return X86::COND_NO;
2898 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2899 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2900 return X86::COND_NP;
2901 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2902 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2903 return X86::COND_NS;
2904 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2905 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2906 return X86::COND_O;
2907 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2908 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2909 return X86::COND_P;
2910 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2911 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2912 return X86::COND_S;
2913 }
2914}
2915
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2916unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2917 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2918 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]2919 case X86::COND_E: return X86::JE_1;
2920 case X86::COND_NE: return X86::JNE_1;
2921 case X86::COND_L: return X86::JL_1;
2922 case X86::COND_LE: return X86::JLE_1;
2923 case X86::COND_G: return X86::JG_1;
2924 case X86::COND_GE: return X86::JGE_1;
2925 case X86::COND_B: return X86::JB_1;
2926 case X86::COND_BE: return X86::JBE_1;
2927 case X86::COND_A: return X86::JA_1;
2928 case X86::COND_AE: return X86::JAE_1;
2929 case X86::COND_S: return X86::JS_1;
2930 case X86::COND_NS: return X86::JNS_1;
2931 case X86::COND_P: return X86::JP_1;
2932 case X86::COND_NP: return X86::JNP_1;
2933 case X86::COND_O: return X86::JO_1;
2934 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2935 }
2936}
2937
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2938/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2939/// e.g. turning COND_E to COND_NE.
2940X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2941 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2942 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2943 case X86::COND_E: return X86::COND_NE;
2944 case X86::COND_NE: return X86::COND_E;
2945 case X86::COND_L: return X86::COND_GE;
2946 case X86::COND_LE: return X86::COND_G;
2947 case X86::COND_G: return X86::COND_LE;
2948 case X86::COND_GE: return X86::COND_L;
2949 case X86::COND_B: return X86::COND_AE;
2950 case X86::COND_BE: return X86::COND_A;
2951 case X86::COND_A: return X86::COND_BE;
2952 case X86::COND_AE: return X86::COND_B;
2953 case X86::COND_S: return X86::COND_NS;
2954 case X86::COND_NS: return X86::COND_S;
2955 case X86::COND_P: return X86::COND_NP;
2956 case X86::COND_NP: return X86::COND_P;
2957 case X86::COND_O: return X86::COND_NO;
2958 case X86::COND_NO: return X86::COND_O;
2959 }
2960}
2961
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2962/// getSwappedCondition - assume the flags are set by MI(a,b), return
2963/// the condition code if we modify the instructions such that flags are
2964/// set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]2965static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2966 switch (CC) {
2967 default: return X86::COND_INVALID;
2968 case X86::COND_E: return X86::COND_E;
2969 case X86::COND_NE: return X86::COND_NE;
2970 case X86::COND_L: return X86::COND_G;
2971 case X86::COND_LE: return X86::COND_GE;
2972 case X86::COND_G: return X86::COND_L;
2973 case X86::COND_GE: return X86::COND_LE;
2974 case X86::COND_B: return X86::COND_A;
2975 case X86::COND_BE: return X86::COND_AE;
2976 case X86::COND_A: return X86::COND_B;
2977 case X86::COND_AE: return X86::COND_BE;
2978 }
2979}
2980
2981/// getSETFromCond - Return a set opcode for the given condition and
2982/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]2983unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2984 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2985 { X86::SETAr, X86::SETAm },
2986 { X86::SETAEr, X86::SETAEm },
2987 { X86::SETBr, X86::SETBm },
2988 { X86::SETBEr, X86::SETBEm },
2989 { X86::SETEr, X86::SETEm },
2990 { X86::SETGr, X86::SETGm },
2991 { X86::SETGEr, X86::SETGEm },
2992 { X86::SETLr, X86::SETLm },
2993 { X86::SETLEr, X86::SETLEm },
2994 { X86::SETNEr, X86::SETNEm },
2995 { X86::SETNOr, X86::SETNOm },
2996 { X86::SETNPr, X86::SETNPm },
2997 { X86::SETNSr, X86::SETNSm },
2998 { X86::SETOr, X86::SETOm },
2999 { X86::SETPr, X86::SETPm },
3000 { X86::SETSr, X86::SETSm }
3001 };
3002
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3003 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3004 return Opc[CC][HasMemoryOperand ? 1 : 0];
3005}
3006
3007/// getCMovFromCond - Return a cmov opcode for the given condition,
3008/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3009unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3010 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3011 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3012 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3013 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3014 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3015 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3016 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3017 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3018 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3019 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3020 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3021 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3022 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3023 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3024 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3025 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3026 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3027 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3028 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3029 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3030 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3031 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3032 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3033 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3034 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3035 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3036 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3037 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3038 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3039 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3040 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3041 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3042 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3043 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3044 };
3045
3046 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3047 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3048 switch(RegBytes) {
3049 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3050 case 2: return Opc[Idx][0];
3051 case 4: return Opc[Idx][1];
3052 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3053 }
3054}
3055
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3056bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3057 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3058
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3059 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3060 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3061 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3062 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3063 return true;
3064 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3065}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3066
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3067bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3068 MachineBasicBlock *&TBB,
3069 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3070 SmallVectorImpl<MachineOperand> &Cond,
3071 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3072 // Start from the bottom of the block and work up, examining the
3073 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3074 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3075 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3076 while (I != MBB.begin()) {
3077 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3078 if (I->isDebugValue())
3079 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3080
3081 // Working from the bottom, when we see a non-terminator instruction, we're
3082 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]3083 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3084 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3085
3086 // A terminator that isn't a branch can't easily be handled by this
3087 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3088 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3089 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3090
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3091 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3092 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3093 UnCondBrIter = I;
3094
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3095 if (!AllowModify) {
3096 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3097 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3098 }
3099
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3100 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3101 while (std::next(I) != MBB.end())
3102 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3103
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3104 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3105 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3106
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3107 // Delete the JMP if it's equivalent to a fall-through.
3108 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3109 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3110 I->eraseFromParent();
3111 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3112 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3113 continue;
3114 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3115
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3116 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3117 TBB = I->getOperand(0).getMBB();
3118 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3119 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3120
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3121 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3122 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3123 if (BranchCode == X86::COND_INVALID)
3124 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3125
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3126 // Working from the bottom, handle the first conditional branch.
3127 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3128 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3129 if (AllowModify && UnCondBrIter != MBB.end() &&
3130 MBB.isLayoutSuccessor(TargetBB)) {
3131 // If we can modify the code and it ends in something like:
3132 //
3133 // jCC L1
3134 // jmp L2
3135 // L1:
3136 // ...
3137 // L2:
3138 //
3139 // Then we can change this to:
3140 //
3141 // jnCC L2
3142 // L1:
3143 // ...
3144 // L2:
3145 //
3146 // Which is a bit more efficient.
3147 // We conditionally jump to the fall-through block.
3148 BranchCode = GetOppositeBranchCondition(BranchCode);
3149 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3150 MachineBasicBlock::iterator OldInst = I;
3151
3152 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3153 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3154 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3155 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3156
3157 OldInst->eraseFromParent();
3158 UnCondBrIter->eraseFromParent();
3159
3160 // Restart the analysis.
3161 UnCondBrIter = MBB.end();
3162 I = MBB.end();
3163 continue;
3164 }
3165
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3166 FBB = TBB;
3167 TBB = I->getOperand(0).getMBB();
3168 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3169 continue;
3170 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3171
3172 // Handle subsequent conditional branches. Only handle the case where all
3173 // conditional branches branch to the same destination and their condition
3174 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3175 assert(Cond.size() == 1);
3176 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3177
3178 // Only handle the case where all conditional branches branch to the same
3179 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3180 if (TBB != I->getOperand(0).getMBB())
3181 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3182
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3183 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3184 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3185 if (OldBranchCode == BranchCode)
3186 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3187
3188 // If they differ, see if they fit one of the known patterns. Theoretically,
3189 // we could handle more patterns here, but we shouldn't expect to see them
3190 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3191 if ((OldBranchCode == X86::COND_NP &&
3192 BranchCode == X86::COND_E) ||
3193 (OldBranchCode == X86::COND_E &&
3194 BranchCode == X86::COND_NP))
3195 BranchCode = X86::COND_NP_OR_E;
3196 else if ((OldBranchCode == X86::COND_P &&
3197 BranchCode == X86::COND_NE) ||
3198 (OldBranchCode == X86::COND_NE &&
3199 BranchCode == X86::COND_P))
3200 BranchCode = X86::COND_NE_OR_P;
3201 else
3202 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3203
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3204 // Update the MachineOperand.
3205 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]3206 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3207
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3208 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3209}
3210
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3211unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3212 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3213 unsigned Count = 0;
3214
3215 while (I != MBB.begin()) {
3216 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3217 if (I->isDebugValue())
3218 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3219 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3220 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3221 break;
3222 // Remove the branch.
3223 I->eraseFromParent();
3224 I = MBB.end();
3225 ++Count;
3226 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3227
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3228 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3229}
3230
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3231unsigned
3232X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3233 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3234 const SmallVectorImpl<MachineOperand> &Cond,
3235 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3236 // Shouldn't be a fall through.
3237 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]3238 assert((Cond.size() == 1 || Cond.size() == 0) &&
3239 "X86 branch conditions have one component!");
3240
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3241 if (Cond.empty()) {
3242 // Unconditional branch?
3243 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3244 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3245 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3246 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3247
3248 // Conditional branch.
3249 unsigned Count = 0;
3250 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3251 switch (CC) {
3252 case X86::COND_NP_OR_E:
3253 // Synthesize NP_OR_E with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3254 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3255 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3256 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3257 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3258 break;
3259 case X86::COND_NE_OR_P:
3260 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3261 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3262 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3263 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3264 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3265 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3266 default: {
3267 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3268 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3269 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3270 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3271 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3272 if (FBB) {
3273 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3274 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3275 ++Count;
3276 }
3277 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3278}
3279
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3280bool X86InstrInfo::
3281canInsertSelect(const MachineBasicBlock &MBB,
3282 const SmallVectorImpl<MachineOperand> &Cond,
3283 unsigned TrueReg, unsigned FalseReg,
3284 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3285 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3286 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3287 return false;
3288 if (Cond.size() != 1)
3289 return false;
3290 // We cannot do the composite conditions, at least not in SSA form.
3291 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3292 return false;
3293
3294 // Check register classes.
3295 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3296 const TargetRegisterClass *RC =
3297 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3298 if (!RC)
3299 return false;
3300
3301 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3302 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3303 X86::GR32RegClass.hasSubClassEq(RC) ||
3304 X86::GR64RegClass.hasSubClassEq(RC)) {
3305 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3306 // Bridge. Probably Ivy Bridge as well.
3307 CondCycles = 2;
3308 TrueCycles = 2;
3309 FalseCycles = 2;
3310 return true;
3311 }
3312
3313 // Can't do vectors.
3314 return false;
3315}
3316
3317void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3318 MachineBasicBlock::iterator I, DebugLoc DL,
3319 unsigned DstReg,
3320 const SmallVectorImpl<MachineOperand> &Cond,
3321 unsigned TrueReg, unsigned FalseReg) const {
3322 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3323 assert(Cond.size() == 1 && "Invalid Cond array");
3324 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3325 MRI.getRegClass(DstReg)->getSize(),
3326 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3327 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3328}
3329
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3330/// isHReg - Test if the given register is a physical h register.
3331static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3332 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3333}
3334
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3335// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3336static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3337 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3338
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3339 // SrcReg(VR128) -> DestReg(GR64)
3340 // SrcReg(VR64) -> DestReg(GR64)
3341 // SrcReg(GR64) -> DestReg(VR128)
3342 // SrcReg(GR64) -> DestReg(VR64)
3343
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3344 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3345 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3346 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3347 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3348 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3349 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3350 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3351 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3352 // Copy from a VR64 register to a GR64 register.
3353 return X86::MOVSDto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3354 } else if (X86::GR64RegClass.contains(SrcReg)) {
3355 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3356 if (X86::VR128XRegClass.contains(DestReg))
3357 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3358 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3359 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3360 if (X86::VR64RegClass.contains(DestReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3361 return X86::MOV64toSDrr;
3362 }
3363
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3364 // SrcReg(FR32) -> DestReg(GR32)
3365 // SrcReg(GR32) -> DestReg(FR32)
3366
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3367 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3368 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3369 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3370
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3371 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3372 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3373 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3374 return 0;
3375}
3376
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3377inline static bool MaskRegClassContains(unsigned Reg) {
3378 return X86::VK8RegClass.contains(Reg) ||
3379 X86::VK16RegClass.contains(Reg) ||
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]3380 X86::VK32RegClass.contains(Reg) ||
3381 X86::VK64RegClass.contains(Reg) ||
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3382 X86::VK1RegClass.contains(Reg);
3383}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3384static
3385unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3386 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3387 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3388 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3389 DestReg = get512BitSuperRegister(DestReg);
3390 SrcReg = get512BitSuperRegister(SrcReg);
3391 return X86::VMOVAPSZrr;
3392 }
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3393 if (MaskRegClassContains(DestReg) &&
3394 MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3395 return X86::KMOVWkk;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3396 if (MaskRegClassContains(DestReg) &&
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3397 (X86::GR32RegClass.contains(SrcReg) ||
3398 X86::GR16RegClass.contains(SrcReg) ||
3399 X86::GR8RegClass.contains(SrcReg))) {
3400 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3401 return X86::KMOVWkr;
3402 }
3403 if ((X86::GR32RegClass.contains(DestReg) ||
3404 X86::GR16RegClass.contains(DestReg) ||
3405 X86::GR8RegClass.contains(DestReg)) &&
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3406 MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3407 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3408 return X86::KMOVWrk;
3409 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3410 return 0;
3411}
3412
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3413void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3414 MachineBasicBlock::iterator MI, DebugLoc DL,
3415 unsigned DestReg, unsigned SrcReg,
3416 bool KillSrc) const {
3417 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3418 bool HasAVX = Subtarget.hasAVX();
3419 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3420 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3421 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3422 Opc = X86::MOV64rr;
3423 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3424 Opc = X86::MOV32rr;
3425 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3426 Opc = X86::MOV16rr;
3427 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3428 // Copying to or from a physical H register on x86-64 requires a NOREX
3429 // move. Otherwise use a normal move.
3430 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3431 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3432 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3433 // Both operands must be encodable without an REX prefix.
3434 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3435 "8-bit H register can not be copied outside GR8_NOREX");
3436 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3437 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3438 }
3439 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3440 Opc = X86::MMX_MOVQ64rr;
3441 else if (HasAVX512)
3442 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3443 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3444 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3445 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3446 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3447 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3448 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3449
3450 if (Opc) {
3451 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3452 .addReg(SrcReg, getKillRegState(KillSrc));
3453 return;
3454 }
3455
3456 // Moving EFLAGS to / from another register requires a push and a pop.
Nadav Rotemd5aae982012-12-21 23:48:49 +0000[diff] [blame]3457 // Notice that we have to adjust the stack if we don't want to clobber the
JF Bastienac8b66b2014-08-05 23:27:34 +0000[diff] [blame]3458 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3459 if (SrcReg == X86::EFLAGS) {
3460 if (X86::GR64RegClass.contains(DestReg)) {
3461 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3462 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3463 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3464 }
3465 if (X86::GR32RegClass.contains(DestReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3466 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3467 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3468 return;
3469 }
3470 }
3471 if (DestReg == X86::EFLAGS) {
3472 if (X86::GR64RegClass.contains(SrcReg)) {
3473 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3474 .addReg(SrcReg, getKillRegState(KillSrc));
3475 BuildMI(MBB, MI, DL, get(X86::POPF64));
3476 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3477 }
3478 if (X86::GR32RegClass.contains(SrcReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3479 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3480 .addReg(SrcReg, getKillRegState(KillSrc));
3481 BuildMI(MBB, MI, DL, get(X86::POPF32));
3482 return;
3483 }
3484 }
3485
3486 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3487 << " to " << RI.getName(DestReg) << '\n');
3488 llvm_unreachable("Cannot emit physreg copy instruction");
3489}
3490
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3491static unsigned getLoadStoreRegOpcode(unsigned Reg,
3492 const TargetRegisterClass *RC,
3493 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3494 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3495 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3496 if (STI.hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]3497 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3498 X86::VK16RegClass.hasSubClassEq(RC))
3499 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3500 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3501 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3502 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3503 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3504 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3505 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3506 }
3507
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3508 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3509 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]3510 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3511 llvm_unreachable("Unknown spill size");
3512 case 1:
3513 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3514 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3515 // Copying to or from a physical H register on x86-64 requires a NOREX
3516 // move. Otherwise use a normal move.
3517 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3518 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3519 return load ? X86::MOV8rm : X86::MOV8mr;
3520 case 2:
3521 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3522 return load ? X86::MOV16rm : X86::MOV16mr;
3523 case 4:
3524 if (X86::GR32RegClass.hasSubClassEq(RC))
3525 return load ? X86::MOV32rm : X86::MOV32mr;
3526 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3527 return load ?
3528 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3529 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3530 if (X86::RFP32RegClass.hasSubClassEq(RC))
3531 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3532 llvm_unreachable("Unknown 4-byte regclass");
3533 case 8:
3534 if (X86::GR64RegClass.hasSubClassEq(RC))
3535 return load ? X86::MOV64rm : X86::MOV64mr;
3536 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3537 return load ?
3538 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3539 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3540 if (X86::VR64RegClass.hasSubClassEq(RC))
3541 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3542 if (X86::RFP64RegClass.hasSubClassEq(RC))
3543 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3544 llvm_unreachable("Unknown 8-byte regclass");
3545 case 10:
3546 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3547 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3548 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3549 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3550 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3551 // If stack is realigned we can use aligned stores.
3552 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3553 return load ?
3554 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3555 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3556 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3557 return load ?
3558 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3559 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3560 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3561 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3562 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3563 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3564 // If stack is realigned we can use aligned stores.
3565 if (isStackAligned)
3566 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3567 else
3568 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3569 case 64:
3570 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3571 if (isStackAligned)
3572 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3573 else
3574 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3575 }
3576}
3577
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3578static unsigned getStoreRegOpcode(unsigned SrcReg,
3579 const TargetRegisterClass *RC,
3580 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3581 const X86Subtarget &STI) {
3582 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3583}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3584
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3585
3586static unsigned getLoadRegOpcode(unsigned DestReg,
3587 const TargetRegisterClass *RC,
3588 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3589 const X86Subtarget &STI) {
3590 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3591}
3592
3593void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3594 MachineBasicBlock::iterator MI,
3595 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3596 const TargetRegisterClass *RC,
3597 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3598 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]3599 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3600 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3601 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]3602 bool isAligned = (MF.getTarget()
3603 .getSubtargetImpl()
3604 ->getFrameLowering()
3605 ->getStackAlignment() >= Alignment) ||
3606 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3607 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3608 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3609 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3610 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3611}
3612
3613void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3614 bool isKill,
3615 SmallVectorImpl<MachineOperand> &Addr,
3616 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3617 MachineInstr::mmo_iterator MMOBegin,
3618 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3619 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3620 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3621 bool isAligned = MMOBegin != MMOEnd &&
3622 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3623 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3624 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3625 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3626 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3627 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3628 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3629 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3630 NewMIs.push_back(MIB);
3631}
3632
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3633
3634void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3635 MachineBasicBlock::iterator MI,
3636 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3637 const TargetRegisterClass *RC,
3638 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3639 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3640 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]3641 bool isAligned = (MF.getTarget()
3642 .getSubtargetImpl()
3643 ->getFrameLowering()
3644 ->getStackAlignment() >= Alignment) ||
3645 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3646 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3647 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3648 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3649}
3650
3651void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3652 SmallVectorImpl<MachineOperand> &Addr,
3653 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3654 MachineInstr::mmo_iterator MMOBegin,
3655 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3656 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3657 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3658 bool isAligned = MMOBegin != MMOEnd &&
3659 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3660 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3661 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3662 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3663 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3664 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3665 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3666 NewMIs.push_back(MIB);
3667}
3668
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3669bool X86InstrInfo::
3670analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3671 int &CmpMask, int &CmpValue) const {
3672 switch (MI->getOpcode()) {
3673 default: break;
3674 case X86::CMP64ri32:
3675 case X86::CMP64ri8:
3676 case X86::CMP32ri:
3677 case X86::CMP32ri8:
3678 case X86::CMP16ri:
3679 case X86::CMP16ri8:
3680 case X86::CMP8ri:
3681 SrcReg = MI->getOperand(0).getReg();
3682 SrcReg2 = 0;
3683 CmpMask = ~0;
3684 CmpValue = MI->getOperand(1).getImm();
3685 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3686 // A SUB can be used to perform comparison.
3687 case X86::SUB64rm:
3688 case X86::SUB32rm:
3689 case X86::SUB16rm:
3690 case X86::SUB8rm:
3691 SrcReg = MI->getOperand(1).getReg();
3692 SrcReg2 = 0;
3693 CmpMask = ~0;
3694 CmpValue = 0;
3695 return true;
3696 case X86::SUB64rr:
3697 case X86::SUB32rr:
3698 case X86::SUB16rr:
3699 case X86::SUB8rr:
3700 SrcReg = MI->getOperand(1).getReg();
3701 SrcReg2 = MI->getOperand(2).getReg();
3702 CmpMask = ~0;
3703 CmpValue = 0;
3704 return true;
3705 case X86::SUB64ri32:
3706 case X86::SUB64ri8:
3707 case X86::SUB32ri:
3708 case X86::SUB32ri8:
3709 case X86::SUB16ri:
3710 case X86::SUB16ri8:
3711 case X86::SUB8ri:
3712 SrcReg = MI->getOperand(1).getReg();
3713 SrcReg2 = 0;
3714 CmpMask = ~0;
3715 CmpValue = MI->getOperand(2).getImm();
3716 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3717 case X86::CMP64rr:
3718 case X86::CMP32rr:
3719 case X86::CMP16rr:
3720 case X86::CMP8rr:
3721 SrcReg = MI->getOperand(0).getReg();
3722 SrcReg2 = MI->getOperand(1).getReg();
3723 CmpMask = ~0;
3724 CmpValue = 0;
3725 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3726 case X86::TEST8rr:
3727 case X86::TEST16rr:
3728 case X86::TEST32rr:
3729 case X86::TEST64rr:
3730 SrcReg = MI->getOperand(0).getReg();
3731 if (MI->getOperand(1).getReg() != SrcReg) return false;
3732 // Compare against zero.
3733 SrcReg2 = 0;
3734 CmpMask = ~0;
3735 CmpValue = 0;
3736 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3737 }
3738 return false;
3739}
3740
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3741/// isRedundantFlagInstr - check whether the first instruction, whose only
3742/// purpose is to update flags, can be made redundant.
3743/// CMPrr can be made redundant by SUBrr if the operands are the same.
3744/// This function can be extended later on.
3745/// SrcReg, SrcRegs: register operands for FlagI.
3746/// ImmValue: immediate for FlagI if it takes an immediate.
3747inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3748 unsigned SrcReg2, int ImmValue,
3749 MachineInstr *OI) {
3750 if (((FlagI->getOpcode() == X86::CMP64rr &&
3751 OI->getOpcode() == X86::SUB64rr) ||
3752 (FlagI->getOpcode() == X86::CMP32rr &&
3753 OI->getOpcode() == X86::SUB32rr)||
3754 (FlagI->getOpcode() == X86::CMP16rr &&
3755 OI->getOpcode() == X86::SUB16rr)||
3756 (FlagI->getOpcode() == X86::CMP8rr &&
3757 OI->getOpcode() == X86::SUB8rr)) &&
3758 ((OI->getOperand(1).getReg() == SrcReg &&
3759 OI->getOperand(2).getReg() == SrcReg2) ||
3760 (OI->getOperand(1).getReg() == SrcReg2 &&
3761 OI->getOperand(2).getReg() == SrcReg)))
3762 return true;
3763
3764 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3765 OI->getOpcode() == X86::SUB64ri32) ||
3766 (FlagI->getOpcode() == X86::CMP64ri8 &&
3767 OI->getOpcode() == X86::SUB64ri8) ||
3768 (FlagI->getOpcode() == X86::CMP32ri &&
3769 OI->getOpcode() == X86::SUB32ri) ||
3770 (FlagI->getOpcode() == X86::CMP32ri8 &&
3771 OI->getOpcode() == X86::SUB32ri8) ||
3772 (FlagI->getOpcode() == X86::CMP16ri &&
3773 OI->getOpcode() == X86::SUB16ri) ||
3774 (FlagI->getOpcode() == X86::CMP16ri8 &&
3775 OI->getOpcode() == X86::SUB16ri8) ||
3776 (FlagI->getOpcode() == X86::CMP8ri &&
3777 OI->getOpcode() == X86::SUB8ri)) &&
3778 OI->getOperand(1).getReg() == SrcReg &&
3779 OI->getOperand(2).getImm() == ImmValue)
3780 return true;
3781 return false;
3782}
3783
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3784/// isDefConvertible - check whether the definition can be converted
3785/// to remove a comparison against zero.
3786inline static bool isDefConvertible(MachineInstr *MI) {
3787 switch (MI->getOpcode()) {
3788 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3789
3790 // The shift instructions only modify ZF if their shift count is non-zero.
3791 // N.B.: The processor truncates the shift count depending on the encoding.
3792 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3793 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3794 return getTruncatedShiftCount(MI, 2) != 0;
3795
3796 // Some left shift instructions can be turned into LEA instructions but only
3797 // if their flags aren't used. Avoid transforming such instructions.
3798 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3799 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3800 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3801 return ShAmt != 0;
3802 }
3803
3804 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3805 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3806 return getTruncatedShiftCount(MI, 3) != 0;
3807
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3808 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3809 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3810 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3811 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3812 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]3813 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3814 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3815 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3816 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3817 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3818 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]3819 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3820 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3821 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3822 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3823 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3824 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3825 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3826 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3827 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3828 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3829 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3830 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3831 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3832 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3833 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3834 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3835 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3836 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3837 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3838 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3839 case X86::ADC32ri: case X86::ADC32ri8:
3840 case X86::ADC32rr: case X86::ADC64ri32:
3841 case X86::ADC64ri8: case X86::ADC64rr:
3842 case X86::SBB32ri: case X86::SBB32ri8:
3843 case X86::SBB32rr: case X86::SBB64ri32:
3844 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]3845 case X86::ANDN32rr: case X86::ANDN32rm:
3846 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]3847 case X86::BEXTR32rr: case X86::BEXTR64rr:
3848 case X86::BEXTR32rm: case X86::BEXTR64rm:
3849 case X86::BLSI32rr: case X86::BLSI32rm:
3850 case X86::BLSI64rr: case X86::BLSI64rm:
3851 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3852 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3853 case X86::BLSR32rr: case X86::BLSR32rm:
3854 case X86::BLSR64rr: case X86::BLSR64rm:
3855 case X86::BZHI32rr: case X86::BZHI32rm:
3856 case X86::BZHI64rr: case X86::BZHI64rm:
3857 case X86::LZCNT16rr: case X86::LZCNT16rm:
3858 case X86::LZCNT32rr: case X86::LZCNT32rm:
3859 case X86::LZCNT64rr: case X86::LZCNT64rm:
3860 case X86::POPCNT16rr:case X86::POPCNT16rm:
3861 case X86::POPCNT32rr:case X86::POPCNT32rm:
3862 case X86::POPCNT64rr:case X86::POPCNT64rm:
3863 case X86::TZCNT16rr: case X86::TZCNT16rm:
3864 case X86::TZCNT32rr: case X86::TZCNT32rm:
3865 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3866 return true;
3867 }
3868}
3869
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3870/// isUseDefConvertible - check whether the use can be converted
3871/// to remove a comparison against zero.
3872static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3873 switch (MI->getOpcode()) {
3874 default: return X86::COND_INVALID;
3875 case X86::LZCNT16rr: case X86::LZCNT16rm:
3876 case X86::LZCNT32rr: case X86::LZCNT32rm:
3877 case X86::LZCNT64rr: case X86::LZCNT64rm:
3878 return X86::COND_B;
3879 case X86::POPCNT16rr:case X86::POPCNT16rm:
3880 case X86::POPCNT32rr:case X86::POPCNT32rm:
3881 case X86::POPCNT64rr:case X86::POPCNT64rm:
3882 return X86::COND_E;
3883 case X86::TZCNT16rr: case X86::TZCNT16rm:
3884 case X86::TZCNT32rr: case X86::TZCNT32rm:
3885 case X86::TZCNT64rr: case X86::TZCNT64rm:
3886 return X86::COND_B;
3887 }
3888}
3889
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3890/// optimizeCompareInstr - Check if there exists an earlier instruction that
3891/// operates on the same source operands and sets flags in the same way as
3892/// Compare; remove Compare if possible.
3893bool X86InstrInfo::
3894optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3895 int CmpMask, int CmpValue,
3896 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3897 // Check whether we can replace SUB with CMP.
3898 unsigned NewOpcode = 0;
3899 switch (CmpInstr->getOpcode()) {
3900 default: break;
3901 case X86::SUB64ri32:
3902 case X86::SUB64ri8:
3903 case X86::SUB32ri:
3904 case X86::SUB32ri8:
3905 case X86::SUB16ri:
3906 case X86::SUB16ri8:
3907 case X86::SUB8ri:
3908 case X86::SUB64rm:
3909 case X86::SUB32rm:
3910 case X86::SUB16rm:
3911 case X86::SUB8rm:
3912 case X86::SUB64rr:
3913 case X86::SUB32rr:
3914 case X86::SUB16rr:
3915 case X86::SUB8rr: {
3916 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3917 return false;
3918 // There is no use of the destination register, we can replace SUB with CMP.
3919 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]3920 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3921 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3922 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3923 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3924 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3925 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3926 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3927 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3928 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3929 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3930 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3931 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3932 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3933 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3934 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3935 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3936 }
3937 CmpInstr->setDesc(get(NewOpcode));
3938 CmpInstr->RemoveOperand(0);
3939 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3940 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3941 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3942 return false;
3943 }
3944 }
3945
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3946 // Get the unique definition of SrcReg.
3947 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3948 if (!MI) return false;
3949
3950 // CmpInstr is the first instruction of the BB.
3951 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3952
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3953 // If we are comparing against zero, check whether we can use MI to update
3954 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3955 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3956 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3957 return false;
3958
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]3959 // If we have a use of the source register between the def and our compare
3960 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3961 // right way.
3962 bool ShouldUpdateCC = false;
3963 X86::CondCode NewCC = X86::COND_INVALID;
3964 if (IsCmpZero && !isDefConvertible(MI)) {
3965 // Scan forward from the use until we hit the use we're looking for or the
3966 // compare instruction.
3967 for (MachineBasicBlock::iterator J = MI;; ++J) {
3968 // Do we have a convertible instruction?
3969 NewCC = isUseDefConvertible(J);
3970 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3971 J->getOperand(1).getReg() == SrcReg) {
3972 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3973 ShouldUpdateCC = true; // Update CC later on.
3974 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3975 // with the new def.
3976 MI = Def = J;
3977 break;
3978 }
3979
3980 if (J == I)
3981 return false;
3982 }
3983 }
3984
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3985 // We are searching for an earlier instruction that can make CmpInstr
3986 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3987 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3988 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3989
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3990 // We iterate backward, starting from the instruction before CmpInstr and
3991 // stop when reaching the definition of a source register or done with the BB.
3992 // RI points to the instruction before CmpInstr.
3993 // If the definition is in this basic block, RE points to the definition;
3994 // otherwise, RE is the rend of the basic block.
3995 MachineBasicBlock::reverse_iterator
3996 RI = MachineBasicBlock::reverse_iterator(I),
3997 RE = CmpInstr->getParent() == MI->getParent() ?
3998 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3999 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4000 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4001 for (; RI != RE; ++RI) {
4002 MachineInstr *Instr = &*RI;
4003 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4004 if (!IsCmpZero &&
4005 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4006 Sub = Instr;
4007 break;
4008 }
4009
4010 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4011 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4012 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4013
4014 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4015 // They are safe to move up, if the definition to EFLAGS is dead and
4016 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4017 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4018 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4019 Movr0Inst = Instr;
4020 continue;
4021 }
4022
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4023 // We can't remove CmpInstr.
4024 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4025 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4026 }
4027
4028 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4029 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4030 return false;
4031
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4032 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4033 Sub->getOperand(2).getReg() == SrcReg);
4034
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4035 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4036 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4037 // If we are done with the basic block, we need to check whether EFLAGS is
4038 // live-out.
4039 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4040 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4041 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4042 for (++I; I != E; ++I) {
4043 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4044 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4045 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4046 // We should check the usage if this instruction uses and updates EFLAGS.
4047 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4048 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4049 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4050 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4051 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4052 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4053 continue;
4054
4055 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]4056 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4057 bool OpcIsSET = false;
4058 if (IsCmpZero || IsSwapped) {
4059 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4060 if (Instr.isBranch())
4061 OldCC = getCondFromBranchOpc(Instr.getOpcode());
4062 else {
4063 OldCC = getCondFromSETOpc(Instr.getOpcode());
4064 if (OldCC != X86::COND_INVALID)
4065 OpcIsSET = true;
4066 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]4067 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4068 }
4069 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4070 }
4071 if (IsCmpZero) {
4072 switch (OldCC) {
4073 default: break;
4074 case X86::COND_A: case X86::COND_AE:
4075 case X86::COND_B: case X86::COND_BE:
4076 case X86::COND_G: case X86::COND_GE:
4077 case X86::COND_L: case X86::COND_LE:
4078 case X86::COND_O: case X86::COND_NO:
4079 // CF and OF are used, we can't perform this optimization.
4080 return false;
4081 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4082
4083 // If we're updating the condition code check if we have to reverse the
4084 // condition.
4085 if (ShouldUpdateCC)
4086 switch (OldCC) {
4087 default:
4088 return false;
4089 case X86::COND_E:
4090 break;
4091 case X86::COND_NE:
4092 NewCC = GetOppositeBranchCondition(NewCC);
4093 break;
4094 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4095 } else if (IsSwapped) {
4096 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4097 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4098 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4099 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4100 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4101 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4102
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4103 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4104 // Synthesize the new opcode.
4105 bool HasMemoryOperand = Instr.hasOneMemOperand();
4106 unsigned NewOpc;
4107 if (Instr.isBranch())
4108 NewOpc = GetCondBranchFromCond(NewCC);
4109 else if(OpcIsSET)
4110 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4111 else {
4112 unsigned DstReg = Instr.getOperand(0).getReg();
4113 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4114 HasMemoryOperand);
4115 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4116
4117 // Push the MachineInstr to OpsToUpdate.
4118 // If it is safe to remove CmpInstr, the condition code of these
4119 // instructions will be modified.
4120 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4121 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4122 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4123 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4124 IsSafe = true;
4125 break;
4126 }
4127 }
4128
4129 // If EFLAGS is not killed nor re-defined, we should check whether it is
4130 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4131 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4132 MachineBasicBlock *MBB = CmpInstr->getParent();
4133 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4134 SE = MBB->succ_end(); SI != SE; ++SI)
4135 if ((*SI)->isLiveIn(X86::EFLAGS))
4136 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4137 }
4138
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4139 // The instruction to be updated is either Sub or MI.
4140 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4141 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4142 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4143 // Look backwards until we find a def that doesn't use the current EFLAGS.
4144 Def = Sub;
4145 MachineBasicBlock::reverse_iterator
4146 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4147 InsertE = Sub->getParent()->rend();
4148 for (; InsertI != InsertE; ++InsertI) {
4149 MachineInstr *Instr = &*InsertI;
4150 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4151 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4152 Sub->getParent()->remove(Movr0Inst);
4153 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4154 Movr0Inst);
4155 break;
4156 }
4157 }
4158 if (InsertI == InsertE)
4159 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4160 }
4161
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]4162 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4163 unsigned i = 0, e = Sub->getNumOperands();
4164 for (; i != e; ++i) {
4165 MachineOperand &MO = Sub->getOperand(i);
4166 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4167 MO.setIsDead(false);
4168 break;
4169 }
4170 }
4171 assert(i != e && "Unable to locate a def EFLAGS operand");
4172
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4173 CmpInstr->eraseFromParent();
4174
4175 // Modify the condition code of instructions in OpsToUpdate.
4176 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4177 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4178 return true;
4179}
4180
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4181/// optimizeLoadInstr - Try to remove the load by folding it to a register
4182/// operand at the use. We fold the load instructions if load defines a virtual
4183/// register, the virtual register is used once in the same BB, and the
4184/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4185MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4186 const MachineRegisterInfo *MRI,
4187 unsigned &FoldAsLoadDefReg,
4188 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4189 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4190 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4191 // To be conservative, if there exists another load, clear the load candidate.
4192 if (MI->mayLoad()) {
4193 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4194 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4195 }
4196
4197 // Check whether we can move DefMI here.
4198 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4199 assert(DefMI);
4200 bool SawStore = false;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4201 if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4202 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4203
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4204 // Collect information about virtual register operands of MI.
4205 unsigned SrcOperandId = 0;
4206 bool FoundSrcOperand = false;
4207 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4208 MachineOperand &MO = MI->getOperand(i);
4209 if (!MO.isReg())
4210 continue;
4211 unsigned Reg = MO.getReg();
4212 if (Reg != FoldAsLoadDefReg)
4213 continue;
4214 // Do not fold if we have a subreg use or a def or multiple uses.
4215 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4216 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4217
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4218 SrcOperandId = i;
4219 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4220 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4221 if (!FoundSrcOperand)
4222 return nullptr;
4223
4224 // Check whether we can fold the def into SrcOperandId.
4225 SmallVector<unsigned, 8> Ops;
4226 Ops.push_back(SrcOperandId);
4227 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4228 if (FoldMI) {
4229 FoldAsLoadDefReg = 0;
4230 return FoldMI;
4231 }
4232
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4233 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4234}
4235
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4236/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4237/// instruction with two undef reads of the register being defined. This is
4238/// used for mapping:
4239/// %xmm4 = V_SET0
4240/// to:
4241/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4242///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4243static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4244 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4245 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4246 unsigned Reg = MIB->getOperand(0).getReg();
4247 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4248
4249 // MachineInstr::addOperand() will insert explicit operands before any
4250 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4251 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4252 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4253 assert(MIB->getOperand(1).getReg() == Reg &&
4254 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4255 return true;
4256}
4257
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4258// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4259// code sequence is needed for other targets.
4260static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4261 const TargetInstrInfo &TII) {
4262 MachineBasicBlock &MBB = *MIB->getParent();
4263 DebugLoc DL = MIB->getDebugLoc();
4264 unsigned Reg = MIB->getOperand(0).getReg();
4265 const GlobalValue *GV =
4266 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4267 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4268 MachineMemOperand *MMO = MBB.getParent()->
4269 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]4270 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4271
4272 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4273 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4274 .addMemOperand(MMO);
4275 MIB->setDebugLoc(DL);
4276 MIB->setDesc(TII.get(X86::MOV64rm));
4277 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4278}
4279
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4280bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4281 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4282 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4283 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]4284 case X86::MOV32r0:
4285 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4286 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4287 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4288 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4289 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4290 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4291 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4292 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4293 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4294 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4295 case X86::FsFLD0SS:
4296 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4297 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4298 case X86::AVX_SET0:
4299 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4300 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4301 case X86::AVX512_512_SET0:
4302 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4303 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4304 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4305 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4306 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]4307 case X86::TEST8ri_NOREX:
4308 MI->setDesc(get(X86::TEST8ri));
4309 return true;
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]4310 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4311 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4312 case X86::KSET1B:
4313 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4314 case TargetOpcode::LOAD_STACK_GUARD:
4315 expandLoadStackGuard(MIB, *this);
4316 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4317 }
4318 return false;
4319}
4320
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4321static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4322 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4323 MachineInstr *MI,
4324 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4325 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4326 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4327 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4328 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4329 MachineInstrBuilder MIB(MF, NewMI);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4330 unsigned NumAddrOps = MOs.size();
4331 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4332 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4333 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4334 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4335
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4336 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4337 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4338 for (unsigned i = 0; i != NumOps; ++i) {
4339 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4340 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4341 }
4342 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4343 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4344 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4345 }
4346 return MIB;
4347}
4348
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4349static MachineInstr *FuseInst(MachineFunction &MF,
4350 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4351 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4352 MachineInstr *MI, const TargetInstrInfo &TII) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4353 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4354 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4355 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4356 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4357
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4358 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4359 MachineOperand &MO = MI->getOperand(i);
4360 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4361 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4362 unsigned NumAddrOps = MOs.size();
4363 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4364 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4365 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4366 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4367 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4368 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4369 }
4370 }
4371 return MIB;
4372}
4373
4374static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4375 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4376 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4377 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4378 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4379
4380 unsigned NumAddrOps = MOs.size();
4381 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4382 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4383 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4384 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4385 return MIB.addImm(0);
4386}
4387
4388MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4389X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4390 MachineInstr *MI, unsigned i,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4391 const SmallVectorImpl<MachineOperand> &MOs,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4392 unsigned Size, unsigned Align,
4393 bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4394 const DenseMap<unsigned,
4395 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4396 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4397 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4398
4399 // Atom favors register form of call. So, we do not fold loads into calls
4400 // when X86Subtarget is Atom.
4401 if (isCallRegIndirect &&
4402 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4403 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4404 }
4405
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4406 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4407 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4408 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4409
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4410 // FIXME: AsmPrinter doesn't know how to handle
4411 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4412 if (MI->getOpcode() == X86::ADD32ri &&
4413 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4414 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4415
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4416 MachineInstr *NewMI = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4417 // Folding a memory location into the two-address part of a two-address
4418 // instruction is different than folding it other places. It requires
4419 // replacing the *two* registers with the memory location.
4420 if (isTwoAddr && NumOps >= 2 && i < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4421 MI->getOperand(0).isReg() &&
4422 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4423 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4424 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4425 isTwoAddrFold = true;
4426 } else if (i == 0) { // If operand 0
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4427 if (MI->getOpcode() == X86::MOV32r0) {
4428 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4429 if (NewMI)
4430 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]4431 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4432
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4433 OpcodeTablePtr = &RegOp2MemOpTable0;
4434 } else if (i == 1) {
4435 OpcodeTablePtr = &RegOp2MemOpTable1;
4436 } else if (i == 2) {
4437 OpcodeTablePtr = &RegOp2MemOpTable2;
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]4438 } else if (i == 3) {
4439 OpcodeTablePtr = &RegOp2MemOpTable3;
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]4440 } else if (i == 4) {
4441 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4442 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4443
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4444 // If table selected...
4445 if (OpcodeTablePtr) {
4446 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4447 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4448 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4449 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4450 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4451 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4452 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4453 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4454 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4455 if (Size) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4456 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4457 if (Size < RCSize) {
4458 // Check if it's safe to fold the load. If the size of the object is
4459 // narrower than the load width, then it's not.
4460 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4461 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4462 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4463 // a 32-bit load which is implicitly zero-extended. This likely is
4464 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4465 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4466 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4467 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4468 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4469 }
4470 }
4471
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4472 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4473 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4474 else
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4475 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4476
4477 if (NarrowToMOV32rm) {
4478 // If this is the special case where we use a MOV32rm to load a 32-bit
4479 // value and zero-extend the top bits. Change the destination register
4480 // to a 32-bit one.
4481 unsigned DstReg = NewMI->getOperand(0).getReg();
4482 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4483 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4484 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4485 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4486 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4487 return NewMI;
4488 }
4489 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4490
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4491 // If the instruction and target operand are commutable, commute the
4492 // instruction and try again.
4493 if (AllowCommute) {
4494 unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2;
4495 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4496 bool HasDef = MI->getDesc().getNumDefs();
4497 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4498 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4499 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4500 bool Tied0 =
4501 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4502 bool Tied1 =
4503 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4504
4505 // If either of the commutable operands are tied to the destination
4506 // then we can not commute + fold.
4507 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4508 (HasDef && Reg0 == Reg2 && Tied1))
4509 return nullptr;
4510
4511 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4512 (CommuteOpIdx2 == OriginalOpIdx)) {
4513 MachineInstr *CommutedMI = commuteInstruction(MI, false);
4514 if (!CommutedMI) {
4515 // Unable to commute.
4516 return nullptr;
4517 }
4518 if (CommutedMI != MI) {
4519 // New instruction. We can't fold from this.
4520 CommutedMI->eraseFromParent();
4521 return nullptr;
4522 }
4523
4524 // Attempt to fold with the commuted version of the instruction.
4525 unsigned CommuteOp =
4526 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4527 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4528 /*AllowCommute=*/false);
4529 if (NewMI)
4530 return NewMI;
4531
4532 // Folding failed again - undo the commute before returning.
4533 MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4534 if (!UncommutedMI) {
4535 // Unable to commute.
4536 return nullptr;
4537 }
4538 if (UncommutedMI != MI) {
4539 // New instruction. It doesn't need to be kept.
4540 UncommutedMI->eraseFromParent();
4541 return nullptr;
4542 }
4543
4544 // Return here to prevent duplicate fuse failure report.
4545 return nullptr;
4546 }
4547 }
4548 }
4549
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4550 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]4551 if (PrintFailedFusing && !MI->isCopy())
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]4552 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4553 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4554}
4555
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4556/// hasPartialRegUpdate - Return true for all instructions that only update
4557/// the first 32 or 64-bits of the destination register and leave the rest
4558/// unmodified. This can be used to avoid folding loads if the instructions
4559/// only update part of the destination register, and the non-updated part is
4560/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4561/// instructions breaks the partial register dependency and it can improve
4562/// performance. e.g.:
4563///
4564/// movss (%rdi), %xmm0
4565/// cvtss2sd %xmm0, %xmm0
4566///
4567/// Instead of
4568/// cvtss2sd (%rdi), %xmm0
4569///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]4570/// FIXME: This should be turned into a TSFlags.
4571///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4572static bool hasPartialRegUpdate(unsigned Opcode) {
4573 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4574 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4575 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4576 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4577 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4578 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4579 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4580 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4581 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4582 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4583 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4584 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4585 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4586 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4587 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4588 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4589 case X86::Int_CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4590 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4591 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4592 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4593 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4594 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4595 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4596 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4597 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4598 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4599 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4600 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4601 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4602 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4603 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4604 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4605 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4606 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4607 case X86::SQRTSSm_Int:
4608 case X86::SQRTSDr:
4609 case X86::SQRTSDm:
4610 case X86::SQRTSDr_Int:
4611 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4612 return true;
4613 }
4614
4615 return false;
4616}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4617
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4618/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4619/// instructions we would like before a partial register update.
4620unsigned X86InstrInfo::
4621getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4622 const TargetRegisterInfo *TRI) const {
4623 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4624 return 0;
4625
4626 // If MI is marked as reading Reg, the partial register update is wanted.
4627 const MachineOperand &MO = MI->getOperand(0);
4628 unsigned Reg = MO.getReg();
4629 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4630 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4631 return 0;
4632 } else {
4633 if (MI->readsRegister(Reg, TRI))
4634 return 0;
4635 }
4636
4637 // If any of the preceding 16 instructions are reading Reg, insert a
4638 // dependency breaking instruction. The magic number is based on a few
4639 // Nehalem experiments.
4640 return 16;
4641}
4642
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4643// Return true for any instruction the copies the high bits of the first source
4644// operand into the unused high bits of the destination operand.
4645static bool hasUndefRegUpdate(unsigned Opcode) {
4646 switch (Opcode) {
4647 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4648 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4649 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4650 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4651 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4652 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4653 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4654 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4655 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4656 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4657 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4658 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4659 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4660 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4661 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4662 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4663 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4664 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4665 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4666 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4667 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4668 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4669 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4670 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4671 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4672 case X86::VRCPSSm:
4673 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4674 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4675 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4676 case X86::VROUNDSDr_Int:
4677 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4678 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4679 case X86::VROUNDSSr_Int:
4680 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4681 case X86::VRSQRTSSm:
4682 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4683 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4684 case X86::VSQRTSSm:
4685 case X86::VSQRTSSm_Int:
4686 case X86::VSQRTSDr:
4687 case X86::VSQRTSDm:
4688 case X86::VSQRTSDm_Int:
4689 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4690 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4691 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4692 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4693 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4694 return true;
4695 }
4696
4697 return false;
4698}
4699
4700/// Inform the ExeDepsFix pass how many idle instructions we would like before
4701/// certain undef register reads.
4702///
4703/// This catches the VCVTSI2SD family of instructions:
4704///
4705/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4706///
4707/// We should to be careful *not* to catch VXOR idioms which are presumably
4708/// handled specially in the pipeline:
4709///
4710/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4711///
4712/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4713/// high bits that are passed-through are not live.
4714unsigned X86InstrInfo::
4715getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4716 const TargetRegisterInfo *TRI) const {
4717 if (!hasUndefRegUpdate(MI->getOpcode()))
4718 return 0;
4719
4720 // Set the OpNum parameter to the first source operand.
4721 OpNum = 1;
4722
4723 const MachineOperand &MO = MI->getOperand(OpNum);
4724 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4725 // Use the same magic number as getPartialRegUpdateClearance.
4726 return 16;
4727 }
4728 return 0;
4729}
4730
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4731void X86InstrInfo::
4732breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4733 const TargetRegisterInfo *TRI) const {
4734 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4735 // If MI kills this register, the false dependence is already broken.
4736 if (MI->killsRegister(Reg, TRI))
4737 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4738 if (X86::VR128RegClass.contains(Reg)) {
4739 // These instructions are all floating point domain, so xorps is the best
4740 // choice.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4741 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4742 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4743 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4744 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4745 } else if (X86::VR256RegClass.contains(Reg)) {
4746 // Use vxorps to clear the full ymm register.
4747 // It wants to read and write the xmm sub-register.
4748 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4749 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4750 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4751 .addReg(Reg, RegState::ImplicitDefine);
4752 } else
4753 return;
4754 MI->addRegisterKilled(Reg, TRI, true);
4755}
4756
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]4757MachineInstr*
4758X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4759 const SmallVectorImpl<unsigned> &Ops,
4760 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4761 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4762 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4763
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4764 // Unless optimizing for size, don't fold to avoid partial
4765 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4766 if (!MF.getFunction()->getAttributes().
4767 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4768 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4769 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4770
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4771 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4772 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4773 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]4774 // If the function stack isn't realigned we don't want to fold instructions
4775 // that need increased alignment.
4776 if (!RI.needsStackRealignment(MF))
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]4777 Alignment = std::min(Alignment, MF.getTarget()
4778 .getSubtargetImpl()
4779 ->getFrameLowering()
4780 ->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4781 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4782 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4783 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4784 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4785 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4786 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]4787 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4788 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4789 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4790 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4791 // Check if it's safe to fold the load. If the size of the object is
4792 // narrower than the load width, then it's not.
4793 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4794 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4795 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4796 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4797 MI->getOperand(1).ChangeToImmediate(0);
4798 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4799 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4800
4801 SmallVector<MachineOperand,4> MOs;
4802 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4803 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4804 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4805}
4806
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4807static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
4808 const MachineFunction &MF) {
4809 unsigned Opc = LoadMI.getOpcode();
4810 unsigned RegSize =
4811 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
4812
4813 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
4814 // These instructions only load 32 bits, we can't fold them if the
4815 // destination register is wider than 32 bits (4 bytes).
4816 return true;
4817
4818 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
4819 // These instructions only load 64 bits, we can't fold them if the
4820 // destination register is wider than 64 bits (8 bytes).
4821 return true;
4822
4823 return false;
4824}
4825
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4826MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4827 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4828 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4829 MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4830 // If loading from a FrameIndex, fold directly from the FrameIndex.
4831 unsigned NumOps = LoadMI->getDesc().getNumOperands();
4832 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4833 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4834 if (isPartialRegisterLoad(*LoadMI, MF))
4835 return nullptr;
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4836 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4837 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]4838
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4839 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4840 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4841
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4842 // Unless optimizing for size, don't fold to avoid partial
4843 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4844 if (!MF.getFunction()->getAttributes().
4845 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4846 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4847 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4848
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]4849 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4850 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]4851 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]4852 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4853 else
4854 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]4855 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4856 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4857 Alignment = 32;
4858 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4859 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4860 case X86::V_SETALLONES:
4861 Alignment = 16;
4862 break;
4863 case X86::FsFLD0SD:
4864 Alignment = 8;
4865 break;
4866 case X86::FsFLD0SS:
4867 Alignment = 4;
4868 break;
4869 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4870 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4871 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4872 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4873 unsigned NewOpc = 0;
4874 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4875 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4876 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4877 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4878 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4879 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4880 }
4881 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4882 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4883 MI->getOperand(1).ChangeToImmediate(0);
4884 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4885 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4886
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]4887 // Make sure the subregisters match.
4888 // Otherwise we risk changing the size of the load.
4889 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4890 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]4891
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4892 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4893 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4894 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4895 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]4896 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4897 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4898 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4899 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4900 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4901 // Create a constant-pool entry and operands to load from it.
4902
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]4903 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4904 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4905 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4906 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]4907
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4908 // x86-32 PIC requires a PIC base register for constant pools.
4909 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4910 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4911 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]4912 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4913 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4914 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]4915 // This doesn't work for several reasons.
4916 // 1. GlobalBaseReg may have been spilled.
4917 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4918 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]4919 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4920
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4921 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4922 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]4923 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4924 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4925 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4926 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4927 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4928 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4929 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]4930 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4931 else
4932 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]4933
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4934 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]4935 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4936 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4937 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4938
4939 // Create operands to load from the constant pool entry.
4940 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4941 MOs.push_back(MachineOperand::CreateImm(1));
4942 MOs.push_back(MachineOperand::CreateReg(0, false));
4943 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4944 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4945 break;
4946 }
4947 default: {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]4948 if (isPartialRegisterLoad(*LoadMI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4949 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]4950
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4951 // Folding a normal load. Just copy the load's address operands.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4952 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4953 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4954 break;
4955 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4956 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4957 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4958 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4959}
4960
4961
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]4962bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4963 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4964 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4965 if (NoFusing) return 0;
4966
4967 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4968 switch (MI->getOpcode()) {
4969 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4970 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4971 case X86::TEST16rr:
4972 case X86::TEST32rr:
4973 case X86::TEST64rr:
4974 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4975 case X86::ADD32ri:
4976 // FIXME: AsmPrinter doesn't know how to handle
4977 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4978 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4979 return false;
4980 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4981 }
4982 }
4983
4984 if (Ops.size() != 1)
4985 return false;
4986
4987 unsigned OpNum = Ops[0];
4988 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4989 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4990 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4991 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4992
4993 // Folding a memory location into the two-address part of a two-address
4994 // instruction is different than folding it other places. It requires
4995 // replacing the *two* registers with the memory location.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4996 const DenseMap<unsigned,
4997 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4998 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4999 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5000 } else if (OpNum == 0) { // If operand 0
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5001 if (Opc == X86::MOV32r0)
5002 return true;
5003
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5004 OpcodeTablePtr = &RegOp2MemOpTable0;
5005 } else if (OpNum == 1) {
5006 OpcodeTablePtr = &RegOp2MemOpTable1;
5007 } else if (OpNum == 2) {
5008 OpcodeTablePtr = &RegOp2MemOpTable2;
Craig Topper7573c8f2012-08-31 22:12:16 +0000[diff] [blame]5009 } else if (OpNum == 3) {
5010 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5011 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5012
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]5013 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5014 return true;
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]5015 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5016}
5017
5018bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5019 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5020 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5021 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5022 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5023 if (I == MemOp2RegOpTable.end())
5024 return false;
5025 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5026 unsigned Index = I->second.second & TB_INDEX_MASK;
5027 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5028 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5029 if (UnfoldLoad && !FoldedLoad)
5030 return false;
5031 UnfoldLoad &= FoldedLoad;
5032 if (UnfoldStore && !FoldedStore)
5033 return false;
5034 UnfoldStore &= FoldedStore;
5035
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5036 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5037 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5038 if (!MI->hasOneMemOperand() &&
5039 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5040 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5041 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5042 // conservatively assume the address is unaligned. That's bad for
5043 // performance.
5044 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5045 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5046 SmallVector<MachineOperand,2> BeforeOps;
5047 SmallVector<MachineOperand,2> AfterOps;
5048 SmallVector<MachineOperand,4> ImpOps;
5049 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5050 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5051 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5052 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5053 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5054 ImpOps.push_back(Op);
5055 else if (i < Index)
5056 BeforeOps.push_back(Op);
5057 else if (i > Index)
5058 AfterOps.push_back(Op);
5059 }
5060
5061 // Emit the load instruction.
5062 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5063 std::pair<MachineInstr::mmo_iterator,
5064 MachineInstr::mmo_iterator> MMOs =
5065 MF.extractLoadMemRefs(MI->memoperands_begin(),
5066 MI->memoperands_end());
5067 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5068 if (UnfoldStore) {
5069 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5070 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5071 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5072 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5073 MO.setIsKill(false);
5074 }
5075 }
5076 }
5077
5078 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5079 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5080 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5081
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5082 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5083 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5084 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5085 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5086 if (FoldedLoad)
5087 MIB.addReg(Reg);
5088 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5089 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5090 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5091 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5092 MIB.addReg(MO.getReg(),
5093 getDefRegState(MO.isDef()) |
5094 RegState::Implicit |
5095 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]5096 getDeadRegState(MO.isDead()) |
5097 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5098 }
5099 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5100 switch (DataMI->getOpcode()) {
5101 default: break;
5102 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5103 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5104 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5105 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5106 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5107 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5108 case X86::CMP8ri: {
5109 MachineOperand &MO0 = DataMI->getOperand(0);
5110 MachineOperand &MO1 = DataMI->getOperand(1);
5111 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5112 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5113 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5114 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5115 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5116 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5117 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5118 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5119 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5120 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5121 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5122 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5123 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5124 MO1.ChangeToRegister(MO0.getReg(), false);
5125 }
5126 }
5127 }
5128 NewMIs.push_back(DataMI);
5129
5130 // Emit the store instruction.
5131 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5132 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5133 std::pair<MachineInstr::mmo_iterator,
5134 MachineInstr::mmo_iterator> MMOs =
5135 MF.extractStoreMemRefs(MI->memoperands_begin(),
5136 MI->memoperands_end());
5137 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5138 }
5139
5140 return true;
5141}
5142
5143bool
5144X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5145 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]5146 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5147 return false;
5148
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5149 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5150 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5151 if (I == MemOp2RegOpTable.end())
5152 return false;
5153 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5154 unsigned Index = I->second.second & TB_INDEX_MASK;
5155 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5156 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5157 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5158 MachineFunction &MF = DAG.getMachineFunction();
5159 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5160 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5161 std::vector<SDValue> AddrOps;
5162 std::vector<SDValue> BeforeOps;
5163 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]5164 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5165 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5166 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5167 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5168 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5169 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5170 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5171 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5172 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5173 AfterOps.push_back(Op);
5174 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5175 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5176 AddrOps.push_back(Chain);
5177
5178 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5179 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5180 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5181 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5182 std::pair<MachineInstr::mmo_iterator,
5183 MachineInstr::mmo_iterator> MMOs =
5184 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5185 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5186 if (!(*MMOs.first) &&
5187 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5188 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5189 // Do not introduce a slow unaligned load.
5190 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5191 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5192 bool isAligned = (*MMOs.first) &&
5193 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5194 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5195 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5196 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5197
5198 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5199 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5200 }
5201
5202 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5203 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5204 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5205 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5206 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5207 VTs.push_back(*DstRC->vt_begin());
5208 }
5209 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5210 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5211 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5212 VTs.push_back(VT);
5213 }
5214 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5215 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5216 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5217 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5218 NewNodes.push_back(NewNode);
5219
5220 // Emit the store instruction.
5221 if (FoldedStore) {
5222 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5223 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5224 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5225 std::pair<MachineInstr::mmo_iterator,
5226 MachineInstr::mmo_iterator> MMOs =
5227 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5228 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5229 if (!(*MMOs.first) &&
5230 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5231 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5232 // Do not introduce a slow unaligned store.
5233 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5234 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5235 bool isAligned = (*MMOs.first) &&
5236 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5237 SDNode *Store =
5238 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5239 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5240 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5241
5242 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5243 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5244 }
5245
5246 return true;
5247}
5248
5249unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5250 bool UnfoldLoad, bool UnfoldStore,
5251 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5252 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5253 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5254 if (I == MemOp2RegOpTable.end())
5255 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5256 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5257 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5258 if (UnfoldLoad && !FoldedLoad)
5259 return 0;
5260 if (UnfoldStore && !FoldedStore)
5261 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5262 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5263 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5264 return I->second.first;
5265}
5266
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5267bool
5268X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5269 int64_t &Offset1, int64_t &Offset2) const {
5270 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5271 return false;
5272 unsigned Opc1 = Load1->getMachineOpcode();
5273 unsigned Opc2 = Load2->getMachineOpcode();
5274 switch (Opc1) {
5275 default: return false;
5276 case X86::MOV8rm:
5277 case X86::MOV16rm:
5278 case X86::MOV32rm:
5279 case X86::MOV64rm:
5280 case X86::LD_Fp32m:
5281 case X86::LD_Fp64m:
5282 case X86::LD_Fp80m:
5283 case X86::MOVSSrm:
5284 case X86::MOVSDrm:
5285 case X86::MMX_MOVD64rm:
5286 case X86::MMX_MOVQ64rm:
5287 case X86::FsMOVAPSrm:
5288 case X86::FsMOVAPDrm:
5289 case X86::MOVAPSrm:
5290 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5291 case X86::MOVAPDrm:
5292 case X86::MOVDQArm:
5293 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5294 // AVX load instructions
5295 case X86::VMOVSSrm:
5296 case X86::VMOVSDrm:
5297 case X86::FsVMOVAPSrm:
5298 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5299 case X86::VMOVAPSrm:
5300 case X86::VMOVUPSrm:
5301 case X86::VMOVAPDrm:
5302 case X86::VMOVDQArm:
5303 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5304 case X86::VMOVAPSYrm:
5305 case X86::VMOVUPSYrm:
5306 case X86::VMOVAPDYrm:
5307 case X86::VMOVDQAYrm:
5308 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5309 break;
5310 }
5311 switch (Opc2) {
5312 default: return false;
5313 case X86::MOV8rm:
5314 case X86::MOV16rm:
5315 case X86::MOV32rm:
5316 case X86::MOV64rm:
5317 case X86::LD_Fp32m:
5318 case X86::LD_Fp64m:
5319 case X86::LD_Fp80m:
5320 case X86::MOVSSrm:
5321 case X86::MOVSDrm:
5322 case X86::MMX_MOVD64rm:
5323 case X86::MMX_MOVQ64rm:
5324 case X86::FsMOVAPSrm:
5325 case X86::FsMOVAPDrm:
5326 case X86::MOVAPSrm:
5327 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5328 case X86::MOVAPDrm:
5329 case X86::MOVDQArm:
5330 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5331 // AVX load instructions
5332 case X86::VMOVSSrm:
5333 case X86::VMOVSDrm:
5334 case X86::FsVMOVAPSrm:
5335 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5336 case X86::VMOVAPSrm:
5337 case X86::VMOVUPSrm:
5338 case X86::VMOVAPDrm:
5339 case X86::VMOVDQArm:
5340 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5341 case X86::VMOVAPSYrm:
5342 case X86::VMOVUPSYrm:
5343 case X86::VMOVAPDYrm:
5344 case X86::VMOVDQAYrm:
5345 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5346 break;
5347 }
5348
5349 // Check if chain operands and base addresses match.
5350 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5351 Load1->getOperand(5) != Load2->getOperand(5))
5352 return false;
5353 // Segment operands should match as well.
5354 if (Load1->getOperand(4) != Load2->getOperand(4))
5355 return false;
5356 // Scale should be 1, Index should be Reg0.
5357 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5358 Load1->getOperand(2) == Load2->getOperand(2)) {
5359 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5360 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5361
5362 // Now let's examine the displacements.
5363 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5364 isa<ConstantSDNode>(Load2->getOperand(3))) {
5365 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5366 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5367 return true;
5368 }
5369 }
5370 return false;
5371}
5372
5373bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5374 int64_t Offset1, int64_t Offset2,
5375 unsigned NumLoads) const {
5376 assert(Offset2 > Offset1);
5377 if ((Offset2 - Offset1) / 8 > 64)
5378 return false;
5379
5380 unsigned Opc1 = Load1->getMachineOpcode();
5381 unsigned Opc2 = Load2->getMachineOpcode();
5382 if (Opc1 != Opc2)
5383 return false; // FIXME: overly conservative?
5384
5385 switch (Opc1) {
5386 default: break;
5387 case X86::LD_Fp32m:
5388 case X86::LD_Fp64m:
5389 case X86::LD_Fp80m:
5390 case X86::MMX_MOVD64rm:
5391 case X86::MMX_MOVQ64rm:
5392 return false;
5393 }
5394
5395 EVT VT = Load1->getValueType(0);
5396 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5397 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5398 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5399 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5400 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5401 if (NumLoads >= 3)
5402 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5403 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5404 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5405 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5406 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5407 case MVT::i8:
5408 case MVT::i16:
5409 case MVT::i32:
5410 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]5411 case MVT::f32:
5412 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5413 if (NumLoads)
5414 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5415 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5416 }
5417
5418 return true;
5419}
5420
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5421bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5422 MachineInstr *Second) const {
5423 // Check if this processor supports macro-fusion. Since this is a minor
5424 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5425 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5426 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5427 return false;
5428
5429 enum {
5430 FuseTest,
5431 FuseCmp,
5432 FuseInc
5433 } FuseKind;
5434
5435 switch(Second->getOpcode()) {
5436 default:
5437 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5438 case X86::JE_1:
5439 case X86::JNE_1:
5440 case X86::JL_1:
5441 case X86::JLE_1:
5442 case X86::JG_1:
5443 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5444 FuseKind = FuseInc;
5445 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5446 case X86::JB_1:
5447 case X86::JBE_1:
5448 case X86::JA_1:
5449 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5450 FuseKind = FuseCmp;
5451 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5452 case X86::JS_1:
5453 case X86::JNS_1:
5454 case X86::JP_1:
5455 case X86::JNP_1:
5456 case X86::JO_1:
5457 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5458 FuseKind = FuseTest;
5459 break;
5460 }
5461 switch (First->getOpcode()) {
5462 default:
5463 return false;
5464 case X86::TEST8rr:
5465 case X86::TEST16rr:
5466 case X86::TEST32rr:
5467 case X86::TEST64rr:
5468 case X86::TEST8ri:
5469 case X86::TEST16ri:
5470 case X86::TEST32ri:
5471 case X86::TEST32i32:
5472 case X86::TEST64i32:
5473 case X86::TEST64ri32:
5474 case X86::TEST8rm:
5475 case X86::TEST16rm:
5476 case X86::TEST32rm:
5477 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]5478 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5479 case X86::AND16i16:
5480 case X86::AND16ri:
5481 case X86::AND16ri8:
5482 case X86::AND16rm:
5483 case X86::AND16rr:
5484 case X86::AND32i32:
5485 case X86::AND32ri:
5486 case X86::AND32ri8:
5487 case X86::AND32rm:
5488 case X86::AND32rr:
5489 case X86::AND64i32:
5490 case X86::AND64ri32:
5491 case X86::AND64ri8:
5492 case X86::AND64rm:
5493 case X86::AND64rr:
5494 case X86::AND8i8:
5495 case X86::AND8ri:
5496 case X86::AND8rm:
5497 case X86::AND8rr:
5498 return true;
5499 case X86::CMP16i16:
5500 case X86::CMP16ri:
5501 case X86::CMP16ri8:
5502 case X86::CMP16rm:
5503 case X86::CMP16rr:
5504 case X86::CMP32i32:
5505 case X86::CMP32ri:
5506 case X86::CMP32ri8:
5507 case X86::CMP32rm:
5508 case X86::CMP32rr:
5509 case X86::CMP64i32:
5510 case X86::CMP64ri32:
5511 case X86::CMP64ri8:
5512 case X86::CMP64rm:
5513 case X86::CMP64rr:
5514 case X86::CMP8i8:
5515 case X86::CMP8ri:
5516 case X86::CMP8rm:
5517 case X86::CMP8rr:
5518 case X86::ADD16i16:
5519 case X86::ADD16ri:
5520 case X86::ADD16ri8:
5521 case X86::ADD16ri8_DB:
5522 case X86::ADD16ri_DB:
5523 case X86::ADD16rm:
5524 case X86::ADD16rr:
5525 case X86::ADD16rr_DB:
5526 case X86::ADD32i32:
5527 case X86::ADD32ri:
5528 case X86::ADD32ri8:
5529 case X86::ADD32ri8_DB:
5530 case X86::ADD32ri_DB:
5531 case X86::ADD32rm:
5532 case X86::ADD32rr:
5533 case X86::ADD32rr_DB:
5534 case X86::ADD64i32:
5535 case X86::ADD64ri32:
5536 case X86::ADD64ri32_DB:
5537 case X86::ADD64ri8:
5538 case X86::ADD64ri8_DB:
5539 case X86::ADD64rm:
5540 case X86::ADD64rr:
5541 case X86::ADD64rr_DB:
5542 case X86::ADD8i8:
5543 case X86::ADD8mi:
5544 case X86::ADD8mr:
5545 case X86::ADD8ri:
5546 case X86::ADD8rm:
5547 case X86::ADD8rr:
5548 case X86::SUB16i16:
5549 case X86::SUB16ri:
5550 case X86::SUB16ri8:
5551 case X86::SUB16rm:
5552 case X86::SUB16rr:
5553 case X86::SUB32i32:
5554 case X86::SUB32ri:
5555 case X86::SUB32ri8:
5556 case X86::SUB32rm:
5557 case X86::SUB32rr:
5558 case X86::SUB64i32:
5559 case X86::SUB64ri32:
5560 case X86::SUB64ri8:
5561 case X86::SUB64rm:
5562 case X86::SUB64rr:
5563 case X86::SUB8i8:
5564 case X86::SUB8ri:
5565 case X86::SUB8rm:
5566 case X86::SUB8rr:
5567 return FuseKind == FuseCmp || FuseKind == FuseInc;
5568 case X86::INC16r:
5569 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5570 case X86::INC64r:
5571 case X86::INC8r:
5572 case X86::DEC16r:
5573 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5574 case X86::DEC64r:
5575 case X86::DEC8r:
5576 return FuseKind == FuseInc;
5577 }
5578}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5579
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5580bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]5581ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5582 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5583 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]5584 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5585 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5586 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5587 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5588}
5589
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5590bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5591isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5592 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5593 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5594 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5595 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5596}
5597
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5598/// getGlobalBaseReg - Return a virtual register initialized with the
5599/// the global base register value. Output instructions required to
5600/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5601///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5602/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5603///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5604unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5605 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5606 "X86-64 PIC uses RIP relative addressing");
5607
5608 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5609 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5610 if (GlobalBaseReg != 0)
5611 return GlobalBaseReg;
5612
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5613 // Create the register. The code to initialize it is inserted
5614 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5615 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]5616 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5617 X86FI->setGlobalBaseReg(GlobalBaseReg);
5618 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5619}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5620
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5621// These are the replaceable SSE instructions. Some of these have Int variants
5622// that we don't include here. We don't want to replace instructions selected
5623// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5624static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]5625 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]5626 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5627 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5628 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5629 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5630 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5631 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5632 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5633 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5634 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5635 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5636 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5637 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5638 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5639 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5640 // AVX 128-bit support
5641 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5642 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5643 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5644 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5645 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5646 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5647 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5648 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5649 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5650 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5651 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5652 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5653 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5654 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5655 // AVX 256-bit support
5656 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5657 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5658 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5659 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5660 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5661 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5662};
5663
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5664static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5665 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]5666 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5667 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5668 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5669 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5670 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5671 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5672 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]5673 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5674 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5675 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5676 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5677 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5678 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]5679 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5680 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5681 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5682 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5683 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5684 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5685 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5686};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5687
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5688// FIXME: Some shuffle and unpack instructions have equivalents in different
5689// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5690
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5691static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5692 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5693 if (ReplaceableInstrs[i][domain-1] == opcode)
5694 return ReplaceableInstrs[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5695 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5696}
5697
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5698static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5699 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5700 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5701 return ReplaceableInstrsAVX2[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5702 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5703}
5704
5705std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5706X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5707 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5708 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5709 uint16_t validDomains = 0;
5710 if (domain && lookup(MI->getOpcode(), domain))
5711 validDomains = 0xe;
5712 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5713 validDomains = hasAVX2 ? 0xe : 0x6;
5714 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5715}
5716
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5717void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5718 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5719 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5720 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5721 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5722 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5723 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5724 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5725 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5726 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5727 assert(table && "Cannot change domain");
5728 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5729}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]5730
5731/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5732void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5733 NopInst.setOpcode(X86::NOOP);
5734}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5735
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5736// This code must remain in sync with getJumpInstrTableEntryBound in this class!
5737// In particular, getJumpInstrTableEntryBound must always return an upper bound
5738// on the encoding lengths of the instructions generated by
5739// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5740void X86InstrInfo::getUnconditionalBranch(
5741 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5742 Branch.setOpcode(X86::JMP_1);
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5743 Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5744}
5745
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5746// This code must remain in sync with getJumpInstrTableEntryBound in this class!
5747// In particular, getJumpInstrTableEntryBound must always return an upper bound
5748// on the encoding lengths of the instructions generated by
5749// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5750void X86InstrInfo::getTrap(MCInst &MI) const {
5751 MI.setOpcode(X86::TRAP);
5752}
5753
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5754// See getTrap and getUnconditionalBranch for conditions on the value returned
5755// by this function.
5756unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
5757 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
5758 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
5759 return 5;
5760}
5761
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5762bool X86InstrInfo::isHighLatencyDef(int opc) const {
5763 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5764 default: return false;
5765 case X86::DIVSDrm:
5766 case X86::DIVSDrm_Int:
5767 case X86::DIVSDrr:
5768 case X86::DIVSDrr_Int:
5769 case X86::DIVSSrm:
5770 case X86::DIVSSrm_Int:
5771 case X86::DIVSSrr:
5772 case X86::DIVSSrr_Int:
5773 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5774 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5775 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5776 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5777 case X86::SQRTSDm:
5778 case X86::SQRTSDm_Int:
5779 case X86::SQRTSDr:
5780 case X86::SQRTSDr_Int:
5781 case X86::SQRTSSm:
5782 case X86::SQRTSSm_Int:
5783 case X86::SQRTSSr:
5784 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5785 // AVX instructions with high latency
5786 case X86::VDIVSDrm:
5787 case X86::VDIVSDrm_Int:
5788 case X86::VDIVSDrr:
5789 case X86::VDIVSDrr_Int:
5790 case X86::VDIVSSrm:
5791 case X86::VDIVSSrm_Int:
5792 case X86::VDIVSSrr:
5793 case X86::VDIVSSrr_Int:
5794 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5795 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5796 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5797 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5798 case X86::VSQRTSDm:
5799 case X86::VSQRTSDm_Int:
5800 case X86::VSQRTSDr:
5801 case X86::VSQRTSSm:
5802 case X86::VSQRTSSm_Int:
5803 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]5804 case X86::VSQRTPDZm:
5805 case X86::VSQRTPDZr:
5806 case X86::VSQRTPSZm:
5807 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]5808 case X86::VSQRTSDZm:
5809 case X86::VSQRTSDZm_Int:
5810 case X86::VSQRTSDZr:
5811 case X86::VSQRTSSZm_Int:
5812 case X86::VSQRTSSZr:
5813 case X86::VSQRTSSZm:
5814 case X86::VDIVSDZrm:
5815 case X86::VDIVSDZrr:
5816 case X86::VDIVSSZrm:
5817 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]5818
5819 case X86::VGATHERQPSZrm:
5820 case X86::VGATHERQPDZrm:
5821 case X86::VGATHERDPDZrm:
5822 case X86::VGATHERDPSZrm:
5823 case X86::VPGATHERQDZrm:
5824 case X86::VPGATHERQQZrm:
5825 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]5826 case X86::VPGATHERDQZrm:
5827 case X86::VSCATTERQPDZmr:
5828 case X86::VSCATTERQPSZmr:
5829 case X86::VSCATTERDPDZmr:
5830 case X86::VSCATTERDPSZmr:
5831 case X86::VPSCATTERQDZmr:
5832 case X86::VPSCATTERQQZmr:
5833 case X86::VPSCATTERDDZmr:
5834 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5835 return true;
5836 }
5837}
5838
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5839bool X86InstrInfo::
5840hasHighOperandLatency(const InstrItineraryData *ItinData,
5841 const MachineRegisterInfo *MRI,
5842 const MachineInstr *DefMI, unsigned DefIdx,
5843 const MachineInstr *UseMI, unsigned UseIdx) const {
5844 return isHighLatencyDef(DefMI->getOpcode());
5845}
5846
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5847namespace {
5848 /// CGBR - Create Global Base Reg pass. This initializes the PIC
5849 /// global base register for x86-32.
5850 struct CGBR : public MachineFunctionPass {
5851 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]5852 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5853
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5854 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5855 const X86TargetMachine *TM =
5856 static_cast<const X86TargetMachine *>(&MF.getTarget());
5857
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]5858 // Don't do anything if this is 64-bit as 64-bit PIC
5859 // uses RIP relative addressing.
5860 if (TM->getSubtarget<X86Subtarget>().is64Bit())
5861 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5862
5863 // Only emit a global base reg in PIC mode.
5864 if (TM->getRelocationModel() != Reloc::PIC_)
5865 return false;
5866
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]5867 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5868 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5869
5870 // If we didn't need a GlobalBaseReg, don't insert code.
5871 if (GlobalBaseReg == 0)
5872 return false;
5873
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5874 // Insert the set of GlobalBaseReg into the first MBB of the function
5875 MachineBasicBlock &FirstMBB = MF.front();
5876 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5877 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5878 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]5879 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5880
5881 unsigned PC;
5882 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]5883 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5884 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]5885 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5886
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5887 // Operand of MovePCtoStack is completely ignored by asm printer. It's
5888 // only used in JIT code emission as displacement to pc.
5889 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5890
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5891 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5892 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5893 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5894 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5895 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5896 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5897 X86II::MO_GOT_ABSOLUTE_ADDRESS);
5898 }
5899
5900 return true;
5901 }
5902
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5903 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5904 return "X86 PIC Global Base Reg Initialization";
5905 }
5906
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5907 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5908 AU.setPreservesCFG();
5909 MachineFunctionPass::getAnalysisUsage(AU);
5910 }
5911 };
5912}
5913
5914char CGBR::ID = 0;
5915FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]5916llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5917
5918namespace {
5919 struct LDTLSCleanup : public MachineFunctionPass {
5920 static char ID;
5921 LDTLSCleanup() : MachineFunctionPass(ID) {}
5922
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]5923 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5924 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5925 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5926 // No point folding accesses if there isn't at least two.
5927 return false;
5928 }
5929
5930 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5931 return VisitNode(DT->getRootNode(), 0);
5932 }
5933
5934 // Visit the dominator subtree rooted at Node in pre-order.
5935 // If TLSBaseAddrReg is non-null, then use that to replace any
5936 // TLS_base_addr instructions. Otherwise, create the register
5937 // when the first such instruction is seen, and then use it
5938 // as we encounter more instructions.
5939 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5940 MachineBasicBlock *BB = Node->getBlock();
5941 bool Changed = false;
5942
5943 // Traverse the current block.
5944 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5945 ++I) {
5946 switch (I->getOpcode()) {
5947 case X86::TLS_base_addr32:
5948 case X86::TLS_base_addr64:
5949 if (TLSBaseAddrReg)
5950 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5951 else
5952 I = SetRegister(I, &TLSBaseAddrReg);
5953 Changed = true;
5954 break;
5955 default:
5956 break;
5957 }
5958 }
5959
5960 // Visit the children of this block in the dominator tree.
5961 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5962 I != E; ++I) {
5963 Changed |= VisitNode(*I, TLSBaseAddrReg);
5964 }
5965
5966 return Changed;
5967 }
5968
5969 // Replace the TLS_base_addr instruction I with a copy from
5970 // TLSBaseAddrReg, returning the new instruction.
5971 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5972 unsigned TLSBaseAddrReg) {
5973 MachineFunction *MF = I->getParent()->getParent();
5974 const X86TargetMachine *TM =
5975 static_cast<const X86TargetMachine *>(&MF->getTarget());
5976 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]5977 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5978
5979 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5980 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5981 TII->get(TargetOpcode::COPY),
5982 is64Bit ? X86::RAX : X86::EAX)
5983 .addReg(TLSBaseAddrReg);
5984
5985 // Erase the TLS_base_addr instruction.
5986 I->eraseFromParent();
5987
5988 return Copy;
5989 }
5990
5991 // Create a virtal register in *TLSBaseAddrReg, and populate it by
5992 // inserting a copy instruction after I. Returns the new instruction.
5993 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5994 MachineFunction *MF = I->getParent()->getParent();
5995 const X86TargetMachine *TM =
5996 static_cast<const X86TargetMachine *>(&MF->getTarget());
5997 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]5998 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]5999
6000 // Create a virtual register for the TLS base address.
6001 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6002 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6003 ? &X86::GR64RegClass
6004 : &X86::GR32RegClass);
6005
6006 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6007 MachineInstr *Next = I->getNextNode();
6008 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6009 TII->get(TargetOpcode::COPY),
6010 *TLSBaseAddrReg)
6011 .addReg(is64Bit ? X86::RAX : X86::EAX);
6012
6013 return Copy;
6014 }
6015
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6016 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6017 return "Local Dynamic TLS Access Clean-up";
6018 }
6019
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6020 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6021 AU.setPreservesCFG();
6022 AU.addRequired<MachineDominatorTree>();
6023 MachineFunctionPass::getAnalysisUsage(AU);
6024 }
6025 };
6026}
6027
6028char LDTLSCleanup::ID = 0;
6029FunctionPass*
6030llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }