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Jia Liub22310f2012-02-18 12:03:15 +00001//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
Michael J. Spencerb88784c2011-04-14 14:33:36 +00002//
John Criswell29265fe2003-10-21 15:17:13 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Michael J. Spencerb88784c2011-04-14 14:33:36 +00007//
John Criswell29265fe2003-10-21 15:17:13 +00008//===----------------------------------------------------------------------===//
Chris Lattner5da8e802003-08-03 15:47:49 +00009//
Craig Topper271064e2011-10-11 06:44:02 +000010// This is a target description file for the Intel i386 architecture, referred
11// to here as the "X86" architecture.
Chris Lattner5da8e802003-08-03 15:47:49 +000012//
13//===----------------------------------------------------------------------===//
14
Chris Lattner25510802003-08-04 04:59:56 +000015// Get the target-independent interfaces which we are implementing...
Chris Lattner5da8e802003-08-03 15:47:49 +000016//
Evan Cheng977e7be2008-11-24 07:34:46 +000017include "llvm/Target/Target.td"
Chris Lattner5da8e802003-08-03 15:47:49 +000018
19//===----------------------------------------------------------------------===//
Anitha Boyapati426feb62012-08-16 03:50:04 +000020// X86 Subtarget state
Evan Cheng13bcc6c2011-07-07 21:06:52 +000021//
22
23def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
Craig Topper3c80d622014-01-06 04:55:54 +000025def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
Evan Cheng13bcc6c2011-07-07 21:06:52 +000029
30//===----------------------------------------------------------------------===//
Anitha Boyapati426feb62012-08-16 03:50:04 +000031// X86 Subtarget features
Bill Wendlinge6182262007-05-04 20:38:40 +000032//===----------------------------------------------------------------------===//
Chris Lattnercc8c5812009-09-02 05:53:04 +000033
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +000034def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
35 "Enable X87 float instructions">;
36
Chris Lattnercc8c5812009-09-02 05:53:04 +000037def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
38 "Enable conditional move instructions">;
39
Benjamin Kramer2f489232010-12-04 20:32:23 +000040def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
41 "Support POPCNT instruction">;
42
Craig Topper09b65982015-10-16 06:03:09 +000043def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
44 "Support fxsave/fxrestore instructions">;
45
Amjad Aboud1db6d7a2015-10-12 11:47:46 +000046def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
47 "Support xsave instructions">;
48
49def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
50 "Support xsaveopt instructions">;
51
52def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
53 "Support xsavec instructions">;
54
55def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
56 "Support xsaves instructions">;
57
Bill Wendlinge6182262007-05-04 20:38:40 +000058def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
59 "Enable SSE instructions",
Chris Lattnercc8c5812009-09-02 05:53:04 +000060 // SSE codegen depends on cmovs, and all
Michael J. Spencerb88784c2011-04-14 14:33:36 +000061 // SSE1+ processors support them.
Eric Christopher11e59832015-10-08 20:10:06 +000062 [FeatureCMOV]>;
Bill Wendlinge6182262007-05-04 20:38:40 +000063def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
64 "Enable SSE2 instructions",
65 [FeatureSSE1]>;
66def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
67 "Enable SSE3 instructions",
68 [FeatureSSE2]>;
69def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
70 "Enable SSSE3 instructions",
71 [FeatureSSE3]>;
Rafael Espindola94a2c562013-08-23 20:21:34 +000072def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
Nate Begemane14fdfa2008-02-03 07:18:54 +000073 "Enable SSE 4.1 instructions",
74 [FeatureSSSE3]>;
Rafael Espindola94a2c562013-08-23 20:21:34 +000075def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
Nate Begemane14fdfa2008-02-03 07:18:54 +000076 "Enable SSE 4.2 instructions",
Craig Topper7bd33052011-12-29 15:51:45 +000077 [FeatureSSE41]>;
Eric Christopher57a6e132015-11-14 03:04:00 +000078// The MMX subtarget feature is separate from the rest of the SSE features
79// because it's important (for odd compatibility reasons) to be able to
80// turn it off explicitly while allowing SSE+ to be on.
81def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
82 "Enable MMX instructions">;
Bill Wendlinge6182262007-05-04 20:38:40 +000083def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
Michael J. Spencer30088ba2011-04-15 00:32:41 +000084 "Enable 3DNow! instructions",
85 [FeatureMMX]>;
Bill Wendlinge6182262007-05-04 20:38:40 +000086def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
Bill Wendlingf985c492007-05-06 07:56:19 +000087 "Enable 3DNow! Athlon instructions",
88 [Feature3DNow]>;
Dan Gohman74037512009-02-03 00:04:43 +000089// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
90// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
91// without disabling 64-bit mode.
Bill Wendlingf985c492007-05-06 07:56:19 +000092def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
Chris Lattner77f7dba2010-03-14 22:24:34 +000093 "Support 64-bit instructions",
94 [FeatureCMOV]>;
Nick Lewycky3be42b82013-10-05 20:11:44 +000095def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
Eli Friedman5e570422011-08-26 21:21:21 +000096 "64-bit with cmpxchg16b",
97 [Feature64Bit]>;
Evan Cheng4c91aa32009-01-02 05:35:45 +000098def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
99 "Bit testing of memory is slow">;
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000100def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
101 "SHLD instruction is slow">;
Zvi Rackover8bc7e4d2016-12-06 19:35:20 +0000102def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
103 "PMULLD instruction is slow">;
Sanjay Patel30145672015-09-01 20:51:51 +0000104// FIXME: This should not apply to CPUs that do not have SSE.
105def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
106 "IsUAMem16Slow", "true",
107 "Slow unaligned 16-byte memory access">;
Sanjay Patel501890e2014-11-21 17:40:04 +0000108def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000109 "IsUAMem32Slow", "true",
110 "Slow unaligned 32-byte memory access">;
Stefanus Du Toit96180b52009-05-26 21:04:35 +0000111def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
Craig Toppera5d1fc22011-12-30 07:16:00 +0000112 "Support SSE 4a instructions",
113 [FeatureSSE3]>;
Evan Chengff1beda2006-10-06 09:17:41 +0000114
Craig Topperf287a452012-01-09 09:02:13 +0000115def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
116 "Enable AVX instructions",
117 [FeatureSSE42]>;
118def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
Craig Topper228d9132011-10-30 19:57:21 +0000119 "Enable AVX2 instructions",
120 [FeatureAVX]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000121def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000122 "Enable AVX-512 instructions",
123 [FeatureAVX2]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000124def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000125 "Enable AVX-512 Exponential and Reciprocal Instructions",
126 [FeatureAVX512]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000127def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000128 "Enable AVX-512 Conflict Detection Instructions",
129 [FeatureAVX512]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000130def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000131 "Enable AVX-512 PreFetch Instructions",
132 [FeatureAVX512]>;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000133def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
134 "true",
135 "Prefetch with Intent to Write and T1 Hint">;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000136def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
137 "Enable AVX-512 Doubleword and Quadword Instructions",
138 [FeatureAVX512]>;
139def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
140 "Enable AVX-512 Byte and Word Instructions",
141 [FeatureAVX512]>;
142def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
143 "Enable AVX-512 Vector Length eXtensions",
144 [FeatureAVX512]>;
Michael Zuckerman97b6a6922016-01-17 13:42:12 +0000145def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
Craig Topper5c842be2016-11-09 04:50:48 +0000146 "Enable AVX-512 Vector Byte Manipulation Instructions",
147 [FeatureBWI]>;
Craig Topper3bb3f732016-02-08 01:23:15 +0000148def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000149 "Enable AVX-512 Integer Fused Multiple-Add",
150 [FeatureAVX512]>;
Asaf Badouh5acf66f2015-12-15 13:35:29 +0000151def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
152 "Enable protection keys">;
Benjamin Kramera0396e42012-05-31 14:34:17 +0000153def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
154 "Enable packed carry-less multiplication instructions",
Craig Topper29dd1482012-05-01 05:28:32 +0000155 [FeatureSSE2]>;
Craig Topper79dbb0c2012-06-03 18:58:46 +0000156def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
Craig Toppere1bd0512011-12-29 19:46:19 +0000157 "Enable three-operand fused multiple-add",
158 [FeatureAVX]>;
David Greene8f6f72c2009-06-26 22:46:54 +0000159def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
Craig Toppera5d1fc22011-12-30 07:16:00 +0000160 "Enable four-operand fused multiple-add",
Craig Topperbae0e9e2012-05-01 06:54:48 +0000161 [FeatureAVX, FeatureSSE4A]>;
Craig Toppera5d1fc22011-12-30 07:16:00 +0000162def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
Craig Topper43518cc2012-05-01 05:41:41 +0000163 "Enable XOP instructions",
Anitha Boyapatiaf3e9832012-08-16 04:04:02 +0000164 [FeatureFMA4]>;
Sanjay Patelffd039b2015-02-03 17:13:04 +0000165def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
166 "HasSSEUnalignedMem", "true",
167 "Allow unaligned memory operands with SSE instructions">;
Eric Christopher2ef63182010-04-02 21:54:27 +0000168def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
Craig Topper29dd1482012-05-01 05:28:32 +0000169 "Enable AES instructions",
170 [FeatureSSE2]>;
Yunzhong Gaodd36e932013-09-24 18:21:52 +0000171def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
172 "Enable TBM instructions">;
Craig Topper786bdb92011-10-03 17:28:23 +0000173def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
174 "Support MOVBE instruction">;
Rafael Espindola94a2c562013-08-23 20:21:34 +0000175def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
Craig Topper786bdb92011-10-03 17:28:23 +0000176 "Support RDRAND instruction">;
Craig Topperfe9179f2011-10-09 07:31:39 +0000177def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
Craig Toppera6d204e2013-09-16 04:29:58 +0000178 "Support 16-bit floating point conversion instructions",
179 [FeatureAVX]>;
Craig Topper228d9132011-10-30 19:57:21 +0000180def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
181 "Support FS/GS Base instructions">;
Craig Topper271064e2011-10-11 06:44:02 +0000182def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
183 "Support LZCNT instruction">;
Craig Topper3657fe42011-10-14 03:21:46 +0000184def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
185 "Support BMI instructions">;
Craig Topperaea148c2011-10-16 07:55:05 +0000186def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
187 "Support BMI2 instructions">;
Michael Liao73cffdd2012-11-08 07:28:54 +0000188def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
189 "Support RTM instructions">;
Kay Tiong Khoof809c642013-02-14 19:08:21 +0000190def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
191 "Support ADX instructions">;
Ben Langmuir16501752013-09-12 15:51:31 +0000192def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
193 "Enable SHA instructions",
194 [FeatureSSE2]>;
Michael Liao5173ee02013-03-26 17:47:11 +0000195def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
196 "Support PRFCHW instructions">;
Michael Liaoa486a112013-03-28 23:41:26 +0000197def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
198 "Support RDSEED instruction">;
Hans Wennborg5000ce82015-12-04 23:00:33 +0000199def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
200 "Support LAHF and SAHF instructions">;
Ashutosh Nema348af9c2016-05-18 11:59:12 +0000201def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
202 "Enable MONITORX/MWAITX timer functionality">;
Craig Topper50f3d142017-02-09 04:27:34 +0000203def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true",
204 "Enable Cache Line Zero">;
Elena Demikhovskyf7e641c2015-06-03 10:30:57 +0000205def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
206 "Support MPX instructions">;
Sanjay Patel53d1d8b2015-10-12 15:24:01 +0000207def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
Evan Cheng1b81fdd2012-02-07 22:50:41 +0000208 "Use LEA for adjusting the stack pointer">;
Alexey Volkovfd1731d2014-11-21 11:19:34 +0000209def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
210 "HasSlowDivide32", "true",
211 "Use 8-bit divide for positive values less than 256">;
Nikolai Bozhenov6bdf92c2017-01-12 19:34:15 +0000212def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
Alexey Volkovfd1731d2014-11-21 11:19:34 +0000213 "HasSlowDivide64", "true",
Nikolai Bozhenov6bdf92c2017-01-12 19:34:15 +0000214 "Use 32-bit divide for positive values less than 2^32">;
Preston Gurda01daac2013-01-08 18:27:24 +0000215def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
216 "PadShortFunctions", "true",
217 "Pad short functions">;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000218def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
219 "Enable Software Guard Extensions">;
220def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
221 "Flush A Cache Line Optimized">;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000222def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
223 "Cache Line Write Back">;
Michael Kuperstein454d1452015-07-23 12:23:45 +0000224// TODO: This feature ought to be renamed.
Sean Silvae1c6b542015-07-27 00:46:59 +0000225// What it really refers to are CPUs for which certain instructions
226// (which ones besides the example below?) are microcoded.
Michael Kuperstein454d1452015-07-23 12:23:45 +0000227// The best examples of this are the memory forms of CALL and PUSH
228// instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
Preston Gurd663e6f92013-03-27 19:14:02 +0000229def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
230 "CallRegIndirect", "true",
231 "Call register indirect">;
Preston Gurd8b7ab4b2013-04-25 20:29:37 +0000232def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
233 "LEA instruction needs inputs at AG stage">;
Alexey Volkov6226de62014-05-20 08:55:50 +0000234def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
235 "LEA instruction with certain arguments is slow">;
Alexey Volkov5260dba2014-06-09 11:40:41 +0000236def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
237 "INC and DEC instructions are slower than ADD and SUB">;
Eric Christopher824f42f2015-05-12 01:26:05 +0000238def FeatureSoftFloat
239 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
240 "Use software floating point features.">;
Amjad Aboud4f977512017-03-03 09:03:24 +0000241// On some X86 processors, there is no performance hazard to writing only the
242// lower parts of a YMM or ZMM register without clearing the upper part.
243def FeatureFastPartialYMMorZMMWrite
244 : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
245 "HasFastPartialYMMorZMMWrite",
246 "true", "Partial writes to YMM/ZMM registers are fast">;
Nikolai Bozhenovf6795302016-08-04 12:47:28 +0000247// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
248// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
249// vector FSQRT has higher throughput than the corresponding NR code.
250// The idea is that throughput bound code is likely to be vectorized, so for
251// vectorized code we should care about the throughput of SQRT operations.
252// But if the code is scalar that probably means that the code has some kind of
253// dependency and we should care more about reducing the latency.
254def FeatureFastScalarFSQRT
255 : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
256 "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
257def FeatureFastVectorFSQRT
258 : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
259 "true", "Vector SQRT is fast (disable Newton-Raphson)">;
Pierre Gousseaub6d652a2016-10-14 16:41:38 +0000260// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
261// be used to replace test/set sequences.
262def FeatureFastLZCNT
263 : SubtargetFeature<
264 "fast-lzcnt", "HasFastLZCNT", "true",
265 "LZCNT instructions are as fast as most simple integer ops">;
David Greene8f6f72c2009-06-26 22:46:54 +0000266
Craig Topperd88389a2017-02-21 06:39:13 +0000267
268// Sandy Bridge and newer processors can use SHLD with the same source on both
269// inputs to implement rotate to avoid the partial flag update of the normal
270// rotate instructions.
271def FeatureFastSHLDRotate
272 : SubtargetFeature<
273 "fast-shld-rotate", "HasFastSHLDRotate", "true",
274 "SHLD can be used as a faster rotate">;
275
Clement Courbet203fc172017-04-21 09:20:50 +0000276// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
277// "string operations"). See "REP String Enhancement" in the Intel Software
Clement Courbet41b43332017-04-21 09:21:05 +0000278// Development Manual. This feature essentially means that REP MOVSB will copy
Clement Courbet203fc172017-04-21 09:20:50 +0000279// using the largest available size instead of copying bytes one by one, making
280// it at least as fast as REPMOVS{W,D,Q}.
281def FeatureERMSB
Clement Courbet1ce3b822017-04-21 09:20:39 +0000282 : SubtargetFeature<
Clement Courbet203fc172017-04-21 09:20:50 +0000283 "ermsb", "HasERMSB", "true",
Clement Courbet1ce3b822017-04-21 09:20:39 +0000284 "REP MOVS/STOS are fast">;
285
Evan Chengff1beda2006-10-06 09:17:41 +0000286//===----------------------------------------------------------------------===//
287// X86 processors supported.
288//===----------------------------------------------------------------------===//
289
Andrew Trick8523b162012-02-01 23:20:51 +0000290include "X86Schedule.td"
291
292def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
293 "Intel Atom processors">;
Preston Gurd3fe264d2013-09-13 19:23:28 +0000294def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
295 "Intel Silvermont processors">;
Andrew Trick8523b162012-02-01 23:20:51 +0000296
Evan Chengff1beda2006-10-06 09:17:41 +0000297class Proc<string Name, list<SubtargetFeature> Features>
Andrew Trick87255e32012-07-07 04:00:00 +0000298 : ProcessorModel<Name, GenericModel, Features>;
Andrew Trick8523b162012-02-01 23:20:51 +0000299
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000300def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>;
301def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>;
302def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>;
303def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
304def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
305def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
306def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>;
307def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
308def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
309 FeatureCMOV, FeatureFXSR]>;
310def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
311 FeatureSSE1, FeatureFXSR]>;
312def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
313 FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
Mitch Bodarte60465d2016-04-27 22:52:35 +0000314
315// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
316// The intent is to enable it for pentium4 which is the current default
317// processor in a vanilla 32-bit clang compilation when no specific
318// architecture is specified. This generally gives a nice performance
319// increase on silvermont, with largely neutral behavior on other
320// contemporary large core processors.
321// pentium-m, pentium4m, prescott and nocona are included as a preventative
322// measure to avoid performance surprises, in case clang's default cpu
323// changes slightly.
324
325def : ProcessorModel<"pentium-m", GenericPostRAModel,
326 [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
327 FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
328
329def : ProcessorModel<"pentium4", GenericPostRAModel,
330 [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
331 FeatureSSE2, FeatureFXSR]>;
332
333def : ProcessorModel<"pentium4m", GenericPostRAModel,
334 [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
335 FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
Chandler Carruth32908d72014-05-07 17:37:03 +0000336
Andrey Turetskiy958eb462016-04-01 10:16:15 +0000337// Intel Quark.
338def : Proc<"lakemont", []>;
339
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000340// Intel Core Duo.
Craig Topper09b65982015-10-16 06:03:09 +0000341def : ProcessorModel<"yonah", SandyBridgeModel,
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000342 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
343 FeatureFXSR, FeatureSlowBTMem]>;
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000344
345// NetBurst.
Mitch Bodarte60465d2016-04-27 22:52:35 +0000346def : ProcessorModel<"prescott", GenericPostRAModel,
347 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
348 FeatureFXSR, FeatureSlowBTMem]>;
349def : ProcessorModel<"nocona", GenericPostRAModel, [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000350 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000351 FeatureSlowUAMem16,
352 FeatureMMX,
353 FeatureSSE3,
Craig Topper09b65982015-10-16 06:03:09 +0000354 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000355 FeatureCMPXCHG16B,
356 FeatureSlowBTMem
357]>;
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000358
359// Intel Core 2 Solo/Duo.
Eric Christopher11e59832015-10-08 20:10:06 +0000360def : ProcessorModel<"core2", SandyBridgeModel, [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000361 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000362 FeatureSlowUAMem16,
363 FeatureMMX,
364 FeatureSSSE3,
Craig Topper09b65982015-10-16 06:03:09 +0000365 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000366 FeatureCMPXCHG16B,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000367 FeatureSlowBTMem,
368 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000369]>;
370def : ProcessorModel<"penryn", SandyBridgeModel, [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000371 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000372 FeatureSlowUAMem16,
373 FeatureMMX,
374 FeatureSSE41,
Craig Topper09b65982015-10-16 06:03:09 +0000375 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000376 FeatureCMPXCHG16B,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000377 FeatureSlowBTMem,
378 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000379]>;
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000380
Chandler Carruthaf8924032014-12-09 10:58:36 +0000381// Atom CPUs.
382class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
Eric Christopher11e59832015-10-08 20:10:06 +0000383 ProcIntelAtom,
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000384 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000385 FeatureSlowUAMem16,
386 FeatureMMX,
387 FeatureSSSE3,
Craig Topper09b65982015-10-16 06:03:09 +0000388 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000389 FeatureCMPXCHG16B,
390 FeatureMOVBE,
391 FeatureSlowBTMem,
Sanjay Patel53d1d8b2015-10-12 15:24:01 +0000392 FeatureLEAForSP,
Eric Christopher11e59832015-10-08 20:10:06 +0000393 FeatureSlowDivide32,
394 FeatureSlowDivide64,
395 FeatureCallRegIndirect,
396 FeatureLEAUsesAG,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000397 FeaturePadShortFunctions,
398 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000399]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000400def : BonnellProc<"bonnell">;
401def : BonnellProc<"atom">; // Pin the generic name to the baseline.
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000402
Chandler Carruthaf8924032014-12-09 10:58:36 +0000403class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
Eric Christopher11e59832015-10-08 20:10:06 +0000404 ProcIntelSLM,
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000405 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000406 FeatureMMX,
407 FeatureSSE42,
Craig Topper09b65982015-10-16 06:03:09 +0000408 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000409 FeatureCMPXCHG16B,
410 FeatureMOVBE,
411 FeaturePOPCNT,
412 FeaturePCLMUL,
413 FeatureAES,
414 FeatureSlowDivide64,
415 FeatureCallRegIndirect,
416 FeaturePRFCHW,
417 FeatureSlowLEA,
418 FeatureSlowIncDec,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000419 FeatureSlowBTMem,
Zvi Rackover8bc7e4d2016-12-06 19:35:20 +0000420 FeatureSlowPMULLD,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000421 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000422]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000423def : SilvermontProc<"silvermont">;
424def : SilvermontProc<"slm">; // Legacy alias.
425
Eric Christopher2ef63182010-04-02 21:54:27 +0000426// "Arrandale" along with corei3 and corei5
Craig Topper3611d9b2015-03-30 06:31:11 +0000427class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000428 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000429 FeatureMMX,
430 FeatureSSE42,
Craig Topper09b65982015-10-16 06:03:09 +0000431 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000432 FeatureCMPXCHG16B,
433 FeatureSlowBTMem,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000434 FeaturePOPCNT,
435 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000436]>;
Craig Topper3611d9b2015-03-30 06:31:11 +0000437def : NehalemProc<"nehalem">;
438def : NehalemProc<"corei7">;
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000439
Eric Christopher2ef63182010-04-02 21:54:27 +0000440// Westmere is a similar machine to nehalem with some additional features.
441// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
Chandler Carruthaf8924032014-12-09 10:58:36 +0000442class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000443 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000444 FeatureMMX,
445 FeatureSSE42,
Craig Topper09b65982015-10-16 06:03:09 +0000446 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000447 FeatureCMPXCHG16B,
448 FeatureSlowBTMem,
449 FeaturePOPCNT,
450 FeatureAES,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000451 FeaturePCLMUL,
452 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000453]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000454def : WestmereProc<"westmere">;
455
Craig Topperf730a6b2016-02-13 21:35:37 +0000456class ProcessorFeatures<list<SubtargetFeature> Inherited,
457 list<SubtargetFeature> NewFeatures> {
458 list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
459}
460
461class ProcModel<string Name, SchedMachineModel Model,
462 list<SubtargetFeature> ProcFeatures,
463 list<SubtargetFeature> OtherFeatures> :
464 ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
465
Nate Begeman8b08f522010-12-10 00:26:57 +0000466// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
467// rather than a superset.
Craig Topperf730a6b2016-02-13 21:35:37 +0000468def SNBFeatures : ProcessorFeatures<[], [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000469 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000470 FeatureMMX,
471 FeatureAVX,
Craig Topper09b65982015-10-16 06:03:09 +0000472 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000473 FeatureCMPXCHG16B,
Eric Christopher11e59832015-10-08 20:10:06 +0000474 FeaturePOPCNT,
475 FeatureAES,
Nikolai Bozhenov6bdf92c2017-01-12 19:34:15 +0000476 FeatureSlowDivide64,
Craig Topper0ee35692015-10-14 05:37:38 +0000477 FeaturePCLMUL,
478 FeatureXSAVE,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000479 FeatureXSAVEOPT,
Nikolai Bozhenovf6795302016-08-04 12:47:28 +0000480 FeatureLAHFSAHF,
Craig Topperd88389a2017-02-21 06:39:13 +0000481 FeatureFastScalarFSQRT,
482 FeatureFastSHLDRotate
Eric Christopher11e59832015-10-08 20:10:06 +0000483]>;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000484
Craig Topperf730a6b2016-02-13 21:35:37 +0000485class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
486 SNBFeatures.Value, [
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000487 FeatureSlowBTMem,
488 FeatureSlowUAMem32
489]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000490def : SandyBridgeProc<"sandybridge">;
491def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
Evan Chengff1beda2006-10-06 09:17:41 +0000492
Craig Topperf730a6b2016-02-13 21:35:37 +0000493def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
Eric Christopher11e59832015-10-08 20:10:06 +0000494 FeatureRDRAND,
495 FeatureF16C,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000496 FeatureFSGSBase
497]>;
498
Craig Topperf730a6b2016-02-13 21:35:37 +0000499class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
500 IVBFeatures.Value, [
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000501 FeatureSlowBTMem,
502 FeatureSlowUAMem32
Eric Christopher11e59832015-10-08 20:10:06 +0000503]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000504def : IvyBridgeProc<"ivybridge">;
505def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
Craig Topper3657fe42011-10-14 03:21:46 +0000506
Craig Topperf730a6b2016-02-13 21:35:37 +0000507def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
Eric Christopher11e59832015-10-08 20:10:06 +0000508 FeatureAVX2,
Eric Christopher11e59832015-10-08 20:10:06 +0000509 FeatureBMI,
510 FeatureBMI2,
Clement Courbet203fc172017-04-21 09:20:50 +0000511 FeatureERMSB,
Eric Christopher11e59832015-10-08 20:10:06 +0000512 FeatureFMA,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000513 FeatureLZCNT,
514 FeatureMOVBE,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000515 FeatureSlowIncDec
Eric Christopher11e59832015-10-08 20:10:06 +0000516]>;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000517
Craig Topperf730a6b2016-02-13 21:35:37 +0000518class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
519 HSWFeatures.Value, []>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000520def : HaswellProc<"haswell">;
521def : HaswellProc<"core-avx2">; // Legacy alias.
522
Craig Topperf730a6b2016-02-13 21:35:37 +0000523def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
Eric Christopher11e59832015-10-08 20:10:06 +0000524 FeatureADX,
Craig Topper86576bd2017-02-09 06:50:59 +0000525 FeatureRDSEED
Eric Christopher11e59832015-10-08 20:10:06 +0000526]>;
Craig Topperf730a6b2016-02-13 21:35:37 +0000527class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
528 BDWFeatures.Value, []>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000529def : BroadwellProc<"broadwell">;
530
Craig Topperf730a6b2016-02-13 21:35:37 +0000531def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000532 FeatureMPX,
Eric Christopher58297412017-03-29 07:40:44 +0000533 FeatureRTM,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000534 FeatureXSAVEC,
535 FeatureXSAVES,
536 FeatureSGX,
Nikolai Bozhenovf6795302016-08-04 12:47:28 +0000537 FeatureCLFLUSHOPT,
538 FeatureFastVectorFSQRT
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000539]>;
540
541// FIXME: define SKL model
Craig Topperf730a6b2016-02-13 21:35:37 +0000542class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
543 SKLFeatures.Value, []>;
Sanjoy Dasaa63dc02016-02-21 17:12:03 +0000544def : SkylakeClientProc<"skylake">;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000545
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000546// FIXME: define KNL model
Craig Topperf730a6b2016-02-13 21:35:37 +0000547class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
548 IVBFeatures.Value, [
Eric Christopher11e59832015-10-08 20:10:06 +0000549 FeatureAVX512,
550 FeatureERI,
551 FeatureCDI,
552 FeaturePFI,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000553 FeaturePREFETCHWT1,
554 FeatureADX,
555 FeatureRDSEED,
Eric Christopher11e59832015-10-08 20:10:06 +0000556 FeatureMOVBE,
557 FeatureLZCNT,
558 FeatureBMI,
559 FeatureBMI2,
Amjad Aboud4f977512017-03-03 09:03:24 +0000560 FeatureFMA,
561 FeatureFastPartialYMMorZMMWrite
Eric Christopher11e59832015-10-08 20:10:06 +0000562]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000563def : KnightsLandingProc<"knl">;
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000564
Craig Topperf730a6b2016-02-13 21:35:37 +0000565def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
Eric Christopher11e59832015-10-08 20:10:06 +0000566 FeatureAVX512,
567 FeatureCDI,
568 FeatureDQI,
569 FeatureBWI,
570 FeatureVLX,
Asaf Badouh5acf66f2015-12-15 13:35:29 +0000571 FeaturePKU,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000572 FeatureCLWB
Eric Christopher11e59832015-10-08 20:10:06 +0000573]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000574
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000575// FIXME: define SKX model
Craig Topperf730a6b2016-02-13 21:35:37 +0000576class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
577 SKXFeatures.Value, []>;
Sanjoy Dasaa63dc02016-02-21 17:12:03 +0000578def : SkylakeServerProc<"skylake-avx512">;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000579def : SkylakeServerProc<"skx">; // Legacy alias.
580
Craig Topperf730a6b2016-02-13 21:35:37 +0000581def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
Elena Demikhovsky9242ea82016-01-18 13:00:31 +0000582 FeatureVBMI,
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000583 FeatureIFMA,
584 FeatureSHA
Elena Demikhovsky9242ea82016-01-18 13:00:31 +0000585]>;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000586
Craig Topperf730a6b2016-02-13 21:35:37 +0000587class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
588 CNLFeatures.Value, []>;
Elena Demikhovsky9242ea82016-01-18 13:00:31 +0000589def : CannonlakeProc<"cannonlake">;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000590
591// AMD CPUs.
Robert Khasanovbfa01312014-07-21 14:54:21 +0000592
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000593def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
594def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
595def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
596def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000597 FeatureSlowBTMem, FeatureSlowSHLD]>;
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000598def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000599 FeatureSlowBTMem, FeatureSlowSHLD]>;
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000600def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
601 Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000602 FeatureSlowSHLD]>;
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000603def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
604 Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000605 FeatureSlowSHLD]>;
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000606def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
607 Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000608 FeatureSlowSHLD]>;
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000609def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
610 Feature3DNowA, FeatureFXSR, Feature64Bit,
611 FeatureSlowBTMem, FeatureSlowSHLD]>;
612def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
613 Feature3DNowA, FeatureFXSR, Feature64Bit,
614 FeatureSlowBTMem, FeatureSlowSHLD]>;
615def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
616 Feature3DNowA, FeatureFXSR, Feature64Bit,
617 FeatureSlowBTMem, FeatureSlowSHLD]>;
618def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
619 Feature3DNowA, FeatureFXSR, Feature64Bit,
620 FeatureSlowBTMem, FeatureSlowSHLD]>;
621def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
622 Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
623 FeatureSlowBTMem, FeatureSlowSHLD]>;
624def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
625 Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
626 FeatureSlowBTMem, FeatureSlowSHLD]>;
627def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
628 Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
629 FeatureSlowBTMem, FeatureSlowSHLD]>;
630def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA,
631 FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
632 FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
633 FeatureLAHFSAHF]>;
634def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA,
635 FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
636 FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
637 FeatureLAHFSAHF]>;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000638
Benjamin Kramer077ae1d2012-01-10 11:50:02 +0000639// Bobcat
Eric Christopher11e59832015-10-08 20:10:06 +0000640def : Proc<"btver1", [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000641 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000642 FeatureMMX,
643 FeatureSSSE3,
644 FeatureSSE4A,
Craig Topper09b65982015-10-16 06:03:09 +0000645 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000646 FeatureCMPXCHG16B,
647 FeaturePRFCHW,
648 FeatureLZCNT,
649 FeaturePOPCNT,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000650 FeatureSlowSHLD,
651 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000652]>;
Sanjay Patel1191adf2014-09-09 20:07:07 +0000653
Benjamin Kramerb44c4272013-05-03 10:20:08 +0000654// Jaguar
Eric Christopher11e59832015-10-08 20:10:06 +0000655def : ProcessorModel<"btver2", BtVer2Model, [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000656 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000657 FeatureMMX,
658 FeatureAVX,
Craig Topper09b65982015-10-16 06:03:09 +0000659 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000660 FeatureSSE4A,
661 FeatureCMPXCHG16B,
662 FeaturePRFCHW,
663 FeatureAES,
664 FeaturePCLMUL,
665 FeatureBMI,
666 FeatureF16C,
667 FeatureMOVBE,
668 FeatureLZCNT,
Pierre Gousseaub6d652a2016-10-14 16:41:38 +0000669 FeatureFastLZCNT,
Eric Christopher11e59832015-10-08 20:10:06 +0000670 FeaturePOPCNT,
Craig Topper0ee35692015-10-14 05:37:38 +0000671 FeatureXSAVE,
672 FeatureXSAVEOPT,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000673 FeatureSlowSHLD,
Yunzhong Gao0de36ec2016-02-12 23:37:57 +0000674 FeatureLAHFSAHF,
Amjad Aboud4f977512017-03-03 09:03:24 +0000675 FeatureFastPartialYMMorZMMWrite
Eric Christopher11e59832015-10-08 20:10:06 +0000676]>;
Sanjay Patele57f3c02014-11-28 18:40:18 +0000677
Benjamin Kramer077ae1d2012-01-10 11:50:02 +0000678// Bulldozer
Eric Christopher11e59832015-10-08 20:10:06 +0000679def : Proc<"bdver1", [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000680 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000681 FeatureXOP,
682 FeatureFMA4,
683 FeatureCMPXCHG16B,
684 FeatureAES,
685 FeaturePRFCHW,
686 FeaturePCLMUL,
687 FeatureMMX,
688 FeatureAVX,
Craig Topper09b65982015-10-16 06:03:09 +0000689 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000690 FeatureSSE4A,
691 FeatureLZCNT,
692 FeaturePOPCNT,
Craig Topper0ee35692015-10-14 05:37:38 +0000693 FeatureXSAVE,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000694 FeatureSlowSHLD,
695 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000696]>;
Benjamin Kramerb44c4272013-05-03 10:20:08 +0000697// Piledriver
Eric Christopher11e59832015-10-08 20:10:06 +0000698def : Proc<"bdver2", [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000699 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000700 FeatureXOP,
701 FeatureFMA4,
702 FeatureCMPXCHG16B,
703 FeatureAES,
704 FeaturePRFCHW,
705 FeaturePCLMUL,
706 FeatureMMX,
707 FeatureAVX,
Craig Topper09b65982015-10-16 06:03:09 +0000708 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000709 FeatureSSE4A,
710 FeatureF16C,
711 FeatureLZCNT,
712 FeaturePOPCNT,
Craig Topper0ee35692015-10-14 05:37:38 +0000713 FeatureXSAVE,
Eric Christopher11e59832015-10-08 20:10:06 +0000714 FeatureBMI,
715 FeatureTBM,
716 FeatureFMA,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000717 FeatureSlowSHLD,
718 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000719]>;
Benjamin Kramerd114def2013-11-04 10:29:20 +0000720
721// Steamroller
Eric Christopher11e59832015-10-08 20:10:06 +0000722def : Proc<"bdver3", [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000723 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000724 FeatureXOP,
725 FeatureFMA4,
726 FeatureCMPXCHG16B,
727 FeatureAES,
728 FeaturePRFCHW,
729 FeaturePCLMUL,
730 FeatureMMX,
731 FeatureAVX,
Craig Topper09b65982015-10-16 06:03:09 +0000732 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000733 FeatureSSE4A,
734 FeatureF16C,
735 FeatureLZCNT,
736 FeaturePOPCNT,
Craig Topper0ee35692015-10-14 05:37:38 +0000737 FeatureXSAVE,
Eric Christopher11e59832015-10-08 20:10:06 +0000738 FeatureBMI,
739 FeatureTBM,
740 FeatureFMA,
Craig Topper0ee35692015-10-14 05:37:38 +0000741 FeatureXSAVEOPT,
Eric Christopher11e59832015-10-08 20:10:06 +0000742 FeatureSlowSHLD,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000743 FeatureFSGSBase,
744 FeatureLAHFSAHF
Eric Christopher11e59832015-10-08 20:10:06 +0000745]>;
Benjamin Kramerd114def2013-11-04 10:29:20 +0000746
Benjamin Kramer60045732014-05-02 15:47:07 +0000747// Excavator
Eric Christopher11e59832015-10-08 20:10:06 +0000748def : Proc<"bdver4", [
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000749 FeatureX87,
Eric Christopher11e59832015-10-08 20:10:06 +0000750 FeatureMMX,
751 FeatureAVX2,
Craig Topper09b65982015-10-16 06:03:09 +0000752 FeatureFXSR,
Eric Christopher11e59832015-10-08 20:10:06 +0000753 FeatureXOP,
754 FeatureFMA4,
755 FeatureCMPXCHG16B,
756 FeatureAES,
757 FeaturePRFCHW,
758 FeaturePCLMUL,
759 FeatureF16C,
760 FeatureLZCNT,
761 FeaturePOPCNT,
Craig Topper0ee35692015-10-14 05:37:38 +0000762 FeatureXSAVE,
Eric Christopher11e59832015-10-08 20:10:06 +0000763 FeatureBMI,
764 FeatureBMI2,
765 FeatureTBM,
766 FeatureFMA,
Craig Topper0ee35692015-10-14 05:37:38 +0000767 FeatureXSAVEOPT,
Simon Pilgrim381a0ad2016-07-24 16:00:53 +0000768 FeatureSlowSHLD,
Hans Wennborg5000ce82015-12-04 23:00:33 +0000769 FeatureFSGSBase,
Ashutosh Nema348af9c2016-05-18 11:59:12 +0000770 FeatureLAHFSAHF,
771 FeatureMWAITX
Eric Christopher11e59832015-10-08 20:10:06 +0000772]>;
Benjamin Kramer60045732014-05-02 15:47:07 +0000773
Craig Topperd55b8312017-01-10 06:01:16 +0000774// TODO: The scheduler model falls to BTVER2 model.
775// The znver1 model has to be put in place.
776// Zen
777def: ProcessorModel<"znver1", BtVer2Model, [
778 FeatureADX,
779 FeatureAES,
780 FeatureAVX2,
781 FeatureBMI,
782 FeatureBMI2,
783 FeatureCLFLUSHOPT,
Craig Topper50f3d142017-02-09 04:27:34 +0000784 FeatureCLZERO,
Craig Topperd55b8312017-01-10 06:01:16 +0000785 FeatureCMPXCHG16B,
786 FeatureF16C,
787 FeatureFMA,
788 FeatureFSGSBase,
789 FeatureFXSR,
790 FeatureFastLZCNT,
791 FeatureLAHFSAHF,
792 FeatureLZCNT,
793 FeatureMMX,
794 FeatureMOVBE,
795 FeatureMWAITX,
796 FeaturePCLMUL,
797 FeaturePOPCNT,
798 FeaturePRFCHW,
799 FeatureRDRAND,
800 FeatureRDSEED,
801 FeatureSHA,
Craig Topperd55b8312017-01-10 06:01:16 +0000802 FeatureSSE4A,
803 FeatureSlowSHLD,
804 FeatureX87,
805 FeatureXSAVE,
806 FeatureXSAVEC,
807 FeatureXSAVEOPT,
808 FeatureXSAVES]>;
809
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000810def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
Evan Chengff1beda2006-10-06 09:17:41 +0000811
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000812def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
813def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
814def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
815def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
816 FeatureSSE1, FeatureFXSR]>;
Evan Chengff1beda2006-10-06 09:17:41 +0000817
Chandler Carruth32908d72014-05-07 17:37:03 +0000818// We also provide a generic 64-bit specific x86 processor model which tries to
819// be good for modern chips without enabling instruction set encodings past the
820// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
821// modern 64-bit x86 chip, and enables features that are generally beneficial.
Michael Liao5bf95782014-12-04 05:20:33 +0000822//
Chandler Carruth32908d72014-05-07 17:37:03 +0000823// We currently use the Sandy Bridge model as the default scheduling model as
824// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
825// covers a huge swath of x86 processors. If there are specific scheduling
826// knobs which need to be tuned differently for AMD chips, we might consider
827// forming a common base for them.
Craig Topper09b65982015-10-16 06:03:09 +0000828def : ProcessorModel<"x86-64", SandyBridgeModel,
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000829 [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
830 Feature64Bit, FeatureSlowBTMem ]>;
Chandler Carruth32908d72014-05-07 17:37:03 +0000831
Evan Chengff1beda2006-10-06 09:17:41 +0000832//===----------------------------------------------------------------------===//
Chris Lattner5da8e802003-08-03 15:47:49 +0000833// Register File Description
834//===----------------------------------------------------------------------===//
835
836include "X86RegisterInfo.td"
Igor Bregerb4442f32017-02-10 07:05:56 +0000837include "X86RegisterBanks.td"
Chris Lattner5da8e802003-08-03 15:47:49 +0000838
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000839//===----------------------------------------------------------------------===//
840// Instruction Descriptions
841//===----------------------------------------------------------------------===//
842
Chris Lattner59a4a912003-08-03 21:54:21 +0000843include "X86InstrInfo.td"
844
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +0000845def X86InstrInfo : InstrInfo;
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000846
Chris Lattner5d00a0b2007-02-26 18:17:14 +0000847//===----------------------------------------------------------------------===//
848// Calling Conventions
849//===----------------------------------------------------------------------===//
850
851include "X86CallingConv.td"
852
853
854//===----------------------------------------------------------------------===//
Jim Grosbach4cf25f52010-10-30 13:48:28 +0000855// Assembly Parser
Chris Lattner5d00a0b2007-02-26 18:17:14 +0000856//===----------------------------------------------------------------------===//
857
Devang Patel85d684a2012-01-09 19:13:28 +0000858def ATTAsmParserVariant : AsmParserVariant {
Daniel Dunbar00331992009-07-29 00:02:19 +0000859 int Variant = 0;
Daniel Dunbare4318712009-08-11 20:59:47 +0000860
Chad Rosier9f7a2212013-04-18 22:35:36 +0000861 // Variant name.
862 string Name = "att";
863
Daniel Dunbare4318712009-08-11 20:59:47 +0000864 // Discard comments in assembly strings.
865 string CommentDelimiter = "#";
866
867 // Recognize hard coded registers.
868 string RegisterPrefix = "%";
Daniel Dunbar00331992009-07-29 00:02:19 +0000869}
870
Devang Patel67bf992a2012-01-10 17:51:54 +0000871def IntelAsmParserVariant : AsmParserVariant {
872 int Variant = 1;
873
Chad Rosier9f7a2212013-04-18 22:35:36 +0000874 // Variant name.
875 string Name = "intel";
876
Devang Patel67bf992a2012-01-10 17:51:54 +0000877 // Discard comments in assembly strings.
878 string CommentDelimiter = ";";
879
880 // Recognize hard coded registers.
881 string RegisterPrefix = "";
882}
883
Jim Grosbach4cf25f52010-10-30 13:48:28 +0000884//===----------------------------------------------------------------------===//
885// Assembly Printers
886//===----------------------------------------------------------------------===//
887
Chris Lattner56832602004-10-03 20:36:57 +0000888// The X86 target supports two different syntaxes for emitting machine code.
889// This is controlled by the -x86-asm-syntax={att|intel}
890def ATTAsmWriter : AsmWriter {
Chris Lattner1cbd3de2009-09-13 19:30:11 +0000891 string AsmWriterClassName = "ATTInstPrinter";
Chris Lattner56832602004-10-03 20:36:57 +0000892 int Variant = 0;
893}
894def IntelAsmWriter : AsmWriter {
Chris Lattner13306a12009-09-20 07:47:59 +0000895 string AsmWriterClassName = "IntelInstPrinter";
Chris Lattner56832602004-10-03 20:36:57 +0000896 int Variant = 1;
897}
898
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000899def X86 : Target {
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000900 // Information about the instructions...
Chris Lattner25510802003-08-04 04:59:56 +0000901 let InstructionSet = X86InstrInfo;
Devang Patel67bf992a2012-01-10 17:51:54 +0000902 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
Chris Lattner56832602004-10-03 20:36:57 +0000903 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000904}