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gerrit-public.fairphone.software / toolchain / llvm-project / af892403c2e6ff5974454e398ea5b380378cc489 / . / llvm / lib / Target / X86 / X86.td
blob: 88f831d264288655b42c06711b637605fdafff47 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
Michael J. Spencerb88784c2011-04-14 14:33:36 +0000[diff] [blame]2//
John Criswell29265fe2003-10-21 15:17:13 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Michael J. Spencerb88784c2011-04-14 14:33:36 +0000[diff] [blame]7//
John Criswell29265fe2003-10-21 15:17:13 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattner5da8e802003-08-03 15:47:49 +0000[diff] [blame]9//
Craig Topper271064e2011-10-11 06:44:02 +0000[diff] [blame]10// This is a target description file for the Intel i386 architecture, referred
11// to here as the "X86" architecture.
Chris Lattner5da8e802003-08-03 15:47:49 +0000[diff] [blame]12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner25510802003-08-04 04:59:56 +0000[diff] [blame]15// Get the target-independent interfaces which we are implementing...
Chris Lattner5da8e802003-08-03 15:47:49 +0000[diff] [blame]16//
Evan Cheng977e7be2008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Chris Lattner5da8e802003-08-03 15:47:49 +0000[diff] [blame]18
19//===----------------------------------------------------------------------===//
Anitha Boyapati426feb62012-08-16 03:50:04 +0000[diff] [blame]20// X86 Subtarget state
Evan Cheng13bcc6c2011-07-07 21:06:52 +0000[diff] [blame]21//
22
23def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
Craig Topper3c80d622014-01-06 04:55:54 +0000[diff] [blame]25def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
Evan Cheng13bcc6c2011-07-07 21:06:52 +0000[diff] [blame]29
30//===----------------------------------------------------------------------===//
Anitha Boyapati426feb62012-08-16 03:50:04 +0000[diff] [blame]31// X86 Subtarget features
Bill Wendlinge6182262007-05-04 20:38:40 +0000[diff] [blame]32//===----------------------------------------------------------------------===//
Chris Lattnercc8c5812009-09-02 05:53:04 +0000[diff] [blame]33
34def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
36
Benjamin Kramer2f489232010-12-04 20:32:23 +0000[diff] [blame]37def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
39
David Greene206351a2010-01-11 16:29:42 +0000[diff] [blame]40
Bill Wendlinge6182262007-05-04 20:38:40 +0000[diff] [blame]41def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
42 "Enable MMX instructions">;
43def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
44 "Enable SSE instructions",
Chris Lattnercc8c5812009-09-02 05:53:04 +0000[diff] [blame]45 // SSE codegen depends on cmovs, and all
Michael J. Spencerb88784c2011-04-14 14:33:36 +0000[diff] [blame]46 // SSE1+ processors support them.
Chris Lattnercc8c5812009-09-02 05:53:04 +0000[diff] [blame]47 [FeatureMMX, FeatureCMOV]>;
Bill Wendlinge6182262007-05-04 20:38:40 +0000[diff] [blame]48def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
50 [FeatureSSE1]>;
51def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
52 "Enable SSE3 instructions",
53 [FeatureSSE2]>;
54def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
55 "Enable SSSE3 instructions",
56 [FeatureSSE3]>;
Rafael Espindola94a2c562013-08-23 20:21:34 +0000[diff] [blame]57def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
Nate Begemane14fdfa2008-02-03 07:18:54 +0000[diff] [blame]58 "Enable SSE 4.1 instructions",
59 [FeatureSSSE3]>;
Rafael Espindola94a2c562013-08-23 20:21:34 +0000[diff] [blame]60def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
Nate Begemane14fdfa2008-02-03 07:18:54 +0000[diff] [blame]61 "Enable SSE 4.2 instructions",
Craig Topper7bd33052011-12-29 15:51:45 +0000[diff] [blame]62 [FeatureSSE41]>;
Bill Wendlinge6182262007-05-04 20:38:40 +0000[diff] [blame]63def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
Michael J. Spencer30088ba2011-04-15 00:32:41 +0000[diff] [blame]64 "Enable 3DNow! instructions",
65 [FeatureMMX]>;
Bill Wendlinge6182262007-05-04 20:38:40 +0000[diff] [blame]66def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
Bill Wendlingf985c492007-05-06 07:56:19 +0000[diff] [blame]67 "Enable 3DNow! Athlon instructions",
68 [Feature3DNow]>;
Dan Gohman74037512009-02-03 00:04:43 +0000[diff] [blame]69// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
71// without disabling 64-bit mode.
Bill Wendlingf985c492007-05-06 07:56:19 +0000[diff] [blame]72def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
Chris Lattner77f7dba2010-03-14 22:24:34 +0000[diff] [blame]73 "Support 64-bit instructions",
74 [FeatureCMOV]>;
Nick Lewycky3be42b82013-10-05 20:11:44 +0000[diff] [blame]75def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
Eli Friedman5e570422011-08-26 21:21:21 +0000[diff] [blame]76 "64-bit with cmpxchg16b",
77 [Feature64Bit]>;
Evan Cheng4c91aa32009-01-02 05:35:45 +0000[diff] [blame]78def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
79 "Bit testing of memory is slow">;
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]80def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
Sanjay Patele57f3c02014-11-28 18:40:18 +0000[diff] [blame]82// FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
83// explicit. Also, it seems this would be the default state for most chips
84// going forward, so it would probably be better to negate the logic and
85// match the 32-byte "slow mem" feature below.
Evan Cheng738b0f92010-04-01 05:58:17 +0000[diff] [blame]86def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
87 "IsUAMemFast", "true",
88 "Fast unaligned memory access">;
Sanjay Patel501890e2014-11-21 17:40:04 +0000[diff] [blame]89def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
90 "IsUAMem32Slow", "true",
91 "Slow unaligned 32-byte memory access">;
Stefanus Du Toit96180b52009-05-26 21:04:35 +0000[diff] [blame]92def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
Craig Toppera5d1fc22011-12-30 07:16:00 +0000[diff] [blame]93 "Support SSE 4a instructions",
94 [FeatureSSE3]>;
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]95
Craig Topperf287a452012-01-09 09:02:13 +0000[diff] [blame]96def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
97 "Enable AVX instructions",
98 [FeatureSSE42]>;
99def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
Craig Topper228d9132011-10-30 19:57:21 +0000[diff] [blame]100 "Enable AVX2 instructions",
101 [FeatureAVX]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000[diff] [blame]102def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000[diff] [blame]103 "Enable AVX-512 instructions",
104 [FeatureAVX2]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000[diff] [blame]105def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]106 "Enable AVX-512 Exponential and Reciprocal Instructions",
107 [FeatureAVX512]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000[diff] [blame]108def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]109 "Enable AVX-512 Conflict Detection Instructions",
110 [FeatureAVX512]>;
Craig Topper5c94bb82013-08-21 03:57:57 +0000[diff] [blame]111def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]112 "Enable AVX-512 PreFetch Instructions",
113 [FeatureAVX512]>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]114def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
115 "Enable AVX-512 Doubleword and Quadword Instructions",
116 [FeatureAVX512]>;
117def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
118 "Enable AVX-512 Byte and Word Instructions",
119 [FeatureAVX512]>;
120def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
121 "Enable AVX-512 Vector Length eXtensions",
122 [FeatureAVX512]>;
Benjamin Kramera0396e42012-05-31 14:34:17 +0000[diff] [blame]123def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
124 "Enable packed carry-less multiplication instructions",
Craig Topper29dd1482012-05-01 05:28:32 +0000[diff] [blame]125 [FeatureSSE2]>;
Craig Topper79dbb0c2012-06-03 18:58:46 +0000[diff] [blame]126def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
Craig Toppere1bd0512011-12-29 19:46:19 +0000[diff] [blame]127 "Enable three-operand fused multiple-add",
128 [FeatureAVX]>;
David Greene8f6f72c2009-06-26 22:46:54 +0000[diff] [blame]129def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
Craig Toppera5d1fc22011-12-30 07:16:00 +0000[diff] [blame]130 "Enable four-operand fused multiple-add",
Craig Topperbae0e9e2012-05-01 06:54:48 +0000[diff] [blame]131 [FeatureAVX, FeatureSSE4A]>;
Craig Toppera5d1fc22011-12-30 07:16:00 +0000[diff] [blame]132def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
Craig Topper43518cc2012-05-01 05:41:41 +0000[diff] [blame]133 "Enable XOP instructions",
Anitha Boyapatiaf3e9832012-08-16 04:04:02 +0000[diff] [blame]134 [FeatureFMA4]>;
David Greene206351a2010-01-11 16:29:42 +0000[diff] [blame]135def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
136 "HasVectorUAMem", "true",
137 "Allow unaligned memory operands on vector/SIMD instructions">;
Eric Christopher2ef63182010-04-02 21:54:27 +0000[diff] [blame]138def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
Craig Topper29dd1482012-05-01 05:28:32 +0000[diff] [blame]139 "Enable AES instructions",
140 [FeatureSSE2]>;
Yunzhong Gaodd36e932013-09-24 18:21:52 +0000[diff] [blame]141def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
142 "Enable TBM instructions">;
Craig Topper786bdb92011-10-03 17:28:23 +0000[diff] [blame]143def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
144 "Support MOVBE instruction">;
Rafael Espindola94a2c562013-08-23 20:21:34 +0000[diff] [blame]145def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
Craig Topper786bdb92011-10-03 17:28:23 +0000[diff] [blame]146 "Support RDRAND instruction">;
Craig Topperfe9179f2011-10-09 07:31:39 +0000[diff] [blame]147def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
Craig Toppera6d204e2013-09-16 04:29:58 +0000[diff] [blame]148 "Support 16-bit floating point conversion instructions",
149 [FeatureAVX]>;
Craig Topper228d9132011-10-30 19:57:21 +0000[diff] [blame]150def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
151 "Support FS/GS Base instructions">;
Craig Topper271064e2011-10-11 06:44:02 +0000[diff] [blame]152def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
153 "Support LZCNT instruction">;
Craig Topper3657fe42011-10-14 03:21:46 +0000[diff] [blame]154def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
155 "Support BMI instructions">;
Craig Topperaea148c2011-10-16 07:55:05 +0000[diff] [blame]156def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
157 "Support BMI2 instructions">;
Michael Liao73cffdd2012-11-08 07:28:54 +0000[diff] [blame]158def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
159 "Support RTM instructions">;
Michael Liaoe344ec92013-03-26 22:46:02 +0000[diff] [blame]160def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
161 "Support HLE">;
Kay Tiong Khoof809c642013-02-14 19:08:21 +0000[diff] [blame]162def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
163 "Support ADX instructions">;
Ben Langmuir16501752013-09-12 15:51:31 +0000[diff] [blame]164def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
165 "Enable SHA instructions",
166 [FeatureSSE2]>;
Kevin Enderby0d928a12014-07-31 23:57:38 +0000[diff] [blame]167def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
168 "Support SGX instructions">;
Michael Liao5173ee02013-03-26 17:47:11 +0000[diff] [blame]169def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
170 "Support PRFCHW instructions">;
Michael Liaoa486a112013-03-28 23:41:26 +0000[diff] [blame]171def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
172 "Support RDSEED instruction">;
Robert Khasanov98441b62014-08-21 09:16:12 +0000[diff] [blame]173def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
174 "Support SMAP instructions">;
Evan Cheng1b81fdd2012-02-07 22:50:41 +0000[diff] [blame]175def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
176 "Use LEA for adjusting the stack pointer">;
Alexey Volkovfd1731d2014-11-21 11:19:34 +0000[diff] [blame]177def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
178 "HasSlowDivide32", "true",
179 "Use 8-bit divide for positive values less than 256">;
180def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
181 "HasSlowDivide64", "true",
182 "Use 16-bit divide for positive values less than 65536">;
Preston Gurda01daac2013-01-08 18:27:24 +0000[diff] [blame]183def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
184 "PadShortFunctions", "true",
185 "Pad short functions">;
Preston Gurd663e6f92013-03-27 19:14:02 +0000[diff] [blame]186def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
187 "CallRegIndirect", "true",
188 "Call register indirect">;
Preston Gurd8b7ab4b2013-04-25 20:29:37 +0000[diff] [blame]189def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
190 "LEA instruction needs inputs at AG stage">;
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]191def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
192 "LEA instruction with certain arguments is slow">;
Alexey Volkov5260dba2014-06-09 11:40:41 +0000[diff] [blame]193def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
194 "INC and DEC instructions are slower than ADD and SUB">;
Sanjay Patel957efc232014-10-24 17:02:16 +0000[diff] [blame]195def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
196 "Use RSQRT* to optimize square root calculations">;
Sanjay Patele2e58922014-11-11 20:51:00 +0000[diff] [blame]197def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
198 "true", "Use RCP* to optimize division calculations">;
David Greene8f6f72c2009-06-26 22:46:54 +0000[diff] [blame]199
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]200//===----------------------------------------------------------------------===//
201// X86 processors supported.
202//===----------------------------------------------------------------------===//
203
Andrew Trick8523b162012-02-01 23:20:51 +0000[diff] [blame]204include "X86Schedule.td"
205
206def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
207 "Intel Atom processors">;
Preston Gurd3fe264d2013-09-13 19:23:28 +0000[diff] [blame]208def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
209 "Intel Silvermont processors">;
Andrew Trick8523b162012-02-01 23:20:51 +0000[diff] [blame]210
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]211class Proc<string Name, list<SubtargetFeature> Features>
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]212 : ProcessorModel<Name, GenericModel, Features>;
Andrew Trick8523b162012-02-01 23:20:51 +0000[diff] [blame]213
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]214def : Proc<"generic", []>;
215def : Proc<"i386", []>;
216def : Proc<"i486", []>;
Dale Johannesen28106752008-10-14 22:06:33 +0000[diff] [blame]217def : Proc<"i586", []>;
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]218def : Proc<"pentium", []>;
219def : Proc<"pentium-mmx", [FeatureMMX]>;
220def : Proc<"i686", []>;
Chris Lattnercc8c5812009-09-02 05:53:04 +0000[diff] [blame]221def : Proc<"pentiumpro", [FeatureCMOV]>;
222def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
Bill Wendling3fb7fdf2007-05-22 05:15:37 +0000[diff] [blame]223def : Proc<"pentium3", [FeatureSSE1]>;
Michael J. Spencer99737382011-05-03 03:42:50 +0000[diff] [blame]224def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
Evan Cheng4c91aa32009-01-02 05:35:45 +0000[diff] [blame]225def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
Bill Wendling3fb7fdf2007-05-22 05:15:37 +0000[diff] [blame]226def : Proc<"pentium4", [FeatureSSE2]>;
Michael J. Spencer99737382011-05-03 03:42:50 +0000[diff] [blame]227def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
Chandler Carruth32908d72014-05-07 17:37:03 +0000[diff] [blame]228
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000[diff] [blame]229// Intel Core Duo.
230def : ProcessorModel<"yonah", SandyBridgeModel,
231 [FeatureSSE3, FeatureSlowBTMem]>;
232
233// NetBurst.
234def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
235def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
236
237// Intel Core 2 Solo/Duo.
238def : ProcessorModel<"core2", SandyBridgeModel,
239 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
240def : ProcessorModel<"penryn", SandyBridgeModel,
241 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
242
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]243// Atom CPUs.
244class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
245 ProcIntelAtom,
246 FeatureSSSE3,
247 FeatureCMPXCHG16B,
248 FeatureMOVBE,
249 FeatureSlowBTMem,
250 FeatureLeaForSP,
251 FeatureSlowDivide32,
252 FeatureSlowDivide64,
253 FeatureCallRegIndirect,
254 FeatureLEAUsesAG,
255 FeaturePadShortFunctions
256 ]>;
257def : BonnellProc<"bonnell">;
258def : BonnellProc<"atom">; // Pin the generic name to the baseline.
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000[diff] [blame]259
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]260class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
261 ProcIntelSLM,
262 FeatureSSE42,
263 FeatureCMPXCHG16B,
264 FeatureMOVBE,
265 FeaturePOPCNT,
266 FeaturePCLMUL,
267 FeatureAES,
268 FeatureSlowDivide64,
269 FeatureCallRegIndirect,
270 FeaturePRFCHW,
271 FeatureSlowLEA,
272 FeatureSlowIncDec,
273 FeatureSlowBTMem,
274 FeatureFastUAMem
275 ]>;
276def : SilvermontProc<"silvermont">;
277def : SilvermontProc<"slm">; // Legacy alias.
278
Eric Christopher2ef63182010-04-02 21:54:27 +0000[diff] [blame]279// "Arrandale" along with corei3 and corei5
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]280class NehalemProc<string Name, list<SubtargetFeature> AdditionalFeatures>
281 : ProcessorModel<Name, SandyBridgeModel, !listconcat([
282 FeatureSSE42,
283 FeatureCMPXCHG16B,
284 FeatureSlowBTMem,
285 FeatureFastUAMem,
286 FeaturePOPCNT
287 ],
288 AdditionalFeatures)>;
289def : NehalemProc<"nehalem", []>;
290def : NehalemProc<"corei7", [FeatureAES]>;
Jakob Stoklund Olesen1ac7e662013-03-26 22:19:12 +0000[diff] [blame]291
Eric Christopher2ef63182010-04-02 21:54:27 +0000[diff] [blame]292// Westmere is a similar machine to nehalem with some additional features.
293// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]294class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
295 FeatureSSE42,
296 FeatureCMPXCHG16B,
297 FeatureSlowBTMem,
298 FeatureFastUAMem,
299 FeaturePOPCNT,
300 FeatureAES,
301 FeaturePCLMUL
302 ]>;
303def : WestmereProc<"westmere">;
304
Nate Begeman8b08f522010-12-10 00:26:57 +0000[diff] [blame]305// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
306// rather than a superset.
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]307class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
308 FeatureAVX,
309 FeatureCMPXCHG16B,
310 FeatureFastUAMem,
311 FeatureSlowUAMem32,
312 FeaturePOPCNT,
313 FeatureAES,
314 FeaturePCLMUL
315 ]>;
316def : SandyBridgeProc<"sandybridge">;
317def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]318
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]319class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
320 FeatureAVX,
321 FeatureCMPXCHG16B,
322 FeatureFastUAMem,
323 FeatureSlowUAMem32,
324 FeaturePOPCNT,
325 FeatureAES,
326 FeaturePCLMUL,
327 FeatureRDRAND,
328 FeatureF16C,
329 FeatureFSGSBase
330 ]>;
331def : IvyBridgeProc<"ivybridge">;
332def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
Craig Topper3657fe42011-10-14 03:21:46 +0000[diff] [blame]333
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]334class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
335 FeatureAVX2,
336 FeatureCMPXCHG16B,
337 FeatureFastUAMem,
338 FeaturePOPCNT,
339 FeatureAES,
340 FeaturePCLMUL,
341 FeatureRDRAND,
342 FeatureF16C,
343 FeatureFSGSBase,
344 FeatureMOVBE,
345 FeatureLZCNT,
346 FeatureBMI,
347 FeatureBMI2,
348 FeatureFMA,
349 FeatureRTM,
350 FeatureHLE,
351 FeatureSlowIncDec
352 ]>;
353def : HaswellProc<"haswell">;
354def : HaswellProc<"core-avx2">; // Legacy alias.
355
356class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
357 FeatureAVX2,
358 FeatureCMPXCHG16B,
359 FeatureFastUAMem,
360 FeaturePOPCNT,
361 FeatureAES,
362 FeaturePCLMUL,
363 FeatureRDRAND,
364 FeatureF16C,
365 FeatureFSGSBase,
366 FeatureMOVBE,
367 FeatureLZCNT,
368 FeatureBMI,
369 FeatureBMI2,
370 FeatureFMA,
371 FeatureRTM,
372 FeatureHLE,
373 FeatureADX,
374 FeatureRDSEED,
375 FeatureSMAP,
376 FeatureSlowIncDec
377 ]>;
378def : BroadwellProc<"broadwell">;
379
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000[diff] [blame]380// FIXME: define KNL model
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]381class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000[diff] [blame]382 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
383 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
384 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
385 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
Elena Demikhovsky678bd5b2014-07-02 14:11:05 +0000[diff] [blame]386 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
387 FeatureSlowIncDec]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]388def : KnightsLandingProc<"knl">;
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000[diff] [blame]389
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]390// FIXME: define SKX model
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]391class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]392 [FeatureAVX512, FeatureCDI,
393 FeatureDQI, FeatureBWI, FeatureVLX,
394 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
395 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
396 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
397 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
Kevin Enderby0d928a12014-07-31 23:57:38 +0000[diff] [blame]398 FeatureSlowIncDec, FeatureSGX]>;
Chandler Carruthaf8924032014-12-09 10:58:36 +0000[diff] [blame^]399def : SkylakeProc<"skylake">;
400def : SkylakeProc<"skx">; // Legacy alias.
401
402
403// AMD CPUs.
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]404
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]405def : Proc<"k6", [FeatureMMX]>;
Michael J. Spencer30088ba2011-04-15 00:32:41 +0000[diff] [blame]406def : Proc<"k6-2", [Feature3DNow]>;
407def : Proc<"k6-3", [Feature3DNow]>;
Alexey Volkovbb2f0472014-03-07 08:28:44 +0000[diff] [blame]408def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]409 FeatureSlowSHLD]>;
410def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem,
411 FeatureSlowSHLD]>;
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]412def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]413 FeatureSlowSHLD]>;
414def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
415 FeatureSlowSHLD]>;
416def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
417 FeatureSlowSHLD]>;
Dan Gohman74037512009-02-03 00:04:43 +0000[diff] [blame]418def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]419 FeatureSlowBTMem, FeatureSlowSHLD]>;
Dan Gohman74037512009-02-03 00:04:43 +0000[diff] [blame]420def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]421 FeatureSlowBTMem, FeatureSlowSHLD]>;
Dan Gohman74037512009-02-03 00:04:43 +0000[diff] [blame]422def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]423 FeatureSlowBTMem, FeatureSlowSHLD]>;
Dan Gohman74037512009-02-03 00:04:43 +0000[diff] [blame]424def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]425 FeatureSlowBTMem, FeatureSlowSHLD]>;
Eli Friedman5e570422011-08-26 21:21:21 +0000[diff] [blame]426def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]427 FeatureSlowBTMem, FeatureSlowSHLD]>;
Eli Friedman5e570422011-08-26 21:21:21 +0000[diff] [blame]428def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]429 FeatureSlowBTMem, FeatureSlowSHLD]>;
Eli Friedman5e570422011-08-26 21:21:21 +0000[diff] [blame]430def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]431 FeatureSlowBTMem, FeatureSlowSHLD]>;
Craig Topperbae0e9e2012-05-01 06:54:48 +0000[diff] [blame]432def : Proc<"amdfam10", [FeatureSSE4A,
Benjamin Kramer5feb3da2011-11-30 15:48:16 +0000[diff] [blame]433 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]434 FeaturePOPCNT, FeatureSlowBTMem,
435 FeatureSlowSHLD]>;
Benjamin Kramer077ae1d2012-01-10 11:50:02 +0000[diff] [blame]436// Bobcat
437def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000[diff] [blame]438 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
439 FeatureSlowSHLD]>;
Sanjay Patel1191adf2014-09-09 20:07:07 +0000[diff] [blame]440
Benjamin Kramerb44c4272013-05-03 10:20:08 +0000[diff] [blame]441// Jaguar
Sanjay Patel1191adf2014-09-09 20:07:07 +0000[diff] [blame]442def : ProcessorModel<"btver2", BtVer2Model,
443 [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
444 FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
445 FeatureBMI, FeatureF16C, FeatureMOVBE,
Sanjay Patele57f3c02014-11-28 18:40:18 +0000[diff] [blame]446 FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
447 FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
448
449// TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
Sanjay Patel1191adf2014-09-09 20:07:07 +0000[diff] [blame]450
Benjamin Kramer077ae1d2012-01-10 11:50:02 +0000[diff] [blame]451// Bulldozer
Craig Topperbae0e9e2012-05-01 06:54:48 +0000[diff] [blame]452def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
Yunzhong Gaodfc277f2013-10-16 19:04:11 +0000[diff] [blame]453 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
Andrea Di Biagiof5b34e52014-11-04 21:18:09 +0000[diff] [blame]454 FeatureAVX, FeatureSSE4A, FeatureLZCNT,
455 FeaturePOPCNT, FeatureSlowSHLD]>;
Benjamin Kramerb44c4272013-05-03 10:20:08 +0000[diff] [blame]456// Piledriver
Craig Topperbae0e9e2012-05-01 06:54:48 +0000[diff] [blame]457def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
Yunzhong Gaodfc277f2013-10-16 19:04:11 +0000[diff] [blame]458 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
Andrea Di Biagiof5b34e52014-11-04 21:18:09 +0000[diff] [blame]459 FeatureAVX, FeatureSSE4A, FeatureF16C,
460 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
461 FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
Benjamin Kramerd114def2013-11-04 10:29:20 +0000[diff] [blame]462
463// Steamroller
464def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
465 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
Andrea Di Biagiof5b34e52014-11-04 21:18:09 +0000[diff] [blame]466 FeatureAVX, FeatureSSE4A, FeatureF16C,
467 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
468 FeatureTBM, FeatureFMA, FeatureSlowSHLD,
469 FeatureFSGSBase]>;
Benjamin Kramerd114def2013-11-04 10:29:20 +0000[diff] [blame]470
Benjamin Kramer60045732014-05-02 15:47:07 +0000[diff] [blame]471// Excavator
472def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
473 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
474 FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
475 FeaturePOPCNT, FeatureBMI, FeatureBMI2,
Andrea Di Biagiof5b34e52014-11-04 21:18:09 +0000[diff] [blame]476 FeatureTBM, FeatureFMA, FeatureSSE4A,
477 FeatureFSGSBase]>;
Benjamin Kramer60045732014-05-02 15:47:07 +0000[diff] [blame]478
Roman Divackyfd690092012-09-12 14:36:02 +0000[diff] [blame]479def : Proc<"geode", [Feature3DNowA]>;
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]480
481def : Proc<"winchip-c6", [FeatureMMX]>;
Michael J. Spencer30088ba2011-04-15 00:32:41 +0000[diff] [blame]482def : Proc<"winchip2", [Feature3DNow]>;
483def : Proc<"c3", [Feature3DNow]>;
Bill Wendling3fb7fdf2007-05-22 05:15:37 +0000[diff] [blame]484def : Proc<"c3-2", [FeatureSSE1]>;
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]485
Chandler Carruth32908d72014-05-07 17:37:03 +0000[diff] [blame]486// We also provide a generic 64-bit specific x86 processor model which tries to
487// be good for modern chips without enabling instruction set encodings past the
488// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
489// modern 64-bit x86 chip, and enables features that are generally beneficial.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]490//
Chandler Carruth32908d72014-05-07 17:37:03 +0000[diff] [blame]491// We currently use the Sandy Bridge model as the default scheduling model as
492// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
493// covers a huge swath of x86 processors. If there are specific scheduling
494// knobs which need to be tuned differently for AMD chips, we might consider
495// forming a common base for them.
496def : ProcessorModel<"x86-64", SandyBridgeModel,
497 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
498 FeatureFastUAMem]>;
499
Evan Chengff1beda2006-10-06 09:17:41 +0000[diff] [blame]500//===----------------------------------------------------------------------===//
Chris Lattner5da8e802003-08-03 15:47:49 +0000[diff] [blame]501// Register File Description
502//===----------------------------------------------------------------------===//
503
504include "X86RegisterInfo.td"
505
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000[diff] [blame]506//===----------------------------------------------------------------------===//
507// Instruction Descriptions
508//===----------------------------------------------------------------------===//
509
Chris Lattner59a4a912003-08-03 21:54:21 +0000[diff] [blame]510include "X86InstrInfo.td"
511
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +0000[diff] [blame]512def X86InstrInfo : InstrInfo;
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000[diff] [blame]513
Chris Lattner5d00a0b2007-02-26 18:17:14 +0000[diff] [blame]514//===----------------------------------------------------------------------===//
515// Calling Conventions
516//===----------------------------------------------------------------------===//
517
518include "X86CallingConv.td"
519
520
521//===----------------------------------------------------------------------===//
Jim Grosbach4cf25f52010-10-30 13:48:28 +0000[diff] [blame]522// Assembly Parser
Chris Lattner5d00a0b2007-02-26 18:17:14 +0000[diff] [blame]523//===----------------------------------------------------------------------===//
524
Daniel Dunbar00331992009-07-29 00:02:19 +0000[diff] [blame]525def ATTAsmParser : AsmParser {
Devang Patel4a6e7782012-01-12 18:03:40 +0000[diff] [blame]526 string AsmParserClassName = "AsmParser";
Devang Patel85d684a2012-01-09 19:13:28 +0000[diff] [blame]527}
528
529def ATTAsmParserVariant : AsmParserVariant {
Daniel Dunbar00331992009-07-29 00:02:19 +0000[diff] [blame]530 int Variant = 0;
Daniel Dunbare4318712009-08-11 20:59:47 +0000[diff] [blame]531
Chad Rosier9f7a2212013-04-18 22:35:36 +0000[diff] [blame]532 // Variant name.
533 string Name = "att";
534
Daniel Dunbare4318712009-08-11 20:59:47 +0000[diff] [blame]535 // Discard comments in assembly strings.
536 string CommentDelimiter = "#";
537
538 // Recognize hard coded registers.
539 string RegisterPrefix = "%";
Daniel Dunbar00331992009-07-29 00:02:19 +0000[diff] [blame]540}
541
Devang Patel67bf992a2012-01-10 17:51:54 +0000[diff] [blame]542def IntelAsmParserVariant : AsmParserVariant {
543 int Variant = 1;
544
Chad Rosier9f7a2212013-04-18 22:35:36 +0000[diff] [blame]545 // Variant name.
546 string Name = "intel";
547
Devang Patel67bf992a2012-01-10 17:51:54 +0000[diff] [blame]548 // Discard comments in assembly strings.
549 string CommentDelimiter = ";";
550
551 // Recognize hard coded registers.
552 string RegisterPrefix = "";
553}
554
Jim Grosbach4cf25f52010-10-30 13:48:28 +0000[diff] [blame]555//===----------------------------------------------------------------------===//
556// Assembly Printers
557//===----------------------------------------------------------------------===//
558
Chris Lattner56832602004-10-03 20:36:57 +0000[diff] [blame]559// The X86 target supports two different syntaxes for emitting machine code.
560// This is controlled by the -x86-asm-syntax={att|intel}
561def ATTAsmWriter : AsmWriter {
Chris Lattner1cbd3de2009-09-13 19:30:11 +0000[diff] [blame]562 string AsmWriterClassName = "ATTInstPrinter";
Chris Lattner56832602004-10-03 20:36:57 +0000[diff] [blame]563 int Variant = 0;
564}
565def IntelAsmWriter : AsmWriter {
Chris Lattner13306a12009-09-20 07:47:59 +0000[diff] [blame]566 string AsmWriterClassName = "IntelInstPrinter";
Chris Lattner56832602004-10-03 20:36:57 +0000[diff] [blame]567 int Variant = 1;
568}
569
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000[diff] [blame]570def X86 : Target {
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000[diff] [blame]571 // Information about the instructions...
Chris Lattner25510802003-08-04 04:59:56 +0000[diff] [blame]572 let InstructionSet = X86InstrInfo;
Daniel Dunbar00331992009-07-29 00:02:19 +0000[diff] [blame]573 let AssemblyParsers = [ATTAsmParser];
Devang Patel67bf992a2012-01-10 17:51:54 +0000[diff] [blame]574 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
Chris Lattner56832602004-10-03 20:36:57 +0000[diff] [blame]575 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
Chris Lattnera8c3cff2003-08-03 18:19:37 +0000[diff] [blame]576}