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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000018#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000019#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000020#include "llvm/Target/TargetSubtargetInfo.h"
21
22using namespace llvm;
23
Quentin Colombet000b5802016-03-11 17:27:51 +000024void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000025 this->MF = &MF;
26 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000027 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000028 this->TII = MF.getSubtarget().getInstrInfo();
29 this->DL = DebugLoc();
30 this->MI = nullptr;
Tim Northover438c77c2016-08-25 17:37:32 +000031 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000032}
33
Quentin Colombet91ebd712016-03-11 17:27:47 +000034void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000035 this->MBB = &MBB;
Tim Northoverb18ea162016-09-20 15:20:36 +000036 this->MI = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000037 Before = Beginning;
38 assert(&getMF() == MBB.getParent() &&
39 "Basic block is in a different function");
40}
41
42void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
43 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000044 setMBB(*MI.getParent());
Quentin Colombet2ad1f852016-02-11 17:44:59 +000045 this->MI = &MI;
46 this->Before = Before;
47}
48
49MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
50 if (MI) {
51 if (Before)
52 return MI;
53 if (!MI->getNextNode())
54 return getMBB().end();
55 return MI->getNextNode();
56 }
57 return Before ? getMBB().begin() : getMBB().end();
58}
59
Tim Northover438c77c2016-08-25 17:37:32 +000060void MachineIRBuilder::recordInsertions(
61 std::function<void(MachineInstr *)> Inserted) {
62 InsertedInstr = Inserted;
63}
64
65void MachineIRBuilder::stopRecordingInsertions() {
66 InsertedInstr = nullptr;
67}
68
Quentin Colombetf9b49342016-03-11 17:27:58 +000069//------------------------------------------------------------------------------
70// Build instruction variants.
71//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000072
Tim Northover0f140c72016-09-09 11:46:34 +000073MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera5e38fa2016-09-22 13:49:25 +000074 return insertInstr(buildInstrNoInsert(Opcode));
75}
76
77MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000078 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera5e38fa2016-09-22 13:49:25 +000079 return MIB;
80}
81
82
83MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Tim Northovera51575f2016-07-29 17:43:52 +000084 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000085 if (InsertedInstr)
86 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000087 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000088}
89
Tim Northover0f140c72016-09-09 11:46:34 +000090MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +000091 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +000092 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +000093 .addDef(Res)
94 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +000095}
Tim Northover33b07d62016-07-22 20:03:43 +000096
Tim Northover032548f2016-09-12 12:10:41 +000097MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
98 const GlobalValue *GV) {
99 assert(MRI->getType(Res).isPointer() && "invalid operand type");
100 assert(MRI->getType(Res).getAddressSpace() ==
101 GV->getType()->getAddressSpace() &&
102 "address space mismatch");
103
104 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
105 .addDef(Res)
106 .addGlobalAddress(GV);
107}
108
Tim Northover0f140c72016-09-09 11:46:34 +0000109MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
110 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000111 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
112 "invalid operand type");
113 assert(MRI->getType(Res) == MRI->getType(Op0) &&
114 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
115
Tim Northover0f140c72016-09-09 11:46:34 +0000116 return buildInstr(TargetOpcode::G_ADD)
Tim Northovera51575f2016-07-29 17:43:52 +0000117 .addDef(Res)
118 .addUse(Op0)
119 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000120}
121
Tim Northovera7653b32016-09-12 11:20:22 +0000122MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
123 unsigned Op1) {
124 assert(MRI->getType(Res).isPointer() &&
125 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
126 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
127
128 return buildInstr(TargetOpcode::G_GEP)
129 .addDef(Res)
130 .addUse(Op0)
131 .addUse(Op1);
132}
133
Tim Northover0f140c72016-09-09 11:46:34 +0000134MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
135 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000136 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
137 "invalid operand type");
138 assert(MRI->getType(Res) == MRI->getType(Op0) &&
139 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
140
Tim Northover0f140c72016-09-09 11:46:34 +0000141 return buildInstr(TargetOpcode::G_SUB)
Tim Northovercecee562016-08-26 17:46:13 +0000142 .addDef(Res)
143 .addUse(Op0)
144 .addUse(Op1);
145}
146
Tim Northover0f140c72016-09-09 11:46:34 +0000147MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
148 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000149 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
150 "invalid operand type");
151 assert(MRI->getType(Res) == MRI->getType(Op0) &&
152 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
153
Tim Northover0f140c72016-09-09 11:46:34 +0000154 return buildInstr(TargetOpcode::G_MUL)
Tim Northovercecee562016-08-26 17:46:13 +0000155 .addDef(Res)
156 .addUse(Op0)
157 .addUse(Op1);
158}
159
Tim Northovera51575f2016-07-29 17:43:52 +0000160MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000161 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000162}
163
Tim Northovera51575f2016-07-29 17:43:52 +0000164MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
165 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000166}
167
Tim Northover0f140c72016-09-09 11:46:34 +0000168MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, int64_t Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000169 assert(MRI->getType(Res).isScalar() && "invalid operand type");
170
Tim Northover0f140c72016-09-09 11:46:34 +0000171 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addImm(Val);
Tim Northover9656f142016-08-04 20:54:13 +0000172}
173
Tim Northover0f140c72016-09-09 11:46:34 +0000174MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
175 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000176 assert(MRI->getType(Res).isScalar() && "invalid operand type");
177
Tim Northover0f140c72016-09-09 11:46:34 +0000178 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000179}
180
Tim Northover0f140c72016-09-09 11:46:34 +0000181MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000182 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000183 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
184
Tim Northover0f140c72016-09-09 11:46:34 +0000185 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000186}
187
Tim Northover0f140c72016-09-09 11:46:34 +0000188MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
189 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000190 assert(MRI->getType(Res).isValid() && "invalid operand type");
191 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
192
Tim Northover0f140c72016-09-09 11:46:34 +0000193 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000194 .addDef(Res)
195 .addUse(Addr)
196 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000197}
198
Tim Northover0f140c72016-09-09 11:46:34 +0000199MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
200 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000201 assert(MRI->getType(Val).isValid() && "invalid operand type");
202 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
203
Tim Northover0f140c72016-09-09 11:46:34 +0000204 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000205 .addUse(Val)
206 .addUse(Addr)
207 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000208}
209
Tim Northover0f140c72016-09-09 11:46:34 +0000210MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
211 unsigned CarryOut,
212 unsigned Op0, unsigned Op1,
213 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000214 assert(MRI->getType(Res).isScalar() && "invalid operand type");
215 assert(MRI->getType(Res) == MRI->getType(Op0) &&
216 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
217 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
218 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
219
Tim Northover0f140c72016-09-09 11:46:34 +0000220 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000221 .addDef(Res)
222 .addDef(CarryOut)
223 .addUse(Op0)
224 .addUse(Op1)
225 .addUse(CarryIn);
226}
227
Tim Northover0f140c72016-09-09 11:46:34 +0000228MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
229 validateTruncExt(Res, Op, true);
230 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000231}
232
Tim Northover0f140c72016-09-09 11:46:34 +0000233MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
234 validateTruncExt(Res, Op, true);
235 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000236}
237
Tim Northover0f140c72016-09-09 11:46:34 +0000238MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
239 validateTruncExt(Res, Op, true);
240 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000241}
242
Tim Northovera7653b32016-09-12 11:20:22 +0000243MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
244 unsigned Op) {
245 unsigned Opcode = TargetOpcode::COPY;
246 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
247 Opcode = TargetOpcode::G_SEXT;
248 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
249 Opcode = TargetOpcode::G_TRUNC;
250
251 return buildInstr(Opcode).addDef(Res).addUse(Op);
252}
253
Tim Northover0f140c72016-09-09 11:46:34 +0000254MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results,
Tim Northover26b76f22016-08-19 18:32:14 +0000255 ArrayRef<uint64_t> Indices,
Tim Northover0f140c72016-09-09 11:46:34 +0000256 unsigned Src) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000257#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000258 assert(Results.size() == Indices.size() && "inconsistent number of regs");
Tim Northover26b76f22016-08-19 18:32:14 +0000259 assert(!Results.empty() && "invalid trivial extract");
Tim Northover991b12b2016-08-30 20:51:25 +0000260 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
261 "extract offsets must be in ascending order");
Tim Northover33b07d62016-07-22 20:03:43 +0000262
Tim Northover1f8b1db2016-09-09 11:46:58 +0000263 assert(MRI->getType(Src).isValid() && "invalid operand type");
264 for (auto Res : Results)
265 assert(MRI->getType(Res).isValid() && "invalid operand type");
266#endif
267
Tim Northover26b76f22016-08-19 18:32:14 +0000268 auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT));
Tim Northover33b07d62016-07-22 20:03:43 +0000269 for (auto Res : Results)
Tim Northovera51575f2016-07-29 17:43:52 +0000270 MIB.addDef(Res);
Tim Northover33b07d62016-07-22 20:03:43 +0000271
Tim Northovera51575f2016-07-29 17:43:52 +0000272 MIB.addUse(Src);
Tim Northover33b07d62016-07-22 20:03:43 +0000273
Tim Northover26b76f22016-08-19 18:32:14 +0000274 for (auto Idx : Indices)
Tim Northover33b07d62016-07-22 20:03:43 +0000275 MIB.addImm(Idx);
Tim Northover26b76f22016-08-19 18:32:14 +0000276
277 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +0000278 if (InsertedInstr)
279 InsertedInstr(MIB);
Tim Northover26b76f22016-08-19 18:32:14 +0000280
Tim Northovera51575f2016-07-29 17:43:52 +0000281 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000282}
283
Tim Northover91c81732016-08-19 17:17:06 +0000284MachineInstrBuilder
Tim Northover0f140c72016-09-09 11:46:34 +0000285MachineIRBuilder::buildSequence(unsigned Res,
Tim Northover91c81732016-08-19 17:17:06 +0000286 ArrayRef<unsigned> Ops,
Tim Northoverb18ea162016-09-20 15:20:36 +0000287 ArrayRef<uint64_t> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000288#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000289 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000290 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000291 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
292 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000293
Tim Northover1f8b1db2016-09-09 11:46:58 +0000294 assert(MRI->getType(Res).isValid() && "invalid operand type");
295 for (auto Op : Ops)
296 assert(MRI->getType(Op).isValid() && "invalid operand type");
297#endif
298
Tim Northover0f140c72016-09-09 11:46:34 +0000299 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE);
Tim Northovera51575f2016-07-29 17:43:52 +0000300 MIB.addDef(Res);
Tim Northover91c81732016-08-19 17:17:06 +0000301 for (unsigned i = 0; i < Ops.size(); ++i) {
302 MIB.addUse(Ops[i]);
Tim Northover26b76f22016-08-19 18:32:14 +0000303 MIB.addImm(Indices[i]);
Tim Northover91c81732016-08-19 17:17:06 +0000304 }
Tim Northovera51575f2016-07-29 17:43:52 +0000305 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000306}
Tim Northover5fb414d2016-07-29 22:32:36 +0000307
Tim Northover0f140c72016-09-09 11:46:34 +0000308MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000309 unsigned Res,
310 bool HasSideEffects) {
311 auto MIB =
312 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000313 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000314 if (Res)
315 MIB.addDef(Res);
316 MIB.addIntrinsicID(ID);
317 return MIB;
318}
Tim Northover32335812016-08-04 18:35:11 +0000319
Tim Northover0f140c72016-09-09 11:46:34 +0000320MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
321 validateTruncExt(Res, Op, false);
322 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000323}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000324
Tim Northover0f140c72016-09-09 11:46:34 +0000325MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
326 validateTruncExt(Res, Op, false);
327 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000328}
329
Tim Northover0f140c72016-09-09 11:46:34 +0000330MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000331 unsigned Res, unsigned Op0,
332 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000333#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000334 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
335 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
Tim Northover4cf0a482016-09-15 10:40:38 +0000336 if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000337 assert(MRI->getType(Res).isScalar() && "type mismatch");
338 else
339 assert(MRI->getType(Res).isVector() &&
340 MRI->getType(Res).getNumElements() ==
341 MRI->getType(Op0).getNumElements() &&
342 "type mismatch");
343#endif
344
Tim Northover0f140c72016-09-09 11:46:34 +0000345 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000346 .addDef(Res)
347 .addPredicate(Pred)
348 .addUse(Op0)
349 .addUse(Op1);
350}
Tim Northover5a28c362016-08-19 20:09:07 +0000351
Tim Northover0f140c72016-09-09 11:46:34 +0000352MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000353 unsigned Res, unsigned Op0,
354 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000355#ifndef NDEBUG
356 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
357 "invalid operand type");
358 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
359 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
360 if (MRI->getType(Op0).isScalar())
361 assert(MRI->getType(Res).isScalar() && "type mismatch");
362 else
363 assert(MRI->getType(Res).isVector() &&
364 MRI->getType(Res).getNumElements() ==
365 MRI->getType(Op0).getNumElements() &&
366 "type mismatch");
367#endif
368
Tim Northover0f140c72016-09-09 11:46:34 +0000369 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000370 .addDef(Res)
371 .addPredicate(Pred)
372 .addUse(Op0)
373 .addUse(Op1);
374}
375
Tim Northover0f140c72016-09-09 11:46:34 +0000376MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000377 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000378#ifndef NDEBUG
379 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
380 "invalid operand type");
381 assert(MRI->getType(Res) == MRI->getType(Op0) &&
382 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
383 if (MRI->getType(Res).isScalar())
384 assert(MRI->getType(Tst).isScalar() && "type mismatch");
385 else
386 assert(MRI->getType(Tst).isVector() &&
387 MRI->getType(Tst).getNumElements() ==
388 MRI->getType(Op0).getNumElements() &&
389 "type mismatch");
390#endif
391
Tim Northover0f140c72016-09-09 11:46:34 +0000392 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000393 .addDef(Res)
394 .addUse(Tst)
395 .addUse(Op0)
396 .addUse(Op1);
397}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000398
Tim Northover0f140c72016-09-09 11:46:34 +0000399void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
400 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000401#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000402 LLT SrcTy = MRI->getType(Src);
403 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000404
405 if (DstTy.isVector()) {
406 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
407 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
408 "different number of elements in a trunc/ext");
409 } else
410 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
411
412 if (IsExtend)
413 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
414 "invalid narrowing extend");
415 else
416 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
417 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000418#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000419}