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Chris Lattner7a60d912005-01-07 07:47:53 +00001//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
Misha Brukman835702a2005-04-21 22:36:52 +00002//
Chris Lattner7a60d912005-01-07 07:47:53 +00003// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
Misha Brukman835702a2005-04-21 22:36:52 +00007//
Chris Lattner7a60d912005-01-07 07:47:53 +00008//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
Anton Korobeynikov915e6172007-04-04 21:14:49 +000015#include "llvm/ADT/BitVector.h"
Jim Laskeydcb2b832006-10-16 20:52:31 +000016#include "llvm/Analysis/AliasAnalysis.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000017#include "llvm/CodeGen/SelectionDAGISel.h"
Evan Cheng739a6a42006-01-21 02:32:06 +000018#include "llvm/CodeGen/ScheduleDAG.h"
Anton Korobeynikov915e6172007-04-04 21:14:49 +000019#include "llvm/Constants.h"
Chris Lattner2e77db62005-05-13 18:50:42 +000020#include "llvm/CallingConv.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000021#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
Chris Lattner435b4022005-11-29 06:21:05 +000023#include "llvm/GlobalVariable.h"
Chris Lattner476e67b2006-01-26 22:24:51 +000024#include "llvm/InlineAsm.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000025#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
Jim Laskeya8bdac82006-03-23 18:06:46 +000027#include "llvm/IntrinsicInst.h"
Reid Spencer71b79e32007-04-09 06:17:21 +000028#include "llvm/ParameterAttributes.h"
Jim Laskeyc56315c2007-01-26 21:22:28 +000029#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000030#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
Nate Begeman4ca2ea52006-04-22 18:53:45 +000032#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000033#include "llvm/CodeGen/MachineInstrBuilder.h"
Jim Laskey29e635d2006-08-02 12:30:23 +000034#include "llvm/CodeGen/SchedulerRegistry.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000035#include "llvm/CodeGen/SelectionDAG.h"
36#include "llvm/CodeGen/SSARegMap.h"
Chris Lattnerd4382f02005-09-13 19:30:54 +000037#include "llvm/Target/MRegisterInfo.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000038#include "llvm/Target/TargetData.h"
39#include "llvm/Target/TargetFrameInfo.h"
40#include "llvm/Target/TargetInstrInfo.h"
41#include "llvm/Target/TargetLowering.h"
42#include "llvm/Target/TargetMachine.h"
Vladimir Prusdf1d4392006-05-23 13:43:15 +000043#include "llvm/Target/TargetOptions.h"
Chris Lattner43535a12005-11-09 04:45:33 +000044#include "llvm/Support/MathExtras.h"
Chris Lattner7a60d912005-01-07 07:47:53 +000045#include "llvm/Support/Debug.h"
Chris Lattner3d27be12006-08-27 12:54:02 +000046#include "llvm/Support/Compiler.h"
Jeff Cohen83c22e02006-02-24 02:52:40 +000047#include <algorithm>
Chris Lattner7a60d912005-01-07 07:47:53 +000048using namespace llvm;
49
Chris Lattner975f5c92005-09-01 18:44:10 +000050#ifndef NDEBUG
Chris Lattnere05a4612005-01-12 03:41:21 +000051static cl::opt<bool>
Evan Cheng739a6a42006-01-21 02:32:06 +000052ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
54static cl::opt<bool>
55ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
Dan Gohman81b62e12007-08-28 20:32:58 +000057static cl::opt<bool>
58ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
59 cl::desc("Pop up a window to show SUnit dags after they are processed"));
Chris Lattnere05a4612005-01-12 03:41:21 +000060#else
Dan Gohman81b62e12007-08-28 20:32:58 +000061static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
Chris Lattnere05a4612005-01-12 03:41:21 +000062#endif
63
Jim Laskey29e635d2006-08-02 12:30:23 +000064//===---------------------------------------------------------------------===//
65///
66/// RegisterScheduler class - Track the registration of instruction schedulers.
67///
68//===---------------------------------------------------------------------===//
69MachinePassRegistry RegisterScheduler::Registry;
70
71//===---------------------------------------------------------------------===//
72///
73/// ISHeuristic command line option for instruction schedulers.
74///
75//===---------------------------------------------------------------------===//
Evan Chengc1e1d972006-01-23 07:01:07 +000076namespace {
Jim Laskey29e635d2006-08-02 12:30:23 +000077 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
Dale Johannesen2182f062007-07-13 17:13:54 +000079 ISHeuristic("pre-RA-sched",
Chris Lattner524c1a22006-08-03 00:18:59 +000080 cl::init(&createDefaultScheduler),
Dale Johannesen2182f062007-07-13 17:13:54 +000081 cl::desc("Instruction schedulers available (before register allocation):"));
Jim Laskey95eda5b2006-08-01 14:21:23 +000082
Jim Laskey03593f72006-08-01 18:29:48 +000083 static RegisterScheduler
Jim Laskey17c67ef2006-08-01 19:14:14 +000084 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
Evan Chengc1e1d972006-01-23 07:01:07 +000086} // namespace
87
Chris Lattner4333f8b2007-04-30 17:29:31 +000088namespace { struct AsmOperandInfo; }
89
Chris Lattner6f87d182006-02-22 22:37:12 +000090namespace {
91 /// RegsForValue - This struct represents the physical registers that a
92 /// particular value is assigned and the type information about the value.
93 /// This is needed because values can be promoted into larger registers and
94 /// expanded into multiple smaller registers than the value.
Chris Lattner996795b2006-06-28 23:17:24 +000095 struct VISIBILITY_HIDDEN RegsForValue {
Dan Gohman78677932007-06-28 23:29:44 +000096 /// Regs - This list holds the register (for legal and promoted values)
Chris Lattner6f87d182006-02-22 22:37:12 +000097 /// or register set (for expanded values) that the value should be assigned
98 /// to.
99 std::vector<unsigned> Regs;
100
101 /// RegVT - The value type of each register.
102 ///
103 MVT::ValueType RegVT;
104
105 /// ValueVT - The value type of the LLVM value, which may be promoted from
106 /// RegVT or made from merging the two expanded parts.
107 MVT::ValueType ValueVT;
108
109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
110
111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
112 : RegVT(regvt), ValueVT(valuevt) {
113 Regs.push_back(Reg);
114 }
115 RegsForValue(const std::vector<unsigned> &regs,
116 MVT::ValueType regvt, MVT::ValueType valuevt)
117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
118 }
119
120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
121 /// this value and returns the result as a ValueVT value. This uses
122 /// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohman78677932007-06-28 23:29:44 +0000123 /// If the Flag pointer is NULL, no flag is used.
Chris Lattner6f87d182006-02-22 22:37:12 +0000124 SDOperand getCopyFromRegs(SelectionDAG &DAG,
Dan Gohman78677932007-06-28 23:29:44 +0000125 SDOperand &Chain, SDOperand *Flag) const;
Chris Lattner571d9642006-02-23 19:21:04 +0000126
127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
128 /// specified value into the registers specified by this object. This uses
129 /// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohman78677932007-06-28 23:29:44 +0000130 /// If the Flag pointer is NULL, no flag is used.
Chris Lattner571d9642006-02-23 19:21:04 +0000131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
Dan Gohman78677932007-06-28 23:29:44 +0000132 SDOperand &Chain, SDOperand *Flag) const;
Chris Lattner571d9642006-02-23 19:21:04 +0000133
134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
135 /// operand list. This adds the code marker and includes the number of
136 /// values added into it.
137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Chris Lattnere7c0ffb2006-02-23 20:06:57 +0000138 std::vector<SDOperand> &Ops) const;
Chris Lattner6f87d182006-02-22 22:37:12 +0000139 };
140}
Evan Chengc1e1d972006-01-23 07:01:07 +0000141
Chris Lattner7a60d912005-01-07 07:47:53 +0000142namespace llvm {
143 //===--------------------------------------------------------------------===//
Jim Laskey17c67ef2006-08-01 19:14:14 +0000144 /// createDefaultScheduler - This creates an instruction scheduler appropriate
145 /// for the target.
146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
147 SelectionDAG *DAG,
148 MachineBasicBlock *BB) {
149 TargetLowering &TLI = IS->getTargetLowering();
150
151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
152 return createTDListDAGScheduler(IS, DAG, BB);
153 } else {
154 assert(TLI.getSchedulingPreference() ==
155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
156 return createBURRListDAGScheduler(IS, DAG, BB);
157 }
158 }
159
160
161 //===--------------------------------------------------------------------===//
Chris Lattner7a60d912005-01-07 07:47:53 +0000162 /// FunctionLoweringInfo - This contains information that is global to a
163 /// function that is used when lowering a region of the function.
Chris Lattnerd0061952005-01-08 19:52:31 +0000164 class FunctionLoweringInfo {
165 public:
Chris Lattner7a60d912005-01-07 07:47:53 +0000166 TargetLowering &TLI;
167 Function &Fn;
168 MachineFunction &MF;
169 SSARegMap *RegMap;
170
171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
172
173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
175
176 /// ValueMap - Since we emit code for the function a basic block at a time,
177 /// we must remember which virtual registers hold the values for
178 /// cross-basic-block values.
Chris Lattner289aa442007-02-04 01:35:11 +0000179 DenseMap<const Value*, unsigned> ValueMap;
Chris Lattner7a60d912005-01-07 07:47:53 +0000180
181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
182 /// the entry block. This allows the allocas to be efficiently referenced
183 /// anywhere in the function.
184 std::map<const AllocaInst*, int> StaticAllocaMap;
185
Duncan Sands92bf2c62007-06-15 19:04:19 +0000186#ifndef NDEBUG
187 SmallSet<Instruction*, 8> CatchInfoLost;
188 SmallSet<Instruction*, 8> CatchInfoFound;
189#endif
190
Chris Lattner7a60d912005-01-07 07:47:53 +0000191 unsigned MakeReg(MVT::ValueType VT) {
192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
193 }
Chris Lattnered0110b2006-10-27 21:36:01 +0000194
195 /// isExportedInst - Return true if the specified value is an instruction
196 /// exported from its block.
197 bool isExportedInst(const Value *V) {
198 return ValueMap.count(V);
199 }
Misha Brukman835702a2005-04-21 22:36:52 +0000200
Chris Lattner49409cb2006-03-16 19:51:18 +0000201 unsigned CreateRegForValue(const Value *V);
202
Chris Lattner7a60d912005-01-07 07:47:53 +0000203 unsigned InitializeRegForValue(const Value *V) {
204 unsigned &R = ValueMap[V];
205 assert(R == 0 && "Already initialized this value register!");
206 return R = CreateRegForValue(V);
207 }
208 };
209}
210
Duncan Sandsfe806382007-07-04 20:52:51 +0000211/// isSelector - Return true if this instruction is a call to the
212/// eh.selector intrinsic.
213static bool isSelector(Instruction *I) {
Duncan Sands92bf2c62007-06-15 19:04:19 +0000214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +0000215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
216 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
Duncan Sands92bf2c62007-06-15 19:04:19 +0000217 return false;
218}
219
Chris Lattner7a60d912005-01-07 07:47:53 +0000220/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
Nate Begemaned728c12006-03-27 01:32:24 +0000221/// PHI nodes or outside of the basic block that defines it, or used by a
222/// switch instruction, which may expand to multiple basic blocks.
Chris Lattner7a60d912005-01-07 07:47:53 +0000223static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
224 if (isa<PHINode>(I)) return true;
225 BasicBlock *BB = I->getParent();
226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
Nate Begemaned728c12006-03-27 01:32:24 +0000227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
Chris Lattnered0110b2006-10-27 21:36:01 +0000228 // FIXME: Remove switchinst special case.
Nate Begemaned728c12006-03-27 01:32:24 +0000229 isa<SwitchInst>(*UI))
Chris Lattner7a60d912005-01-07 07:47:53 +0000230 return true;
231 return false;
232}
233
Chris Lattner6871b232005-10-30 19:42:35 +0000234/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
Nate Begemaned728c12006-03-27 01:32:24 +0000235/// entry block, return true. This includes arguments used by switches, since
236/// the switch may expand into multiple basic blocks.
Chris Lattner6871b232005-10-30 19:42:35 +0000237static bool isOnlyUsedInEntryBlock(Argument *A) {
238 BasicBlock *Entry = A->getParent()->begin();
239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
Nate Begemaned728c12006-03-27 01:32:24 +0000240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
Chris Lattner6871b232005-10-30 19:42:35 +0000241 return false; // Use not in entry block.
242 return true;
243}
244
Chris Lattner7a60d912005-01-07 07:47:53 +0000245FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Misha Brukman835702a2005-04-21 22:36:52 +0000246 Function &fn, MachineFunction &mf)
Chris Lattner7a60d912005-01-07 07:47:53 +0000247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
248
Chris Lattner6871b232005-10-30 19:42:35 +0000249 // Create a vreg for each argument register that is not dead and is used
250 // outside of the entry block for the function.
251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
252 AI != E; ++AI)
253 if (!isOnlyUsedInEntryBlock(AI))
254 InitializeRegForValue(AI);
255
Chris Lattner7a60d912005-01-07 07:47:53 +0000256 // Initialize the mapping of values to registers. This is only set up for
257 // instruction values that are used outside of the block that defines
258 // them.
Jeff Cohenf8a5e5ae2005-10-01 03:57:14 +0000259 Function::iterator BB = Fn.begin(), EB = Fn.end();
Chris Lattner7a60d912005-01-07 07:47:53 +0000260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
Reid Spencere0fc4df2006-10-20 07:07:24 +0000262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
Chris Lattner7a60d912005-01-07 07:47:53 +0000263 const Type *Ty = AI->getAllocatedType();
Duncan Sands44b87212007-11-01 20:53:16 +0000264 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Nate Begeman3ee3e692005-11-06 09:00:38 +0000265 unsigned Align =
Chris Lattner945e4372007-02-14 05:52:17 +0000266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
Nate Begeman3ee3e692005-11-06 09:00:38 +0000267 AI->getAlignment());
Chris Lattnercbefe722005-05-13 23:14:17 +0000268
Reid Spencere0fc4df2006-10-20 07:07:24 +0000269 TySize *= CUI->getZExtValue(); // Get total allocated size.
Chris Lattner0a71a9a2005-10-18 22:14:06 +0000270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
Chris Lattner7a60d912005-01-07 07:47:53 +0000271 StaticAllocaMap[AI] =
Chris Lattnercb0ed0c2007-04-25 04:08:28 +0000272 MF.getFrameInfo()->CreateStackObject(TySize, Align);
Chris Lattner7a60d912005-01-07 07:47:53 +0000273 }
274
Jeff Cohenf8a5e5ae2005-10-01 03:57:14 +0000275 for (; BB != EB; ++BB)
276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
Chris Lattner7a60d912005-01-07 07:47:53 +0000277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
278 if (!isa<AllocaInst>(I) ||
279 !StaticAllocaMap.count(cast<AllocaInst>(I)))
280 InitializeRegForValue(I);
281
282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
283 // also creates the initial PHI MachineInstrs, though none of the input
284 // operands are populated.
Jeff Cohenf8a5e5ae2005-10-01 03:57:14 +0000285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
Chris Lattner7a60d912005-01-07 07:47:53 +0000286 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
287 MBBMap[BB] = MBB;
288 MF.getBasicBlockList().push_back(MBB);
289
290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
291 // appropriate.
292 PHINode *PN;
Chris Lattner84a03502006-10-27 23:50:33 +0000293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
294 if (PN->use_empty()) continue;
295
296 MVT::ValueType VT = TLI.getValueType(PN->getType());
Dan Gohmana8665142007-06-25 16:23:39 +0000297 unsigned NumRegisters = TLI.getNumRegisters(VT);
Chris Lattner84a03502006-10-27 23:50:33 +0000298 unsigned PHIReg = ValueMap[PN];
299 assert(PHIReg && "PHI node does not have an assigned virtual register!");
Evan Cheng20350c42006-11-27 23:37:22 +0000300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
Dan Gohman04deef32007-06-21 14:42:22 +0000301 for (unsigned i = 0; i != NumRegisters; ++i)
Evan Cheng20350c42006-11-27 23:37:22 +0000302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
Chris Lattner84a03502006-10-27 23:50:33 +0000303 }
Chris Lattner7a60d912005-01-07 07:47:53 +0000304 }
305}
306
Chris Lattner49409cb2006-03-16 19:51:18 +0000307/// CreateRegForValue - Allocate the appropriate number of virtual registers of
308/// the correctly promoted or expanded types. Assign these registers
309/// consecutive vreg numbers and return the first assigned number.
310unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
311 MVT::ValueType VT = TLI.getValueType(V->getType());
312
Dan Gohman78677932007-06-28 23:29:44 +0000313 unsigned NumRegisters = TLI.getNumRegisters(VT);
314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
Bill Wendling47917b62007-04-24 21:13:23 +0000315
Dan Gohman7139a482007-06-27 14:34:07 +0000316 unsigned R = MakeReg(RegisterVT);
317 for (unsigned i = 1; i != NumRegisters; ++i)
318 MakeReg(RegisterVT);
319
Chris Lattner49409cb2006-03-16 19:51:18 +0000320 return R;
321}
Chris Lattner7a60d912005-01-07 07:47:53 +0000322
323//===----------------------------------------------------------------------===//
324/// SelectionDAGLowering - This is the common target-independent lowering
325/// implementation that is parameterized by a TargetLowering object.
326/// Also, targets can overload any lowering method.
327///
328namespace llvm {
329class SelectionDAGLowering {
330 MachineBasicBlock *CurMBB;
331
Chris Lattner79084302007-02-04 01:31:47 +0000332 DenseMap<const Value*, SDOperand> NodeMap;
Chris Lattner7a60d912005-01-07 07:47:53 +0000333
Chris Lattner4d9651c2005-01-17 22:19:26 +0000334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
335 /// them up and then emit token factor nodes when possible. This allows us to
336 /// get simple disambiguation between loads without worrying about alias
337 /// analysis.
338 std::vector<SDOperand> PendingLoads;
339
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000340 /// Case - A struct to record the Value for a switch case, and the
341 /// case's target basic block.
342 struct Case {
343 Constant* Low;
344 Constant* High;
345 MachineBasicBlock* BB;
346
347 Case() : Low(0), High(0), BB(0) { }
348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
349 Low(low), High(high), BB(bb) { }
350 uint64_t size() const {
351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
353 return (rHigh - rLow + 1ULL);
354 }
355 };
356
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000357 struct CaseBits {
358 uint64_t Mask;
359 MachineBasicBlock* BB;
360 unsigned Bits;
361
362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
363 Mask(mask), BB(bb), Bits(bits) { }
364 };
365
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000366 typedef std::vector<Case> CaseVector;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000367 typedef std::vector<CaseBits> CaseBitsVector;
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000368 typedef CaseVector::iterator CaseItr;
369 typedef std::pair<CaseItr, CaseItr> CaseRange;
Nate Begemaned728c12006-03-27 01:32:24 +0000370
371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
372 /// of conditional branches.
373 struct CaseRec {
374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
375 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
376
377 /// CaseBB - The MBB in which to emit the compare and branch
378 MachineBasicBlock *CaseBB;
379 /// LT, GE - If nonzero, we know the current case value must be less-than or
380 /// greater-than-or-equal-to these Constants.
381 Constant *LT;
382 Constant *GE;
383 /// Range - A pair of iterators representing the range of case values to be
384 /// processed at this point in the binary search tree.
385 CaseRange Range;
386 };
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +0000387
388 typedef std::vector<CaseRec> CaseRecVector;
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000389
390 /// The comparison function for sorting the switch case values in the vector.
391 /// WARNING: Case ranges should be disjoint!
Nate Begemaned728c12006-03-27 01:32:24 +0000392 struct CaseCmp {
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000393 bool operator () (const Case& C1, const Case& C2) {
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
397 return CI1->getValue().slt(CI2->getValue());
Nate Begemaned728c12006-03-27 01:32:24 +0000398 }
399 };
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000400
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000401 struct CaseBitsCmp {
402 bool operator () (const CaseBits& C1, const CaseBits& C2) {
403 return C1.Bits > C2.Bits;
404 }
405 };
406
Anton Korobeynikov915e6172007-04-04 21:14:49 +0000407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
Nate Begemaned728c12006-03-27 01:32:24 +0000408
Chris Lattner7a60d912005-01-07 07:47:53 +0000409public:
410 // TLI - This is information that describes the available target features we
411 // need for lowering. This indicates when operations are unavailable,
412 // implemented with a libcall, etc.
413 TargetLowering &TLI;
414 SelectionDAG &DAG;
Owen Anderson20a631f2006-05-03 01:29:57 +0000415 const TargetData *TD;
Dan Gohman8dc0b932007-08-27 16:26:13 +0000416 AliasAnalysis &AA;
Chris Lattner7a60d912005-01-07 07:47:53 +0000417
Nate Begemaned728c12006-03-27 01:32:24 +0000418 /// SwitchCases - Vector of CaseBlock structures used to communicate
419 /// SwitchInst code generation information.
420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
Anton Korobeynikov70378262007-03-25 15:07:15 +0000421 /// JTCases - Vector of JumpTable structures used to communicate
422 /// SwitchInst code generation information.
423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
Nate Begemaned728c12006-03-27 01:32:24 +0000425
Chris Lattner7a60d912005-01-07 07:47:53 +0000426 /// FuncInfo - Information about the function as a whole.
427 ///
428 FunctionLoweringInfo &FuncInfo;
429
430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
Dan Gohman8dc0b932007-08-27 16:26:13 +0000431 AliasAnalysis &aa,
Misha Brukman835702a2005-04-21 22:36:52 +0000432 FunctionLoweringInfo &funcinfo)
Dan Gohman8dc0b932007-08-27 16:26:13 +0000433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
Anton Korobeynikov70378262007-03-25 15:07:15 +0000434 FuncInfo(funcinfo) {
Chris Lattner7a60d912005-01-07 07:47:53 +0000435 }
436
Chris Lattner4108bb02005-01-17 19:43:36 +0000437 /// getRoot - Return the current virtual root of the Selection DAG.
438 ///
439 SDOperand getRoot() {
Chris Lattner4d9651c2005-01-17 22:19:26 +0000440 if (PendingLoads.empty())
441 return DAG.getRoot();
Misha Brukman835702a2005-04-21 22:36:52 +0000442
Chris Lattner4d9651c2005-01-17 22:19:26 +0000443 if (PendingLoads.size() == 1) {
444 SDOperand Root = PendingLoads[0];
445 DAG.setRoot(Root);
446 PendingLoads.clear();
447 return Root;
448 }
449
450 // Otherwise, we have to make a token factor node.
Chris Lattnerc24a1d32006-08-08 02:23:42 +0000451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
452 &PendingLoads[0], PendingLoads.size());
Chris Lattner4d9651c2005-01-17 22:19:26 +0000453 PendingLoads.clear();
454 DAG.setRoot(Root);
455 return Root;
Chris Lattner4108bb02005-01-17 19:43:36 +0000456 }
457
Chris Lattnered0110b2006-10-27 21:36:01 +0000458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
459
Chris Lattner7a60d912005-01-07 07:47:53 +0000460 void visit(Instruction &I) { visit(I.getOpcode(), I); }
461
462 void visit(unsigned Opcode, User &I) {
Chris Lattnerd5e604d2006-11-10 04:41:34 +0000463 // Note: this doesn't use InstVisitor, because it has to work with
464 // ConstantExpr's in addition to instructions.
Chris Lattner7a60d912005-01-07 07:47:53 +0000465 switch (Opcode) {
466 default: assert(0 && "Unknown instruction type encountered!");
467 abort();
468 // Build the switch statement using the Instruction.def file.
469#define HANDLE_INST(NUM, OPCODE, CLASS) \
470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
471#include "llvm/Instruction.def"
472 }
473 }
474
475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
476
Chris Lattner4024c002006-03-15 22:19:46 +0000477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
Evan Chenge71fe34d2006-10-09 20:57:25 +0000478 const Value *SV, SDOperand Root,
Christopher Lamb8af6d582007-04-22 23:15:30 +0000479 bool isVolatile, unsigned Alignment);
Chris Lattner7a60d912005-01-07 07:47:53 +0000480
481 SDOperand getIntPtrConstant(uint64_t Val) {
482 return DAG.getConstant(Val, TLI.getPointerTy());
483 }
484
Chris Lattner8471b152006-03-16 19:57:50 +0000485 SDOperand getValue(const Value *V);
Chris Lattner7a60d912005-01-07 07:47:53 +0000486
Chris Lattner79084302007-02-04 01:31:47 +0000487 void setValue(const Value *V, SDOperand NewN) {
Chris Lattner7a60d912005-01-07 07:47:53 +0000488 SDOperand &N = NodeMap[V];
489 assert(N.Val == 0 && "Already set a value for this node!");
Chris Lattner79084302007-02-04 01:31:47 +0000490 N = NewN;
Chris Lattner7a60d912005-01-07 07:47:53 +0000491 }
Chris Lattner1558fc62006-02-01 18:59:47 +0000492
Chris Lattner8cfd33b2007-04-30 21:11:17 +0000493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
494 std::set<unsigned> &OutputRegs,
495 std::set<unsigned> &InputRegs);
Nate Begemaned728c12006-03-27 01:32:24 +0000496
Chris Lattnered0110b2006-10-27 21:36:01 +0000497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
499 unsigned Opc);
Chris Lattner84a03502006-10-27 23:50:33 +0000500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
Chris Lattnered0110b2006-10-27 21:36:01 +0000501 void ExportFromCurrentBlock(Value *V);
Duncan Sandsad0ea2d2007-11-27 13:23:08 +0000502 void LowerCallTo(Instruction &I, const Type *CalledValueTy,
503 const ParamAttrsList *PAL, unsigned CallingConv,
Anton Korobeynikov3b327822007-05-23 11:08:31 +0000504 bool IsTailCall, SDOperand Callee, unsigned OpIdx,
505 MachineBasicBlock *LandingPad = NULL);
Duncan Sandsad0ea2d2007-11-27 13:23:08 +0000506
Chris Lattner7a60d912005-01-07 07:47:53 +0000507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
Nate Begemaned728c12006-03-27 01:32:24 +0000510 void visitSwitch(SwitchInst &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
512
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +0000513 // Helpers for visitSwitch
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +0000514 bool handleSmallSwitchRange(CaseRec& CR,
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +0000515 CaseRecVector& WorkList,
516 Value* SV,
517 MachineBasicBlock* Default);
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +0000518 bool handleJTSwitchCase(CaseRec& CR,
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +0000519 CaseRecVector& WorkList,
520 Value* SV,
521 MachineBasicBlock* Default);
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +0000522 bool handleBTSplitSwitchCase(CaseRec& CR,
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +0000523 CaseRecVector& WorkList,
524 Value* SV,
525 MachineBasicBlock* Default);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
528 Value* SV,
529 MachineBasicBlock* Default);
Nate Begemaned728c12006-03-27 01:32:24 +0000530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +0000531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
533 unsigned Reg,
534 SelectionDAGISel::BitTestCase &B);
Nate Begeman4ca2ea52006-04-22 18:53:45 +0000535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
Anton Korobeynikov70378262007-03-25 15:07:15 +0000536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
Nate Begemaned728c12006-03-27 01:32:24 +0000538
Chris Lattner7a60d912005-01-07 07:47:53 +0000539 // These all get lowered before this pass.
Jim Laskey4b37a4c2007-02-21 22:53:45 +0000540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000542
Dan Gohmana8665142007-06-25 16:23:39 +0000543 void visitBinary(User &I, unsigned OpCode);
Nate Begeman127321b2005-11-18 07:42:56 +0000544 void visitShift(User &I, unsigned Opcode);
Nate Begemanb2e089c2005-11-19 00:36:38 +0000545 void visitAdd(User &I) {
Dan Gohmana8665142007-06-25 16:23:39 +0000546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
Reid Spencer7e80b0b2006-10-26 06:15:43 +0000548 else
Dan Gohmana8665142007-06-25 16:23:39 +0000549 visitBinary(I, ISD::ADD);
Chris Lattner6f3b5772005-09-28 22:28:18 +0000550 }
Chris Lattnerf68fd0b2005-04-02 05:04:50 +0000551 void visitSub(User &I);
Reid Spencer7e80b0b2006-10-26 06:15:43 +0000552 void visitMul(User &I) {
Dan Gohmana8665142007-06-25 16:23:39 +0000553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
Reid Spencer7e80b0b2006-10-26 06:15:43 +0000555 else
Dan Gohmana8665142007-06-25 16:23:39 +0000556 visitBinary(I, ISD::MUL);
Chris Lattner6f3b5772005-09-28 22:28:18 +0000557 }
Dan Gohmana8665142007-06-25 16:23:39 +0000558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
Reid Spencer2eadb532007-01-21 00:29:26 +0000567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
Reid Spencerfdff9382006-11-08 06:47:33 +0000568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
Reid Spencerd9436b62006-11-20 01:22:35 +0000570 void visitICmp(User &I);
571 void visitFCmp(User &I);
Reid Spencer6c38f0b2006-11-27 01:05:10 +0000572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000585
Chris Lattner67271862006-03-29 00:11:43 +0000586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
Chris Lattner098c01e2006-04-08 04:15:24 +0000588 void visitShuffleVector(User &I);
Chris Lattner32206f52006-03-18 01:44:44 +0000589
Chris Lattner7a60d912005-01-07 07:47:53 +0000590 void visitGetElementPtr(User &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000591 void visitSelect(User &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000592
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
Chris Lattner476e67b2006-01-26 22:24:51 +0000600 void visitInlineAsm(CallInst &I);
Chris Lattnercd6f0f42005-11-09 19:44:01 +0000601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
Chris Lattnerd96b09a2006-03-24 02:22:33 +0000602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
Chris Lattner7a60d912005-01-07 07:47:53 +0000603
Chris Lattner7a60d912005-01-07 07:47:53 +0000604 void visitVAStart(CallInst &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
Chris Lattner7a60d912005-01-07 07:47:53 +0000608
Chris Lattner875def92005-01-11 05:56:49 +0000609 void visitMemIntrinsic(CallInst &I, unsigned Op);
Chris Lattner7a60d912005-01-07 07:47:53 +0000610
611 void visitUserOp1(Instruction &I) {
612 assert(0 && "UserOp1 should not exist at instruction selection time!");
613 abort();
614 }
615 void visitUserOp2(Instruction &I) {
616 assert(0 && "UserOp2 should not exist at instruction selection time!");
617 abort();
618 }
619};
620} // end namespace llvm
621
Dan Gohmand258e802007-07-05 20:12:34 +0000622
623/// getCopyFromParts - Create a value that contains the
624/// specified legal parts combined into the value they represent.
625static SDOperand getCopyFromParts(SelectionDAG &DAG,
626 const SDOperand *Parts,
627 unsigned NumParts,
628 MVT::ValueType PartVT,
629 MVT::ValueType ValueVT,
Dan Gohmand258e802007-07-05 20:12:34 +0000630 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
631 if (!MVT::isVector(ValueVT) || NumParts == 1) {
632 SDOperand Val = Parts[0];
633
634 // If the value was expanded, copy from the top part.
635 if (NumParts > 1) {
636 assert(NumParts == 2 &&
637 "Cannot expand to more than 2 elts yet!");
638 SDOperand Hi = Parts[1];
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000639 if (!DAG.getTargetLoweringInfo().isLittleEndian())
Dan Gohmand258e802007-07-05 20:12:34 +0000640 std::swap(Val, Hi);
641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
642 }
643
644 // Otherwise, if the value was promoted or extended, truncate it to the
645 // appropriate type.
646 if (PartVT == ValueVT)
647 return Val;
648
649 if (MVT::isVector(PartVT)) {
650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
Dan Gohmane3583812007-10-12 14:33:11 +0000651 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
652 }
653
654 if (MVT::isVector(ValueVT)) {
655 assert(NumParts == 1 &&
656 MVT::getVectorElementType(ValueVT) == PartVT &&
657 MVT::getVectorNumElements(ValueVT) == 1 &&
658 "Only trivial scalar-to-vector conversions should get here!");
659 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
Dan Gohmand258e802007-07-05 20:12:34 +0000660 }
661
662 if (MVT::isInteger(PartVT) &&
663 MVT::isInteger(ValueVT)) {
664 if (ValueVT < PartVT) {
665 // For a truncate, see if we have any information to
666 // indicate whether the truncated bits will always be
667 // zero or sign-extension.
668 if (AssertOp != ISD::DELETED_NODE)
669 Val = DAG.getNode(AssertOp, PartVT, Val,
670 DAG.getValueType(ValueVT));
671 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
672 } else {
673 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
674 }
675 }
676
677 if (MVT::isFloatingPoint(PartVT) &&
678 MVT::isFloatingPoint(ValueVT))
679 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
680
681 if (MVT::getSizeInBits(PartVT) ==
682 MVT::getSizeInBits(ValueVT))
683 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
684
685 assert(0 && "Unknown mismatch!");
686 }
687
688 // Handle a multi-element vector.
689 MVT::ValueType IntermediateVT, RegisterVT;
690 unsigned NumIntermediates;
691 unsigned NumRegs =
692 DAG.getTargetLoweringInfo()
693 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
694 RegisterVT);
695
696 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
697 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
698 assert(RegisterVT == Parts[0].getValueType() &&
699 "Part type doesn't match part!");
700
701 // Assemble the parts into intermediate operands.
702 SmallVector<SDOperand, 8> Ops(NumIntermediates);
703 if (NumIntermediates == NumParts) {
704 // If the register was not expanded, truncate or copy the value,
705 // as appropriate.
706 for (unsigned i = 0; i != NumParts; ++i)
707 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000708 PartVT, IntermediateVT);
Dan Gohmand258e802007-07-05 20:12:34 +0000709 } else if (NumParts > 0) {
710 // If the intermediate type was expanded, build the intermediate operands
711 // from the parts.
Dan Gohman4ff9fb12007-07-30 19:09:17 +0000712 assert(NumParts % NumIntermediates == 0 &&
Dan Gohmand258e802007-07-05 20:12:34 +0000713 "Must expand into a divisible number of parts!");
Dan Gohman4ff9fb12007-07-30 19:09:17 +0000714 unsigned Factor = NumParts / NumIntermediates;
Dan Gohmand258e802007-07-05 20:12:34 +0000715 for (unsigned i = 0; i != NumIntermediates; ++i)
716 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000717 PartVT, IntermediateVT);
Dan Gohmand258e802007-07-05 20:12:34 +0000718 }
719
720 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
721 // operands.
722 return DAG.getNode(MVT::isVector(IntermediateVT) ?
723 ISD::CONCAT_VECTORS :
724 ISD::BUILD_VECTOR,
Dan Gohman4ff9fb12007-07-30 19:09:17 +0000725 ValueVT, &Ops[0], NumIntermediates);
Dan Gohmand258e802007-07-05 20:12:34 +0000726}
727
728/// getCopyToParts - Create a series of nodes that contain the
729/// specified value split into legal parts.
730static void getCopyToParts(SelectionDAG &DAG,
731 SDOperand Val,
732 SDOperand *Parts,
733 unsigned NumParts,
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000734 MVT::ValueType PartVT) {
Dan Gohmana17799a2007-08-10 14:59:38 +0000735 TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 MVT::ValueType PtrVT = TLI.getPointerTy();
Dan Gohmand258e802007-07-05 20:12:34 +0000737 MVT::ValueType ValueVT = Val.getValueType();
738
739 if (!MVT::isVector(ValueVT) || NumParts == 1) {
740 // If the value was expanded, copy from the parts.
741 if (NumParts > 1) {
742 for (unsigned i = 0; i != NumParts; ++i)
743 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
Dan Gohmana17799a2007-08-10 14:59:38 +0000744 DAG.getConstant(i, PtrVT));
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000745 if (!DAG.getTargetLoweringInfo().isLittleEndian())
Dan Gohmand258e802007-07-05 20:12:34 +0000746 std::reverse(Parts, Parts + NumParts);
747 return;
748 }
749
750 // If there is a single part and the types differ, this must be
751 // a promotion.
752 if (PartVT != ValueVT) {
753 if (MVT::isVector(PartVT)) {
754 assert(MVT::isVector(ValueVT) &&
755 "Not a vector-vector cast?");
756 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
Dan Gohmane3583812007-10-12 14:33:11 +0000757 } else if (MVT::isVector(ValueVT)) {
758 assert(NumParts == 1 &&
759 MVT::getVectorElementType(ValueVT) == PartVT &&
760 MVT::getVectorNumElements(ValueVT) == 1 &&
761 "Only trivial vector-to-scalar conversions should get here!");
762 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
763 DAG.getConstant(0, PtrVT));
Dan Gohmand258e802007-07-05 20:12:34 +0000764 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
765 if (PartVT < ValueVT)
766 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
767 else
768 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
769 } else if (MVT::isFloatingPoint(PartVT) &&
770 MVT::isFloatingPoint(ValueVT)) {
771 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
772 } else if (MVT::getSizeInBits(PartVT) ==
773 MVT::getSizeInBits(ValueVT)) {
774 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
775 } else {
776 assert(0 && "Unknown mismatch!");
777 }
778 }
779 Parts[0] = Val;
780 return;
781 }
782
783 // Handle a multi-element vector.
784 MVT::ValueType IntermediateVT, RegisterVT;
785 unsigned NumIntermediates;
786 unsigned NumRegs =
787 DAG.getTargetLoweringInfo()
788 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
789 RegisterVT);
790 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
791
792 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
793 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
794
795 // Split the vector into intermediate operands.
796 SmallVector<SDOperand, 8> Ops(NumIntermediates);
797 for (unsigned i = 0; i != NumIntermediates; ++i)
798 if (MVT::isVector(IntermediateVT))
799 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
800 IntermediateVT, Val,
801 DAG.getConstant(i * (NumElements / NumIntermediates),
Dan Gohmana17799a2007-08-10 14:59:38 +0000802 PtrVT));
Dan Gohmand258e802007-07-05 20:12:34 +0000803 else
804 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
805 IntermediateVT, Val,
Dan Gohmana17799a2007-08-10 14:59:38 +0000806 DAG.getConstant(i, PtrVT));
Dan Gohmand258e802007-07-05 20:12:34 +0000807
808 // Split the intermediate operands into legal parts.
809 if (NumParts == NumIntermediates) {
810 // If the register was not expanded, promote or copy the value,
811 // as appropriate.
812 for (unsigned i = 0; i != NumParts; ++i)
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000813 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
Dan Gohmand258e802007-07-05 20:12:34 +0000814 } else if (NumParts > 0) {
815 // If the intermediate type was expanded, split each the value into
816 // legal parts.
817 assert(NumParts % NumIntermediates == 0 &&
818 "Must expand into a divisible number of parts!");
819 unsigned Factor = NumParts / NumIntermediates;
820 for (unsigned i = 0; i != NumIntermediates; ++i)
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000821 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
Dan Gohmand258e802007-07-05 20:12:34 +0000822 }
823}
824
825
Chris Lattner8471b152006-03-16 19:57:50 +0000826SDOperand SelectionDAGLowering::getValue(const Value *V) {
827 SDOperand &N = NodeMap[V];
828 if (N.Val) return N;
829
830 const Type *VTy = V->getType();
831 MVT::ValueType VT = TLI.getValueType(VTy);
832 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
833 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
834 visit(CE->getOpcode(), *CE);
Chris Lattner79084302007-02-04 01:31:47 +0000835 SDOperand N1 = NodeMap[V];
836 assert(N1.Val && "visit didn't populate the ValueMap!");
837 return N1;
Chris Lattner8471b152006-03-16 19:57:50 +0000838 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
839 return N = DAG.getGlobalAddress(GV, VT);
840 } else if (isa<ConstantPointerNull>(C)) {
841 return N = DAG.getConstant(0, TLI.getPointerTy());
842 } else if (isa<UndefValue>(C)) {
Reid Spencerd84d35b2007-02-15 02:26:10 +0000843 if (!isa<VectorType>(VTy))
Chris Lattnerc16b05e2006-03-19 00:20:20 +0000844 return N = DAG.getNode(ISD::UNDEF, VT);
845
Dan Gohmana8665142007-06-25 16:23:39 +0000846 // Create a BUILD_VECTOR of undef nodes.
Reid Spencerd84d35b2007-02-15 02:26:10 +0000847 const VectorType *PTy = cast<VectorType>(VTy);
Chris Lattnerc16b05e2006-03-19 00:20:20 +0000848 unsigned NumElements = PTy->getNumElements();
849 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
850
Chris Lattnerc24a1d32006-08-08 02:23:42 +0000851 SmallVector<SDOperand, 8> Ops;
Chris Lattnerc16b05e2006-03-19 00:20:20 +0000852 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
853
854 // Create a VConstant node with generic Vector type.
Dan Gohmana8665142007-06-25 16:23:39 +0000855 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
856 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
Chris Lattnerc24a1d32006-08-08 02:23:42 +0000857 &Ops[0], Ops.size());
Chris Lattner8471b152006-03-16 19:57:50 +0000858 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
Dale Johannesenbed9dc42007-09-06 18:13:44 +0000859 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
Reid Spencerd84d35b2007-02-15 02:26:10 +0000860 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
Chris Lattner8471b152006-03-16 19:57:50 +0000861 unsigned NumElements = PTy->getNumElements();
862 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
Chris Lattner8471b152006-03-16 19:57:50 +0000863
864 // Now that we know the number and type of the elements, push a
865 // Constant or ConstantFP node onto the ops list for each element of
Dan Gohman06c60b62007-07-16 14:29:03 +0000866 // the vector constant.
Chris Lattnerc24a1d32006-08-08 02:23:42 +0000867 SmallVector<SDOperand, 8> Ops;
Reid Spencerd84d35b2007-02-15 02:26:10 +0000868 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
Chris Lattner67271862006-03-29 00:11:43 +0000869 for (unsigned i = 0; i != NumElements; ++i)
870 Ops.push_back(getValue(CP->getOperand(i)));
Chris Lattner8471b152006-03-16 19:57:50 +0000871 } else {
Dan Gohman06c60b62007-07-16 14:29:03 +0000872 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
Chris Lattner8471b152006-03-16 19:57:50 +0000873 SDOperand Op;
874 if (MVT::isFloatingPoint(PVT))
875 Op = DAG.getConstantFP(0, PVT);
876 else
877 Op = DAG.getConstant(0, PVT);
878 Ops.assign(NumElements, Op);
879 }
880
Dan Gohmana8665142007-06-25 16:23:39 +0000881 // Create a BUILD_VECTOR node.
882 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
883 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
Chris Lattner79084302007-02-04 01:31:47 +0000884 Ops.size());
Chris Lattner8471b152006-03-16 19:57:50 +0000885 } else {
886 // Canonicalize all constant ints to be unsigned.
Zhou Sheng75b871f2007-01-11 12:24:14 +0000887 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
Chris Lattner8471b152006-03-16 19:57:50 +0000888 }
889 }
890
891 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
892 std::map<const AllocaInst*, int>::iterator SI =
893 FuncInfo.StaticAllocaMap.find(AI);
894 if (SI != FuncInfo.StaticAllocaMap.end())
895 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
896 }
897
Chris Lattner8c504cf2007-02-25 18:40:32 +0000898 unsigned InReg = FuncInfo.ValueMap[V];
899 assert(InReg && "Value not in map!");
Chris Lattner8471b152006-03-16 19:57:50 +0000900
Dan Gohman78677932007-06-28 23:29:44 +0000901 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
902 unsigned NumRegs = TLI.getNumRegisters(VT);
Chris Lattner5fe1f542006-03-31 02:06:56 +0000903
Dan Gohman78677932007-06-28 23:29:44 +0000904 std::vector<unsigned> Regs(NumRegs);
905 for (unsigned i = 0; i != NumRegs; ++i)
906 Regs[i] = InReg + i;
907
908 RegsForValue RFV(Regs, RegisterVT, VT);
909 SDOperand Chain = DAG.getEntryNode();
910
911 return RFV.getCopyFromRegs(DAG, Chain, NULL);
Chris Lattner8471b152006-03-16 19:57:50 +0000912}
913
914
Chris Lattner7a60d912005-01-07 07:47:53 +0000915void SelectionDAGLowering::visitRet(ReturnInst &I) {
916 if (I.getNumOperands() == 0) {
Chris Lattner4108bb02005-01-17 19:43:36 +0000917 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
Chris Lattner7a60d912005-01-07 07:47:53 +0000918 return;
919 }
Chris Lattnerc24a1d32006-08-08 02:23:42 +0000920 SmallVector<SDOperand, 8> NewValues;
Nate Begeman8c47c3a2006-01-27 21:09:22 +0000921 NewValues.push_back(getRoot());
922 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
923 SDOperand RetOp = getValue(I.getOperand(i));
924
925 // If this is an integer return value, we need to promote it ourselves to
Dan Gohmand258e802007-07-05 20:12:34 +0000926 // the full width of a register, since getCopyToParts and Legalize will use
927 // ANY_EXTEND rather than sign/zero.
Evan Chenga2e99532006-05-26 23:09:09 +0000928 // FIXME: C calling convention requires the return type to be promoted to
929 // at least 32-bit. But this is not necessary for non-C calling conventions.
Nate Begeman8c47c3a2006-01-27 21:09:22 +0000930 if (MVT::isInteger(RetOp.getValueType()) &&
931 RetOp.getValueType() < MVT::i64) {
932 MVT::ValueType TmpVT;
933 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
934 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
935 else
936 TmpVT = MVT::i32;
Duncan Sandsad0ea2d2007-11-27 13:23:08 +0000937 const ParamAttrsList *PAL = I.getParent()->getParent()->getParamAttrs();
Reid Spencere6f81872007-01-03 16:49:33 +0000938 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
Duncan Sandsad0ea2d2007-11-27 13:23:08 +0000939 if (PAL && PAL->paramHasAttr(0, ParamAttr::SExt))
Reid Spencer0917adf2007-01-03 04:25:33 +0000940 ExtendKind = ISD::SIGN_EXTEND;
Duncan Sandsad0ea2d2007-11-27 13:23:08 +0000941 if (PAL && PAL->paramHasAttr(0, ParamAttr::ZExt))
Reid Spencere63b6512006-12-31 05:55:36 +0000942 ExtendKind = ISD::ZERO_EXTEND;
Reid Spencer2a34b912007-01-03 05:03:05 +0000943 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
Dan Gohmand258e802007-07-05 20:12:34 +0000944 NewValues.push_back(RetOp);
945 NewValues.push_back(DAG.getConstant(false, MVT::i32));
946 } else {
947 MVT::ValueType VT = RetOp.getValueType();
948 unsigned NumParts = TLI.getNumRegisters(VT);
949 MVT::ValueType PartVT = TLI.getRegisterType(VT);
950 SmallVector<SDOperand, 4> Parts(NumParts);
Dan Gohmanf8f531b2007-07-09 20:59:04 +0000951 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
Dan Gohmand258e802007-07-05 20:12:34 +0000952 for (unsigned i = 0; i < NumParts; ++i) {
953 NewValues.push_back(Parts[i]);
954 NewValues.push_back(DAG.getConstant(false, MVT::i32));
955 }
Nate Begeman8c47c3a2006-01-27 21:09:22 +0000956 }
Chris Lattner7a60d912005-01-07 07:47:53 +0000957 }
Chris Lattnerc24a1d32006-08-08 02:23:42 +0000958 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
959 &NewValues[0], NewValues.size()));
Chris Lattner7a60d912005-01-07 07:47:53 +0000960}
961
Chris Lattnered0110b2006-10-27 21:36:01 +0000962/// ExportFromCurrentBlock - If this condition isn't known to be exported from
963/// the current basic block, add it to ValueMap now so that we'll get a
964/// CopyTo/FromReg.
965void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
966 // No need to export constants.
967 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
968
969 // Already exported?
970 if (FuncInfo.isExportedInst(V)) return;
971
972 unsigned Reg = FuncInfo.InitializeRegForValue(V);
973 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
974}
975
Chris Lattner84a03502006-10-27 23:50:33 +0000976bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
977 const BasicBlock *FromBB) {
978 // The operands of the setcc have to be in this block. We don't know
979 // how to export them from some other block.
980 if (Instruction *VI = dyn_cast<Instruction>(V)) {
981 // Can export from current BB.
982 if (VI->getParent() == FromBB)
983 return true;
984
985 // Is already exported, noop.
986 return FuncInfo.isExportedInst(V);
987 }
988
989 // If this is an argument, we can export it if the BB is the entry block or
990 // if it is already exported.
991 if (isa<Argument>(V)) {
992 if (FromBB == &FromBB->getParent()->getEntryBlock())
993 return true;
994
995 // Otherwise, can only export this if it is already exported.
996 return FuncInfo.isExportedInst(V);
997 }
998
999 // Otherwise, constants can always be exported.
1000 return true;
1001}
1002
Chris Lattnere60ae822006-10-29 21:01:20 +00001003static bool InBlock(const Value *V, const BasicBlock *BB) {
1004 if (const Instruction *I = dyn_cast<Instruction>(V))
1005 return I->getParent() == BB;
1006 return true;
1007}
1008
Chris Lattnered0110b2006-10-27 21:36:01 +00001009/// FindMergedConditions - If Cond is an expression like
1010void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1011 MachineBasicBlock *TBB,
1012 MachineBasicBlock *FBB,
1013 MachineBasicBlock *CurBB,
1014 unsigned Opc) {
Chris Lattnered0110b2006-10-27 21:36:01 +00001015 // If this node is not part of the or/and tree, emit it as a branch.
Reid Spencer266e42b2006-12-23 06:05:41 +00001016 Instruction *BOp = dyn_cast<Instruction>(Cond);
Chris Lattnered0110b2006-10-27 21:36:01 +00001017
Reid Spencer266e42b2006-12-23 06:05:41 +00001018 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1019 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
Chris Lattnere60ae822006-10-29 21:01:20 +00001020 BOp->getParent() != CurBB->getBasicBlock() ||
1021 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1022 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
Chris Lattnered0110b2006-10-27 21:36:01 +00001023 const BasicBlock *BB = CurBB->getBasicBlock();
1024
Reid Spencer266e42b2006-12-23 06:05:41 +00001025 // If the leaf of the tree is a comparison, merge the condition into
1026 // the caseblock.
1027 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1028 // The operands of the cmp have to be in this block. We don't know
Chris Lattnerf31b9ef2006-10-29 18:23:37 +00001029 // how to export them from some other block. If this is the first block
1030 // of the sequence, no exporting is needed.
1031 (CurBB == CurMBB ||
1032 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1033 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
Reid Spencer266e42b2006-12-23 06:05:41 +00001034 BOp = cast<Instruction>(Cond);
1035 ISD::CondCode Condition;
1036 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1037 switch (IC->getPredicate()) {
1038 default: assert(0 && "Unknown icmp predicate opcode!");
1039 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1040 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1041 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1042 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1043 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1044 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1045 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1046 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1047 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1048 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1049 }
1050 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1051 ISD::CondCode FPC, FOC;
1052 switch (FC->getPredicate()) {
1053 default: assert(0 && "Unknown fcmp predicate opcode!");
1054 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1055 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1056 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1057 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1058 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1059 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1060 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1061 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1062 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1063 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1064 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1065 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1066 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1067 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1068 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1069 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1070 }
1071 if (FiniteOnlyFPMath())
1072 Condition = FOC;
1073 else
1074 Condition = FPC;
1075 } else {
Chris Lattner79084302007-02-04 01:31:47 +00001076 Condition = ISD::SETEQ; // silence warning.
Reid Spencer266e42b2006-12-23 06:05:41 +00001077 assert(0 && "Unknown compare instruction");
Chris Lattnered0110b2006-10-27 21:36:01 +00001078 }
1079
Chris Lattnered0110b2006-10-27 21:36:01 +00001080 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001081 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
Chris Lattnered0110b2006-10-27 21:36:01 +00001082 SwitchCases.push_back(CB);
1083 return;
1084 }
1085
1086 // Create a CaseBlock record representing this branch.
Zhou Sheng75b871f2007-01-11 12:24:14 +00001087 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001088 NULL, TBB, FBB, CurBB);
Chris Lattnered0110b2006-10-27 21:36:01 +00001089 SwitchCases.push_back(CB);
Chris Lattnered0110b2006-10-27 21:36:01 +00001090 return;
1091 }
1092
Chris Lattnerf1b54fd2006-10-27 21:54:23 +00001093
1094 // Create TmpBB after CurBB.
Chris Lattnered0110b2006-10-27 21:36:01 +00001095 MachineFunction::iterator BBI = CurBB;
1096 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1097 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1098
Chris Lattnerf1b54fd2006-10-27 21:54:23 +00001099 if (Opc == Instruction::Or) {
1100 // Codegen X | Y as:
1101 // jmp_if_X TBB
1102 // jmp TmpBB
1103 // TmpBB:
1104 // jmp_if_Y TBB
1105 // jmp FBB
1106 //
Chris Lattnered0110b2006-10-27 21:36:01 +00001107
Chris Lattnerf1b54fd2006-10-27 21:54:23 +00001108 // Emit the LHS condition.
1109 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1110
1111 // Emit the RHS condition into TmpBB.
1112 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1113 } else {
1114 assert(Opc == Instruction::And && "Unknown merge op!");
1115 // Codegen X & Y as:
1116 // jmp_if_X TmpBB
1117 // jmp FBB
1118 // TmpBB:
1119 // jmp_if_Y TBB
1120 // jmp FBB
1121 //
1122 // This requires creation of TmpBB after CurBB.
1123
1124 // Emit the LHS condition.
1125 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1126
1127 // Emit the RHS condition into TmpBB.
1128 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1129 }
Chris Lattnered0110b2006-10-27 21:36:01 +00001130}
1131
Chris Lattner427301f2006-10-31 22:37:42 +00001132/// If the set of cases should be emitted as a series of branches, return true.
1133/// If we should emit this as a bunch of and/or'd together conditions, return
1134/// false.
1135static bool
1136ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1137 if (Cases.size() != 2) return true;
1138
Chris Lattnerfe43bef2006-10-31 23:06:00 +00001139 // If this is two comparisons of the same values or'd or and'd together, they
1140 // will get folded into a single comparison, so don't emit two blocks.
1141 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1142 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1143 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1144 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1145 return false;
1146 }
1147
Chris Lattner427301f2006-10-31 22:37:42 +00001148 return true;
1149}
1150
Chris Lattner7a60d912005-01-07 07:47:53 +00001151void SelectionDAGLowering::visitBr(BranchInst &I) {
1152 // Update machine-CFG edges.
1153 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
Chris Lattner7a60d912005-01-07 07:47:53 +00001154
1155 // Figure out which block is immediately after the current one.
1156 MachineBasicBlock *NextBlock = 0;
1157 MachineFunction::iterator BBI = CurMBB;
1158 if (++BBI != CurMBB->getParent()->end())
1159 NextBlock = BBI;
1160
1161 if (I.isUnconditional()) {
1162 // If this is not a fall-through branch, emit the branch.
1163 if (Succ0MBB != NextBlock)
Chris Lattner4108bb02005-01-17 19:43:36 +00001164 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
Misha Brukman77451162005-04-22 04:01:18 +00001165 DAG.getBasicBlock(Succ0MBB)));
Chris Lattner7a60d912005-01-07 07:47:53 +00001166
Chris Lattner963ddad2006-10-24 17:57:59 +00001167 // Update machine-CFG edges.
1168 CurMBB->addSuccessor(Succ0MBB);
1169
1170 return;
1171 }
1172
1173 // If this condition is one of the special cases we handle, do special stuff
1174 // now.
1175 Value *CondVal = I.getCondition();
Chris Lattner963ddad2006-10-24 17:57:59 +00001176 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
Chris Lattnered0110b2006-10-27 21:36:01 +00001177
1178 // If this is a series of conditions that are or'd or and'd together, emit
1179 // this as a sequence of branches instead of setcc's with and/or operations.
1180 // For example, instead of something like:
1181 // cmp A, B
1182 // C = seteq
1183 // cmp D, E
1184 // F = setle
1185 // or C, F
1186 // jnz foo
1187 // Emit:
1188 // cmp A, B
1189 // je foo
1190 // cmp D, E
1191 // jle foo
1192 //
1193 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1194 if (BOp->hasOneUse() &&
Chris Lattnerf1b54fd2006-10-27 21:54:23 +00001195 (BOp->getOpcode() == Instruction::And ||
Chris Lattnered0110b2006-10-27 21:36:01 +00001196 BOp->getOpcode() == Instruction::Or)) {
1197 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
Chris Lattnerfe43bef2006-10-31 23:06:00 +00001198 // If the compares in later blocks need to use values not currently
1199 // exported from this block, export them now. This block should always
1200 // be the first entry.
1201 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1202
Chris Lattner427301f2006-10-31 22:37:42 +00001203 // Allow some cases to be rejected.
1204 if (ShouldEmitAsBranches(SwitchCases)) {
Chris Lattner427301f2006-10-31 22:37:42 +00001205 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1206 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1207 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1208 }
1209
1210 // Emit the branch for this block.
1211 visitSwitchCase(SwitchCases[0]);
1212 SwitchCases.erase(SwitchCases.begin());
1213 return;
Chris Lattnerf31b9ef2006-10-29 18:23:37 +00001214 }
1215
Chris Lattnerfe43bef2006-10-31 23:06:00 +00001216 // Okay, we decided not to do this, remove any inserted MBB's and clear
1217 // SwitchCases.
1218 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1219 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1220
Chris Lattner427301f2006-10-31 22:37:42 +00001221 SwitchCases.clear();
Chris Lattnered0110b2006-10-27 21:36:01 +00001222 }
1223 }
Chris Lattner61bcf912006-10-24 18:07:37 +00001224
1225 // Create a CaseBlock record representing this branch.
Zhou Sheng75b871f2007-01-11 12:24:14 +00001226 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001227 NULL, Succ0MBB, Succ1MBB, CurMBB);
Chris Lattner61bcf912006-10-24 18:07:37 +00001228 // Use visitSwitchCase to actually insert the fast branch sequence for this
1229 // cond branch.
1230 visitSwitchCase(CB);
Chris Lattner7a60d912005-01-07 07:47:53 +00001231}
1232
Nate Begemaned728c12006-03-27 01:32:24 +00001233/// visitSwitchCase - Emits the necessary code to represent a single node in
1234/// the binary search tree resulting from lowering a switch instruction.
1235void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
Chris Lattner963ddad2006-10-24 17:57:59 +00001236 SDOperand Cond;
1237 SDOperand CondLHS = getValue(CB.CmpLHS);
1238
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001239 // Build the setcc now.
1240 if (CB.CmpMHS == NULL) {
1241 // Fold "(X == true)" to X and "(X == false)" to !X to
1242 // handle common cases produced by branch lowering.
1243 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1244 Cond = CondLHS;
1245 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1246 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1247 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1248 } else
1249 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1250 } else {
1251 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
Anton Korobeynikov70378262007-03-25 15:07:15 +00001252
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001253 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1254 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1255
1256 SDOperand CmpOp = getValue(CB.CmpMHS);
1257 MVT::ValueType VT = CmpOp.getValueType();
1258
1259 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1260 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1261 } else {
1262 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1263 Cond = DAG.getSetCC(MVT::i1, SUB,
1264 DAG.getConstant(High-Low, VT), ISD::SETULE);
1265 }
1266
1267 }
1268
Nate Begemaned728c12006-03-27 01:32:24 +00001269 // Set NextBlock to be the MBB immediately after the current one, if any.
1270 // This is used to avoid emitting unnecessary branches to the next block.
1271 MachineBasicBlock *NextBlock = 0;
1272 MachineFunction::iterator BBI = CurMBB;
1273 if (++BBI != CurMBB->getParent()->end())
1274 NextBlock = BBI;
1275
1276 // If the lhs block is the next block, invert the condition so that we can
1277 // fall through to the lhs instead of the rhs block.
Chris Lattner963ddad2006-10-24 17:57:59 +00001278 if (CB.TrueBB == NextBlock) {
1279 std::swap(CB.TrueBB, CB.FalseBB);
Nate Begemaned728c12006-03-27 01:32:24 +00001280 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1281 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1282 }
1283 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
Chris Lattner963ddad2006-10-24 17:57:59 +00001284 DAG.getBasicBlock(CB.TrueBB));
1285 if (CB.FalseBB == NextBlock)
Nate Begemaned728c12006-03-27 01:32:24 +00001286 DAG.setRoot(BrCond);
1287 else
1288 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
Chris Lattner963ddad2006-10-24 17:57:59 +00001289 DAG.getBasicBlock(CB.FalseBB)));
Nate Begemaned728c12006-03-27 01:32:24 +00001290 // Update successor info
Chris Lattner963ddad2006-10-24 17:57:59 +00001291 CurMBB->addSuccessor(CB.TrueBB);
1292 CurMBB->addSuccessor(CB.FalseBB);
Nate Begemaned728c12006-03-27 01:32:24 +00001293}
1294
Anton Korobeynikov70378262007-03-25 15:07:15 +00001295/// visitJumpTable - Emit JumpTable node in the current MBB
Nate Begeman4ca2ea52006-04-22 18:53:45 +00001296void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
Nate Begeman4ca2ea52006-04-22 18:53:45 +00001297 // Emit the code for the jump table
Scott Michel4cfa6162007-04-24 01:24:20 +00001298 assert(JT.Reg != -1U && "Should lower JT Header first!");
Nate Begeman4ca2ea52006-04-22 18:53:45 +00001299 MVT::ValueType PTy = TLI.getPointerTy();
Evan Cheng84a28d42006-10-30 08:00:44 +00001300 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1301 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1302 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1303 Table, Index));
1304 return;
Nate Begeman4ca2ea52006-04-22 18:53:45 +00001305}
1306
Anton Korobeynikov70378262007-03-25 15:07:15 +00001307/// visitJumpTableHeader - This function emits necessary code to produce index
1308/// in the JumpTable from switch case.
1309void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1310 SelectionDAGISel::JumpTableHeader &JTH) {
1311 // Subtract the lowest switch case value from the value being switched on
1312 // and conditional branch to default mbb if the result is greater than the
1313 // difference between smallest and largest cases.
1314 SDOperand SwitchOp = getValue(JTH.SValue);
1315 MVT::ValueType VT = SwitchOp.getValueType();
1316 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1317 DAG.getConstant(JTH.First, VT));
1318
1319 // The SDNode we just created, which holds the value being switched on
1320 // minus the the smallest case value, needs to be copied to a virtual
1321 // register so it can be used as an index into the jump table in a
1322 // subsequent basic block. This value may be smaller or larger than the
1323 // target's pointer type, and therefore require extension or truncating.
Dan Gohmana8665142007-06-25 16:23:39 +00001324 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
Anton Korobeynikov70378262007-03-25 15:07:15 +00001325 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1326 else
1327 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1328
1329 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1330 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1331 JT.Reg = JumpTableReg;
1332
1333 // Emit the range check for the jump table, and branch to the default
1334 // block for the switch statement if the value being switched on exceeds
1335 // the largest case in the switch.
1336 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1337 DAG.getConstant(JTH.Last-JTH.First,VT),
1338 ISD::SETUGT);
1339
1340 // Set NextBlock to be the MBB immediately after the current one, if any.
1341 // This is used to avoid emitting unnecessary branches to the next block.
1342 MachineBasicBlock *NextBlock = 0;
1343 MachineFunction::iterator BBI = CurMBB;
1344 if (++BBI != CurMBB->getParent()->end())
1345 NextBlock = BBI;
1346
1347 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1348 DAG.getBasicBlock(JT.Default));
1349
1350 if (JT.MBB == NextBlock)
1351 DAG.setRoot(BrCond);
1352 else
1353 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001354 DAG.getBasicBlock(JT.MBB)));
1355
1356 return;
Anton Korobeynikov70378262007-03-25 15:07:15 +00001357}
1358
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001359/// visitBitTestHeader - This function emits necessary code to produce value
1360/// suitable for "bit tests"
1361void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1362 // Subtract the minimum value
1363 SDOperand SwitchOp = getValue(B.SValue);
1364 MVT::ValueType VT = SwitchOp.getValueType();
1365 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1366 DAG.getConstant(B.First, VT));
1367
1368 // Check range
1369 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1370 DAG.getConstant(B.Range, VT),
1371 ISD::SETUGT);
1372
1373 SDOperand ShiftOp;
Dan Gohmana8665142007-06-25 16:23:39 +00001374 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001375 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1376 else
1377 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1378
1379 // Make desired shift
1380 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1381 DAG.getConstant(1, TLI.getPointerTy()),
1382 ShiftOp);
1383
1384 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1385 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1386 B.Reg = SwitchReg;
1387
1388 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1389 DAG.getBasicBlock(B.Default));
1390
1391 // Set NextBlock to be the MBB immediately after the current one, if any.
1392 // This is used to avoid emitting unnecessary branches to the next block.
1393 MachineBasicBlock *NextBlock = 0;
1394 MachineFunction::iterator BBI = CurMBB;
1395 if (++BBI != CurMBB->getParent()->end())
1396 NextBlock = BBI;
1397
1398 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1399 if (MBB == NextBlock)
1400 DAG.setRoot(BrRange);
1401 else
1402 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1403 DAG.getBasicBlock(MBB)));
1404
1405 CurMBB->addSuccessor(B.Default);
1406 CurMBB->addSuccessor(MBB);
1407
1408 return;
1409}
1410
1411/// visitBitTestCase - this function produces one "bit test"
1412void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1413 unsigned Reg,
1414 SelectionDAGISel::BitTestCase &B) {
1415 // Emit bit tests and jumps
1416 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1417
1418 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1419 SwitchVal,
1420 DAG.getConstant(B.Mask,
1421 TLI.getPointerTy()));
1422 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1423 DAG.getConstant(0, TLI.getPointerTy()),
1424 ISD::SETNE);
1425 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1426 AndCmp, DAG.getBasicBlock(B.TargetBB));
1427
1428 // Set NextBlock to be the MBB immediately after the current one, if any.
1429 // This is used to avoid emitting unnecessary branches to the next block.
1430 MachineBasicBlock *NextBlock = 0;
1431 MachineFunction::iterator BBI = CurMBB;
1432 if (++BBI != CurMBB->getParent()->end())
1433 NextBlock = BBI;
1434
1435 if (NextMBB == NextBlock)
1436 DAG.setRoot(BrAnd);
1437 else
1438 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1439 DAG.getBasicBlock(NextMBB)));
1440
1441 CurMBB->addSuccessor(B.TargetBB);
1442 CurMBB->addSuccessor(NextMBB);
1443
1444 return;
1445}
Anton Korobeynikov70378262007-03-25 15:07:15 +00001446
Jim Laskey4b37a4c2007-02-21 22:53:45 +00001447void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1448 // Retrieve successors.
1449 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
Duncan Sands97f72362007-06-13 05:51:31 +00001450 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
Duncan Sands61166502007-06-06 10:05:18 +00001451
Duncan Sandsad0ea2d2007-11-27 13:23:08 +00001452 LowerCallTo(I, I.getCalledValue()->getType(), I.getParamAttrs(),
Duncan Sands97f72362007-06-13 05:51:31 +00001453 I.getCallingConv(),
1454 false,
1455 getValue(I.getOperand(0)),
1456 3, LandingPad);
Duncan Sands61166502007-06-06 10:05:18 +00001457
Duncan Sands97f72362007-06-13 05:51:31 +00001458 // If the value of the invoke is used outside of its defining block, make it
1459 // available as a virtual register.
1460 if (!I.use_empty()) {
1461 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1462 if (VMI != FuncInfo.ValueMap.end())
1463 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
Jim Laskey14059d92007-02-25 21:43:59 +00001464 }
Duncan Sands97f72362007-06-13 05:51:31 +00001465
1466 // Drop into normal successor.
1467 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1468 DAG.getBasicBlock(Return)));
1469
1470 // Update successor info
1471 CurMBB->addSuccessor(Return);
1472 CurMBB->addSuccessor(LandingPad);
Jim Laskey4b37a4c2007-02-21 22:53:45 +00001473}
1474
1475void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1476}
1477
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001478/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001479/// small case ranges).
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001480bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001481 CaseRecVector& WorkList,
1482 Value* SV,
1483 MachineBasicBlock* Default) {
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001484 Case& BackCase = *(CR.Range.second-1);
1485
1486 // Size is the number of Cases represented by this range.
1487 unsigned Size = CR.Range.second - CR.Range.first;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001488 if (Size > 3)
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001489 return false;
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001490
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001491 // Get the MachineFunction which holds the current MBB. This is used when
1492 // inserting any additional MBBs necessary to represent the switch.
1493 MachineFunction *CurMF = CurMBB->getParent();
1494
1495 // Figure out which block is immediately after the current one.
1496 MachineBasicBlock *NextBlock = 0;
1497 MachineFunction::iterator BBI = CR.CaseBB;
1498
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001499 if (++BBI != CurMBB->getParent()->end())
1500 NextBlock = BBI;
1501
1502 // TODO: If any two of the cases has the same destination, and if one value
1503 // is the same as the other, but has one bit unset that the other has set,
1504 // use bit manipulation to do two compares at once. For example:
1505 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1506
1507 // Rearrange the case blocks so that the last one falls through if possible.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001508 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001509 // The last case block won't fall through into 'NextBlock' if we emit the
1510 // branches in this order. See if rearranging a case value would help.
1511 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001512 if (I->BB == NextBlock) {
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001513 std::swap(*I, BackCase);
1514 break;
1515 }
1516 }
1517 }
1518
1519 // Create a CaseBlock record representing a conditional branch to
1520 // the Case's target mbb if the value being switched on SV is equal
1521 // to C.
1522 MachineBasicBlock *CurBlock = CR.CaseBB;
1523 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1524 MachineBasicBlock *FallThrough;
1525 if (I != E-1) {
1526 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1527 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1528 } else {
1529 // If the last case doesn't match, go to the default block.
1530 FallThrough = Default;
1531 }
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001532
1533 Value *RHS, *LHS, *MHS;
1534 ISD::CondCode CC;
1535 if (I->High == I->Low) {
1536 // This is just small small case range :) containing exactly 1 case
1537 CC = ISD::SETEQ;
1538 LHS = SV; RHS = I->High; MHS = NULL;
1539 } else {
1540 CC = ISD::SETLE;
1541 LHS = I->Low; MHS = SV; RHS = I->High;
1542 }
1543 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1544 I->BB, FallThrough, CurBlock);
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001545
1546 // If emitting the first comparison, just call visitSwitchCase to emit the
1547 // code into the current block. Otherwise, push the CaseBlock onto the
1548 // vector to be later processed by SDISel, and insert the node's MBB
1549 // before the next MBB.
1550 if (CurBlock == CurMBB)
1551 visitSwitchCase(CB);
1552 else
1553 SwitchCases.push_back(CB);
1554
1555 CurBlock = FallThrough;
1556 }
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001557
1558 return true;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001559}
1560
Anton Korobeynikov192d09c2007-05-09 20:07:08 +00001561static inline bool areJTsAllowed(const TargetLowering &TLI) {
1562 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1563 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1564}
1565
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001566/// handleJTSwitchCase - Emit jumptable for current switch case range
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001567bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001568 CaseRecVector& WorkList,
1569 Value* SV,
1570 MachineBasicBlock* Default) {
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001571 Case& FrontCase = *CR.Range.first;
1572 Case& BackCase = *(CR.Range.second-1);
1573
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001574 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1575 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1576
1577 uint64_t TSize = 0;
1578 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1579 I!=E; ++I)
1580 TSize += I->size();
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001581
Anton Korobeynikov192d09c2007-05-09 20:07:08 +00001582 if (!areJTsAllowed(TLI) || TSize <= 3)
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001583 return false;
1584
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001585 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1586 if (Density < 0.4)
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001587 return false;
1588
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001589 DOUT << "Lowering jump table\n"
1590 << "First entry: " << First << ". Last entry: " << Last << "\n"
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001591 << "Size: " << TSize << ". Density: " << Density << "\n\n";
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001592
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001593 // Get the MachineFunction which holds the current MBB. This is used when
1594 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001595 MachineFunction *CurMF = CurMBB->getParent();
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001596
1597 // Figure out which block is immediately after the current one.
1598 MachineBasicBlock *NextBlock = 0;
1599 MachineFunction::iterator BBI = CR.CaseBB;
1600
1601 if (++BBI != CurMBB->getParent()->end())
1602 NextBlock = BBI;
1603
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001604 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1605
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001606 // Create a new basic block to hold the code for loading the address
1607 // of the jump table, and jumping to it. Update successor information;
1608 // we will either branch to the default case for the switch, or the jump
1609 // table.
1610 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1611 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1612 CR.CaseBB->addSuccessor(Default);
1613 CR.CaseBB->addSuccessor(JumpTableBB);
1614
1615 // Build a vector of destination BBs, corresponding to each target
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001616 // of the jump table. If the value of the jump table slot corresponds to
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001617 // a case statement, push the case's BB onto the vector, otherwise, push
1618 // the default BB.
1619 std::vector<MachineBasicBlock*> DestBBs;
1620 int64_t TEI = First;
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001621 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1622 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1623 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1624
1625 if ((Low <= TEI) && (TEI <= High)) {
1626 DestBBs.push_back(I->BB);
1627 if (TEI==High)
1628 ++I;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001629 } else {
1630 DestBBs.push_back(Default);
1631 }
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001632 }
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001633
1634 // Update successor info. Add one edge to each unique successor.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001635 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001636 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1637 E = DestBBs.end(); I != E; ++I) {
1638 if (!SuccsHandled[(*I)->getNumber()]) {
1639 SuccsHandled[(*I)->getNumber()] = true;
1640 JumpTableBB->addSuccessor(*I);
1641 }
1642 }
1643
1644 // Create a jump table index for this jump table, or return an existing
1645 // one.
1646 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1647
1648 // Set the jump table information so that we can codegen it as a second
1649 // MachineBasicBlock
Scott Michel4cfa6162007-04-24 01:24:20 +00001650 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001651 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1652 (CR.CaseBB == CurMBB));
1653 if (CR.CaseBB == CurMBB)
1654 visitJumpTableHeader(JT, JTH);
1655
1656 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001657
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001658 return true;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001659}
1660
1661/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1662/// 2 subtrees.
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001663bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001664 CaseRecVector& WorkList,
1665 Value* SV,
1666 MachineBasicBlock* Default) {
1667 // Get the MachineFunction which holds the current MBB. This is used when
1668 // inserting any additional MBBs necessary to represent the switch.
1669 MachineFunction *CurMF = CurMBB->getParent();
1670
1671 // Figure out which block is immediately after the current one.
1672 MachineBasicBlock *NextBlock = 0;
1673 MachineFunction::iterator BBI = CR.CaseBB;
1674
1675 if (++BBI != CurMBB->getParent()->end())
1676 NextBlock = BBI;
1677
1678 Case& FrontCase = *CR.Range.first;
1679 Case& BackCase = *(CR.Range.second-1);
1680 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1681
1682 // Size is the number of Cases represented by this range.
1683 unsigned Size = CR.Range.second - CR.Range.first;
1684
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001685 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1686 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001687 double FMetric = 0;
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001688 CaseItr Pivot = CR.Range.first + Size/2;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001689
1690 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1691 // (heuristically) allow us to emit JumpTable's later.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001692 uint64_t TSize = 0;
1693 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1694 I!=E; ++I)
1695 TSize += I->size();
1696
1697 uint64_t LSize = FrontCase.size();
1698 uint64_t RSize = TSize-LSize;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001699 DOUT << "Selecting best pivot: \n"
1700 << "First: " << First << ", Last: " << Last <<"\n"
1701 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001702 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001703 J!=E; ++I, ++J) {
1704 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1705 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001706 assert((RBegin-LEnd>=1) && "Invalid case distance");
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001707 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1708 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
Anton Korobeynikovda964a22007-04-09 21:57:03 +00001709 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001710 // Should always split in some non-trivial place
1711 DOUT <<"=>Step\n"
1712 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1713 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1714 << "Metric: " << Metric << "\n";
1715 if (FMetric < Metric) {
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001716 Pivot = J;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001717 FMetric = Metric;
1718 DOUT << "Current metric set to: " << FMetric << "\n";
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001719 }
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001720
1721 LSize += J->size();
1722 RSize -= J->size();
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001723 }
Anton Korobeynikov192d09c2007-05-09 20:07:08 +00001724 if (areJTsAllowed(TLI)) {
1725 // If our case is dense we *really* should handle it earlier!
1726 assert((FMetric > 0) && "Should handle dense range earlier!");
1727 } else {
1728 Pivot = CR.Range.first + Size/2;
1729 }
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001730
1731 CaseRange LHSR(CR.Range.first, Pivot);
1732 CaseRange RHSR(Pivot, CR.Range.second);
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001733 Constant *C = Pivot->Low;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001734 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1735
1736 // We know that we branch to the LHS if the Value being switched on is
1737 // less than the Pivot value, C. We use this to optimize our binary
1738 // tree a bit, by recognizing that if SV is greater than or equal to the
1739 // LHS's Case Value, and that Case Value is exactly one less than the
1740 // Pivot's Value, then we can branch directly to the LHS's Target,
1741 // rather than creating a leaf node for it.
1742 if ((LHSR.second - LHSR.first) == 1 &&
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001743 LHSR.first->High == CR.GE &&
1744 cast<ConstantInt>(C)->getSExtValue() ==
1745 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1746 TrueBB = LHSR.first->BB;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001747 } else {
1748 TrueBB = new MachineBasicBlock(LLVMBB);
1749 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1750 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1751 }
1752
1753 // Similar to the optimization above, if the Value being switched on is
1754 // known to be less than the Constant CR.LT, and the current Case Value
1755 // is CR.LT - 1, then we can branch directly to the target block for
1756 // the current Case Value, rather than emitting a RHS leaf node for it.
1757 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001758 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1759 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1760 FalseBB = RHSR.first->BB;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001761 } else {
1762 FalseBB = new MachineBasicBlock(LLVMBB);
1763 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1764 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1765 }
1766
1767 // Create a CaseBlock record representing a conditional branch to
1768 // the LHS node if the value being switched on SV is less than C.
1769 // Otherwise, branch to LHS.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001770 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1771 TrueBB, FalseBB, CR.CaseBB);
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001772
1773 if (CR.CaseBB == CurMBB)
1774 visitSwitchCase(CB);
1775 else
1776 SwitchCases.push_back(CB);
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001777
1778 return true;
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001779}
1780
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001781/// handleBitTestsSwitchCase - if current case range has few destination and
1782/// range span less, than machine word bitwidth, encode case range into series
1783/// of masks and emit bit tests with these masks.
1784bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1785 CaseRecVector& WorkList,
1786 Value* SV,
Chris Lattner7196f092007-04-14 02:26:56 +00001787 MachineBasicBlock* Default){
Dan Gohman1796f1f2007-05-18 17:52:13 +00001788 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001789
1790 Case& FrontCase = *CR.Range.first;
1791 Case& BackCase = *(CR.Range.second-1);
1792
1793 // Get the MachineFunction which holds the current MBB. This is used when
1794 // inserting any additional MBBs necessary to represent the switch.
1795 MachineFunction *CurMF = CurMBB->getParent();
1796
1797 unsigned numCmps = 0;
1798 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1799 I!=E; ++I) {
1800 // Single case counts one, case range - two.
1801 if (I->Low == I->High)
1802 numCmps +=1;
1803 else
1804 numCmps +=2;
1805 }
1806
1807 // Count unique destinations
1808 SmallSet<MachineBasicBlock*, 4> Dests;
1809 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1810 Dests.insert(I->BB);
1811 if (Dests.size() > 3)
1812 // Don't bother the code below, if there are too much unique destinations
1813 return false;
1814 }
1815 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1816 << "Total number of comparisons: " << numCmps << "\n";
1817
1818 // Compute span of values.
1819 Constant* minValue = FrontCase.Low;
1820 Constant* maxValue = BackCase.High;
1821 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1822 cast<ConstantInt>(minValue)->getSExtValue();
1823 DOUT << "Compare range: " << range << "\n"
1824 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1825 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1826
Anton Korobeynikovd7ae7f12007-04-26 20:44:04 +00001827 if (range>=IntPtrBits ||
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001828 (!(Dests.size() == 1 && numCmps >= 3) &&
1829 !(Dests.size() == 2 && numCmps >= 5) &&
1830 !(Dests.size() >= 3 && numCmps >= 6)))
1831 return false;
1832
1833 DOUT << "Emitting bit tests\n";
1834 int64_t lowBound = 0;
1835
1836 // Optimize the case where all the case values fit in a
1837 // word without having to subtract minValue. In this case,
1838 // we can optimize away the subtraction.
1839 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
Anton Korobeynikov8a1a84f2007-04-14 13:25:55 +00001840 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001841 range = cast<ConstantInt>(maxValue)->getSExtValue();
1842 } else {
1843 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1844 }
1845
1846 CaseBitsVector CasesBits;
1847 unsigned i, count = 0;
1848
1849 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1850 MachineBasicBlock* Dest = I->BB;
1851 for (i = 0; i < count; ++i)
1852 if (Dest == CasesBits[i].BB)
1853 break;
1854
1855 if (i == count) {
1856 assert((count < 3) && "Too much destinations to test!");
1857 CasesBits.push_back(CaseBits(0, Dest, 0));
1858 count++;
1859 }
1860
1861 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1862 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1863
1864 for (uint64_t j = lo; j <= hi; j++) {
Anton Korobeynikov8a1a84f2007-04-14 13:25:55 +00001865 CasesBits[i].Mask |= 1ULL << j;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001866 CasesBits[i].Bits++;
1867 }
1868
1869 }
1870 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1871
1872 SelectionDAGISel::BitTestInfo BTC;
1873
1874 // Figure out which block is immediately after the current one.
1875 MachineFunction::iterator BBI = CR.CaseBB;
1876 ++BBI;
1877
1878 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1879
1880 DOUT << "Cases:\n";
1881 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1882 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1883 << ", BB: " << CasesBits[i].BB << "\n";
1884
1885 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1886 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1887 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1888 CaseBB,
1889 CasesBits[i].BB));
1890 }
1891
1892 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
Jeff Cohen0475f3b2007-04-09 14:32:59 +00001893 -1U, (CR.CaseBB == CurMBB),
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001894 CR.CaseBB, Default, BTC);
1895
1896 if (CR.CaseBB == CurMBB)
1897 visitBitTestHeader(BTB);
1898
1899 BitTestCases.push_back(BTB);
1900
1901 return true;
1902}
1903
1904
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001905// Clusterify - Transform simple list of Cases into list of CaseRange's
1906unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1907 const SwitchInst& SI) {
1908 unsigned numCmps = 0;
1909
1910 // Start with "simple" cases
1911 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1912 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1913 Cases.push_back(Case(SI.getSuccessorValue(i),
1914 SI.getSuccessorValue(i),
1915 SMBB));
1916 }
Chris Lattner698b1cb2007-11-27 06:14:32 +00001917 std::sort(Cases.begin(), Cases.end(), CaseCmp());
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001918
1919 // Merge case into clusters
1920 if (Cases.size()>=2)
David Greene4c1e6f32007-06-29 03:42:23 +00001921 // Must recompute end() each iteration because it may be
1922 // invalidated by erase if we hold on to it
Chris Lattnerf81d5882007-11-24 07:07:01 +00001923 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001924 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1925 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1926 MachineBasicBlock* nextBB = J->BB;
1927 MachineBasicBlock* currentBB = I->BB;
1928
1929 // If the two neighboring cases go to the same destination, merge them
1930 // into a single case.
1931 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1932 I->High = J->High;
1933 J = Cases.erase(J);
1934 } else {
1935 I = J++;
1936 }
1937 }
1938
1939 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1940 if (I->Low != I->High)
1941 // A range counts double, since it requires two compares.
1942 ++numCmps;
1943 }
1944
1945 return numCmps;
1946}
1947
1948void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
Nate Begemaned728c12006-03-27 01:32:24 +00001949 // Figure out which block is immediately after the current one.
1950 MachineBasicBlock *NextBlock = 0;
1951 MachineFunction::iterator BBI = CurMBB;
Bill Wendlingbe96e1c2006-10-19 21:46:38 +00001952
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001953 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
Chris Lattner6d6fc262006-10-22 21:36:53 +00001954
Nate Begemaned728c12006-03-27 01:32:24 +00001955 // If there is only the default destination, branch to it if it is not the
1956 // next basic block. Otherwise, just fall through.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001957 if (SI.getNumOperands() == 2) {
Nate Begemaned728c12006-03-27 01:32:24 +00001958 // Update machine-CFG edges.
Bill Wendlingbe96e1c2006-10-19 21:46:38 +00001959
Nate Begemaned728c12006-03-27 01:32:24 +00001960 // If this is not a fall-through branch, emit the branch.
Chris Lattner6d6fc262006-10-22 21:36:53 +00001961 if (Default != NextBlock)
Nate Begemaned728c12006-03-27 01:32:24 +00001962 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
Chris Lattner6d6fc262006-10-22 21:36:53 +00001963 DAG.getBasicBlock(Default)));
Bill Wendlingbe96e1c2006-10-19 21:46:38 +00001964
Chris Lattner6d6fc262006-10-22 21:36:53 +00001965 CurMBB->addSuccessor(Default);
Nate Begemaned728c12006-03-27 01:32:24 +00001966 return;
1967 }
1968
1969 // If there are any non-default case statements, create a vector of Cases
1970 // representing each one, and sort the vector so that we can efficiently
1971 // create a binary search tree from them.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001972 CaseVector Cases;
1973 unsigned numCmps = Clusterify(Cases, SI);
1974 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1975 << ". Total compares: " << numCmps << "\n";
Bill Wendlingbe96e1c2006-10-19 21:46:38 +00001976
Nate Begemaned728c12006-03-27 01:32:24 +00001977 // Get the Value to be switched on and default basic blocks, which will be
1978 // inserted into CaseBlock records, representing basic blocks in the binary
1979 // search tree.
Anton Korobeynikov915e6172007-04-04 21:14:49 +00001980 Value *SV = SI.getOperand(0);
Nate Begeman4ca2ea52006-04-22 18:53:45 +00001981
Nate Begemaned728c12006-03-27 01:32:24 +00001982 // Push the initial CaseRec onto the worklist
Anton Korobeynikov3a9d6812007-03-27 11:29:11 +00001983 CaseRecVector WorkList;
Anton Korobeynikov70378262007-03-25 15:07:15 +00001984 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1985
1986 while (!WorkList.empty()) {
Nate Begemaned728c12006-03-27 01:32:24 +00001987 // Grab a record representing a case range to process off the worklist
Anton Korobeynikov70378262007-03-25 15:07:15 +00001988 CaseRec CR = WorkList.back();
1989 WorkList.pop_back();
Anton Korobeynikov70378262007-03-25 15:07:15 +00001990
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001991 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1992 continue;
1993
Anton Korobeynikov70378262007-03-25 15:07:15 +00001994 // If the range has few cases (two or less) emit a series of specific
1995 // tests.
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00001996 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1997 continue;
1998
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00001999 // If the switch has more than 5 blocks, and at least 40% dense, and the
Anton Korobeynikov70378262007-03-25 15:07:15 +00002000 // target supports indirect branches, then emit a jump table rather than
2001 // lowering the switch to a binary tree of conditional branches.
Anton Korobeynikov37a0bfe2007-03-27 12:05:48 +00002002 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2003 continue;
2004
2005 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2006 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2007 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
Nate Begemaned728c12006-03-27 01:32:24 +00002008 }
2009}
2010
Anton Korobeynikov70378262007-03-25 15:07:15 +00002011
Chris Lattnerf68fd0b2005-04-02 05:04:50 +00002012void SelectionDAGLowering::visitSub(User &I) {
2013 // -0.0 - X --> fneg
Reid Spencer2eadb532007-01-21 00:29:26 +00002014 const Type *Ty = I.getType();
Reid Spencerd84d35b2007-02-15 02:26:10 +00002015 if (isa<VectorType>(Ty)) {
Dan Gohmana8665142007-06-25 16:23:39 +00002016 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2017 const VectorType *DestTy = cast<VectorType>(I.getType());
2018 const Type *ElTy = DestTy->getElementType();
Evan Chengfa68d062007-06-29 21:44:35 +00002019 if (ElTy->isFloatingPoint()) {
2020 unsigned VL = DestTy->getNumElements();
Dale Johannesen98d3a082007-09-14 22:26:36 +00002021 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
Evan Chengfa68d062007-06-29 21:44:35 +00002022 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2023 if (CV == CNZ) {
2024 SDOperand Op2 = getValue(I.getOperand(1));
2025 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2026 return;
2027 }
Dan Gohmana8665142007-06-25 16:23:39 +00002028 }
2029 }
2030 }
2031 if (Ty->isFloatingPoint()) {
Chris Lattner6f3b5772005-09-28 22:28:18 +00002032 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
Dale Johannesen98d3a082007-09-14 22:26:36 +00002033 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
Chris Lattner6f3b5772005-09-28 22:28:18 +00002034 SDOperand Op2 = getValue(I.getOperand(1));
2035 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2036 return;
2037 }
Dan Gohmana8665142007-06-25 16:23:39 +00002038 }
2039
2040 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
Chris Lattnerf68fd0b2005-04-02 05:04:50 +00002041}
2042
Dan Gohmana8665142007-06-25 16:23:39 +00002043void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
Chris Lattner7a60d912005-01-07 07:47:53 +00002044 SDOperand Op1 = getValue(I.getOperand(0));
2045 SDOperand Op2 = getValue(I.getOperand(1));
Reid Spencer2eadb532007-01-21 00:29:26 +00002046
2047 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
Reid Spencer7e80b0b2006-10-26 06:15:43 +00002048}
2049
Nate Begeman127321b2005-11-18 07:42:56 +00002050void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2051 SDOperand Op1 = getValue(I.getOperand(0));
2052 SDOperand Op2 = getValue(I.getOperand(1));
2053
Dan Gohmana8665142007-06-25 16:23:39 +00002054 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2055 MVT::getSizeInBits(Op2.getValueType()))
Reid Spencer2341c222007-02-02 02:16:23 +00002056 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2057 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2058 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
Nate Begeman127321b2005-11-18 07:42:56 +00002059
Chris Lattner7a60d912005-01-07 07:47:53 +00002060 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2061}
2062
Reid Spencerd9436b62006-11-20 01:22:35 +00002063void SelectionDAGLowering::visitICmp(User &I) {
Reid Spencer266e42b2006-12-23 06:05:41 +00002064 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2065 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2066 predicate = IC->getPredicate();
2067 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2068 predicate = ICmpInst::Predicate(IC->getPredicate());
2069 SDOperand Op1 = getValue(I.getOperand(0));
2070 SDOperand Op2 = getValue(I.getOperand(1));
Reid Spencerd9436b62006-11-20 01:22:35 +00002071 ISD::CondCode Opcode;
Reid Spencer266e42b2006-12-23 06:05:41 +00002072 switch (predicate) {
Reid Spencerd9436b62006-11-20 01:22:35 +00002073 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2074 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2075 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2076 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2077 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2078 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2079 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2080 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2081 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2082 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2083 default:
2084 assert(!"Invalid ICmp predicate value");
2085 Opcode = ISD::SETEQ;
2086 break;
2087 }
2088 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2089}
2090
2091void SelectionDAGLowering::visitFCmp(User &I) {
Reid Spencer266e42b2006-12-23 06:05:41 +00002092 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2093 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2094 predicate = FC->getPredicate();
2095 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2096 predicate = FCmpInst::Predicate(FC->getPredicate());
Chris Lattner7a60d912005-01-07 07:47:53 +00002097 SDOperand Op1 = getValue(I.getOperand(0));
2098 SDOperand Op2 = getValue(I.getOperand(1));
Reid Spencer266e42b2006-12-23 06:05:41 +00002099 ISD::CondCode Condition, FOC, FPC;
2100 switch (predicate) {
2101 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2102 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2103 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2104 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2105 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2106 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2107 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2108 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2109 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2110 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2111 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2112 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2113 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2114 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2115 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2116 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2117 default:
2118 assert(!"Invalid FCmp predicate value");
2119 FOC = FPC = ISD::SETFALSE;
2120 break;
2121 }
2122 if (FiniteOnlyFPMath())
2123 Condition = FOC;
2124 else
2125 Condition = FPC;
2126 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
Chris Lattner7a60d912005-01-07 07:47:53 +00002127}
2128
2129void SelectionDAGLowering::visitSelect(User &I) {
2130 SDOperand Cond = getValue(I.getOperand(0));
2131 SDOperand TrueVal = getValue(I.getOperand(1));
2132 SDOperand FalseVal = getValue(I.getOperand(2));
Dan Gohmana8665142007-06-25 16:23:39 +00002133 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2134 TrueVal, FalseVal));
Chris Lattner7a60d912005-01-07 07:47:53 +00002135}
2136
Reid Spencer6c38f0b2006-11-27 01:05:10 +00002137
2138void SelectionDAGLowering::visitTrunc(User &I) {
2139 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2140 SDOperand N = getValue(I.getOperand(0));
2141 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2142 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2143}
2144
2145void SelectionDAGLowering::visitZExt(User &I) {
2146 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2147 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2148 SDOperand N = getValue(I.getOperand(0));
2149 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2150 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2151}
2152
2153void SelectionDAGLowering::visitSExt(User &I) {
2154 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2155 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2156 SDOperand N = getValue(I.getOperand(0));
2157 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2158 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2159}
2160
2161void SelectionDAGLowering::visitFPTrunc(User &I) {
2162 // FPTrunc is never a no-op cast, no need to check
2163 SDOperand N = getValue(I.getOperand(0));
2164 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2165 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2166}
2167
2168void SelectionDAGLowering::visitFPExt(User &I){
2169 // FPTrunc is never a no-op cast, no need to check
2170 SDOperand N = getValue(I.getOperand(0));
2171 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2172 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2173}
2174
2175void SelectionDAGLowering::visitFPToUI(User &I) {
2176 // FPToUI is never a no-op cast, no need to check
2177 SDOperand N = getValue(I.getOperand(0));
2178 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2179 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2180}
2181
2182void SelectionDAGLowering::visitFPToSI(User &I) {
2183 // FPToSI is never a no-op cast, no need to check
2184 SDOperand N = getValue(I.getOperand(0));
2185 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2186 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2187}
2188
2189void SelectionDAGLowering::visitUIToFP(User &I) {
2190 // UIToFP is never a no-op cast, no need to check
2191 SDOperand N = getValue(I.getOperand(0));
2192 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2193 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2194}
2195
2196void SelectionDAGLowering::visitSIToFP(User &I){
2197 // UIToFP is never a no-op cast, no need to check
2198 SDOperand N = getValue(I.getOperand(0));
2199 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2200 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2201}
2202
2203void SelectionDAGLowering::visitPtrToInt(User &I) {
2204 // What to do depends on the size of the integer and the size of the pointer.
2205 // We can either truncate, zero extend, or no-op, accordingly.
Chris Lattner7a60d912005-01-07 07:47:53 +00002206 SDOperand N = getValue(I.getOperand(0));
Chris Lattner2f4119a2006-03-22 20:09:35 +00002207 MVT::ValueType SrcVT = N.getValueType();
Chris Lattner4024c002006-03-15 22:19:46 +00002208 MVT::ValueType DestVT = TLI.getValueType(I.getType());
Reid Spencer6c38f0b2006-11-27 01:05:10 +00002209 SDOperand Result;
2210 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2211 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2212 else
2213 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2214 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2215 setValue(&I, Result);
2216}
Chris Lattner7a60d912005-01-07 07:47:53 +00002217
Reid Spencer6c38f0b2006-11-27 01:05:10 +00002218void SelectionDAGLowering::visitIntToPtr(User &I) {
2219 // What to do depends on the size of the integer and the size of the pointer.
2220 // We can either truncate, zero extend, or no-op, accordingly.
2221 SDOperand N = getValue(I.getOperand(0));
2222 MVT::ValueType SrcVT = N.getValueType();
2223 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2224 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2225 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2226 else
2227 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2228 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2229}
2230
2231void SelectionDAGLowering::visitBitCast(User &I) {
2232 SDOperand N = getValue(I.getOperand(0));
2233 MVT::ValueType DestVT = TLI.getValueType(I.getType());
Reid Spencer6c38f0b2006-11-27 01:05:10 +00002234
2235 // BitCast assures us that source and destination are the same size so this
2236 // is either a BIT_CONVERT or a no-op.
2237 if (DestVT != N.getValueType())
2238 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2239 else
2240 setValue(&I, N); // noop cast.
Chris Lattner7a60d912005-01-07 07:47:53 +00002241}
2242
Chris Lattner67271862006-03-29 00:11:43 +00002243void SelectionDAGLowering::visitInsertElement(User &I) {
Chris Lattner32206f52006-03-18 01:44:44 +00002244 SDOperand InVec = getValue(I.getOperand(0));
2245 SDOperand InVal = getValue(I.getOperand(1));
2246 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2247 getValue(I.getOperand(2)));
2248
Dan Gohmana8665142007-06-25 16:23:39 +00002249 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2250 TLI.getValueType(I.getType()),
2251 InVec, InVal, InIdx));
Chris Lattner32206f52006-03-18 01:44:44 +00002252}
2253
Chris Lattner67271862006-03-29 00:11:43 +00002254void SelectionDAGLowering::visitExtractElement(User &I) {
Chris Lattner7c0cd8c2006-03-21 20:44:12 +00002255 SDOperand InVec = getValue(I.getOperand(0));
2256 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2257 getValue(I.getOperand(1)));
Dan Gohmana8665142007-06-25 16:23:39 +00002258 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
Chris Lattner7c0cd8c2006-03-21 20:44:12 +00002259 TLI.getValueType(I.getType()), InVec, InIdx));
2260}
Chris Lattner32206f52006-03-18 01:44:44 +00002261
Chris Lattner098c01e2006-04-08 04:15:24 +00002262void SelectionDAGLowering::visitShuffleVector(User &I) {
2263 SDOperand V1 = getValue(I.getOperand(0));
2264 SDOperand V2 = getValue(I.getOperand(1));
2265 SDOperand Mask = getValue(I.getOperand(2));
2266
Dan Gohmana8665142007-06-25 16:23:39 +00002267 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2268 TLI.getValueType(I.getType()),
2269 V1, V2, Mask));
Chris Lattner098c01e2006-04-08 04:15:24 +00002270}
2271
2272
Chris Lattner7a60d912005-01-07 07:47:53 +00002273void SelectionDAGLowering::visitGetElementPtr(User &I) {
2274 SDOperand N = getValue(I.getOperand(0));
2275 const Type *Ty = I.getOperand(0)->getType();
Chris Lattner7a60d912005-01-07 07:47:53 +00002276
2277 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2278 OI != E; ++OI) {
2279 Value *Idx = *OI;
Chris Lattner35397782005-12-05 07:10:48 +00002280 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
Reid Spencere0fc4df2006-10-20 07:07:24 +00002281 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
Chris Lattner7a60d912005-01-07 07:47:53 +00002282 if (Field) {
2283 // N = N + Offset
Chris Lattnerc473d8e2007-02-10 19:55:17 +00002284 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
Chris Lattner7a60d912005-01-07 07:47:53 +00002285 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
Misha Brukman77451162005-04-22 04:01:18 +00002286 getIntPtrConstant(Offset));
Chris Lattner7a60d912005-01-07 07:47:53 +00002287 }
2288 Ty = StTy->getElementType(Field);
2289 } else {
2290 Ty = cast<SequentialType>(Ty)->getElementType();
Chris Lattner19a83992005-01-07 21:56:57 +00002291
Chris Lattner43535a12005-11-09 04:45:33 +00002292 // If this is a constant subscript, handle it quickly.
2293 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
Reid Spencere0fc4df2006-10-20 07:07:24 +00002294 if (CI->getZExtValue() == 0) continue;
Reid Spencere63b6512006-12-31 05:55:36 +00002295 uint64_t Offs =
Dale Johannesenb6c05b12007-10-01 23:08:35 +00002296 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
Chris Lattner43535a12005-11-09 04:45:33 +00002297 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2298 continue;
Chris Lattner7a60d912005-01-07 07:47:53 +00002299 }
Chris Lattner43535a12005-11-09 04:45:33 +00002300
2301 // N = N + Idx * ElementSize;
Dale Johannesenb6c05b12007-10-01 23:08:35 +00002302 uint64_t ElementSize = TD->getABITypeSize(Ty);
Chris Lattner43535a12005-11-09 04:45:33 +00002303 SDOperand IdxN = getValue(Idx);
2304
2305 // If the index is smaller or larger than intptr_t, truncate or extend
2306 // it.
2307 if (IdxN.getValueType() < N.getValueType()) {
Reid Spencere63b6512006-12-31 05:55:36 +00002308 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
Chris Lattner43535a12005-11-09 04:45:33 +00002309 } else if (IdxN.getValueType() > N.getValueType())
2310 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2311
2312 // If this is a multiply by a power of two, turn it into a shl
2313 // immediately. This is a very common case.
2314 if (isPowerOf2_64(ElementSize)) {
2315 unsigned Amt = Log2_64(ElementSize);
2316 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
Chris Lattner41fd6d52005-11-09 16:50:40 +00002317 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
Chris Lattner43535a12005-11-09 04:45:33 +00002318 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2319 continue;
2320 }
2321
2322 SDOperand Scale = getIntPtrConstant(ElementSize);
2323 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2324 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
Chris Lattner7a60d912005-01-07 07:47:53 +00002325 }
2326 }
2327 setValue(&I, N);
2328}
2329
2330void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2331 // If this is a fixed sized alloca in the entry block of the function,
2332 // allocate it statically on the stack.
2333 if (FuncInfo.StaticAllocaMap.count(&I))
2334 return; // getValue will auto-populate this.
2335
2336 const Type *Ty = I.getAllocatedType();
Duncan Sands44b87212007-11-01 20:53:16 +00002337 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Chris Lattner50ee0e42007-01-20 22:35:55 +00002338 unsigned Align =
Chris Lattner945e4372007-02-14 05:52:17 +00002339 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
Chris Lattner50ee0e42007-01-20 22:35:55 +00002340 I.getAlignment());
Chris Lattner7a60d912005-01-07 07:47:53 +00002341
2342 SDOperand AllocSize = getValue(I.getArraySize());
Chris Lattnereccb73d2005-01-22 23:04:37 +00002343 MVT::ValueType IntPtr = TLI.getPointerTy();
2344 if (IntPtr < AllocSize.getValueType())
2345 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2346 else if (IntPtr > AllocSize.getValueType())
2347 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
Chris Lattner7a60d912005-01-07 07:47:53 +00002348
Chris Lattnereccb73d2005-01-22 23:04:37 +00002349 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
Chris Lattner7a60d912005-01-07 07:47:53 +00002350 getIntPtrConstant(TySize));
2351
Evan Cheng95667c52007-08-16 23:46:29 +00002352 // Handle alignment. If the requested alignment is less than or equal to
2353 // the stack alignment, ignore it. If the size is greater than or equal to
2354 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
Chris Lattner7a60d912005-01-07 07:47:53 +00002355 unsigned StackAlign =
2356 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
Evan Cheng95667c52007-08-16 23:46:29 +00002357 if (Align <= StackAlign)
Chris Lattner7a60d912005-01-07 07:47:53 +00002358 Align = 0;
Evan Cheng95667c52007-08-16 23:46:29 +00002359
2360 // Round the size of the allocation up to the stack alignment size
2361 // by add SA-1 to the size.
2362 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2363 getIntPtrConstant(StackAlign-1));
2364 // Mask out the low bits for alignment purposes.
2365 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2366 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
Chris Lattner7a60d912005-01-07 07:47:53 +00002367
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002368 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
Chris Lattnerbd887772006-08-14 23:53:35 +00002369 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2370 MVT::Other);
2371 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
Chris Lattner79084302007-02-04 01:31:47 +00002372 setValue(&I, DSA);
2373 DAG.setRoot(DSA.getValue(1));
Chris Lattner7a60d912005-01-07 07:47:53 +00002374
2375 // Inform the Frame Information that we have just allocated a variable-sized
2376 // object.
2377 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2378}
2379
Chris Lattner7a60d912005-01-07 07:47:53 +00002380void SelectionDAGLowering::visitLoad(LoadInst &I) {
2381 SDOperand Ptr = getValue(I.getOperand(0));
Misha Brukman835702a2005-04-21 22:36:52 +00002382
Chris Lattner4d9651c2005-01-17 22:19:26 +00002383 SDOperand Root;
2384 if (I.isVolatile())
2385 Root = getRoot();
2386 else {
2387 // Do not serialize non-volatile loads against each other.
2388 Root = DAG.getRoot();
2389 }
Chris Lattner4024c002006-03-15 22:19:46 +00002390
Evan Chenge71fe34d2006-10-09 20:57:25 +00002391 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
Christopher Lamb8af6d582007-04-22 23:15:30 +00002392 Root, I.isVolatile(), I.getAlignment()));
Chris Lattner4024c002006-03-15 22:19:46 +00002393}
2394
2395SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
Evan Chenge71fe34d2006-10-09 20:57:25 +00002396 const Value *SV, SDOperand Root,
Christopher Lamb8af6d582007-04-22 23:15:30 +00002397 bool isVolatile,
2398 unsigned Alignment) {
Dan Gohmana8665142007-06-25 16:23:39 +00002399 SDOperand L =
2400 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2401 isVolatile, Alignment);
Chris Lattner4d9651c2005-01-17 22:19:26 +00002402
Chris Lattner4024c002006-03-15 22:19:46 +00002403 if (isVolatile)
Chris Lattner4d9651c2005-01-17 22:19:26 +00002404 DAG.setRoot(L.getValue(1));
2405 else
2406 PendingLoads.push_back(L.getValue(1));
Chris Lattner4024c002006-03-15 22:19:46 +00002407
2408 return L;
Chris Lattner7a60d912005-01-07 07:47:53 +00002409}
2410
2411
2412void SelectionDAGLowering::visitStore(StoreInst &I) {
2413 Value *SrcV = I.getOperand(0);
2414 SDOperand Src = getValue(SrcV);
2415 SDOperand Ptr = getValue(I.getOperand(1));
Evan Cheng258657e2006-12-20 01:27:29 +00002416 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
Christopher Lamb8af6d582007-04-22 23:15:30 +00002417 I.isVolatile(), I.getAlignment()));
Chris Lattner7a60d912005-01-07 07:47:53 +00002418}
2419
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002420/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
2421/// access memory and has no other side effects at all.
2422static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
2423#define GET_NO_MEMORY_INTRINSICS
2424#include "llvm/Intrinsics.gen"
2425#undef GET_NO_MEMORY_INTRINSICS
2426 return false;
2427}
2428
Chris Lattnera9c59156b2006-04-02 03:41:14 +00002429// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
2430// have any side-effects or if it only reads memory.
2431static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
2432#define GET_SIDE_EFFECT_INFO
2433#include "llvm/Intrinsics.gen"
2434#undef GET_SIDE_EFFECT_INFO
2435 return false;
2436}
2437
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002438/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2439/// node.
2440void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2441 unsigned Intrinsic) {
Chris Lattner313229c2006-03-24 22:49:42 +00002442 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
Chris Lattnera9c59156b2006-04-02 03:41:14 +00002443 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002444
2445 // Build the operand list.
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002446 SmallVector<SDOperand, 8> Ops;
Chris Lattnera9c59156b2006-04-02 03:41:14 +00002447 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2448 if (OnlyLoad) {
2449 // We don't need to serialize loads against other loads.
2450 Ops.push_back(DAG.getRoot());
2451 } else {
2452 Ops.push_back(getRoot());
2453 }
2454 }
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002455
2456 // Add the intrinsic ID as an integer operand.
2457 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2458
2459 // Add all operands of the call to the operand list.
2460 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2461 SDOperand Op = getValue(I.getOperand(i));
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002462 assert(TLI.isTypeLegal(Op.getValueType()) &&
2463 "Intrinsic uses a non-legal type?");
2464 Ops.push_back(Op);
2465 }
2466
2467 std::vector<MVT::ValueType> VTs;
2468 if (I.getType() != Type::VoidTy) {
2469 MVT::ValueType VT = TLI.getValueType(I.getType());
Dan Gohmana8665142007-06-25 16:23:39 +00002470 if (MVT::isVector(VT)) {
Reid Spencerd84d35b2007-02-15 02:26:10 +00002471 const VectorType *DestTy = cast<VectorType>(I.getType());
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002472 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2473
2474 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2475 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2476 }
2477
2478 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2479 VTs.push_back(VT);
2480 }
2481 if (HasChain)
2482 VTs.push_back(MVT::Other);
2483
Chris Lattnerbd887772006-08-14 23:53:35 +00002484 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2485
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002486 // Create the node.
Chris Lattnere55d1712006-03-28 00:40:33 +00002487 SDOperand Result;
2488 if (!HasChain)
Chris Lattnerbd887772006-08-14 23:53:35 +00002489 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2490 &Ops[0], Ops.size());
Chris Lattnere55d1712006-03-28 00:40:33 +00002491 else if (I.getType() != Type::VoidTy)
Chris Lattnerbd887772006-08-14 23:53:35 +00002492 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2493 &Ops[0], Ops.size());
Chris Lattnere55d1712006-03-28 00:40:33 +00002494 else
Chris Lattnerbd887772006-08-14 23:53:35 +00002495 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2496 &Ops[0], Ops.size());
Chris Lattnere55d1712006-03-28 00:40:33 +00002497
Chris Lattnera9c59156b2006-04-02 03:41:14 +00002498 if (HasChain) {
2499 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2500 if (OnlyLoad)
2501 PendingLoads.push_back(Chain);
2502 else
2503 DAG.setRoot(Chain);
2504 }
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002505 if (I.getType() != Type::VoidTy) {
Reid Spencerd84d35b2007-02-15 02:26:10 +00002506 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
Dan Gohmana8665142007-06-25 16:23:39 +00002507 MVT::ValueType VT = TLI.getValueType(PTy);
2508 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002509 }
2510 setValue(&I, Result);
2511 }
2512}
2513
Duncan Sands81df18a2007-07-06 09:10:03 +00002514/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Duncan Sandsfe806382007-07-04 20:52:51 +00002515static GlobalVariable *ExtractTypeInfo (Value *V) {
Duncan Sands81df18a2007-07-06 09:10:03 +00002516 V = IntrinsicInst::StripPointerCasts(V);
2517 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
Duncan Sandsfe806382007-07-04 20:52:51 +00002518 assert (GV || isa<ConstantPointerNull>(V) &&
2519 "TypeInfo must be a global variable or NULL");
2520 return GV;
2521}
2522
Duncan Sands92bf2c62007-06-15 19:04:19 +00002523/// addCatchInfo - Extract the personality and type infos from an eh.selector
Duncan Sandsfe806382007-07-04 20:52:51 +00002524/// call, and add them to the specified machine basic block.
Duncan Sands92bf2c62007-06-15 19:04:19 +00002525static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2526 MachineBasicBlock *MBB) {
2527 // Inform the MachineModuleInfo of the personality for this landing pad.
2528 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2529 assert(CE->getOpcode() == Instruction::BitCast &&
2530 isa<Function>(CE->getOperand(0)) &&
2531 "Personality should be a function");
2532 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2533
2534 // Gather all the type infos for this landing pad and pass them along to
2535 // MachineModuleInfo.
2536 std::vector<GlobalVariable *> TyInfo;
Duncan Sandsfe806382007-07-04 20:52:51 +00002537 unsigned N = I.getNumOperands();
2538
2539 for (unsigned i = N - 1; i > 2; --i) {
2540 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2541 unsigned FilterLength = CI->getZExtValue();
Duncan Sandsef5a6542007-08-27 15:47:50 +00002542 unsigned FirstCatch = i + FilterLength + !FilterLength;
Duncan Sandsfe806382007-07-04 20:52:51 +00002543 assert (FirstCatch <= N && "Invalid filter length");
2544
2545 if (FirstCatch < N) {
2546 TyInfo.reserve(N - FirstCatch);
2547 for (unsigned j = FirstCatch; j < N; ++j)
2548 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2549 MMI->addCatchTypeInfo(MBB, TyInfo);
2550 TyInfo.clear();
2551 }
2552
Duncan Sandsef5a6542007-08-27 15:47:50 +00002553 if (!FilterLength) {
2554 // Cleanup.
2555 MMI->addCleanup(MBB);
2556 } else {
2557 // Filter.
2558 TyInfo.reserve(FilterLength - 1);
2559 for (unsigned j = i + 1; j < FirstCatch; ++j)
2560 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2561 MMI->addFilterTypeInfo(MBB, TyInfo);
2562 TyInfo.clear();
2563 }
Duncan Sandsfe806382007-07-04 20:52:51 +00002564
2565 N = i;
2566 }
Duncan Sands92bf2c62007-06-15 19:04:19 +00002567 }
Duncan Sandsfe806382007-07-04 20:52:51 +00002568
2569 if (N > 3) {
2570 TyInfo.reserve(N - 3);
2571 for (unsigned j = 3; j < N; ++j)
2572 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
Duncan Sands92bf2c62007-06-15 19:04:19 +00002573 MMI->addCatchTypeInfo(MBB, TyInfo);
Duncan Sandsfe806382007-07-04 20:52:51 +00002574 }
Duncan Sands92bf2c62007-06-15 19:04:19 +00002575}
2576
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002577/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2578/// we want to emit this as a call to a named external function, return the name
2579/// otherwise lower it and return null.
2580const char *
2581SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2582 switch (Intrinsic) {
Chris Lattnerd96b09a2006-03-24 02:22:33 +00002583 default:
2584 // By default, turn this into a target intrinsic node.
2585 visitTargetIntrinsic(I, Intrinsic);
2586 return 0;
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002587 case Intrinsic::vastart: visitVAStart(I); return 0;
2588 case Intrinsic::vaend: visitVAEnd(I); return 0;
2589 case Intrinsic::vacopy: visitVACopy(I); return 0;
Nate Begemaneda59972007-01-29 22:58:52 +00002590 case Intrinsic::returnaddress:
2591 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2592 getValue(I.getOperand(1))));
2593 return 0;
2594 case Intrinsic::frameaddress:
2595 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2596 getValue(I.getOperand(1))));
2597 return 0;
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002598 case Intrinsic::setjmp:
Anton Korobeynikov3b7c2572006-12-10 23:12:42 +00002599 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002600 break;
2601 case Intrinsic::longjmp:
Anton Korobeynikov3b7c2572006-12-10 23:12:42 +00002602 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002603 break;
Chris Lattner093c1592006-03-03 00:00:25 +00002604 case Intrinsic::memcpy_i32:
2605 case Intrinsic::memcpy_i64:
2606 visitMemIntrinsic(I, ISD::MEMCPY);
2607 return 0;
2608 case Intrinsic::memset_i32:
2609 case Intrinsic::memset_i64:
2610 visitMemIntrinsic(I, ISD::MEMSET);
2611 return 0;
2612 case Intrinsic::memmove_i32:
2613 case Intrinsic::memmove_i64:
2614 visitMemIntrinsic(I, ISD::MEMMOVE);
2615 return 0;
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002616
Chris Lattner5d4e61d2005-12-13 17:40:33 +00002617 case Intrinsic::dbg_stoppoint: {
Jim Laskeyc56315c2007-01-26 21:22:28 +00002618 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskeya8bdac82006-03-23 18:06:46 +00002619 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
Jim Laskeyc56315c2007-01-26 21:22:28 +00002620 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002621 SDOperand Ops[5];
Chris Lattner435b4022005-11-29 06:21:05 +00002622
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002623 Ops[0] = getRoot();
2624 Ops[1] = getValue(SPI.getLineValue());
2625 Ops[2] = getValue(SPI.getColumnValue());
Chris Lattner435b4022005-11-29 06:21:05 +00002626
Jim Laskeyc56315c2007-01-26 21:22:28 +00002627 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
Jim Laskey5995d012006-02-11 01:01:30 +00002628 assert(DD && "Not a debug information descriptor");
Jim Laskeya8bdac82006-03-23 18:06:46 +00002629 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2630
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002631 Ops[3] = DAG.getString(CompileUnit->getFileName());
2632 Ops[4] = DAG.getString(CompileUnit->getDirectory());
Jim Laskey5995d012006-02-11 01:01:30 +00002633
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002634 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
Chris Lattner5d4e61d2005-12-13 17:40:33 +00002635 }
Jim Laskeya8bdac82006-03-23 18:06:46 +00002636
Chris Lattnerf2b62f32005-11-16 07:22:30 +00002637 return 0;
Chris Lattner435b4022005-11-29 06:21:05 +00002638 }
Jim Laskeya8bdac82006-03-23 18:06:46 +00002639 case Intrinsic::dbg_region_start: {
Jim Laskeyc56315c2007-01-26 21:22:28 +00002640 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskeya8bdac82006-03-23 18:06:46 +00002641 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
Jim Laskeyc56315c2007-01-26 21:22:28 +00002642 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2643 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
Jim Laskeyf9e54452007-01-26 14:34:52 +00002644 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002645 DAG.getConstant(LabelID, MVT::i32)));
Jim Laskeya8bdac82006-03-23 18:06:46 +00002646 }
2647
Chris Lattnerf2b62f32005-11-16 07:22:30 +00002648 return 0;
Jim Laskeya8bdac82006-03-23 18:06:46 +00002649 }
2650 case Intrinsic::dbg_region_end: {
Jim Laskeyc56315c2007-01-26 21:22:28 +00002651 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskeya8bdac82006-03-23 18:06:46 +00002652 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
Jim Laskeyc56315c2007-01-26 21:22:28 +00002653 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2654 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
Jim Laskeyf9e54452007-01-26 14:34:52 +00002655 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002656 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
Jim Laskeya8bdac82006-03-23 18:06:46 +00002657 }
2658
Chris Lattnerf2b62f32005-11-16 07:22:30 +00002659 return 0;
Jim Laskeya8bdac82006-03-23 18:06:46 +00002660 }
2661 case Intrinsic::dbg_func_start: {
Jim Laskeyc56315c2007-01-26 21:22:28 +00002662 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskeya8bdac82006-03-23 18:06:46 +00002663 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
Jim Laskeyc56315c2007-01-26 21:22:28 +00002664 if (MMI && FSI.getSubprogram() &&
2665 MMI->Verify(FSI.getSubprogram())) {
2666 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
Jim Laskeyf9e54452007-01-26 14:34:52 +00002667 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002668 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
Jim Laskeya8bdac82006-03-23 18:06:46 +00002669 }
2670
Chris Lattnerf2b62f32005-11-16 07:22:30 +00002671 return 0;
Jim Laskeya8bdac82006-03-23 18:06:46 +00002672 }
2673 case Intrinsic::dbg_declare: {
Jim Laskeyc56315c2007-01-26 21:22:28 +00002674 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskeya8bdac82006-03-23 18:06:46 +00002675 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
Jim Laskeyc56315c2007-01-26 21:22:28 +00002676 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
Jim Laskey53f1ecc2006-03-24 09:50:27 +00002677 SDOperand AddressOp = getValue(DI.getAddress());
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002678 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
Jim Laskeyc56315c2007-01-26 21:22:28 +00002679 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
Jim Laskeya8bdac82006-03-23 18:06:46 +00002680 }
2681
2682 return 0;
2683 }
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002684
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002685 case Intrinsic::eh_exception: {
Evan Cheng77f541d2007-06-27 18:45:32 +00002686 if (ExceptionHandling) {
Duncan Sands003c0b12007-07-06 09:18:59 +00002687 if (!CurMBB->isLandingPad()) {
2688 // FIXME: Mark exception register as live in. Hack for PR1508.
2689 unsigned Reg = TLI.getExceptionAddressRegister();
2690 if (Reg) CurMBB->addLiveIn(Reg);
2691 }
Jim Laskey504e9942007-02-22 15:38:06 +00002692 // Insert the EXCEPTIONADDR instruction.
2693 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2694 SDOperand Ops[1];
2695 Ops[0] = DAG.getRoot();
2696 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2697 setValue(&I, Op);
2698 DAG.setRoot(Op.getValue(1));
Jim Laskeye1d1c052007-02-24 09:45:44 +00002699 } else {
Jim Laskeycf465fc2007-02-28 18:37:04 +00002700 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
Jim Laskey504e9942007-02-22 15:38:06 +00002701 }
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002702 return 0;
2703 }
2704
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002705 case Intrinsic::eh_selector_i32:
2706 case Intrinsic::eh_selector_i64: {
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002707 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002708 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2709 MVT::i32 : MVT::i64);
2710
Duncan Sands92bf2c62007-06-15 19:04:19 +00002711 if (ExceptionHandling && MMI) {
2712 if (CurMBB->isLandingPad())
2713 addCatchInfo(I, MMI, CurMBB);
Evan Cheng77f541d2007-06-27 18:45:32 +00002714 else {
Duncan Sands92bf2c62007-06-15 19:04:19 +00002715#ifndef NDEBUG
Duncan Sands92bf2c62007-06-15 19:04:19 +00002716 FuncInfo.CatchInfoLost.insert(&I);
2717#endif
Duncan Sands003c0b12007-07-06 09:18:59 +00002718 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2719 unsigned Reg = TLI.getExceptionSelectorRegister();
2720 if (Reg) CurMBB->addLiveIn(Reg);
Evan Cheng77f541d2007-06-27 18:45:32 +00002721 }
Jim Laskey504e9942007-02-22 15:38:06 +00002722
2723 // Insert the EHSELECTION instruction.
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002724 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
Jim Laskey504e9942007-02-22 15:38:06 +00002725 SDOperand Ops[2];
2726 Ops[0] = getValue(I.getOperand(1));
2727 Ops[1] = getRoot();
2728 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2729 setValue(&I, Op);
2730 DAG.setRoot(Op.getValue(1));
Jim Laskeye1d1c052007-02-24 09:45:44 +00002731 } else {
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002732 setValue(&I, DAG.getConstant(0, VT));
Jim Laskey504e9942007-02-22 15:38:06 +00002733 }
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002734
2735 return 0;
2736 }
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002737
2738 case Intrinsic::eh_typeid_for_i32:
2739 case Intrinsic::eh_typeid_for_i64: {
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002740 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002741 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2742 MVT::i32 : MVT::i64);
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002743
Jim Laskey504e9942007-02-22 15:38:06 +00002744 if (MMI) {
2745 // Find the type id for the given typeinfo.
Duncan Sandsfe806382007-07-04 20:52:51 +00002746 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
Duncan Sands4cb9eb82007-05-04 17:12:26 +00002747
Jim Laskey504e9942007-02-22 15:38:06 +00002748 unsigned TypeID = MMI->getTypeIDFor(GV);
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002749 setValue(&I, DAG.getConstant(TypeID, VT));
Jim Laskeye1d1c052007-02-24 09:45:44 +00002750 } else {
Duncan Sands9d974202007-07-06 14:46:23 +00002751 // Return something different to eh_selector.
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00002752 setValue(&I, DAG.getConstant(1, VT));
Jim Laskey504e9942007-02-22 15:38:06 +00002753 }
Jim Laskey4b37a4c2007-02-21 22:53:45 +00002754
2755 return 0;
2756 }
2757
Anton Korobeynikov383a3242007-07-14 14:06:15 +00002758 case Intrinsic::eh_return: {
2759 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2760
2761 if (MMI && ExceptionHandling) {
2762 MMI->setCallsEHReturn(true);
2763 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2764 MVT::Other,
2765 getRoot(),
2766 getValue(I.getOperand(1)),
2767 getValue(I.getOperand(2))));
2768 } else {
2769 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2770 }
2771
2772 return 0;
2773 }
2774
2775 case Intrinsic::eh_unwind_init: {
2776 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2777 MMI->setCallsUnwindInit(true);
2778 }
2779
2780 return 0;
2781 }
2782
2783 case Intrinsic::eh_dwarf_cfa: {
2784 if (ExceptionHandling) {
2785 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
Anton Korobeynikov97cdac82007-08-23 07:21:06 +00002786 SDOperand CfaArg;
2787 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2788 CfaArg = DAG.getNode(ISD::TRUNCATE,
2789 TLI.getPointerTy(), getValue(I.getOperand(1)));
2790 else
2791 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2792 TLI.getPointerTy(), getValue(I.getOperand(1)));
2793
Anton Korobeynikov383a3242007-07-14 14:06:15 +00002794 SDOperand Offset = DAG.getNode(ISD::ADD,
2795 TLI.getPointerTy(),
2796 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
Anton Korobeynikov97cdac82007-08-23 07:21:06 +00002797 TLI.getPointerTy()),
2798 CfaArg);
Anton Korobeynikov383a3242007-07-14 14:06:15 +00002799 setValue(&I, DAG.getNode(ISD::ADD,
2800 TLI.getPointerTy(),
2801 DAG.getNode(ISD::FRAMEADDR,
2802 TLI.getPointerTy(),
2803 DAG.getConstant(0,
2804 TLI.getPointerTy())),
2805 Offset));
2806 } else {
2807 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2808 }
2809
2810 return 0;
2811 }
2812
Dale Johannesen4d4e77a2007-10-02 17:43:59 +00002813 case Intrinsic::sqrt:
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002814 setValue(&I, DAG.getNode(ISD::FSQRT,
2815 getValue(I.getOperand(1)).getValueType(),
2816 getValue(I.getOperand(1))));
2817 return 0;
Dale Johannesen4d4e77a2007-10-02 17:43:59 +00002818 case Intrinsic::powi:
Chris Lattnerf0359b32006-09-09 06:03:30 +00002819 setValue(&I, DAG.getNode(ISD::FPOWI,
2820 getValue(I.getOperand(1)).getValueType(),
2821 getValue(I.getOperand(1)),
2822 getValue(I.getOperand(2))));
2823 return 0;
Dan Gohmanbe370072007-10-12 00:01:22 +00002824 case Intrinsic::sin:
2825 setValue(&I, DAG.getNode(ISD::FSIN,
2826 getValue(I.getOperand(1)).getValueType(),
2827 getValue(I.getOperand(1))));
2828 return 0;
2829 case Intrinsic::cos:
2830 setValue(&I, DAG.getNode(ISD::FCOS,
2831 getValue(I.getOperand(1)).getValueType(),
2832 getValue(I.getOperand(1))));
2833 return 0;
2834 case Intrinsic::pow:
2835 setValue(&I, DAG.getNode(ISD::FPOW,
2836 getValue(I.getOperand(1)).getValueType(),
2837 getValue(I.getOperand(1)),
2838 getValue(I.getOperand(2))));
2839 return 0;
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002840 case Intrinsic::pcmarker: {
2841 SDOperand Tmp = getValue(I.getOperand(1));
2842 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2843 return 0;
2844 }
Andrew Lenharthde1b5d62005-11-11 22:48:54 +00002845 case Intrinsic::readcyclecounter: {
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002846 SDOperand Op = getRoot();
Chris Lattnerbd887772006-08-14 23:53:35 +00002847 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2848 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2849 &Op, 1);
Andrew Lenharthde1b5d62005-11-11 22:48:54 +00002850 setValue(&I, Tmp);
2851 DAG.setRoot(Tmp.getValue(1));
Andrew Lenharth01aa5632005-11-11 16:47:30 +00002852 return 0;
Andrew Lenharthde1b5d62005-11-11 22:48:54 +00002853 }
Chris Lattnerf269d842007-04-10 03:20:39 +00002854 case Intrinsic::part_select: {
Reid Spencer85460ac2007-04-05 01:20:18 +00002855 // Currently not implemented: just abort
Reid Spencerc6251a72007-04-12 02:48:46 +00002856 assert(0 && "part_select intrinsic not implemented");
2857 abort();
2858 }
2859 case Intrinsic::part_set: {
2860 // Currently not implemented: just abort
2861 assert(0 && "part_set intrinsic not implemented");
Reid Spencer85460ac2007-04-05 01:20:18 +00002862 abort();
Reid Spencercce90f52007-04-04 23:48:25 +00002863 }
Reid Spencer3a0843e2007-04-01 07:34:11 +00002864 case Intrinsic::bswap:
Nate Begeman2fba8a32006-01-14 03:14:10 +00002865 setValue(&I, DAG.getNode(ISD::BSWAP,
2866 getValue(I.getOperand(1)).getValueType(),
2867 getValue(I.getOperand(1))));
2868 return 0;
Reid Spencer3a0843e2007-04-01 07:34:11 +00002869 case Intrinsic::cttz: {
2870 SDOperand Arg = getValue(I.getOperand(1));
2871 MVT::ValueType Ty = Arg.getValueType();
2872 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
Reid Spencer3a0843e2007-04-01 07:34:11 +00002873 setValue(&I, result);
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002874 return 0;
Reid Spencer3a0843e2007-04-01 07:34:11 +00002875 }
2876 case Intrinsic::ctlz: {
2877 SDOperand Arg = getValue(I.getOperand(1));
2878 MVT::ValueType Ty = Arg.getValueType();
2879 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
Reid Spencer3a0843e2007-04-01 07:34:11 +00002880 setValue(&I, result);
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002881 return 0;
Reid Spencer3a0843e2007-04-01 07:34:11 +00002882 }
2883 case Intrinsic::ctpop: {
2884 SDOperand Arg = getValue(I.getOperand(1));
2885 MVT::ValueType Ty = Arg.getValueType();
2886 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
Reid Spencer3a0843e2007-04-01 07:34:11 +00002887 setValue(&I, result);
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002888 return 0;
Reid Spencer3a0843e2007-04-01 07:34:11 +00002889 }
Chris Lattnerb3266452006-01-13 02:50:02 +00002890 case Intrinsic::stacksave: {
Chris Lattnerc24a1d32006-08-08 02:23:42 +00002891 SDOperand Op = getRoot();
Chris Lattnerbd887772006-08-14 23:53:35 +00002892 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2893 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
Chris Lattnerb3266452006-01-13 02:50:02 +00002894 setValue(&I, Tmp);
2895 DAG.setRoot(Tmp.getValue(1));
2896 return 0;
2897 }
Chris Lattnerdeda32a2006-01-23 05:22:07 +00002898 case Intrinsic::stackrestore: {
2899 SDOperand Tmp = getValue(I.getOperand(1));
2900 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
Chris Lattnerb3266452006-01-13 02:50:02 +00002901 return 0;
Chris Lattnerdeda32a2006-01-23 05:22:07 +00002902 }
Chris Lattner9e8b6332005-12-12 22:51:16 +00002903 case Intrinsic::prefetch:
2904 // FIXME: Currently discarding prefetches.
2905 return 0;
Tanya Lattnere199f972007-06-15 22:26:58 +00002906
2907 case Intrinsic::var_annotation:
2908 // Discard annotate attributes
2909 return 0;
Duncan Sands644f9172007-07-27 12:58:54 +00002910
Duncan Sands644f9172007-07-27 12:58:54 +00002911 case Intrinsic::init_trampoline: {
2912 const Function *F =
2913 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2914
2915 SDOperand Ops[6];
2916 Ops[0] = getRoot();
2917 Ops[1] = getValue(I.getOperand(1));
2918 Ops[2] = getValue(I.getOperand(2));
2919 Ops[3] = getValue(I.getOperand(3));
2920 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2921 Ops[5] = DAG.getSrcValue(F);
2922
Duncan Sands86e01192007-09-11 14:10:23 +00002923 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2924 DAG.getNodeValueTypes(TLI.getPointerTy(),
2925 MVT::Other), 2,
2926 Ops, 6);
2927
2928 setValue(&I, Tmp);
2929 DAG.setRoot(Tmp.getValue(1));
Duncan Sands644f9172007-07-27 12:58:54 +00002930 return 0;
2931 }
Anton Korobeynikov66b91e66e2007-11-15 23:25:33 +00002932 case Intrinsic::flt_rounds: {
2933 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
2934 return 0;
2935 }
Chris Lattnercd6f0f42005-11-09 19:44:01 +00002936 }
2937}
2938
2939
Jim Laskey31fef782007-02-23 21:45:01 +00002940void SelectionDAGLowering::LowerCallTo(Instruction &I,
2941 const Type *CalledValueTy,
Duncan Sandsad0ea2d2007-11-27 13:23:08 +00002942 const ParamAttrsList *Attrs,
Jim Laskey31fef782007-02-23 21:45:01 +00002943 unsigned CallingConv,
2944 bool IsTailCall,
Anton Korobeynikov3b327822007-05-23 11:08:31 +00002945 SDOperand Callee, unsigned OpIdx,
2946 MachineBasicBlock *LandingPad) {
Jim Laskey31fef782007-02-23 21:45:01 +00002947 const PointerType *PT = cast<PointerType>(CalledValueTy);
Jim Laskey504e9942007-02-22 15:38:06 +00002948 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
Anton Korobeynikov3b327822007-05-23 11:08:31 +00002949 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2950 unsigned BeginLabel = 0, EndLabel = 0;
2951
Jim Laskey504e9942007-02-22 15:38:06 +00002952 TargetLowering::ArgListTy Args;
2953 TargetLowering::ArgListEntry Entry;
2954 Args.reserve(I.getNumOperands());
2955 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2956 Value *Arg = I.getOperand(i);
2957 SDOperand ArgNode = getValue(Arg);
2958 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
Duncan Sands671e8c42007-05-07 20:49:28 +00002959
2960 unsigned attrInd = i - OpIdx + 1;
2961 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt);
2962 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt);
2963 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg);
2964 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet);
Duncan Sands644f9172007-07-27 12:58:54 +00002965 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest);
Rafael Espindola9c3d20d2007-08-20 15:18:24 +00002966 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal);
Jim Laskey504e9942007-02-22 15:38:06 +00002967 Args.push_back(Entry);
2968 }
2969
Duncan Sands3c1b7fc2007-09-05 11:27:52 +00002970 if (ExceptionHandling && MMI && LandingPad) {
Anton Korobeynikov3b327822007-05-23 11:08:31 +00002971 // Insert a label before the invoke call to mark the try range. This can be
2972 // used to detect deletion of the invoke via the MachineModuleInfo.
2973 BeginLabel = MMI->NextLabelID();
2974 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2975 DAG.getConstant(BeginLabel, MVT::i32)));
2976 }
2977
Jim Laskey504e9942007-02-22 15:38:06 +00002978 std::pair<SDOperand,SDOperand> Result =
2979 TLI.LowerCallTo(getRoot(), I.getType(),
Reid Spencera472f662007-04-11 02:44:20 +00002980 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
Jim Laskey31fef782007-02-23 21:45:01 +00002981 FTy->isVarArg(), CallingConv, IsTailCall,
Jim Laskey504e9942007-02-22 15:38:06 +00002982 Callee, Args, DAG);
2983 if (I.getType() != Type::VoidTy)
2984 setValue(&I, Result.first);
2985 DAG.setRoot(Result.second);
Anton Korobeynikov3b327822007-05-23 11:08:31 +00002986
Duncan Sands3c1b7fc2007-09-05 11:27:52 +00002987 if (ExceptionHandling && MMI && LandingPad) {
Anton Korobeynikov3b327822007-05-23 11:08:31 +00002988 // Insert a label at the end of the invoke call to mark the try range. This
2989 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2990 EndLabel = MMI->NextLabelID();
2991 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2992 DAG.getConstant(EndLabel, MVT::i32)));
2993
2994 // Inform MachineModuleInfo of range.
2995 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2996 }
Jim Laskey504e9942007-02-22 15:38:06 +00002997}
2998
2999
Chris Lattner7a60d912005-01-07 07:47:53 +00003000void SelectionDAGLowering::visitCall(CallInst &I) {
Chris Lattner18d2b342005-01-08 22:48:57 +00003001 const char *RenameFn = 0;
Chris Lattnercd6f0f42005-11-09 19:44:01 +00003002 if (Function *F = I.getCalledFunction()) {
Chris Lattner33a7f512007-09-10 21:15:22 +00003003 if (F->isDeclaration()) {
Chris Lattnercd6f0f42005-11-09 19:44:01 +00003004 if (unsigned IID = F->getIntrinsicID()) {
3005 RenameFn = visitIntrinsicCall(I, IID);
3006 if (!RenameFn)
3007 return;
Chris Lattner33a7f512007-09-10 21:15:22 +00003008 }
3009 }
3010
3011 // Check for well-known libc/libm calls. If the function is internal, it
3012 // can't be a library call.
3013 unsigned NameLen = F->getNameLen();
3014 if (!F->hasInternalLinkage() && NameLen) {
3015 const char *NameStr = F->getNameStart();
3016 if (NameStr[0] == 'c' &&
3017 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3018 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3019 if (I.getNumOperands() == 3 && // Basic sanity checks.
3020 I.getOperand(1)->getType()->isFloatingPoint() &&
3021 I.getType() == I.getOperand(1)->getType() &&
3022 I.getType() == I.getOperand(2)->getType()) {
3023 SDOperand LHS = getValue(I.getOperand(1));
3024 SDOperand RHS = getValue(I.getOperand(2));
3025 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3026 LHS, RHS));
3027 return;
3028 }
3029 } else if (NameStr[0] == 'f' &&
3030 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
Dale Johannesenb6d56402007-09-26 21:10:55 +00003031 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3032 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
Chris Lattner33a7f512007-09-10 21:15:22 +00003033 if (I.getNumOperands() == 2 && // Basic sanity checks.
3034 I.getOperand(1)->getType()->isFloatingPoint() &&
3035 I.getType() == I.getOperand(1)->getType()) {
3036 SDOperand Tmp = getValue(I.getOperand(1));
3037 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3038 return;
3039 }
3040 } else if (NameStr[0] == 's' &&
3041 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
Dale Johannesenb6d56402007-09-26 21:10:55 +00003042 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3043 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
Chris Lattner33a7f512007-09-10 21:15:22 +00003044 if (I.getNumOperands() == 2 && // Basic sanity checks.
3045 I.getOperand(1)->getType()->isFloatingPoint() &&
3046 I.getType() == I.getOperand(1)->getType()) {
3047 SDOperand Tmp = getValue(I.getOperand(1));
3048 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3049 return;
3050 }
3051 } else if (NameStr[0] == 'c' &&
3052 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
Dale Johannesenb6d56402007-09-26 21:10:55 +00003053 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3054 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
Chris Lattner33a7f512007-09-10 21:15:22 +00003055 if (I.getNumOperands() == 2 && // Basic sanity checks.
3056 I.getOperand(1)->getType()->isFloatingPoint() &&
3057 I.getType() == I.getOperand(1)->getType()) {
3058 SDOperand Tmp = getValue(I.getOperand(1));
3059 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3060 return;
Chris Lattner80026402005-04-30 04:43:14 +00003061 }
Chris Lattnere4f71d02005-05-14 13:56:55 +00003062 }
Chris Lattner33a7f512007-09-10 21:15:22 +00003063 }
Chris Lattner476e67b2006-01-26 22:24:51 +00003064 } else if (isa<InlineAsm>(I.getOperand(0))) {
3065 visitInlineAsm(I);
3066 return;
Chris Lattnercd6f0f42005-11-09 19:44:01 +00003067 }
Misha Brukman835702a2005-04-21 22:36:52 +00003068
Chris Lattner18d2b342005-01-08 22:48:57 +00003069 SDOperand Callee;
3070 if (!RenameFn)
3071 Callee = getValue(I.getOperand(0));
3072 else
3073 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
Anton Korobeynikov3b327822007-05-23 11:08:31 +00003074
Duncan Sandsad0ea2d2007-11-27 13:23:08 +00003075 LowerCallTo(I, I.getCalledValue()->getType(), I.getParamAttrs(),
Anton Korobeynikov3b327822007-05-23 11:08:31 +00003076 I.getCallingConv(),
3077 I.isTailCall(),
3078 Callee,
3079 1);
Chris Lattner7a60d912005-01-07 07:47:53 +00003080}
3081
Jim Laskey504e9942007-02-22 15:38:06 +00003082
Dan Gohman78677932007-06-28 23:29:44 +00003083/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3084/// this value and returns the result as a ValueVT value. This uses
3085/// Chain/Flag as the input and updates them for the output Chain/Flag.
3086/// If the Flag pointer is NULL, no flag is used.
3087SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3088 SDOperand &Chain, SDOperand *Flag)const{
Dan Gohman78677932007-06-28 23:29:44 +00003089 // Copy the legal parts from the registers.
3090 unsigned NumParts = Regs.size();
3091 SmallVector<SDOperand, 8> Parts(NumParts);
Dan Gohman533dd162007-07-02 16:18:06 +00003092 for (unsigned i = 0; i != NumParts; ++i) {
Dan Gohman78677932007-06-28 23:29:44 +00003093 SDOperand Part = Flag ?
3094 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3095 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3096 Chain = Part.getValue(1);
3097 if (Flag)
3098 *Flag = Part.getValue(2);
3099 Parts[i] = Part;
Chris Lattner705948d2006-06-08 18:22:48 +00003100 }
Chris Lattner77f04792007-03-25 05:00:54 +00003101
Dan Gohman78677932007-06-28 23:29:44 +00003102 // Assemble the legal parts into the final value.
Dan Gohmanf8f531b2007-07-09 20:59:04 +00003103 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
Chris Lattner6f87d182006-02-22 22:37:12 +00003104}
3105
Chris Lattner571d9642006-02-23 19:21:04 +00003106/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3107/// specified value into the registers specified by this object. This uses
3108/// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohman78677932007-06-28 23:29:44 +00003109/// If the Flag pointer is NULL, no flag is used.
Chris Lattner571d9642006-02-23 19:21:04 +00003110void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
Dan Gohman78677932007-06-28 23:29:44 +00003111 SDOperand &Chain, SDOperand *Flag) const {
Dan Gohman78677932007-06-28 23:29:44 +00003112 // Get the list of the values's legal parts.
3113 unsigned NumParts = Regs.size();
3114 SmallVector<SDOperand, 8> Parts(NumParts);
Dan Gohmanf8f531b2007-07-09 20:59:04 +00003115 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
Dan Gohman78677932007-06-28 23:29:44 +00003116
3117 // Copy the parts into the registers.
Dan Gohman533dd162007-07-02 16:18:06 +00003118 for (unsigned i = 0; i != NumParts; ++i) {
Dan Gohman78677932007-06-28 23:29:44 +00003119 SDOperand Part = Flag ?
Dan Gohmanf8f531b2007-07-09 20:59:04 +00003120 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3121 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
Dan Gohman78677932007-06-28 23:29:44 +00003122 Chain = Part.getValue(0);
3123 if (Flag)
3124 *Flag = Part.getValue(1);
Chris Lattner571d9642006-02-23 19:21:04 +00003125 }
3126}
Chris Lattner6f87d182006-02-22 22:37:12 +00003127
Chris Lattner571d9642006-02-23 19:21:04 +00003128/// AddInlineAsmOperands - Add this value to the specified inlineasm node
3129/// operand list. This adds the code marker and includes the number of
3130/// values added into it.
3131void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Chris Lattnere7c0ffb2006-02-23 20:06:57 +00003132 std::vector<SDOperand> &Ops) const {
Chris Lattnerb49917d2007-04-09 00:33:58 +00003133 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3134 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
Chris Lattner571d9642006-02-23 19:21:04 +00003135 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3136 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3137}
Chris Lattner6f87d182006-02-22 22:37:12 +00003138
3139/// isAllocatableRegister - If the specified register is safe to allocate,
3140/// i.e. it isn't a stack pointer or some other special register, return the
3141/// register class for the register. Otherwise, return null.
3142static const TargetRegisterClass *
Chris Lattnerb1124f32006-02-22 23:09:03 +00003143isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3144 const TargetLowering &TLI, const MRegisterInfo *MRI) {
Chris Lattnerbec582f2006-04-02 00:24:45 +00003145 MVT::ValueType FoundVT = MVT::Other;
3146 const TargetRegisterClass *FoundRC = 0;
Chris Lattnerb1124f32006-02-22 23:09:03 +00003147 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3148 E = MRI->regclass_end(); RCI != E; ++RCI) {
Chris Lattnerbec582f2006-04-02 00:24:45 +00003149 MVT::ValueType ThisVT = MVT::Other;
3150
Chris Lattnerb1124f32006-02-22 23:09:03 +00003151 const TargetRegisterClass *RC = *RCI;
3152 // If none of the the value types for this register class are valid, we
3153 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Chris Lattnerb1124f32006-02-22 23:09:03 +00003154 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3155 I != E; ++I) {
3156 if (TLI.isTypeLegal(*I)) {
Chris Lattnerbec582f2006-04-02 00:24:45 +00003157 // If we have already found this register in a different register class,
3158 // choose the one with the largest VT specified. For example, on
3159 // PowerPC, we favor f64 register classes over f32.
3160 if (FoundVT == MVT::Other ||
3161 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3162 ThisVT = *I;
3163 break;
3164 }
Chris Lattnerb1124f32006-02-22 23:09:03 +00003165 }
3166 }
3167
Chris Lattnerbec582f2006-04-02 00:24:45 +00003168 if (ThisVT == MVT::Other) continue;
Chris Lattnerb1124f32006-02-22 23:09:03 +00003169
Chris Lattner6f87d182006-02-22 22:37:12 +00003170 // NOTE: This isn't ideal. In particular, this might allocate the
3171 // frame pointer in functions that need it (due to them not being taken
3172 // out of allocation, because a variable sized allocation hasn't been seen
3173 // yet). This is a slight code pessimization, but should still work.
Chris Lattnerb1124f32006-02-22 23:09:03 +00003174 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3175 E = RC->allocation_order_end(MF); I != E; ++I)
Chris Lattnerbec582f2006-04-02 00:24:45 +00003176 if (*I == Reg) {
3177 // We found a matching register class. Keep looking at others in case
3178 // we find one with larger registers that this physreg is also in.
3179 FoundRC = RC;
3180 FoundVT = ThisVT;
3181 break;
3182 }
Chris Lattner1558fc62006-02-01 18:59:47 +00003183 }
Chris Lattnerbec582f2006-04-02 00:24:45 +00003184 return FoundRC;
Chris Lattner6f87d182006-02-22 22:37:12 +00003185}
3186
Chris Lattner1558fc62006-02-01 18:59:47 +00003187
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003188namespace {
3189/// AsmOperandInfo - This contains information for each constraint that we are
3190/// lowering.
3191struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3192 /// ConstraintCode - This contains the actual string for the code, like "m".
3193 std::string ConstraintCode;
Chris Lattnerb2e55562007-04-28 21:01:43 +00003194
3195 /// ConstraintType - Information about the constraint code, e.g. Register,
3196 /// RegisterClass, Memory, Other, Unknown.
3197 TargetLowering::ConstraintType ConstraintType;
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003198
3199 /// CallOperand/CallOperandval - If this is the result output operand or a
3200 /// clobber, this is null, otherwise it is the incoming operand to the
3201 /// CallInst. This gets modified as the asm is processed.
3202 SDOperand CallOperand;
3203 Value *CallOperandVal;
3204
3205 /// ConstraintVT - The ValueType for the operand value.
3206 MVT::ValueType ConstraintVT;
3207
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003208 /// AssignedRegs - If this is a register or register class operand, this
3209 /// contains the set of register corresponding to the operand.
3210 RegsForValue AssignedRegs;
3211
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003212 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
Chris Lattnerb2e55562007-04-28 21:01:43 +00003213 : InlineAsm::ConstraintInfo(info),
3214 ConstraintType(TargetLowering::C_Unknown),
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003215 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3216 }
Chris Lattneref073322007-04-30 17:16:27 +00003217
3218 void ComputeConstraintToUse(const TargetLowering &TLI);
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003219
3220 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3221 /// busy in OutputRegs/InputRegs.
3222 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3223 std::set<unsigned> &OutputRegs,
3224 std::set<unsigned> &InputRegs) const {
3225 if (isOutReg)
3226 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3227 if (isInReg)
3228 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3229 }
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003230};
3231} // end anon namespace.
Chris Lattner6f87d182006-02-22 22:37:12 +00003232
Chris Lattneref073322007-04-30 17:16:27 +00003233/// getConstraintGenerality - Return an integer indicating how general CT is.
3234static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3235 switch (CT) {
3236 default: assert(0 && "Unknown constraint type!");
3237 case TargetLowering::C_Other:
3238 case TargetLowering::C_Unknown:
3239 return 0;
3240 case TargetLowering::C_Register:
3241 return 1;
3242 case TargetLowering::C_RegisterClass:
3243 return 2;
3244 case TargetLowering::C_Memory:
3245 return 3;
3246 }
3247}
3248
3249void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3250 assert(!Codes.empty() && "Must have at least one constraint");
3251
3252 std::string *Current = &Codes[0];
3253 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3254 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3255 ConstraintCode = *Current;
3256 ConstraintType = CurType;
3257 return;
3258 }
3259
3260 unsigned CurGenerality = getConstraintGenerality(CurType);
3261
3262 // If we have multiple constraints, try to pick the most general one ahead
3263 // of time. This isn't a wonderful solution, but handles common cases.
3264 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3265 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3266 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3267 if (ThisGenerality > CurGenerality) {
3268 // This constraint letter is more general than the previous one,
3269 // use it.
3270 CurType = ThisType;
3271 Current = &Codes[j];
3272 CurGenerality = ThisGenerality;
3273 }
3274 }
3275
3276 ConstraintCode = *Current;
3277 ConstraintType = CurType;
3278}
3279
3280
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003281void SelectionDAGLowering::
3282GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
Chris Lattner4333f8b2007-04-30 17:29:31 +00003283 std::set<unsigned> &OutputRegs,
3284 std::set<unsigned> &InputRegs) {
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003285 // Compute whether this value requires an input register, an output register,
3286 // or both.
3287 bool isOutReg = false;
3288 bool isInReg = false;
3289 switch (OpInfo.Type) {
3290 case InlineAsm::isOutput:
3291 isOutReg = true;
3292
3293 // If this is an early-clobber output, or if there is an input
3294 // constraint that matches this, we need to reserve the input register
3295 // so no other inputs allocate to it.
3296 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3297 break;
3298 case InlineAsm::isInput:
3299 isInReg = true;
3300 isOutReg = false;
3301 break;
3302 case InlineAsm::isClobber:
3303 isOutReg = true;
3304 isInReg = true;
3305 break;
3306 }
3307
3308
3309 MachineFunction &MF = DAG.getMachineFunction();
Chris Lattner4333f8b2007-04-30 17:29:31 +00003310 std::vector<unsigned> Regs;
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003311
3312 // If this is a constraint for a single physreg, or a constraint for a
3313 // register class, find it.
3314 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3315 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3316 OpInfo.ConstraintVT);
Chris Lattner4333f8b2007-04-30 17:29:31 +00003317
3318 unsigned NumRegs = 1;
3319 if (OpInfo.ConstraintVT != MVT::Other)
Dan Gohman04deef32007-06-21 14:42:22 +00003320 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
Chris Lattner4333f8b2007-04-30 17:29:31 +00003321 MVT::ValueType RegVT;
3322 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3323
Chris Lattner4333f8b2007-04-30 17:29:31 +00003324
3325 // If this is a constraint for a specific physical register, like {r17},
3326 // assign it now.
3327 if (PhysReg.first) {
3328 if (OpInfo.ConstraintVT == MVT::Other)
3329 ValueVT = *PhysReg.second->vt_begin();
3330
3331 // Get the actual register value type. This is important, because the user
3332 // may have asked for (e.g.) the AX register in i32 type. We need to
3333 // remember that AX is actually i16 to get the right extension.
3334 RegVT = *PhysReg.second->vt_begin();
3335
3336 // This is a explicit reference to a physical register.
3337 Regs.push_back(PhysReg.first);
3338
3339 // If this is an expanded reference, add the rest of the regs to Regs.
3340 if (NumRegs != 1) {
3341 TargetRegisterClass::iterator I = PhysReg.second->begin();
3342 TargetRegisterClass::iterator E = PhysReg.second->end();
3343 for (; *I != PhysReg.first; ++I)
3344 assert(I != E && "Didn't find reg!");
3345
3346 // Already added the first reg.
3347 --NumRegs; ++I;
3348 for (; NumRegs; --NumRegs, ++I) {
3349 assert(I != E && "Ran out of registers to allocate!");
3350 Regs.push_back(*I);
3351 }
3352 }
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003353 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3354 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3355 return;
Chris Lattner4333f8b2007-04-30 17:29:31 +00003356 }
3357
3358 // Otherwise, if this was a reference to an LLVM register class, create vregs
3359 // for this reference.
3360 std::vector<unsigned> RegClassRegs;
Chris Lattnerf852e332007-06-15 19:11:01 +00003361 const TargetRegisterClass *RC = PhysReg.second;
3362 if (RC) {
Chris Lattner4333f8b2007-04-30 17:29:31 +00003363 // If this is an early clobber or tied register, our regalloc doesn't know
3364 // how to maintain the constraint. If it isn't, go ahead and create vreg
3365 // and let the regalloc do the right thing.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003366 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3367 // If there is some other early clobber and this is an input register,
3368 // then we are forced to pre-allocate the input reg so it doesn't
3369 // conflict with the earlyclobber.
3370 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
Chris Lattner4333f8b2007-04-30 17:29:31 +00003371 RegVT = *PhysReg.second->vt_begin();
3372
3373 if (OpInfo.ConstraintVT == MVT::Other)
3374 ValueVT = RegVT;
3375
3376 // Create the appropriate number of virtual registers.
3377 SSARegMap *RegMap = MF.getSSARegMap();
3378 for (; NumRegs; --NumRegs)
3379 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3380
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003381 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3382 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3383 return;
Chris Lattner4333f8b2007-04-30 17:29:31 +00003384 }
3385
3386 // Otherwise, we can't allocate it. Let the code below figure out how to
3387 // maintain these constraints.
3388 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3389
3390 } else {
3391 // This is a reference to a register class that doesn't directly correspond
3392 // to an LLVM register class. Allocate NumRegs consecutive, available,
3393 // registers from the class.
3394 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3395 OpInfo.ConstraintVT);
3396 }
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003397
Chris Lattner4333f8b2007-04-30 17:29:31 +00003398 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3399 unsigned NumAllocated = 0;
3400 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3401 unsigned Reg = RegClassRegs[i];
3402 // See if this register is available.
3403 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3404 (isInReg && InputRegs.count(Reg))) { // Already used.
3405 // Make sure we find consecutive registers.
3406 NumAllocated = 0;
3407 continue;
3408 }
3409
3410 // Check to see if this register is allocatable (i.e. don't give out the
3411 // stack pointer).
Chris Lattnerf852e332007-06-15 19:11:01 +00003412 if (RC == 0) {
3413 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3414 if (!RC) { // Couldn't allocate this register.
3415 // Reset NumAllocated to make sure we return consecutive registers.
3416 NumAllocated = 0;
3417 continue;
3418 }
Chris Lattner4333f8b2007-04-30 17:29:31 +00003419 }
3420
3421 // Okay, this register is good, we can use it.
3422 ++NumAllocated;
3423
3424 // If we allocated enough consecutive registers, succeed.
3425 if (NumAllocated == NumRegs) {
3426 unsigned RegStart = (i-NumAllocated)+1;
3427 unsigned RegEnd = i+1;
3428 // Mark all of the allocated registers used.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003429 for (unsigned i = RegStart; i != RegEnd; ++i)
3430 Regs.push_back(RegClassRegs[i]);
Chris Lattner4333f8b2007-04-30 17:29:31 +00003431
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003432 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3433 OpInfo.ConstraintVT);
3434 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3435 return;
Chris Lattner4333f8b2007-04-30 17:29:31 +00003436 }
3437 }
3438
3439 // Otherwise, we couldn't allocate enough registers for this.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003440 return;
Chris Lattner4333f8b2007-04-30 17:29:31 +00003441}
3442
3443
Chris Lattner476e67b2006-01-26 22:24:51 +00003444/// visitInlineAsm - Handle a call to an InlineAsm object.
3445///
3446void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
3447 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
Chris Lattner476e67b2006-01-26 22:24:51 +00003448
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003449 /// ConstraintOperands - Information about all of the constraints.
3450 std::vector<AsmOperandInfo> ConstraintOperands;
Chris Lattner476e67b2006-01-26 22:24:51 +00003451
3452 SDOperand Chain = getRoot();
3453 SDOperand Flag;
3454
Chris Lattner1558fc62006-02-01 18:59:47 +00003455 std::set<unsigned> OutputRegs, InputRegs;
Chris Lattner7ad77df2006-02-22 00:56:39 +00003456
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003457 // Do a prepass over the constraints, canonicalizing them, and building up the
3458 // ConstraintOperands list.
3459 std::vector<InlineAsm::ConstraintInfo>
3460 ConstraintInfos = IA->ParseConstraints();
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003461
3462 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3463 // constraint. If so, we can't let the register allocator allocate any input
3464 // registers, because it will not know to avoid the earlyclobbered output reg.
3465 bool SawEarlyClobber = false;
3466
3467 unsigned OpNo = 1; // OpNo - The operand of the CallInst.
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003468 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3469 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3470 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3471
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003472 MVT::ValueType OpVT = MVT::Other;
3473
3474 // Compute the value type for each operand.
3475 switch (OpInfo.Type) {
Chris Lattner7ad77df2006-02-22 00:56:39 +00003476 case InlineAsm::isOutput:
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003477 if (!OpInfo.isIndirect) {
3478 // The return value of the call is this value. As such, there is no
3479 // corresponding argument.
Chris Lattner7ad77df2006-02-22 00:56:39 +00003480 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3481 OpVT = TLI.getValueType(I.getType());
3482 } else {
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003483 OpInfo.CallOperandVal = I.getOperand(OpNo++);
Chris Lattner7ad77df2006-02-22 00:56:39 +00003484 }
3485 break;
3486 case InlineAsm::isInput:
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003487 OpInfo.CallOperandVal = I.getOperand(OpNo++);
Chris Lattner7ad77df2006-02-22 00:56:39 +00003488 break;
3489 case InlineAsm::isClobber:
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003490 // Nothing to do.
Chris Lattner7ad77df2006-02-22 00:56:39 +00003491 break;
3492 }
Chris Lattner7ad77df2006-02-22 00:56:39 +00003493
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003494 // If this is an input or an indirect output, process the call argument.
Dale Johannesen4646aa32007-11-05 21:20:28 +00003495 // BasicBlocks are labels, currently appearing only in asm's.
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003496 if (OpInfo.CallOperandVal) {
Dale Johannesen4646aa32007-11-05 21:20:28 +00003497 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3498 OpInfo.CallOperand =
3499 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]);
3500 else {
3501 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3502 const Type *OpTy = OpInfo.CallOperandVal->getType();
3503 // If this is an indirect operand, the operand is a pointer to the
3504 // accessed type.
3505 if (OpInfo.isIndirect)
3506 OpTy = cast<PointerType>(OpTy)->getElementType();
3507
3508 // If OpTy is not a first-class value, it may be a struct/union that we
3509 // can tile with integers.
3510 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3511 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3512 switch (BitSize) {
3513 default: break;
3514 case 1:
3515 case 8:
3516 case 16:
3517 case 32:
3518 case 64:
3519 OpTy = IntegerType::get(BitSize);
3520 break;
3521 }
Chris Lattner412d61a2007-04-29 18:58:03 +00003522 }
Dale Johannesen4646aa32007-11-05 21:20:28 +00003523
3524 OpVT = TLI.getValueType(OpTy, true);
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003525 }
3526 }
3527
3528 OpInfo.ConstraintVT = OpVT;
Chris Lattnerb2e55562007-04-28 21:01:43 +00003529
Chris Lattneref073322007-04-30 17:16:27 +00003530 // Compute the constraint code and ConstraintType to use.
3531 OpInfo.ComputeConstraintToUse(TLI);
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003532
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003533 // Keep track of whether we see an earlyclobber.
3534 SawEarlyClobber |= OpInfo.isEarlyClobber;
Chris Lattner401d8db2007-04-28 21:12:06 +00003535
3536 // If this is a memory input, and if the operand is not indirect, do what we
3537 // need to to provide an address for the memory input.
3538 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3539 !OpInfo.isIndirect) {
3540 assert(OpInfo.Type == InlineAsm::isInput &&
3541 "Can only indirectify direct input operands!");
3542
3543 // Memory operands really want the address of the value. If we don't have
3544 // an indirect input, put it in the constpool if we can, otherwise spill
3545 // it to a stack slot.
3546
3547 // If the operand is a float, integer, or vector constant, spill to a
3548 // constant pool entry to get its address.
3549 Value *OpVal = OpInfo.CallOperandVal;
3550 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3551 isa<ConstantVector>(OpVal)) {
3552 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3553 TLI.getPointerTy());
3554 } else {
3555 // Otherwise, create a stack slot and emit a store to it before the
3556 // asm.
3557 const Type *Ty = OpVal->getType();
Duncan Sands44b87212007-11-01 20:53:16 +00003558 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Chris Lattner401d8db2007-04-28 21:12:06 +00003559 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3560 MachineFunction &MF = DAG.getMachineFunction();
3561 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3562 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3563 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3564 OpInfo.CallOperand = StackSlot;
3565 }
3566
3567 // There is no longer a Value* corresponding to this operand.
3568 OpInfo.CallOperandVal = 0;
3569 // It is now an indirect operand.
3570 OpInfo.isIndirect = true;
3571 }
3572
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003573 // If this constraint is for a specific register, allocate it before
3574 // anything else.
3575 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3576 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003577 }
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003578 ConstraintInfos.clear();
3579
3580
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003581 // Second pass - Loop over all of the operands, assigning virtual or physregs
3582 // to registerclass operands.
3583 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3584 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3585
3586 // C_Register operands have already been allocated, Other/Memory don't need
3587 // to be.
3588 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3589 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3590 }
3591
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003592 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3593 std::vector<SDOperand> AsmNodeOperands;
3594 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3595 AsmNodeOperands.push_back(
3596 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3597
Chris Lattner3a5ed552006-02-01 01:28:23 +00003598
Chris Lattner5c79f982006-02-21 23:12:12 +00003599 // Loop over all of the inputs, copying the operand values into the
3600 // appropriate registers and processing the output regs.
Chris Lattner6f87d182006-02-22 22:37:12 +00003601 RegsForValue RetValRegs;
Chris Lattner5c79f982006-02-21 23:12:12 +00003602
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003603 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3604 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3605
3606 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3607 AsmOperandInfo &OpInfo = ConstraintOperands[i];
Chris Lattner7ad77df2006-02-22 00:56:39 +00003608
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003609 switch (OpInfo.Type) {
Chris Lattner3a5ed552006-02-01 01:28:23 +00003610 case InlineAsm::isOutput: {
Chris Lattnerde339fa2007-04-28 21:03:16 +00003611 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3612 OpInfo.ConstraintType != TargetLowering::C_Register) {
Chris Lattnerd102ed02007-04-28 06:08:13 +00003613 // Memory output, or 'other' output (e.g. 'X' constraint).
Chris Lattner401d8db2007-04-28 21:12:06 +00003614 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
Chris Lattner9fed5b62006-02-27 23:45:39 +00003615
Chris Lattner9fed5b62006-02-27 23:45:39 +00003616 // Add information to the INLINEASM node to know about this output.
3617 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
Chris Lattnerc7596ef2007-05-15 01:33:58 +00003618 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3619 TLI.getPointerTy()));
Chris Lattner401d8db2007-04-28 21:12:06 +00003620 AsmNodeOperands.push_back(OpInfo.CallOperand);
Chris Lattner9fed5b62006-02-27 23:45:39 +00003621 break;
3622 }
3623
Chris Lattnerb2e55562007-04-28 21:01:43 +00003624 // Otherwise, this is a register or register class output.
Chris Lattner9fed5b62006-02-27 23:45:39 +00003625
Chris Lattner6f87d182006-02-22 22:37:12 +00003626 // Copy the output from the appropriate register. Find a register that
Chris Lattner7ad77df2006-02-22 00:56:39 +00003627 // we can use.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003628 if (OpInfo.AssignedRegs.Regs.empty()) {
Bill Wendling22e978a2006-12-07 20:04:42 +00003629 cerr << "Couldn't allocate output reg for contraint '"
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003630 << OpInfo.ConstraintCode << "'!\n";
Chris Lattner968f8032006-10-31 07:33:13 +00003631 exit(1);
3632 }
Chris Lattner7ad77df2006-02-22 00:56:39 +00003633
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003634 if (!OpInfo.isIndirect) {
3635 // This is the result value of the call.
Chris Lattner6f87d182006-02-22 22:37:12 +00003636 assert(RetValRegs.Regs.empty() &&
Chris Lattner3a5ed552006-02-01 01:28:23 +00003637 "Cannot have multiple output constraints yet!");
Chris Lattner3a5ed552006-02-01 01:28:23 +00003638 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003639 RetValRegs = OpInfo.AssignedRegs;
Chris Lattner3a5ed552006-02-01 01:28:23 +00003640 } else {
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003641 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003642 OpInfo.CallOperandVal));
Chris Lattner3a5ed552006-02-01 01:28:23 +00003643 }
Chris Lattner2e56e892006-01-31 02:03:41 +00003644
3645 // Add information to the INLINEASM node to know that this register is
3646 // set.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003647 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3648 AsmNodeOperands);
Chris Lattner2e56e892006-01-31 02:03:41 +00003649 break;
3650 }
3651 case InlineAsm::isInput: {
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003652 SDOperand InOperandVal = OpInfo.CallOperand;
Chris Lattner65ad53f2006-02-04 02:16:44 +00003653
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003654 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
Chris Lattner7f5880b2006-02-02 00:25:23 +00003655 // If this is required to match an output register we have already set,
3656 // just use its register.
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003657 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
Chris Lattner65ad53f2006-02-04 02:16:44 +00003658
Chris Lattner571d9642006-02-23 19:21:04 +00003659 // Scan until we find the definition we already emitted of this operand.
3660 // When we find it, create a RegsForValue operand.
3661 unsigned CurOp = 2; // The first operand.
3662 for (; OperandNo; --OperandNo) {
3663 // Advance to the next operand.
3664 unsigned NumOps =
3665 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattnerb0305322006-07-20 19:02:21 +00003666 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3667 (NumOps & 7) == 4 /*MEM*/) &&
Chris Lattner571d9642006-02-23 19:21:04 +00003668 "Skipped past definitions?");
3669 CurOp += (NumOps>>3)+1;
3670 }
3671
3672 unsigned NumOps =
3673 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattnere3eeb242007-02-01 01:21:12 +00003674 if ((NumOps & 7) == 2 /*REGDEF*/) {
3675 // Add NumOps>>3 registers to MatchedRegs.
3676 RegsForValue MatchedRegs;
3677 MatchedRegs.ValueVT = InOperandVal.getValueType();
3678 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3679 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3680 unsigned Reg =
3681 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3682 MatchedRegs.Regs.push_back(Reg);
3683 }
Chris Lattner571d9642006-02-23 19:21:04 +00003684
Chris Lattnere3eeb242007-02-01 01:21:12 +00003685 // Use the produced MatchedRegs object to
Dan Gohman78677932007-06-28 23:29:44 +00003686 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
Chris Lattnere3eeb242007-02-01 01:21:12 +00003687 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3688 break;
3689 } else {
3690 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3691 assert(0 && "matching constraints for memory operands unimp");
Chris Lattner571d9642006-02-23 19:21:04 +00003692 }
Chris Lattner7f5880b2006-02-02 00:25:23 +00003693 }
Chris Lattner7ef7a642006-02-24 01:11:24 +00003694
Chris Lattnerb2e55562007-04-28 21:01:43 +00003695 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003696 assert(!OpInfo.isIndirect &&
Chris Lattner1deacd62007-04-28 06:42:38 +00003697 "Don't know how to handle indirect other inputs yet!");
3698
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00003699 std::vector<SDOperand> Ops;
3700 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3701 Ops, DAG);
3702 if (Ops.empty()) {
Bill Wendling22e978a2006-12-07 20:04:42 +00003703 cerr << "Invalid operand for inline asm constraint '"
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003704 << OpInfo.ConstraintCode << "'!\n";
Chris Lattner6f043b92006-10-31 19:41:18 +00003705 exit(1);
3706 }
Chris Lattner7ef7a642006-02-24 01:11:24 +00003707
3708 // Add information to the INLINEASM node to know about this input.
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00003709 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
Chris Lattnerc7596ef2007-05-15 01:33:58 +00003710 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3711 TLI.getPointerTy()));
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00003712 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
Chris Lattner7ef7a642006-02-24 01:11:24 +00003713 break;
Chris Lattnerb2e55562007-04-28 21:01:43 +00003714 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
Chris Lattner401d8db2007-04-28 21:12:06 +00003715 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
Chris Lattner1deacd62007-04-28 06:42:38 +00003716 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3717 "Memory operands expect pointer values");
3718
Chris Lattner7ef7a642006-02-24 01:11:24 +00003719 // Add information to the INLINEASM node to know about this input.
3720 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
Chris Lattnerc7596ef2007-05-15 01:33:58 +00003721 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3722 TLI.getPointerTy()));
Chris Lattner7ef7a642006-02-24 01:11:24 +00003723 AsmNodeOperands.push_back(InOperandVal);
3724 break;
3725 }
3726
Chris Lattnerb2e55562007-04-28 21:01:43 +00003727 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3728 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3729 "Unknown constraint type!");
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003730 assert(!OpInfo.isIndirect &&
Chris Lattner1deacd62007-04-28 06:42:38 +00003731 "Don't know how to handle indirect register inputs yet!");
Chris Lattner7ef7a642006-02-24 01:11:24 +00003732
3733 // Copy the input into the appropriate registers.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003734 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3735 "Couldn't allocate input reg!");
Chris Lattner7ef7a642006-02-24 01:11:24 +00003736
Dan Gohman78677932007-06-28 23:29:44 +00003737 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
Chris Lattner7ef7a642006-02-24 01:11:24 +00003738
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003739 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3740 AsmNodeOperands);
Chris Lattner2e56e892006-01-31 02:03:41 +00003741 break;
3742 }
Chris Lattner571d9642006-02-23 19:21:04 +00003743 case InlineAsm::isClobber: {
Chris Lattner571d9642006-02-23 19:21:04 +00003744 // Add the clobbered value to the operand list, so that the register
3745 // allocator is aware that the physreg got clobbered.
Chris Lattner8cfd33b2007-04-30 21:11:17 +00003746 if (!OpInfo.AssignedRegs.Regs.empty())
3747 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3748 AsmNodeOperands);
Chris Lattner2e56e892006-01-31 02:03:41 +00003749 break;
3750 }
Chris Lattner571d9642006-02-23 19:21:04 +00003751 }
Chris Lattner2e56e892006-01-31 02:03:41 +00003752 }
Chris Lattner476e67b2006-01-26 22:24:51 +00003753
3754 // Finish up input operands.
3755 AsmNodeOperands[0] = Chain;
3756 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3757
Chris Lattnerbd887772006-08-14 23:53:35 +00003758 Chain = DAG.getNode(ISD::INLINEASM,
3759 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
Chris Lattnerc24a1d32006-08-08 02:23:42 +00003760 &AsmNodeOperands[0], AsmNodeOperands.size());
Chris Lattner476e67b2006-01-26 22:24:51 +00003761 Flag = Chain.getValue(1);
3762
Chris Lattner2e56e892006-01-31 02:03:41 +00003763 // If this asm returns a register value, copy the result from that register
3764 // and set it as the value of the call.
Chris Lattner51114992007-04-12 06:00:20 +00003765 if (!RetValRegs.Regs.empty()) {
Dan Gohman78677932007-06-28 23:29:44 +00003766 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
Chris Lattner51114992007-04-12 06:00:20 +00003767
3768 // If the result of the inline asm is a vector, it may have the wrong
3769 // width/num elts. Make sure to convert it to the right type with
Dan Gohmana8665142007-06-25 16:23:39 +00003770 // bit_convert.
3771 if (MVT::isVector(Val.getValueType())) {
Chris Lattner51114992007-04-12 06:00:20 +00003772 const VectorType *VTy = cast<VectorType>(I.getType());
Dan Gohmana8665142007-06-25 16:23:39 +00003773 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
Chris Lattner51114992007-04-12 06:00:20 +00003774
Dan Gohmana8665142007-06-25 16:23:39 +00003775 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
Chris Lattner51114992007-04-12 06:00:20 +00003776 }
3777
3778 setValue(&I, Val);
3779 }
Chris Lattner476e67b2006-01-26 22:24:51 +00003780
Chris Lattner2e56e892006-01-31 02:03:41 +00003781 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3782
3783 // Process indirect outputs, first output all of the flagged copies out of
3784 // physregs.
3785 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
Chris Lattner6f87d182006-02-22 22:37:12 +00003786 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
Chris Lattner2e56e892006-01-31 02:03:41 +00003787 Value *Ptr = IndirectStoresToEmit[i].second;
Dan Gohman78677932007-06-28 23:29:44 +00003788 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
Chris Lattner6f87d182006-02-22 22:37:12 +00003789 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
Chris Lattner2e56e892006-01-31 02:03:41 +00003790 }
3791
3792 // Emit the non-flagged stores from the physregs.
Chris Lattnerc24a1d32006-08-08 02:23:42 +00003793 SmallVector<SDOperand, 8> OutChains;
Chris Lattner2e56e892006-01-31 02:03:41 +00003794 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
Chris Lattnerd7e3b6c2007-04-28 20:49:53 +00003795 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
Chris Lattner2e56e892006-01-31 02:03:41 +00003796 getValue(StoresToEmit[i].second),
Evan Chengab51cf22006-10-13 21:14:26 +00003797 StoresToEmit[i].second, 0));
Chris Lattner2e56e892006-01-31 02:03:41 +00003798 if (!OutChains.empty())
Chris Lattnerc24a1d32006-08-08 02:23:42 +00003799 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3800 &OutChains[0], OutChains.size());
Chris Lattner476e67b2006-01-26 22:24:51 +00003801 DAG.setRoot(Chain);
3802}
3803
3804
Chris Lattner7a60d912005-01-07 07:47:53 +00003805void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3806 SDOperand Src = getValue(I.getOperand(0));
3807
3808 MVT::ValueType IntPtr = TLI.getPointerTy();
Chris Lattnereccb73d2005-01-22 23:04:37 +00003809
3810 if (IntPtr < Src.getValueType())
3811 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3812 else if (IntPtr > Src.getValueType())
3813 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
Chris Lattner7a60d912005-01-07 07:47:53 +00003814
3815 // Scale the source by the type size.
Duncan Sands44b87212007-11-01 20:53:16 +00003816 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
Chris Lattner7a60d912005-01-07 07:47:53 +00003817 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3818 Src, getIntPtrConstant(ElementSize));
3819
Reid Spencere63b6512006-12-31 05:55:36 +00003820 TargetLowering::ArgListTy Args;
3821 TargetLowering::ArgListEntry Entry;
3822 Entry.Node = Src;
3823 Entry.Ty = TLI.getTargetData()->getIntPtrType();
Reid Spencere63b6512006-12-31 05:55:36 +00003824 Args.push_back(Entry);
Chris Lattner1f45cd72005-01-08 19:26:18 +00003825
3826 std::pair<SDOperand,SDOperand> Result =
Reid Spencere63b6512006-12-31 05:55:36 +00003827 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
Chris Lattner1f45cd72005-01-08 19:26:18 +00003828 DAG.getExternalSymbol("malloc", IntPtr),
3829 Args, DAG);
3830 setValue(&I, Result.first); // Pointers always fit in registers
3831 DAG.setRoot(Result.second);
Chris Lattner7a60d912005-01-07 07:47:53 +00003832}
3833
3834void SelectionDAGLowering::visitFree(FreeInst &I) {
Reid Spencere63b6512006-12-31 05:55:36 +00003835 TargetLowering::ArgListTy Args;
3836 TargetLowering::ArgListEntry Entry;
3837 Entry.Node = getValue(I.getOperand(0));
3838 Entry.Ty = TLI.getTargetData()->getIntPtrType();
Reid Spencere63b6512006-12-31 05:55:36 +00003839 Args.push_back(Entry);
Chris Lattner7a60d912005-01-07 07:47:53 +00003840 MVT::ValueType IntPtr = TLI.getPointerTy();
Chris Lattner1f45cd72005-01-08 19:26:18 +00003841 std::pair<SDOperand,SDOperand> Result =
Reid Spencere63b6512006-12-31 05:55:36 +00003842 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
Chris Lattner1f45cd72005-01-08 19:26:18 +00003843 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3844 DAG.setRoot(Result.second);
Chris Lattner7a60d912005-01-07 07:47:53 +00003845}
3846
Chris Lattner13d7c252005-08-26 20:54:47 +00003847// InsertAtEndOfBasicBlock - This method should be implemented by targets that
3848// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3849// instructions are special in various ways, which require special support to
3850// insert. The specified MachineInstr is created but not inserted into any
3851// basic blocks, and the scheduler passes ownership of it to this method.
3852MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3853 MachineBasicBlock *MBB) {
Bill Wendling22e978a2006-12-07 20:04:42 +00003854 cerr << "If a target marks an instruction with "
3855 << "'usesCustomDAGSchedInserter', it must implement "
3856 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
Chris Lattner13d7c252005-08-26 20:54:47 +00003857 abort();
3858 return 0;
3859}
3860
Chris Lattner58cfd792005-01-09 00:00:49 +00003861void SelectionDAGLowering::visitVAStart(CallInst &I) {
Nate Begemane74795c2006-01-25 18:21:52 +00003862 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3863 getValue(I.getOperand(1)),
3864 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner58cfd792005-01-09 00:00:49 +00003865}
3866
3867void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
Nate Begemane74795c2006-01-25 18:21:52 +00003868 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3869 getValue(I.getOperand(0)),
3870 DAG.getSrcValue(I.getOperand(0)));
3871 setValue(&I, V);
3872 DAG.setRoot(V.getValue(1));
Chris Lattner7a60d912005-01-07 07:47:53 +00003873}
3874
3875void SelectionDAGLowering::visitVAEnd(CallInst &I) {
Nate Begemane74795c2006-01-25 18:21:52 +00003876 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3877 getValue(I.getOperand(1)),
3878 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner7a60d912005-01-07 07:47:53 +00003879}
3880
3881void SelectionDAGLowering::visitVACopy(CallInst &I) {
Nate Begemane74795c2006-01-25 18:21:52 +00003882 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3883 getValue(I.getOperand(1)),
3884 getValue(I.getOperand(2)),
3885 DAG.getSrcValue(I.getOperand(1)),
3886 DAG.getSrcValue(I.getOperand(2))));
Chris Lattner7a60d912005-01-07 07:47:53 +00003887}
3888
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003889/// TargetLowering::LowerArguments - This is the default LowerArguments
3890/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
Chris Lattneraaa23d92006-05-16 22:53:20 +00003891/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3892/// integrated into SDISel.
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003893std::vector<SDOperand>
3894TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
Duncan Sandsad0ea2d2007-11-27 13:23:08 +00003895 const ParamAttrsList *Attrs = F.getParamAttrs();
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003896 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3897 std::vector<SDOperand> Ops;
Chris Lattner3d826992006-05-16 06:45:34 +00003898 Ops.push_back(DAG.getRoot());
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003899 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3900 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3901
3902 // Add one result value for each formal argument.
3903 std::vector<MVT::ValueType> RetVals;
Anton Korobeynikov06f7d4b2007-01-28 18:01:49 +00003904 unsigned j = 1;
Anton Korobeynikov9fa38392007-01-28 16:04:40 +00003905 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3906 I != E; ++I, ++j) {
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003907 MVT::ValueType VT = getValueType(I->getType());
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00003908 unsigned Flags = ISD::ParamFlags::NoFlagSet;
Lauro Ramos Venancio9956dcf2007-02-13 13:50:08 +00003909 unsigned OriginalAlignment =
Chris Lattner945e4372007-02-14 05:52:17 +00003910 getTargetData()->getABITypeAlignment(I->getType());
Lauro Ramos Venancio9956dcf2007-02-13 13:50:08 +00003911
Chris Lattnerab5d0ac2007-02-26 02:56:58 +00003912 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3913 // that is zero extended!
Reid Spencera472f662007-04-11 02:44:20 +00003914 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt))
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00003915 Flags &= ~(ISD::ParamFlags::SExt);
Reid Spencera472f662007-04-11 02:44:20 +00003916 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt))
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00003917 Flags |= ISD::ParamFlags::SExt;
Reid Spencera472f662007-04-11 02:44:20 +00003918 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg))
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00003919 Flags |= ISD::ParamFlags::InReg;
Reid Spencera472f662007-04-11 02:44:20 +00003920 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00003921 Flags |= ISD::ParamFlags::StructReturn;
Rafael Espindola66011c12007-08-10 14:44:42 +00003922 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) {
Rafael Espindolab567e3f2007-07-06 10:57:03 +00003923 Flags |= ISD::ParamFlags::ByVal;
Rafael Espindola66011c12007-08-10 14:44:42 +00003924 const PointerType *Ty = cast<PointerType>(I->getType());
3925 const StructType *STy = cast<StructType>(Ty->getElementType());
Rafael Espindola1de0c862007-09-07 14:52:14 +00003926 unsigned StructAlign =
3927 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy));
Duncan Sands44b87212007-11-01 20:53:16 +00003928 unsigned StructSize = getTargetData()->getABITypeSize(STy);
Rafael Espindola66011c12007-08-10 14:44:42 +00003929 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
3930 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
3931 }
Duncan Sands644f9172007-07-27 12:58:54 +00003932 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest))
3933 Flags |= ISD::ParamFlags::Nest;
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00003934 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
Chris Lattnerab5d0ac2007-02-26 02:56:58 +00003935
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003936 switch (getTypeAction(VT)) {
3937 default: assert(0 && "Unknown type action!");
3938 case Legal:
3939 RetVals.push_back(VT);
Anton Korobeynikov037c8672007-01-28 13:31:35 +00003940 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003941 break;
3942 case Promote:
3943 RetVals.push_back(getTypeToTransformTo(VT));
Anton Korobeynikov037c8672007-01-28 13:31:35 +00003944 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003945 break;
Dan Gohman78677932007-06-28 23:29:44 +00003946 case Expand: {
3947 // If this is an illegal type, it needs to be broken up to fit into
3948 // registers.
3949 MVT::ValueType RegisterVT = getRegisterType(VT);
3950 unsigned NumRegs = getNumRegisters(VT);
3951 for (unsigned i = 0; i != NumRegs; ++i) {
3952 RetVals.push_back(RegisterVT);
3953 // if it isn't first piece, alignment must be 1
3954 if (i > 0)
3955 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3956 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3957 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003958 }
3959 break;
3960 }
Dan Gohman78677932007-06-28 23:29:44 +00003961 }
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003962 }
Evan Cheng9618df12006-04-25 23:03:35 +00003963
Chris Lattner3d826992006-05-16 06:45:34 +00003964 RetVals.push_back(MVT::Other);
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003965
3966 // Create the node.
Chris Lattnerbd887772006-08-14 23:53:35 +00003967 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3968 DAG.getNodeValueTypes(RetVals), RetVals.size(),
Chris Lattnerc24a1d32006-08-08 02:23:42 +00003969 &Ops[0], Ops.size()).Val;
Dan Gohman533dd162007-07-02 16:18:06 +00003970 unsigned NumArgRegs = Result->getNumValues() - 1;
3971 DAG.setRoot(SDOperand(Result, NumArgRegs));
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003972
3973 // Set up the return result vector.
3974 Ops.clear();
3975 unsigned i = 0;
Reid Spencere63b6512006-12-31 05:55:36 +00003976 unsigned Idx = 1;
3977 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3978 ++I, ++Idx) {
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003979 MVT::ValueType VT = getValueType(I->getType());
3980
3981 switch (getTypeAction(VT)) {
3982 default: assert(0 && "Unknown type action!");
3983 case Legal:
3984 Ops.push_back(SDOperand(Result, i++));
3985 break;
3986 case Promote: {
3987 SDOperand Op(Result, i++);
3988 if (MVT::isInteger(VT)) {
Reid Spencera472f662007-04-11 02:44:20 +00003989 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt))
Chris Lattner96035be2007-01-04 22:22:37 +00003990 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3991 DAG.getValueType(VT));
Reid Spencera472f662007-04-11 02:44:20 +00003992 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt))
Chris Lattner96035be2007-01-04 22:22:37 +00003993 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3994 DAG.getValueType(VT));
Chris Lattnerd3b504a2006-04-12 16:20:43 +00003995 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3996 } else {
3997 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3998 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3999 }
4000 Ops.push_back(Op);
4001 break;
4002 }
Dan Gohman533dd162007-07-02 16:18:06 +00004003 case Expand: {
4004 MVT::ValueType PartVT = getRegisterType(VT);
4005 unsigned NumParts = getNumRegisters(VT);
4006 SmallVector<SDOperand, 4> Parts(NumParts);
4007 for (unsigned j = 0; j != NumParts; ++j)
4008 Parts[j] = SDOperand(Result, i++);
Dan Gohmanf8f531b2007-07-09 20:59:04 +00004009 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
Chris Lattnerd3b504a2006-04-12 16:20:43 +00004010 break;
4011 }
Dan Gohman533dd162007-07-02 16:18:06 +00004012 }
Chris Lattnerd3b504a2006-04-12 16:20:43 +00004013 }
Dan Gohman533dd162007-07-02 16:18:06 +00004014 assert(i == NumArgRegs && "Argument register count mismatch!");
Chris Lattnerd3b504a2006-04-12 16:20:43 +00004015 return Ops;
4016}
4017
Chris Lattneraaa23d92006-05-16 22:53:20 +00004018
4019/// TargetLowering::LowerCallTo - This is the default LowerCallTo
4020/// implementation, which just inserts an ISD::CALL node, which is later custom
4021/// lowered by the target to something concrete. FIXME: When all targets are
4022/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4023std::pair<SDOperand, SDOperand>
Reid Spencere63b6512006-12-31 05:55:36 +00004024TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4025 bool RetTyIsSigned, bool isVarArg,
Chris Lattneraaa23d92006-05-16 22:53:20 +00004026 unsigned CallingConv, bool isTailCall,
4027 SDOperand Callee,
4028 ArgListTy &Args, SelectionDAG &DAG) {
Chris Lattner65879ca2006-08-16 22:57:46 +00004029 SmallVector<SDOperand, 32> Ops;
Chris Lattneraaa23d92006-05-16 22:53:20 +00004030 Ops.push_back(Chain); // Op#0 - Chain
4031 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4032 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4033 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4034 Ops.push_back(Callee);
4035
4036 // Handle all of the outgoing arguments.
4037 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
Reid Spencere63b6512006-12-31 05:55:36 +00004038 MVT::ValueType VT = getValueType(Args[i].Ty);
4039 SDOperand Op = Args[i].Node;
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00004040 unsigned Flags = ISD::ParamFlags::NoFlagSet;
Lauro Ramos Venancio9956dcf2007-02-13 13:50:08 +00004041 unsigned OriginalAlignment =
Chris Lattner945e4372007-02-14 05:52:17 +00004042 getTargetData()->getABITypeAlignment(Args[i].Ty);
Anton Korobeynikovf0b93162007-03-06 06:10:33 +00004043
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00004044 if (Args[i].isSExt)
4045 Flags |= ISD::ParamFlags::SExt;
4046 if (Args[i].isZExt)
4047 Flags |= ISD::ParamFlags::ZExt;
Anton Korobeynikovf0b93162007-03-06 06:10:33 +00004048 if (Args[i].isInReg)
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00004049 Flags |= ISD::ParamFlags::InReg;
Anton Korobeynikovf0b93162007-03-06 06:10:33 +00004050 if (Args[i].isSRet)
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00004051 Flags |= ISD::ParamFlags::StructReturn;
Rafael Espindola9c3d20d2007-08-20 15:18:24 +00004052 if (Args[i].isByVal) {
4053 Flags |= ISD::ParamFlags::ByVal;
4054 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4055 const StructType *STy = cast<StructType>(Ty->getElementType());
Rafael Espindola1de0c862007-09-07 14:52:14 +00004056 unsigned StructAlign =
4057 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy));
Duncan Sands44b87212007-11-01 20:53:16 +00004058 unsigned StructSize = getTargetData()->getABITypeSize(STy);
Rafael Espindola9c3d20d2007-08-20 15:18:24 +00004059 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
4060 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
4061 }
Duncan Sands644f9172007-07-27 12:58:54 +00004062 if (Args[i].isNest)
4063 Flags |= ISD::ParamFlags::Nest;
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00004064 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
Anton Korobeynikovf0b93162007-03-06 06:10:33 +00004065
Chris Lattneraaa23d92006-05-16 22:53:20 +00004066 switch (getTypeAction(VT)) {
4067 default: assert(0 && "Unknown type action!");
Lauro Ramos Venancio9956dcf2007-02-13 13:50:08 +00004068 case Legal:
Chris Lattneraaa23d92006-05-16 22:53:20 +00004069 Ops.push_back(Op);
Anton Korobeynikov037c8672007-01-28 13:31:35 +00004070 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattneraaa23d92006-05-16 22:53:20 +00004071 break;
4072 case Promote:
4073 if (MVT::isInteger(VT)) {
Anton Korobeynikoved4b3032007-03-07 16:25:09 +00004074 unsigned ExtOp;
4075 if (Args[i].isSExt)
4076 ExtOp = ISD::SIGN_EXTEND;
4077 else if (Args[i].isZExt)
4078 ExtOp = ISD::ZERO_EXTEND;
4079 else
4080 ExtOp = ISD::ANY_EXTEND;
Chris Lattneraaa23d92006-05-16 22:53:20 +00004081 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4082 } else {
4083 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
Dale Johannesena2b3c172007-07-03 00:53:03 +00004084 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
Chris Lattneraaa23d92006-05-16 22:53:20 +00004085 }
4086 Ops.push_back(Op);
Anton Korobeynikov037c8672007-01-28 13:31:35 +00004087 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattneraaa23d92006-05-16 22:53:20 +00004088 break;
Dan Gohman533dd162007-07-02 16:18:06 +00004089 case Expand: {
4090 MVT::ValueType PartVT = getRegisterType(VT);
4091 unsigned NumParts = getNumRegisters(VT);
4092 SmallVector<SDOperand, 4> Parts(NumParts);
Dan Gohmanf8f531b2007-07-09 20:59:04 +00004093 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
Dan Gohman533dd162007-07-02 16:18:06 +00004094 for (unsigned i = 0; i != NumParts; ++i) {
4095 // if it isn't first piece, alignment must be 1
4096 unsigned MyFlags = Flags;
4097 if (i != 0)
4098 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4099 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4100
4101 Ops.push_back(Parts[i]);
4102 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
Chris Lattneraaa23d92006-05-16 22:53:20 +00004103 }
4104 break;
4105 }
Dan Gohman533dd162007-07-02 16:18:06 +00004106 }
Chris Lattneraaa23d92006-05-16 22:53:20 +00004107 }
4108
4109 // Figure out the result value types.
Dan Gohman78677932007-06-28 23:29:44 +00004110 MVT::ValueType VT = getValueType(RetTy);
4111 MVT::ValueType RegisterVT = getRegisterType(VT);
4112 unsigned NumRegs = getNumRegisters(VT);
4113 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4114 for (unsigned i = 0; i != NumRegs; ++i)
4115 RetTys[i] = RegisterVT;
Chris Lattneraaa23d92006-05-16 22:53:20 +00004116
4117 RetTys.push_back(MVT::Other); // Always has a chain.
4118
Dan Gohman78677932007-06-28 23:29:44 +00004119 // Create the CALL node.
Chris Lattner65879ca2006-08-16 22:57:46 +00004120 SDOperand Res = DAG.getNode(ISD::CALL,
Dan Gohman78677932007-06-28 23:29:44 +00004121 DAG.getVTList(&RetTys[0], NumRegs + 1),
Chris Lattner65879ca2006-08-16 22:57:46 +00004122 &Ops[0], Ops.size());
Chris Lattner3ffe7182007-08-02 18:08:16 +00004123 Chain = Res.getValue(NumRegs);
Dan Gohman78677932007-06-28 23:29:44 +00004124
4125 // Gather up the call result into a single value.
4126 if (RetTy != Type::VoidTy) {
4127 ISD::NodeType AssertOp = ISD::AssertSext;
4128 if (!RetTyIsSigned)
4129 AssertOp = ISD::AssertZext;
4130 SmallVector<SDOperand, 4> Results(NumRegs);
4131 for (unsigned i = 0; i != NumRegs; ++i)
4132 Results[i] = Res.getValue(i);
Dan Gohmanf8f531b2007-07-09 20:59:04 +00004133 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
Chris Lattneraaa23d92006-05-16 22:53:20 +00004134 }
Dan Gohman78677932007-06-28 23:29:44 +00004135
4136 return std::make_pair(Res, Chain);
Chris Lattneraaa23d92006-05-16 22:53:20 +00004137}
4138
Chris Lattner29dcc712005-05-14 05:50:48 +00004139SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner897cd7d2005-01-16 07:28:41 +00004140 assert(0 && "LowerOperation not implemented for this target!");
4141 abort();
Misha Brukman73e929f2005-02-17 21:39:27 +00004142 return SDOperand();
Chris Lattner897cd7d2005-01-16 07:28:41 +00004143}
4144
Nate Begeman595ec732006-01-28 03:14:31 +00004145SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4146 SelectionDAG &DAG) {
4147 assert(0 && "CustomPromoteOperation not implemented for this target!");
4148 abort();
4149 return SDOperand();
4150}
4151
Evan Cheng6781b6e2006-02-15 21:59:04 +00004152/// getMemsetValue - Vectorized representation of the memset value
Evan Cheng81fcea82006-02-14 08:22:34 +00004153/// operand.
4154static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
Evan Cheng93e48652006-02-15 22:12:35 +00004155 SelectionDAG &DAG) {
Evan Cheng81fcea82006-02-14 08:22:34 +00004156 MVT::ValueType CurVT = VT;
4157 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4158 uint64_t Val = C->getValue() & 255;
4159 unsigned Shift = 8;
4160 while (CurVT != MVT::i8) {
4161 Val = (Val << Shift) | Val;
4162 Shift <<= 1;
4163 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
Evan Cheng81fcea82006-02-14 08:22:34 +00004164 }
4165 return DAG.getConstant(Val, VT);
4166 } else {
4167 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4168 unsigned Shift = 8;
4169 while (CurVT != MVT::i8) {
4170 Value =
4171 DAG.getNode(ISD::OR, VT,
4172 DAG.getNode(ISD::SHL, VT, Value,
4173 DAG.getConstant(Shift, MVT::i8)), Value);
4174 Shift <<= 1;
4175 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
Evan Cheng81fcea82006-02-14 08:22:34 +00004176 }
4177
4178 return Value;
4179 }
4180}
4181
Evan Cheng6781b6e2006-02-15 21:59:04 +00004182/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4183/// used when a memcpy is turned into a memset when the source is a constant
4184/// string ptr.
4185static SDOperand getMemsetStringVal(MVT::ValueType VT,
4186 SelectionDAG &DAG, TargetLowering &TLI,
4187 std::string &Str, unsigned Offset) {
Evan Cheng6781b6e2006-02-15 21:59:04 +00004188 uint64_t Val = 0;
Dan Gohman1796f1f2007-05-18 17:52:13 +00004189 unsigned MSB = MVT::getSizeInBits(VT) / 8;
Evan Cheng6781b6e2006-02-15 21:59:04 +00004190 if (TLI.isLittleEndian())
4191 Offset = Offset + MSB - 1;
4192 for (unsigned i = 0; i != MSB; ++i) {
Evan Cheng6e12a052006-11-29 01:38:07 +00004193 Val = (Val << 8) | (unsigned char)Str[Offset];
Evan Cheng6781b6e2006-02-15 21:59:04 +00004194 Offset += TLI.isLittleEndian() ? -1 : 1;
4195 }
4196 return DAG.getConstant(Val, VT);
4197}
4198
Evan Cheng81fcea82006-02-14 08:22:34 +00004199/// getMemBasePlusOffset - Returns base and offset node for the
4200static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4201 SelectionDAG &DAG, TargetLowering &TLI) {
4202 MVT::ValueType VT = Base.getValueType();
4203 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4204}
4205
Evan Chengdb2a7a72006-02-14 20:12:38 +00004206/// MeetsMaxMemopRequirement - Determines if the number of memory ops required
Evan Chengd5026102006-02-14 09:11:59 +00004207/// to replace the memset / memcpy is below the threshold. It also returns the
4208/// types of the sequence of memory ops to perform memset / memcpy.
Evan Chengdb2a7a72006-02-14 20:12:38 +00004209static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4210 unsigned Limit, uint64_t Size,
4211 unsigned Align, TargetLowering &TLI) {
Evan Cheng81fcea82006-02-14 08:22:34 +00004212 MVT::ValueType VT;
4213
4214 if (TLI.allowsUnalignedMemoryAccesses()) {
4215 VT = MVT::i64;
4216 } else {
4217 switch (Align & 7) {
4218 case 0:
4219 VT = MVT::i64;
4220 break;
4221 case 4:
4222 VT = MVT::i32;
4223 break;
4224 case 2:
4225 VT = MVT::i16;
4226 break;
4227 default:
4228 VT = MVT::i8;
4229 break;
4230 }
4231 }
4232
Evan Chengd5026102006-02-14 09:11:59 +00004233 MVT::ValueType LVT = MVT::i64;
4234 while (!TLI.isTypeLegal(LVT))
4235 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4236 assert(MVT::isInteger(LVT));
Evan Cheng81fcea82006-02-14 08:22:34 +00004237
Evan Chengd5026102006-02-14 09:11:59 +00004238 if (VT > LVT)
4239 VT = LVT;
4240
Evan Cheng04514992006-02-14 23:05:54 +00004241 unsigned NumMemOps = 0;
Evan Cheng81fcea82006-02-14 08:22:34 +00004242 while (Size != 0) {
Dan Gohman1796f1f2007-05-18 17:52:13 +00004243 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
Evan Cheng81fcea82006-02-14 08:22:34 +00004244 while (VTSize > Size) {
4245 VT = (MVT::ValueType)((unsigned)VT - 1);
Evan Cheng81fcea82006-02-14 08:22:34 +00004246 VTSize >>= 1;
4247 }
Evan Chengd5026102006-02-14 09:11:59 +00004248 assert(MVT::isInteger(VT));
4249
4250 if (++NumMemOps > Limit)
4251 return false;
Evan Cheng81fcea82006-02-14 08:22:34 +00004252 MemOps.push_back(VT);
4253 Size -= VTSize;
4254 }
Evan Chengd5026102006-02-14 09:11:59 +00004255
4256 return true;
Evan Cheng81fcea82006-02-14 08:22:34 +00004257}
4258
Chris Lattner875def92005-01-11 05:56:49 +00004259void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
Evan Cheng81fcea82006-02-14 08:22:34 +00004260 SDOperand Op1 = getValue(I.getOperand(1));
4261 SDOperand Op2 = getValue(I.getOperand(2));
4262 SDOperand Op3 = getValue(I.getOperand(3));
4263 SDOperand Op4 = getValue(I.getOperand(4));
4264 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4265 if (Align == 0) Align = 1;
4266
Dan Gohman8dc0b932007-08-27 16:26:13 +00004267 // If the source and destination are known to not be aliases, we can
4268 // lower memmove as memcpy.
4269 if (Op == ISD::MEMMOVE) {
Anton Korobeynikov122bf4b2007-09-07 11:39:35 +00004270 uint64_t Size = -1ULL;
Dan Gohman8dc0b932007-08-27 16:26:13 +00004271 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4272 Size = C->getValue();
4273 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4274 AliasAnalysis::NoAlias)
4275 Op = ISD::MEMCPY;
4276 }
4277
Evan Cheng81fcea82006-02-14 08:22:34 +00004278 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4279 std::vector<MVT::ValueType> MemOps;
Evan Cheng81fcea82006-02-14 08:22:34 +00004280
4281 // Expand memset / memcpy to a series of load / store ops
4282 // if the size operand falls below a certain threshold.
Chris Lattnerc24a1d32006-08-08 02:23:42 +00004283 SmallVector<SDOperand, 8> OutChains;
Evan Cheng81fcea82006-02-14 08:22:34 +00004284 switch (Op) {
Evan Cheng038521e2006-02-14 19:45:56 +00004285 default: break; // Do nothing for now.
Evan Cheng81fcea82006-02-14 08:22:34 +00004286 case ISD::MEMSET: {
Evan Chengdb2a7a72006-02-14 20:12:38 +00004287 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4288 Size->getValue(), Align, TLI)) {
Evan Chengd5026102006-02-14 09:11:59 +00004289 unsigned NumMemOps = MemOps.size();
Evan Cheng81fcea82006-02-14 08:22:34 +00004290 unsigned Offset = 0;
4291 for (unsigned i = 0; i < NumMemOps; i++) {
4292 MVT::ValueType VT = MemOps[i];
Dan Gohman1796f1f2007-05-18 17:52:13 +00004293 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
Evan Cheng93e48652006-02-15 22:12:35 +00004294 SDOperand Value = getMemsetValue(Op2, VT, DAG);
Evan Chengdf9ac472006-10-05 23:01:46 +00004295 SDOperand Store = DAG.getStore(getRoot(), Value,
Chris Lattner6f87d182006-02-22 22:37:12 +00004296 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
Evan Chengab51cf22006-10-13 21:14:26 +00004297 I.getOperand(1), Offset);
Evan Chenge2038bd2006-02-15 01:54:51 +00004298 OutChains.push_back(Store);
Evan Cheng81fcea82006-02-14 08:22:34 +00004299 Offset += VTSize;
4300 }
Evan Cheng81fcea82006-02-14 08:22:34 +00004301 }
Evan Chenge2038bd2006-02-15 01:54:51 +00004302 break;
Evan Cheng81fcea82006-02-14 08:22:34 +00004303 }
Evan Chenge2038bd2006-02-15 01:54:51 +00004304 case ISD::MEMCPY: {
4305 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4306 Size->getValue(), Align, TLI)) {
4307 unsigned NumMemOps = MemOps.size();
Evan Chengc3dcf5a2006-02-16 23:11:42 +00004308 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
Evan Cheng6781b6e2006-02-15 21:59:04 +00004309 GlobalAddressSDNode *G = NULL;
4310 std::string Str;
Evan Chengc3dcf5a2006-02-16 23:11:42 +00004311 bool CopyFromStr = false;
Evan Cheng6781b6e2006-02-15 21:59:04 +00004312
4313 if (Op2.getOpcode() == ISD::GlobalAddress)
4314 G = cast<GlobalAddressSDNode>(Op2);
4315 else if (Op2.getOpcode() == ISD::ADD &&
4316 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4317 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4318 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
Evan Chengc3dcf5a2006-02-16 23:11:42 +00004319 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
Evan Cheng6781b6e2006-02-15 21:59:04 +00004320 }
4321 if (G) {
4322 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
Evan Chengfeba5072006-11-29 01:58:12 +00004323 if (GV && GV->isConstant()) {
Evan Cheng38280c02006-03-10 23:52:03 +00004324 Str = GV->getStringValue(false);
Evan Chengc3dcf5a2006-02-16 23:11:42 +00004325 if (!Str.empty()) {
4326 CopyFromStr = true;
4327 SrcOff += SrcDelta;
4328 }
4329 }
Evan Cheng6781b6e2006-02-15 21:59:04 +00004330 }
4331
Evan Chenge2038bd2006-02-15 01:54:51 +00004332 for (unsigned i = 0; i < NumMemOps; i++) {
4333 MVT::ValueType VT = MemOps[i];
Dan Gohman1796f1f2007-05-18 17:52:13 +00004334 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
Evan Cheng6781b6e2006-02-15 21:59:04 +00004335 SDOperand Value, Chain, Store;
4336
Evan Chengc3dcf5a2006-02-16 23:11:42 +00004337 if (CopyFromStr) {
Evan Cheng6781b6e2006-02-15 21:59:04 +00004338 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4339 Chain = getRoot();
4340 Store =
Evan Chengdf9ac472006-10-05 23:01:46 +00004341 DAG.getStore(Chain, Value,
4342 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
Evan Chengab51cf22006-10-13 21:14:26 +00004343 I.getOperand(1), DstOff);
Evan Cheng6781b6e2006-02-15 21:59:04 +00004344 } else {
4345 Value = DAG.getLoad(VT, getRoot(),
Bill Wendling6d15b322007-10-26 20:24:42 +00004346 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4347 I.getOperand(2), SrcOff, false, Align);
Evan Cheng6781b6e2006-02-15 21:59:04 +00004348 Chain = Value.getValue(1);
4349 Store =
Evan Chengdf9ac472006-10-05 23:01:46 +00004350 DAG.getStore(Chain, Value,
4351 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
Bill Wendling6d15b322007-10-26 20:24:42 +00004352 I.getOperand(1), DstOff, false, Align);
Evan Cheng6781b6e2006-02-15 21:59:04 +00004353 }
Evan Chenge2038bd2006-02-15 01:54:51 +00004354 OutChains.push_back(Store);
Evan Cheng6781b6e2006-02-15 21:59:04 +00004355 SrcOff += VTSize;
4356 DstOff += VTSize;
Evan Chenge2038bd2006-02-15 01:54:51 +00004357 }
4358 }
4359 break;
4360 }
4361 }
4362
4363 if (!OutChains.empty()) {
Chris Lattnerc24a1d32006-08-08 02:23:42 +00004364 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4365 &OutChains[0], OutChains.size()));
Evan Chenge2038bd2006-02-15 01:54:51 +00004366 return;
Evan Cheng81fcea82006-02-14 08:22:34 +00004367 }
4368 }
4369
Rafael Espindola846c19dd2007-10-19 10:41:11 +00004370 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4371 SDOperand Node;
4372 switch(Op) {
4373 default:
4374 assert(0 && "Unknown Op");
4375 case ISD::MEMCPY:
4376 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4377 break;
4378 case ISD::MEMMOVE:
4379 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4380 break;
4381 case ISD::MEMSET:
4382 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4383 break;
4384 }
4385 DAG.setRoot(Node);
Chris Lattner7a60d912005-01-07 07:47:53 +00004386}
4387
Chris Lattner875def92005-01-11 05:56:49 +00004388//===----------------------------------------------------------------------===//
4389// SelectionDAGISel code
4390//===----------------------------------------------------------------------===//
Chris Lattner7a60d912005-01-07 07:47:53 +00004391
4392unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4393 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4394}
4395
Chris Lattnerc9950c12005-08-17 06:37:43 +00004396void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
Jim Laskeydcb2b832006-10-16 20:52:31 +00004397 AU.addRequired<AliasAnalysis>();
Chris Lattnerf6a6d3c2007-03-31 04:18:03 +00004398 AU.setPreservesAll();
Chris Lattnerc9950c12005-08-17 06:37:43 +00004399}
Chris Lattner7a60d912005-01-07 07:47:53 +00004400
Chris Lattner35397782005-12-05 07:10:48 +00004401
Chris Lattnerbba52192006-10-28 19:22:10 +00004402
Chris Lattner7a60d912005-01-07 07:47:53 +00004403bool SelectionDAGISel::runOnFunction(Function &Fn) {
Dan Gohman8dc0b932007-08-27 16:26:13 +00004404 // Get alias analysis for load/store combining.
4405 AA = &getAnalysis<AliasAnalysis>();
4406
Chris Lattner7a60d912005-01-07 07:47:53 +00004407 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4408 RegMap = MF.getSSARegMap();
Bill Wendling22e978a2006-12-07 20:04:42 +00004409 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
Chris Lattner7a60d912005-01-07 07:47:53 +00004410
4411 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4412
Duncan Sands74137362007-06-13 16:53:21 +00004413 if (ExceptionHandling)
4414 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4415 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4416 // Mark landing pad.
4417 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
Duncan Sands61166502007-06-06 10:05:18 +00004418
4419 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
Chris Lattner7a60d912005-01-07 07:47:53 +00004420 SelectBasicBlock(I, MF, FuncInfo);
Misha Brukman835702a2005-04-21 22:36:52 +00004421
Evan Cheng276b44b2007-02-10 02:43:39 +00004422 // Add function live-ins to entry block live-in set.
4423 BasicBlock *EntryBB = &Fn.getEntryBlock();
4424 BB = FuncInfo.MBBMap[EntryBB];
4425 if (!MF.livein_empty())
4426 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4427 E = MF.livein_end(); I != E; ++I)
4428 BB->addLiveIn(I->first);
4429
Duncan Sands92bf2c62007-06-15 19:04:19 +00004430#ifndef NDEBUG
4431 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4432 "Not all catch info was assigned to a landing pad!");
4433#endif
4434
Chris Lattner7a60d912005-01-07 07:47:53 +00004435 return true;
4436}
4437
Chris Lattnered0110b2006-10-27 21:36:01 +00004438SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4439 unsigned Reg) {
4440 SDOperand Op = getValue(V);
Chris Lattnere727af02005-01-13 20:50:02 +00004441 assert((Op.getOpcode() != ISD::CopyFromReg ||
Chris Lattner33182322005-08-16 21:55:35 +00004442 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
Chris Lattnere727af02005-01-13 20:50:02 +00004443 "Copy from a reg to the same reg!");
Chris Lattner33182322005-08-16 21:55:35 +00004444
Chris Lattner33182322005-08-16 21:55:35 +00004445 MVT::ValueType SrcVT = Op.getValueType();
Dan Gohman78677932007-06-28 23:29:44 +00004446 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4447 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4448 SmallVector<SDOperand, 8> Regs(NumRegs);
4449 SmallVector<SDOperand, 8> Chains(NumRegs);
4450
4451 // Copy the value by legal parts into sequential virtual registers.
Dan Gohmanf8f531b2007-07-09 20:59:04 +00004452 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
Dan Gohman533dd162007-07-02 16:18:06 +00004453 for (unsigned i = 0; i != NumRegs; ++i)
Dan Gohman78677932007-06-28 23:29:44 +00004454 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4455 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
Chris Lattner7a60d912005-01-07 07:47:53 +00004456}
4457
Chris Lattner16f64df2005-01-17 17:15:02 +00004458void SelectionDAGISel::
Evan Chengde608342007-02-10 01:08:18 +00004459LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
Chris Lattner16f64df2005-01-17 17:15:02 +00004460 std::vector<SDOperand> &UnorderedChains) {
4461 // If this is the entry block, emit arguments.
Evan Chengde608342007-02-10 01:08:18 +00004462 Function &F = *LLVMBB->getParent();
Chris Lattnere3c2cf42005-01-17 17:55:19 +00004463 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
Chris Lattner6871b232005-10-30 19:42:35 +00004464 SDOperand OldRoot = SDL.DAG.getRoot();
4465 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
Chris Lattner16f64df2005-01-17 17:15:02 +00004466
Chris Lattner6871b232005-10-30 19:42:35 +00004467 unsigned a = 0;
4468 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4469 AI != E; ++AI, ++a)
4470 if (!AI->use_empty()) {
4471 SDL.setValue(AI, Args[a]);
Evan Cheng3784f3c52006-04-27 08:29:42 +00004472
Chris Lattner6871b232005-10-30 19:42:35 +00004473 // If this argument is live outside of the entry block, insert a copy from
4474 // whereever we got it to the vreg that other BB's will reference it as.
Chris Lattner8c504cf2007-02-25 18:40:32 +00004475 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4476 if (VMI != FuncInfo.ValueMap.end()) {
4477 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
Chris Lattner6871b232005-10-30 19:42:35 +00004478 UnorderedChains.push_back(Copy);
4479 }
Chris Lattnere3c2cf42005-01-17 17:55:19 +00004480 }
Chris Lattner6871b232005-10-30 19:42:35 +00004481
Chris Lattner6871b232005-10-30 19:42:35 +00004482 // Finally, if the target has anything special to do, allow it to do so.
Chris Lattner957cb672006-05-16 06:10:58 +00004483 // FIXME: this should insert code into the DAG!
Chris Lattner6871b232005-10-30 19:42:35 +00004484 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
Chris Lattner16f64df2005-01-17 17:15:02 +00004485}
4486
Duncan Sands92bf2c62007-06-15 19:04:19 +00004487static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4488 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
Duncan Sands92bf2c62007-06-15 19:04:19 +00004489 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
Duncan Sandsfe806382007-07-04 20:52:51 +00004490 if (isSelector(I)) {
Duncan Sands92bf2c62007-06-15 19:04:19 +00004491 // Apply the catch info to DestBB.
4492 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4493#ifndef NDEBUG
Duncan Sandsd4494352007-11-15 09:54:37 +00004494 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4495 FLI.CatchInfoFound.insert(I);
Duncan Sands92bf2c62007-06-15 19:04:19 +00004496#endif
4497 }
4498}
4499
Arnold Schwaighofer9ccea992007-10-11 19:40:01 +00004500/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
Arnold Schwaighofer1f0da1f2007-10-12 21:30:57 +00004501/// DAG and fixes their tailcall attribute operand.
Arnold Schwaighofer9ccea992007-10-11 19:40:01 +00004502static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4503 TargetLowering& TLI) {
4504 SDNode * Ret = NULL;
4505 SDOperand Terminator = DAG.getRoot();
4506
4507 // Find RET node.
4508 if (Terminator.getOpcode() == ISD::RET) {
4509 Ret = Terminator.Val;
4510 }
4511
4512 // Fix tail call attribute of CALL nodes.
4513 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4514 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4515 if (BI->getOpcode() == ISD::CALL) {
4516 SDOperand OpRet(Ret, 0);
4517 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4518 bool isMarkedTailCall =
4519 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4520 // If CALL node has tail call attribute set to true and the call is not
4521 // eligible (no RET or the target rejects) the attribute is fixed to
Arnold Schwaighofer1f0da1f2007-10-12 21:30:57 +00004522 // false. The TargetLowering::IsEligibleForTailCallOptimization function
Arnold Schwaighofer9ccea992007-10-11 19:40:01 +00004523 // must correctly identify tail call optimizable calls.
4524 if (isMarkedTailCall &&
4525 (Ret==NULL ||
4526 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4527 SmallVector<SDOperand, 32> Ops;
4528 unsigned idx=0;
4529 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4530 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4531 if (idx!=3)
4532 Ops.push_back(*I);
4533 else
4534 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4535 }
4536 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4537 }
4538 }
4539 }
4540}
4541
Chris Lattner7a60d912005-01-07 07:47:53 +00004542void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4543 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
Nate Begemaned728c12006-03-27 01:32:24 +00004544 FunctionLoweringInfo &FuncInfo) {
Dan Gohman8dc0b932007-08-27 16:26:13 +00004545 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo);
Chris Lattner718b5c22005-01-13 17:59:43 +00004546
4547 std::vector<SDOperand> UnorderedChains;
Misha Brukman835702a2005-04-21 22:36:52 +00004548
Chris Lattner6871b232005-10-30 19:42:35 +00004549 // Lower any arguments needed in this block if this is the entry block.
Dan Gohmandcb291f2007-03-22 16:38:57 +00004550 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
Chris Lattner6871b232005-10-30 19:42:35 +00004551 LowerArguments(LLVMBB, SDL, UnorderedChains);
Chris Lattner7a60d912005-01-07 07:47:53 +00004552
4553 BB = FuncInfo.MBBMap[LLVMBB];
4554 SDL.setCurrentBasicBlock(BB);
4555
Duncan Sands92bf2c62007-06-15 19:04:19 +00004556 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Duncan Sands61166502007-06-06 10:05:18 +00004557
Duncan Sands92bf2c62007-06-15 19:04:19 +00004558 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4559 // Add a label to mark the beginning of the landing pad. Deletion of the
4560 // landing pad can thus be detected via the MachineModuleInfo.
4561 unsigned LabelID = MMI->addLandingPad(BB);
4562 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4563 DAG.getConstant(LabelID, MVT::i32)));
4564
Evan Cheng77f541d2007-06-27 18:45:32 +00004565 // Mark exception register as live in.
4566 unsigned Reg = TLI.getExceptionAddressRegister();
4567 if (Reg) BB->addLiveIn(Reg);
4568
4569 // Mark exception selector register as live in.
4570 Reg = TLI.getExceptionSelectorRegister();
4571 if (Reg) BB->addLiveIn(Reg);
4572
Duncan Sands92bf2c62007-06-15 19:04:19 +00004573 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4574 // function and list of typeids logically belong to the invoke (or, if you
4575 // like, the basic block containing the invoke), and need to be associated
4576 // with it in the dwarf exception handling tables. Currently however the
Duncan Sandsfe806382007-07-04 20:52:51 +00004577 // information is provided by an intrinsic (eh.selector) that can be moved
4578 // to unexpected places by the optimizers: if the unwind edge is critical,
4579 // then breaking it can result in the intrinsics being in the successor of
4580 // the landing pad, not the landing pad itself. This results in exceptions
4581 // not being caught because no typeids are associated with the invoke.
4582 // This may not be the only way things can go wrong, but it is the only way
4583 // we try to work around for the moment.
Duncan Sands92bf2c62007-06-15 19:04:19 +00004584 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4585
4586 if (Br && Br->isUnconditional()) { // Critical edge?
4587 BasicBlock::iterator I, E;
4588 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
Duncan Sandsfe806382007-07-04 20:52:51 +00004589 if (isSelector(I))
Duncan Sands92bf2c62007-06-15 19:04:19 +00004590 break;
4591
4592 if (I == E)
4593 // No catch info found - try to extract some from the successor.
4594 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
Duncan Sands61166502007-06-06 10:05:18 +00004595 }
4596 }
4597
Chris Lattner7a60d912005-01-07 07:47:53 +00004598 // Lower all of the non-terminator instructions.
4599 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4600 I != E; ++I)
4601 SDL.visit(*I);
Duncan Sands97f72362007-06-13 05:51:31 +00004602
Chris Lattner7a60d912005-01-07 07:47:53 +00004603 // Ensure that all instructions which are used outside of their defining
Duncan Sands97f72362007-06-13 05:51:31 +00004604 // blocks are available as virtual registers. Invoke is handled elsewhere.
Chris Lattner7a60d912005-01-07 07:47:53 +00004605 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
Duncan Sands97f72362007-06-13 05:51:31 +00004606 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
Chris Lattner289aa442007-02-04 01:35:11 +00004607 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
Chris Lattner7a60d912005-01-07 07:47:53 +00004608 if (VMI != FuncInfo.ValueMap.end())
Chris Lattner718b5c22005-01-13 17:59:43 +00004609 UnorderedChains.push_back(
Chris Lattnered0110b2006-10-27 21:36:01 +00004610 SDL.CopyValueToVirtualRegister(I, VMI->second));
Chris Lattner7a60d912005-01-07 07:47:53 +00004611 }
4612
4613 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4614 // ensure constants are generated when needed. Remember the virtual registers
4615 // that need to be added to the Machine PHI nodes as input. We cannot just
4616 // directly add them, because expansion might result in multiple MBB's for one
4617 // BB. As such, the start of the BB might correspond to a different MBB than
4618 // the end.
Misha Brukman835702a2005-04-21 22:36:52 +00004619 //
Chris Lattner84a03502006-10-27 23:50:33 +00004620 TerminatorInst *TI = LLVMBB->getTerminator();
Chris Lattner7a60d912005-01-07 07:47:53 +00004621
4622 // Emit constants only once even if used by multiple PHI nodes.
4623 std::map<Constant*, unsigned> ConstantsOut;
Chris Lattner707339a52006-09-07 01:59:34 +00004624
Chris Lattner84a03502006-10-27 23:50:33 +00004625 // Vector bool would be better, but vector<bool> is really slow.
4626 std::vector<unsigned char> SuccsHandled;
4627 if (TI->getNumSuccessors())
4628 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4629
Dan Gohmanf8f531b2007-07-09 20:59:04 +00004630 // Check successor nodes' PHI nodes that expect a constant to be available
4631 // from this block.
Chris Lattner7a60d912005-01-07 07:47:53 +00004632 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4633 BasicBlock *SuccBB = TI->getSuccessor(succ);
Chris Lattner707339a52006-09-07 01:59:34 +00004634 if (!isa<PHINode>(SuccBB->begin())) continue;
Chris Lattner84a03502006-10-27 23:50:33 +00004635 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
Chris Lattner707339a52006-09-07 01:59:34 +00004636
Chris Lattner84a03502006-10-27 23:50:33 +00004637 // If this terminator has multiple identical successors (common for
4638 // switches), only handle each succ once.
4639 unsigned SuccMBBNo = SuccMBB->getNumber();
4640 if (SuccsHandled[SuccMBBNo]) continue;
4641 SuccsHandled[SuccMBBNo] = true;
4642
4643 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
Chris Lattner7a60d912005-01-07 07:47:53 +00004644 PHINode *PN;
4645
4646 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4647 // nodes and Machine PHI nodes, but the incoming operands have not been
4648 // emitted yet.
4649 for (BasicBlock::iterator I = SuccBB->begin();
Chris Lattner84a03502006-10-27 23:50:33 +00004650 (PN = dyn_cast<PHINode>(I)); ++I) {
4651 // Ignore dead phi's.
4652 if (PN->use_empty()) continue;
4653
4654 unsigned Reg;
4655 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
Chris Lattner90f42382006-11-29 01:12:32 +00004656
Chris Lattner84a03502006-10-27 23:50:33 +00004657 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4658 unsigned &RegOut = ConstantsOut[C];
4659 if (RegOut == 0) {
4660 RegOut = FuncInfo.CreateRegForValue(C);
4661 UnorderedChains.push_back(
4662 SDL.CopyValueToVirtualRegister(C, RegOut));
Chris Lattner7a60d912005-01-07 07:47:53 +00004663 }
Chris Lattner84a03502006-10-27 23:50:33 +00004664 Reg = RegOut;
4665 } else {
4666 Reg = FuncInfo.ValueMap[PHIOp];
4667 if (Reg == 0) {
4668 assert(isa<AllocaInst>(PHIOp) &&
4669 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4670 "Didn't codegen value into a register!??");
4671 Reg = FuncInfo.CreateRegForValue(PHIOp);
4672 UnorderedChains.push_back(
4673 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
Chris Lattnerba380352006-03-31 02:12:18 +00004674 }
Chris Lattner7a60d912005-01-07 07:47:53 +00004675 }
Chris Lattner84a03502006-10-27 23:50:33 +00004676
4677 // Remember that this register needs to added to the machine PHI node as
4678 // the input for this MBB.
4679 MVT::ValueType VT = TLI.getValueType(PN->getType());
Dan Gohmana8665142007-06-25 16:23:39 +00004680 unsigned NumRegisters = TLI.getNumRegisters(VT);
Dan Gohman04deef32007-06-21 14:42:22 +00004681 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
Chris Lattner84a03502006-10-27 23:50:33 +00004682 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4683 }
Chris Lattner7a60d912005-01-07 07:47:53 +00004684 }
4685 ConstantsOut.clear();
4686
Chris Lattner718b5c22005-01-13 17:59:43 +00004687 // Turn all of the unordered chains into one factored node.
Chris Lattner24516842005-01-13 19:53:14 +00004688 if (!UnorderedChains.empty()) {
Chris Lattnerb7cad902005-11-09 05:03:03 +00004689 SDOperand Root = SDL.getRoot();
4690 if (Root.getOpcode() != ISD::EntryToken) {
4691 unsigned i = 0, e = UnorderedChains.size();
4692 for (; i != e; ++i) {
4693 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4694 if (UnorderedChains[i].Val->getOperand(0) == Root)
4695 break; // Don't add the root if we already indirectly depend on it.
4696 }
4697
4698 if (i == e)
4699 UnorderedChains.push_back(Root);
4700 }
Chris Lattnerc24a1d32006-08-08 02:23:42 +00004701 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4702 &UnorderedChains[0], UnorderedChains.size()));
Chris Lattner718b5c22005-01-13 17:59:43 +00004703 }
4704
Chris Lattner7a60d912005-01-07 07:47:53 +00004705 // Lower the terminator after the copies are emitted.
Duncan Sands97f72362007-06-13 05:51:31 +00004706 SDL.visit(*LLVMBB->getTerminator());
Chris Lattner4108bb02005-01-17 19:43:36 +00004707
Nate Begemaned728c12006-03-27 01:32:24 +00004708 // Copy over any CaseBlock records that may now exist due to SwitchInst
Nate Begeman4ca2ea52006-04-22 18:53:45 +00004709 // lowering, as well as any jump table information.
Nate Begemaned728c12006-03-27 01:32:24 +00004710 SwitchCases.clear();
4711 SwitchCases = SDL.SwitchCases;
Anton Korobeynikov70378262007-03-25 15:07:15 +00004712 JTCases.clear();
4713 JTCases = SDL.JTCases;
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004714 BitTestCases.clear();
4715 BitTestCases = SDL.BitTestCases;
4716
Chris Lattner4108bb02005-01-17 19:43:36 +00004717 // Make sure the root of the DAG is up-to-date.
4718 DAG.setRoot(SDL.getRoot());
Arnold Schwaighofer9ccea992007-10-11 19:40:01 +00004719
4720 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4721 // with correct tailcall attribute so that the target can rely on the tailcall
4722 // attribute indicating whether the call is really eligible for tail call
4723 // optimization.
4724 CheckDAGForTailCallsAndFixThem(DAG, TLI);
Chris Lattner7a60d912005-01-07 07:47:53 +00004725}
4726
Nate Begemaned728c12006-03-27 01:32:24 +00004727void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
Dan Gohmanfadf40a2007-10-08 15:12:17 +00004728 DOUT << "Lowered selection DAG:\n";
4729 DEBUG(DAG.dump());
4730
Chris Lattnerbcfebeb2005-10-10 16:47:10 +00004731 // Run the DAG combiner in pre-legalize mode.
Dan Gohman8dc0b932007-08-27 16:26:13 +00004732 DAG.Combine(false, *AA);
Nate Begeman007c6502005-09-07 00:15:36 +00004733
Dan Gohmanfadf40a2007-10-08 15:12:17 +00004734 DOUT << "Optimized lowered selection DAG:\n";
Chris Lattner7a60d912005-01-07 07:47:53 +00004735 DEBUG(DAG.dump());
Nate Begemaned728c12006-03-27 01:32:24 +00004736
Chris Lattner7a60d912005-01-07 07:47:53 +00004737 // Second step, hack on the DAG until it only uses operations and types that
4738 // the target supports.
Chris Lattner3cfb56d2007-10-15 06:10:22 +00004739#if 0 // Enable this some day.
4740 DAG.LegalizeTypes();
4741 // Someday even later, enable a dag combine pass here.
4742#endif
Chris Lattnerffcb0ae2005-01-23 04:36:26 +00004743 DAG.Legalize();
Nate Begemaned728c12006-03-27 01:32:24 +00004744
Bill Wendling22e978a2006-12-07 20:04:42 +00004745 DOUT << "Legalized selection DAG:\n";
Chris Lattner7a60d912005-01-07 07:47:53 +00004746 DEBUG(DAG.dump());
Nate Begemaned728c12006-03-27 01:32:24 +00004747
Chris Lattnerbcfebeb2005-10-10 16:47:10 +00004748 // Run the DAG combiner in post-legalize mode.
Dan Gohman8dc0b932007-08-27 16:26:13 +00004749 DAG.Combine(true, *AA);
Nate Begeman007c6502005-09-07 00:15:36 +00004750
Dan Gohmanfadf40a2007-10-08 15:12:17 +00004751 DOUT << "Optimized legalized selection DAG:\n";
4752 DEBUG(DAG.dump());
4753
Evan Cheng739a6a42006-01-21 02:32:06 +00004754 if (ViewISelDAGs) DAG.viewGraph();
Evan Cheng51ab4492006-04-28 02:09:19 +00004755
Chris Lattner5ca31d92005-03-30 01:10:47 +00004756 // Third, instruction select all of the operations to machine code, adding the
4757 // code to the MachineBasicBlock.
Chris Lattner7a60d912005-01-07 07:47:53 +00004758 InstructionSelectBasicBlock(DAG);
Nate Begemaned728c12006-03-27 01:32:24 +00004759
Bill Wendling22e978a2006-12-07 20:04:42 +00004760 DOUT << "Selected machine code:\n";
Chris Lattner7a60d912005-01-07 07:47:53 +00004761 DEBUG(BB->dump());
Nate Begemaned728c12006-03-27 01:32:24 +00004762}
Chris Lattner7a60d912005-01-07 07:47:53 +00004763
Nate Begemaned728c12006-03-27 01:32:24 +00004764void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4765 FunctionLoweringInfo &FuncInfo) {
4766 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4767 {
Jim Laskeyc56315c2007-01-26 21:22:28 +00004768 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
Nate Begemaned728c12006-03-27 01:32:24 +00004769 CurDAG = &DAG;
4770
4771 // First step, lower LLVM code to some DAG. This DAG may use operations and
4772 // types that are not supported by the target.
4773 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4774
4775 // Second step, emit the lowered DAG as machine code.
4776 CodeGenAndEmitDAG(DAG);
4777 }
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004778
4779 DOUT << "Total amount of phi nodes to update: "
4780 << PHINodesToUpdate.size() << "\n";
4781 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4782 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4783 << ", " << PHINodesToUpdate[i].second << ")\n";);
Nate Begemaned728c12006-03-27 01:32:24 +00004784
Chris Lattner5ca31d92005-03-30 01:10:47 +00004785 // Next, now that we know what the last MBB the LLVM BB expanded is, update
Chris Lattner7a60d912005-01-07 07:47:53 +00004786 // PHI nodes in successors.
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004787 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
Nate Begemaned728c12006-03-27 01:32:24 +00004788 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4789 MachineInstr *PHI = PHINodesToUpdate[i].first;
4790 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4791 "This is not a machine PHI node that we are updating!");
Chris Lattneraf23f9b2006-09-05 02:31:13 +00004792 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
Nate Begemaned728c12006-03-27 01:32:24 +00004793 PHI->addMachineBasicBlockOperand(BB);
4794 }
4795 return;
Chris Lattner7a60d912005-01-07 07:47:53 +00004796 }
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004797
4798 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4799 // Lower header first, if it wasn't already lowered
4800 if (!BitTestCases[i].Emitted) {
4801 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4802 CurDAG = &HSDAG;
Dan Gohman8dc0b932007-08-27 16:26:13 +00004803 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004804 // Set the current basic block to the mbb we wish to insert the code into
4805 BB = BitTestCases[i].Parent;
4806 HSDL.setCurrentBasicBlock(BB);
4807 // Emit the code
4808 HSDL.visitBitTestHeader(BitTestCases[i]);
4809 HSDAG.setRoot(HSDL.getRoot());
4810 CodeGenAndEmitDAG(HSDAG);
4811 }
4812
4813 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4814 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4815 CurDAG = &BSDAG;
Dan Gohman8dc0b932007-08-27 16:26:13 +00004816 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004817 // Set the current basic block to the mbb we wish to insert the code into
4818 BB = BitTestCases[i].Cases[j].ThisBB;
4819 BSDL.setCurrentBasicBlock(BB);
4820 // Emit the code
4821 if (j+1 != ej)
4822 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4823 BitTestCases[i].Reg,
4824 BitTestCases[i].Cases[j]);
4825 else
4826 BSDL.visitBitTestCase(BitTestCases[i].Default,
4827 BitTestCases[i].Reg,
4828 BitTestCases[i].Cases[j]);
4829
4830
4831 BSDAG.setRoot(BSDL.getRoot());
4832 CodeGenAndEmitDAG(BSDAG);
4833 }
4834
4835 // Update PHI Nodes
4836 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4837 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4838 MachineBasicBlock *PHIBB = PHI->getParent();
4839 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4840 "This is not a machine PHI node that we are updating!");
4841 // This is "default" BB. We have two jumps to it. From "header" BB and
4842 // from last "case" BB.
4843 if (PHIBB == BitTestCases[i].Default) {
4844 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4845 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
Anton Korobeynikove2880402007-04-13 06:53:51 +00004846 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004847 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
4848 }
4849 // One of "cases" BB.
4850 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4851 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4852 if (cBB->succ_end() !=
4853 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4854 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4855 PHI->addMachineBasicBlockOperand(cBB);
4856 }
4857 }
4858 }
4859 }
4860
Nate Begeman866b4b42006-04-23 06:26:20 +00004861 // If the JumpTable record is filled in, then we need to emit a jump table.
4862 // Updating the PHI nodes is tricky in this case, since we need to determine
4863 // whether the PHI is a successor of the range check MBB or the jump table MBB
Anton Korobeynikov70378262007-03-25 15:07:15 +00004864 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4865 // Lower header first, if it wasn't already lowered
4866 if (!JTCases[i].first.Emitted) {
4867 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4868 CurDAG = &HSDAG;
Dan Gohman8dc0b932007-08-27 16:26:13 +00004869 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
Anton Korobeynikov70378262007-03-25 15:07:15 +00004870 // Set the current basic block to the mbb we wish to insert the code into
4871 BB = JTCases[i].first.HeaderBB;
4872 HSDL.setCurrentBasicBlock(BB);
4873 // Emit the code
4874 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4875 HSDAG.setRoot(HSDL.getRoot());
4876 CodeGenAndEmitDAG(HSDAG);
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004877 }
Anton Korobeynikov70378262007-03-25 15:07:15 +00004878
4879 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4880 CurDAG = &JSDAG;
Dan Gohman8dc0b932007-08-27 16:26:13 +00004881 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo);
Nate Begeman4ca2ea52006-04-22 18:53:45 +00004882 // Set the current basic block to the mbb we wish to insert the code into
Anton Korobeynikov70378262007-03-25 15:07:15 +00004883 BB = JTCases[i].second.MBB;
4884 JSDL.setCurrentBasicBlock(BB);
Nate Begeman4ca2ea52006-04-22 18:53:45 +00004885 // Emit the code
Anton Korobeynikov70378262007-03-25 15:07:15 +00004886 JSDL.visitJumpTable(JTCases[i].second);
4887 JSDAG.setRoot(JSDL.getRoot());
4888 CodeGenAndEmitDAG(JSDAG);
4889
Nate Begeman4ca2ea52006-04-22 18:53:45 +00004890 // Update PHI Nodes
4891 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4892 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4893 MachineBasicBlock *PHIBB = PHI->getParent();
4894 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4895 "This is not a machine PHI node that we are updating!");
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004896 // "default" BB. We can go there only from header BB.
Anton Korobeynikov70378262007-03-25 15:07:15 +00004897 if (PHIBB == JTCases[i].second.Default) {
Chris Lattneraf23f9b2006-09-05 02:31:13 +00004898 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
Anton Korobeynikov70378262007-03-25 15:07:15 +00004899 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
Nate Begemandf488392006-05-03 03:48:02 +00004900 }
Anton Korobeynikov506eaf72007-04-09 12:31:58 +00004901 // JT BB. Just iterate over successors here
Nate Begemandf488392006-05-03 03:48:02 +00004902 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
Chris Lattneraf23f9b2006-09-05 02:31:13 +00004903 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
Nate Begemandf488392006-05-03 03:48:02 +00004904 PHI->addMachineBasicBlockOperand(BB);
Nate Begeman4ca2ea52006-04-22 18:53:45 +00004905 }
4906 }
Nate Begeman4ca2ea52006-04-22 18:53:45 +00004907 }
4908
Chris Lattner76a7bc82006-10-22 23:00:53 +00004909 // If the switch block involved a branch to one of the actual successors, we
4910 // need to update PHI nodes in that block.
4911 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4912 MachineInstr *PHI = PHINodesToUpdate[i].first;
4913 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4914 "This is not a machine PHI node that we are updating!");
4915 if (BB->isSuccessor(PHI->getParent())) {
4916 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4917 PHI->addMachineBasicBlockOperand(BB);
4918 }
4919 }
4920
Nate Begemaned728c12006-03-27 01:32:24 +00004921 // If we generated any switch lowering information, build and codegen any
4922 // additional DAGs necessary.
Chris Lattner707339a52006-09-07 01:59:34 +00004923 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
Jim Laskeyc56315c2007-01-26 21:22:28 +00004924 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
Nate Begemaned728c12006-03-27 01:32:24 +00004925 CurDAG = &SDAG;
Dan Gohman8dc0b932007-08-27 16:26:13 +00004926 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo);
Chris Lattner707339a52006-09-07 01:59:34 +00004927
Nate Begemaned728c12006-03-27 01:32:24 +00004928 // Set the current basic block to the mbb we wish to insert the code into
4929 BB = SwitchCases[i].ThisBB;
4930 SDL.setCurrentBasicBlock(BB);
Chris Lattner707339a52006-09-07 01:59:34 +00004931
Nate Begemaned728c12006-03-27 01:32:24 +00004932 // Emit the code
4933 SDL.visitSwitchCase(SwitchCases[i]);
4934 SDAG.setRoot(SDL.getRoot());
4935 CodeGenAndEmitDAG(SDAG);
Chris Lattner707339a52006-09-07 01:59:34 +00004936
4937 // Handle any PHI nodes in successors of this chunk, as if we were coming
4938 // from the original BB before switch expansion. Note that PHI nodes can
4939 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4940 // handle them the right number of times.
Chris Lattner963ddad2006-10-24 17:57:59 +00004941 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
Chris Lattner707339a52006-09-07 01:59:34 +00004942 for (MachineBasicBlock::iterator Phi = BB->begin();
4943 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4944 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4945 for (unsigned pn = 0; ; ++pn) {
4946 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4947 if (PHINodesToUpdate[pn].first == Phi) {
4948 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4949 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4950 break;
4951 }
4952 }
Nate Begemaned728c12006-03-27 01:32:24 +00004953 }
Chris Lattner707339a52006-09-07 01:59:34 +00004954
4955 // Don't process RHS if same block as LHS.
Chris Lattner963ddad2006-10-24 17:57:59 +00004956 if (BB == SwitchCases[i].FalseBB)
4957 SwitchCases[i].FalseBB = 0;
Chris Lattner707339a52006-09-07 01:59:34 +00004958
4959 // If we haven't handled the RHS, do so now. Otherwise, we're done.
Chris Lattner61bcf912006-10-24 18:07:37 +00004960 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
Chris Lattner963ddad2006-10-24 17:57:59 +00004961 SwitchCases[i].FalseBB = 0;
Nate Begemaned728c12006-03-27 01:32:24 +00004962 }
Chris Lattner963ddad2006-10-24 17:57:59 +00004963 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
Chris Lattner5ca31d92005-03-30 01:10:47 +00004964 }
Chris Lattner7a60d912005-01-07 07:47:53 +00004965}
Evan Cheng739a6a42006-01-21 02:32:06 +00004966
Jim Laskey95eda5b2006-08-01 14:21:23 +00004967
Evan Cheng739a6a42006-01-21 02:32:06 +00004968//===----------------------------------------------------------------------===//
4969/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4970/// target node in the graph.
4971void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4972 if (ViewSchedDAGs) DAG.viewGraph();
Evan Chengc1e1d972006-01-23 07:01:07 +00004973
Jim Laskey29e635d2006-08-02 12:30:23 +00004974 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
Jim Laskey95eda5b2006-08-01 14:21:23 +00004975
4976 if (!Ctor) {
Jim Laskey29e635d2006-08-02 12:30:23 +00004977 Ctor = ISHeuristic;
Jim Laskey17c67ef2006-08-01 19:14:14 +00004978 RegisterScheduler::setDefault(Ctor);
Evan Chengc1e1d972006-01-23 07:01:07 +00004979 }
Jim Laskey95eda5b2006-08-01 14:21:23 +00004980
Jim Laskey03593f72006-08-01 18:29:48 +00004981 ScheduleDAG *SL = Ctor(this, &DAG, BB);
Chris Lattnere23928c2006-01-21 19:12:11 +00004982 BB = SL->Run();
Dan Gohman81b62e12007-08-28 20:32:58 +00004983
4984 if (ViewSUnitDAGs) SL->viewGraph();
4985
Evan Chengf9adce92006-02-04 06:49:00 +00004986 delete SL;
Evan Cheng739a6a42006-01-21 02:32:06 +00004987}
Chris Lattnerdcf785b2006-02-24 02:13:54 +00004988
Chris Lattner47639db2006-03-06 00:22:00 +00004989
Jim Laskey03593f72006-08-01 18:29:48 +00004990HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4991 return new HazardRecognizer();
4992}
4993
Chris Lattner6df34962006-10-11 03:58:02 +00004994//===----------------------------------------------------------------------===//
4995// Helper functions used by the generated instruction selector.
4996//===----------------------------------------------------------------------===//
4997// Calls to these methods are generated by tblgen.
4998
4999/// CheckAndMask - The isel is trying to match something like (and X, 255). If
5000/// the dag combiner simplified the 255, we still want to match. RHS is the
5001/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5002/// specified in the .td file (e.g. 255).
5003bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
Dan Gohmanf0bb1282007-07-24 23:00:27 +00005004 int64_t DesiredMaskS) const {
Chris Lattner6df34962006-10-11 03:58:02 +00005005 uint64_t ActualMask = RHS->getValue();
5006 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5007
5008 // If the actual mask exactly matches, success!
5009 if (ActualMask == DesiredMask)
5010 return true;
5011
5012 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5013 if (ActualMask & ~DesiredMask)
5014 return false;
5015
5016 // Otherwise, the DAG Combiner may have proven that the value coming in is
5017 // either already zero or is not demanded. Check for known zero input bits.
5018 uint64_t NeededMask = DesiredMask & ~ActualMask;
Dan Gohman309d3d52007-06-22 14:59:07 +00005019 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
Chris Lattner6df34962006-10-11 03:58:02 +00005020 return true;
5021
5022 // TODO: check to see if missing bits are just not demanded.
5023
5024 // Otherwise, this pattern doesn't match.
5025 return false;
5026}
5027
5028/// CheckOrMask - The isel is trying to match something like (or X, 255). If
5029/// the dag combiner simplified the 255, we still want to match. RHS is the
5030/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5031/// specified in the .td file (e.g. 255).
5032bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
Dan Gohmanf0bb1282007-07-24 23:00:27 +00005033 int64_t DesiredMaskS) const {
Chris Lattner6df34962006-10-11 03:58:02 +00005034 uint64_t ActualMask = RHS->getValue();
5035 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5036
5037 // If the actual mask exactly matches, success!
5038 if (ActualMask == DesiredMask)
5039 return true;
5040
5041 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5042 if (ActualMask & ~DesiredMask)
5043 return false;
5044
5045 // Otherwise, the DAG Combiner may have proven that the value coming in is
5046 // either already zero or is not demanded. Check for known zero input bits.
5047 uint64_t NeededMask = DesiredMask & ~ActualMask;
5048
5049 uint64_t KnownZero, KnownOne;
Dan Gohman309d3d52007-06-22 14:59:07 +00005050 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
Chris Lattner6df34962006-10-11 03:58:02 +00005051
5052 // If all the missing bits in the or are already known to be set, match!
5053 if ((NeededMask & KnownOne) == NeededMask)
5054 return true;
5055
5056 // TODO: check to see if missing bits are just not demanded.
5057
5058 // Otherwise, this pattern doesn't match.
5059 return false;
5060}
5061
Jim Laskey03593f72006-08-01 18:29:48 +00005062
Chris Lattnerdcf785b2006-02-24 02:13:54 +00005063/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5064/// by tblgen. Others should not call it.
5065void SelectionDAGISel::
5066SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5067 std::vector<SDOperand> InOps;
5068 std::swap(InOps, Ops);
5069
5070 Ops.push_back(InOps[0]); // input chain.
5071 Ops.push_back(InOps[1]); // input asm string.
5072
Chris Lattnerdcf785b2006-02-24 02:13:54 +00005073 unsigned i = 2, e = InOps.size();
5074 if (InOps[e-1].getValueType() == MVT::Flag)
5075 --e; // Don't process a flag operand if it is here.
5076
5077 while (i != e) {
5078 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5079 if ((Flags & 7) != 4 /*MEM*/) {
5080 // Just skip over this operand, copying the operands verbatim.
5081 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5082 i += (Flags >> 3) + 1;
5083 } else {
5084 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5085 // Otherwise, this is a memory operand. Ask the target to select it.
5086 std::vector<SDOperand> SelOps;
5087 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
Bill Wendling22e978a2006-12-07 20:04:42 +00005088 cerr << "Could not match memory address. Inline asm failure!\n";
Chris Lattnerdcf785b2006-02-24 02:13:54 +00005089 exit(1);
5090 }
5091
5092 // Add this to the output node.
Chris Lattnerb49917d2007-04-09 00:33:58 +00005093 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Chris Lattner9bd5ed62006-12-16 21:14:48 +00005094 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
Chris Lattnerb49917d2007-04-09 00:33:58 +00005095 IntPtrTy));
Chris Lattnerdcf785b2006-02-24 02:13:54 +00005096 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5097 i += 2;
5098 }
5099 }
5100
5101 // Add the flag input back if present.
5102 if (e != InOps.size())
5103 Ops.push_back(InOps.back());
5104}
Devang Patel09f162c2007-05-01 21:15:47 +00005105
Devang Patel8c78a0b2007-05-03 01:11:54 +00005106char SelectionDAGISel::ID = 0;