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Jia Liu9f610112012-02-17 08:55:11 +00001//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00007//
Akira Hatanakae2489122011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00009//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
Akira Hatanakae2489122011-04-15 21:51:11 +000012//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000013
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000014#include "MipsInstrInfo.h"
Akira Hatanaka9c6028f2011-07-07 23:56:50 +000015#include "InstPrinter/MipsInstPrinter.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "MipsMachineFunction.h"
Eric Christopherd8abc3a2015-01-08 18:18:54 +000017#include "MipsSubtarget.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000018#include "llvm/ADT/STLExtras.h"
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000019#include "llvm/CodeGen/MachineInstrBuilder.h"
Dan Gohmand5ca70642009-06-03 20:30:14 +000020#include "llvm/CodeGen/MachineRegisterInfo.h"
Torok Edwin56d06592009-07-11 20:10:48 +000021#include "llvm/Support/ErrorHandling.h"
Evan Cheng2bb40352011-08-24 18:08:43 +000022#include "llvm/Support/TargetRegistry.h"
Evan Cheng1e210d02011-06-28 20:07:07 +000023
Chandler Carruthd174b722014-04-22 02:03:14 +000024using namespace llvm;
25
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +000026#define GET_INSTRINFO_CTOR_DTOR
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000027#include "MipsGenInstrInfo.inc"
28
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +000029// Pin the vtable to this file.
30void MipsInstrInfo::anchor() {}
31
Eric Christopher675cb4d2014-07-18 23:25:00 +000032MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
33 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
34 Subtarget(STI), UncondBrOpc(UncondBr) {}
Akira Hatanaka9c6028f2011-07-07 23:56:50 +000035
Eric Christopher675cb4d2014-07-18 23:25:00 +000036const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
37 if (STI.inMips16Mode())
38 return llvm::createMips16InstrInfo(STI);
Akira Hatanakafab89292012-08-02 18:21:47 +000039
Eric Christopher675cb4d2014-07-18 23:25:00 +000040 return llvm::createMipsSEInstrInfo(STI);
Akira Hatanakafab89292012-08-02 18:21:47 +000041}
42
Akira Hatanakab7fa3c92012-07-31 21:49:49 +000043bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
Dan Gohman0d1e9a82008-10-03 15:45:36 +000044 return op.isImm() && op.getImm() == 0;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000045}
46
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000047/// insertNoop - If data hazard condition is found insert the target nop
48/// instruction.
Simon Dardis9a3f32c2016-03-29 13:02:19 +000049// FIXME: This appears to be dead code.
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000050void MipsInstrInfo::
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +000051insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000052{
Chris Lattner6f306d72010-04-02 20:16:16 +000053 DebugLoc DL;
Bill Wendlingf6d609a2009-02-12 00:02:55 +000054 BuildMI(MBB, MI, DL, get(Mips::NOP));
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000055}
56
Justin Lebar0af80cd2016-07-15 18:26:59 +000057MachineMemOperand *
58MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
59 MachineMemOperand::Flags Flags) const {
Akira Hatanaka1cf75762011-12-24 03:11:18 +000060 MachineFunction &MF = *MBB.getParent();
Matthias Braun941a7052016-07-28 18:40:00 +000061 MachineFrameInfo &MFI = MF.getFrameInfo();
Akira Hatanaka1cf75762011-12-24 03:11:18 +000062 unsigned Align = MFI.getObjectAlignment(FI);
Jia Liuf54f60f2012-02-28 07:46:26 +000063
Alex Lorenze40c8a22015-08-11 23:09:45 +000064 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
Justin Lebar0af80cd2016-07-15 18:26:59 +000065 Flags, MFI.getObjectSize(FI), Align);
Akira Hatanaka1cf75762011-12-24 03:11:18 +000066}
67
Akira Hatanakae2489122011-04-15 21:51:11 +000068//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000069// Branch Analysis
Akira Hatanakae2489122011-04-15 21:51:11 +000070//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000071
Akira Hatanakab7fa3c92012-07-31 21:49:49 +000072void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
73 MachineBasicBlock *&BB,
74 SmallVectorImpl<MachineOperand> &Cond) const {
Akira Hatanaka067d8152013-05-13 17:43:19 +000075 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
Akira Hatanaka93f898f2011-04-01 17:39:08 +000076 int NumOp = Inst->getNumExplicitOperands();
Jia Liuf54f60f2012-02-28 07:46:26 +000077
Akira Hatanaka93f898f2011-04-01 17:39:08 +000078 // for both int and fp branches, the last explicit operand is the
79 // MBB.
80 BB = Inst->getOperand(NumOp-1).getMBB();
81 Cond.push_back(MachineOperand::CreateImm(Opc));
Bruno Cardoso Lopesbcaf6e52008-07-28 19:11:24 +000082
Akira Hatanaka93f898f2011-04-01 17:39:08 +000083 for (int i=0; i<NumOp-1; i++)
84 Cond.push_back(Inst->getOperand(i));
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000085}
86
Jacques Pienaar71c30a12016-07-15 14:41:04 +000087bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +000088 MachineBasicBlock *&TBB,
89 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +000090 SmallVectorImpl<MachineOperand> &Cond,
Akira Hatanaka7320b232013-03-01 01:10:17 +000091 bool AllowModify) const {
92 SmallVector<MachineInstr*, 2> BranchInstrs;
Jacques Pienaar71c30a12016-07-15 14:41:04 +000093 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
Akira Hatanakafcdd9b12012-09-13 17:12:37 +000094
Akira Hatanaka7320b232013-03-01 01:10:17 +000095 return (BT == BT_None) || (BT == BT_Indirect);
Jia Liuf54f60f2012-02-28 07:46:26 +000096}
97
Benjamin Kramerbdc49562016-06-12 15:39:02 +000098void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
99 const DebugLoc &DL,
100 ArrayRef<MachineOperand> Cond) const {
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000101 unsigned Opc = Cond[0].getImm();
Evan Cheng6cc775f2011-06-28 19:10:37 +0000102 const MCInstrDesc &MCID = get(Opc);
103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000104
Akira Hatanakafcdd9b12012-09-13 17:12:37 +0000105 for (unsigned i = 1; i < Cond.size(); ++i) {
Simon Dardisc38d3912017-06-13 14:11:29 +0000106 assert((Cond[i].isImm() || Cond[i].isReg()) &&
107 "Cannot copy operand for conditional branch!");
108 MIB.add(Cond[i]);
Akira Hatanakafcdd9b12012-09-13 17:12:37 +0000109 }
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000110 MIB.addMBB(TBB);
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000111}
112
Matt Arsenaulte8e0f5c2016-09-14 17:24:15 +0000113unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000114 MachineBasicBlock *TBB,
115 MachineBasicBlock *FBB,
116 ArrayRef<MachineOperand> Cond,
Matt Arsenaulta2b036e2016-09-14 17:23:48 +0000117 const DebugLoc &DL,
118 int *BytesAdded) const {
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000119 // Shouldn't be a fall through.
Matt Arsenaulte8e0f5c2016-09-14 17:24:15 +0000120 assert(TBB && "insertBranch must not be told to insert a fallthrough");
Matt Arsenaulta2b036e2016-09-14 17:23:48 +0000121 assert(!BytesAdded && "code size not handled");
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000122
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000123 // # of condition operands:
124 // Unconditional branches: 0
125 // Floating point branches: 1 (opc)
126 // Int BranchZero: 2 (opc, reg)
127 // Int Branch: 3 (opc, reg0, reg1)
128 assert((Cond.size() <= 3) &&
129 "# of Mips branch conditions must be <= 3!");
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000130
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000131 // Two-way Conditional branch.
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000132 if (FBB) {
133 BuildCondBr(MBB, TBB, DL, Cond);
Akira Hatanaka5d5e0d82011-12-12 22:39:35 +0000134 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000135 return 2;
136 }
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000137
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000138 // One way branch.
139 // Unconditional branch.
140 if (Cond.empty())
Akira Hatanaka5d5e0d82011-12-12 22:39:35 +0000141 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000142 else // Conditional branch.
143 BuildCondBr(MBB, TBB, DL, Cond);
144 return 1;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000145}
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000146
Matt Arsenault1b9fc8e2016-09-14 20:43:16 +0000147unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
Matt Arsenaulta2b036e2016-09-14 17:23:48 +0000148 int *BytesRemoved) const {
149 assert(!BytesRemoved && "code size not handled");
150
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000151 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000152 unsigned removed;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000153
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000154 // Skip all the debug instructions.
155 while (I != REnd && I->isDebugValue())
156 ++I;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000157
Duncan P. N. Exon Smith18720962016-09-11 18:51:28 +0000158 if (I == REnd)
159 return 0;
160
161 MachineBasicBlock::iterator FirstBr = ++I.getReverse();
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000162
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000163 // Up to 2 branches are removed.
164 // Note that indirect branches are not removed.
Eric Christopher675cb4d2014-07-18 23:25:00 +0000165 for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
Akira Hatanaka067d8152013-05-13 17:43:19 +0000166 if (!getAnalyzableBrOpc(I->getOpcode()))
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000167 break;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000168
Duncan P. N. Exon Smith18720962016-09-11 18:51:28 +0000169 MBB.erase((--I).getReverse(), FirstBr);
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000170
171 return removed;
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000172}
173
Matt Arsenault1b9fc8e2016-09-14 20:43:16 +0000174/// reverseBranchCondition - Return the inverse opcode of the
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000175/// specified Branch instruction.
Matt Arsenault1b9fc8e2016-09-14 20:43:16 +0000176bool MipsInstrInfo::reverseBranchCondition(
Eric Christopher754d54f2014-07-18 20:35:49 +0000177 SmallVectorImpl<MachineOperand> &Cond) const {
Akira Hatanaka93f898f2011-04-01 17:39:08 +0000178 assert( (Cond.size() && Cond.size() <= 3) &&
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000179 "Invalid Mips branch condition!");
Akira Hatanaka067d8152013-05-13 17:43:19 +0000180 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
Bruno Cardoso Lopes7b616f52007-08-18 01:56:48 +0000181 return false;
182}
Dan Gohmand5ca70642009-06-03 20:30:14 +0000183
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000184MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
Eric Christopher754d54f2014-07-18 20:35:49 +0000185 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
186 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
187 SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
Akira Hatanaka7320b232013-03-01 01:10:17 +0000188
189 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
190
191 // Skip all the debug instructions.
192 while (I != REnd && I->isDebugValue())
193 ++I;
194
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000195 if (I == REnd || !isUnpredicatedTerminator(*I)) {
Akira Hatanaka7320b232013-03-01 01:10:17 +0000196 // This block ends with no branches (it just falls through to its succ).
197 // Leave TBB/FBB null.
Craig Topper062a2ba2014-04-25 05:30:21 +0000198 TBB = FBB = nullptr;
Akira Hatanaka7320b232013-03-01 01:10:17 +0000199 return BT_NoBranch;
200 }
201
202 MachineInstr *LastInst = &*I;
203 unsigned LastOpc = LastInst->getOpcode();
204 BranchInstrs.push_back(LastInst);
205
206 // Not an analyzable branch (e.g., indirect jump).
Akira Hatanaka067d8152013-05-13 17:43:19 +0000207 if (!getAnalyzableBrOpc(LastOpc))
Akira Hatanaka7320b232013-03-01 01:10:17 +0000208 return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
209
210 // Get the second to last instruction in the block.
211 unsigned SecondLastOpc = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000212 MachineInstr *SecondLastInst = nullptr;
Akira Hatanaka7320b232013-03-01 01:10:17 +0000213
214 if (++I != REnd) {
215 SecondLastInst = &*I;
Akira Hatanaka067d8152013-05-13 17:43:19 +0000216 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
Akira Hatanaka7320b232013-03-01 01:10:17 +0000217
218 // Not an analyzable branch (must be an indirect jump).
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000219 if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
Akira Hatanaka7320b232013-03-01 01:10:17 +0000220 return BT_None;
221 }
222
Akira Hatanaka7320b232013-03-01 01:10:17 +0000223 // If there is only one terminator instruction, process it.
224 if (!SecondLastOpc) {
Matheus Almeida6de62d32013-10-01 12:53:00 +0000225 // Unconditional branch.
Daniel Sandersf9d8b8c2016-05-06 13:23:51 +0000226 if (LastInst->isUnconditionalBranch()) {
Akira Hatanaka7320b232013-03-01 01:10:17 +0000227 TBB = LastInst->getOperand(0).getMBB();
228 return BT_Uncond;
229 }
230
231 // Conditional branch
232 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
233 return BT_Cond;
234 }
235
236 // If we reached here, there are two branches.
237 // If there are three terminators, we don't know what sort of block this is.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000238 if (++I != REnd && isUnpredicatedTerminator(*I))
Akira Hatanaka7320b232013-03-01 01:10:17 +0000239 return BT_None;
240
Akira Hatanaka28dc83c2013-03-01 01:22:26 +0000241 BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
242
Akira Hatanaka7320b232013-03-01 01:10:17 +0000243 // If second to last instruction is an unconditional branch,
244 // analyze it and remove the last instruction.
Daniel Sandersf9d8b8c2016-05-06 13:23:51 +0000245 if (SecondLastInst->isUnconditionalBranch()) {
Akira Hatanaka7320b232013-03-01 01:10:17 +0000246 // Return if the last instruction cannot be removed.
247 if (!AllowModify)
248 return BT_None;
249
250 TBB = SecondLastInst->getOperand(0).getMBB();
251 LastInst->eraseFromParent();
252 BranchInstrs.pop_back();
253 return BT_Uncond;
254 }
255
256 // Conditional branch followed by an unconditional branch.
257 // The last one must be unconditional.
Daniel Sandersf9d8b8c2016-05-06 13:23:51 +0000258 if (!LastInst->isUnconditionalBranch())
Akira Hatanaka7320b232013-03-01 01:10:17 +0000259 return BT_None;
260
261 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
262 FBB = LastInst->getOperand(0).getMBB();
263
264 return BT_CondUncond;
265}
266
Daniel Sanderse8efff32016-03-14 16:24:05 +0000267/// Return the corresponding compact (no delay slot) form of a branch.
268unsigned MipsInstrInfo::getEquivalentCompactForm(
269 const MachineBasicBlock::iterator I) const {
270 unsigned Opcode = I->getOpcode();
Simon Dardisd9d41f52016-04-05 12:50:29 +0000271 bool canUseShortMicroMipsCTI = false;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000272
Simon Dardisd9d41f52016-04-05 12:50:29 +0000273 if (Subtarget.inMicroMipsMode()) {
274 switch (Opcode) {
275 case Mips::BNE:
Hrvoje Varga2db00ce2016-07-22 07:18:33 +0000276 case Mips::BNE_MM:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000277 case Mips::BEQ:
Hrvoje Varga2db00ce2016-07-22 07:18:33 +0000278 case Mips::BEQ_MM:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000279 // microMIPS has NE,EQ branches that do not have delay slots provided one
280 // of the operands is zero.
281 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
282 canUseShortMicroMipsCTI = true;
283 break;
284 // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
285 // expanded to JR_MM, so they can be replaced with JRC16_MM.
286 case Mips::JR:
287 case Mips::PseudoReturn:
288 case Mips::PseudoIndirectBranch:
Simon Dardisea343152016-08-18 13:22:43 +0000289 case Mips::TAILCALLREG:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000290 canUseShortMicroMipsCTI = true;
291 break;
292 }
293 }
294
Simon Dardis669d8dd2016-05-18 10:38:01 +0000295 // MIPSR6 forbids both operands being the zero register.
296 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
297 (I->getOperand(0).isReg() &&
298 (I->getOperand(0).getReg() == Mips::ZERO ||
299 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
300 (I->getOperand(1).isReg() &&
301 (I->getOperand(1).getReg() == Mips::ZERO ||
302 I->getOperand(1).getReg() == Mips::ZERO_64)))
303 return 0;
304
Simon Dardisd9d41f52016-04-05 12:50:29 +0000305 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
Daniel Sanderse8efff32016-03-14 16:24:05 +0000306 switch (Opcode) {
307 case Mips::B:
308 return Mips::BC;
309 case Mips::BAL:
310 return Mips::BALC;
311 case Mips::BEQ:
Hrvoje Varga2db00ce2016-07-22 07:18:33 +0000312 case Mips::BEQ_MM:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000313 if (canUseShortMicroMipsCTI)
Daniel Sanderse8efff32016-03-14 16:24:05 +0000314 return Mips::BEQZC_MM;
Simon Dardis03676dc2016-05-31 09:54:55 +0000315 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
316 return 0;
317 return Mips::BEQC;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000318 case Mips::BNE:
Hrvoje Varga2db00ce2016-07-22 07:18:33 +0000319 case Mips::BNE_MM:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000320 if (canUseShortMicroMipsCTI)
Daniel Sanderse8efff32016-03-14 16:24:05 +0000321 return Mips::BNEZC_MM;
Simon Dardis03676dc2016-05-31 09:54:55 +0000322 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
323 return 0;
324 return Mips::BNEC;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000325 case Mips::BGE:
Simon Dardis669d8dd2016-05-18 10:38:01 +0000326 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
327 return 0;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000328 return Mips::BGEC;
329 case Mips::BGEU:
Simon Dardis669d8dd2016-05-18 10:38:01 +0000330 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
331 return 0;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000332 return Mips::BGEUC;
333 case Mips::BGEZ:
334 return Mips::BGEZC;
335 case Mips::BGTZ:
336 return Mips::BGTZC;
337 case Mips::BLEZ:
338 return Mips::BLEZC;
339 case Mips::BLT:
Simon Dardis669d8dd2016-05-18 10:38:01 +0000340 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
341 return 0;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000342 return Mips::BLTC;
343 case Mips::BLTU:
Simon Dardis669d8dd2016-05-18 10:38:01 +0000344 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
345 return 0;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000346 return Mips::BLTUC;
347 case Mips::BLTZ:
348 return Mips::BLTZC;
Simon Dardis68a204d2016-07-26 10:25:07 +0000349 case Mips::BEQ64:
350 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
351 return 0;
352 return Mips::BEQC64;
353 case Mips::BNE64:
354 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
355 return 0;
356 return Mips::BNEC64;
357 case Mips::BGTZ64:
358 return Mips::BGTZC64;
359 case Mips::BGEZ64:
360 return Mips::BGEZC64;
361 case Mips::BLTZ64:
362 return Mips::BLTZC64;
363 case Mips::BLEZ64:
364 return Mips::BLEZC64;
Simon Dardisd9d41f52016-04-05 12:50:29 +0000365 // For MIPSR6, the instruction 'jic' can be used for these cases. Some
366 // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
367 case Mips::JR:
368 case Mips::PseudoReturn:
369 case Mips::PseudoIndirectBranch:
Simon Dardisea343152016-08-18 13:22:43 +0000370 case Mips::TAILCALLREG:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000371 if (canUseShortMicroMipsCTI)
372 return Mips::JRC16_MM;
373 return Mips::JIC;
374 case Mips::JALRPseudo:
375 return Mips::JIALC;
376 case Mips::JR64:
377 case Mips::PseudoReturn64:
378 case Mips::PseudoIndirectBranch64:
Simon Dardisea343152016-08-18 13:22:43 +0000379 case Mips::TAILCALLREG64:
Simon Dardisd9d41f52016-04-05 12:50:29 +0000380 return Mips::JIC64;
381 case Mips::JALR64Pseudo:
382 return Mips::JIALC64;
Simon Dardis669d8dd2016-05-18 10:38:01 +0000383 default:
Daniel Sanderse8efff32016-03-14 16:24:05 +0000384 return 0;
385 }
386 }
387
388 return 0;
389}
390
391/// Predicate for distingushing between control transfer instructions and all
392/// other instructions for handling forbidden slots. Consider inline assembly
393/// as unsafe as well.
394bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
395 if (MI.isInlineAsm())
396 return false;
397
398 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
399
400}
401
402/// Predicate for distingushing instructions that have forbidden slots.
403bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
404 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
405}
406
Akira Hatanakaacd1a7d2012-06-14 01:16:45 +0000407/// Return the number of bytes of code the specified instruction may be.
Sjoerd Meijer89217f82016-07-28 16:32:22 +0000408unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
Duncan P. N. Exon Smith670900b2016-07-15 23:09:47 +0000409 switch (MI.getOpcode()) {
Akira Hatanakaacd1a7d2012-06-14 01:16:45 +0000410 default:
Duncan P. N. Exon Smith670900b2016-07-15 23:09:47 +0000411 return MI.getDesc().getSize();
Akira Hatanakaacd1a7d2012-06-14 01:16:45 +0000412 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
Duncan P. N. Exon Smith670900b2016-07-15 23:09:47 +0000413 const MachineFunction *MF = MI.getParent()->getParent();
414 const char *AsmStr = MI.getOperand(0).getSymbolName();
Akira Hatanakaacd1a7d2012-06-14 01:16:45 +0000415 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
416 }
Reed Kotler91ae9822013-10-27 21:57:36 +0000417 case Mips::CONSTPOOL_ENTRY:
418 // If this machine instr is a constant pool entry, its size is recorded as
419 // operand #2.
Duncan P. N. Exon Smith670900b2016-07-15 23:09:47 +0000420 return MI.getOperand(2).getImm();
Akira Hatanakaacd1a7d2012-06-14 01:16:45 +0000421 }
422}
Akira Hatanaka310e26a2013-05-13 17:57:42 +0000423
424MachineInstrBuilder
425MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
426 MachineBasicBlock::iterator I) const {
427 MachineInstrBuilder MIB;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000428
Simon Dardis68a204d2016-07-26 10:25:07 +0000429 // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
Daniel Sanderse8efff32016-03-14 16:24:05 +0000430 // Pick the zero form of the branch for readable assembly and for greater
431 // branch distance in non-microMIPS mode.
Simon Dardis4893aff2016-08-16 17:16:11 +0000432 // Additional MIPSR6 does not permit the use of register $zero for compact
433 // branches.
Simon Dardisd9d41f52016-04-05 12:50:29 +0000434 // FIXME: Certain atomic sequences on mips64 generate 32bit references to
435 // Mips::ZERO, which is incorrect. This test should be updated to use
436 // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
437 // are fixed.
Simon Dardis4893aff2016-08-16 17:16:11 +0000438 int ZeroOperandPosition = -1;
439 bool BranchWithZeroOperand = false;
440 if (I->isBranch() && !I->isPseudo()) {
441 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
442 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
443 BranchWithZeroOperand = ZeroOperandPosition != -1;
444 }
Simon Dardisd9d41f52016-04-05 12:50:29 +0000445
446 if (BranchWithZeroOperand) {
Daniel Sanderse8efff32016-03-14 16:24:05 +0000447 switch (NewOpc) {
448 case Mips::BEQC:
449 NewOpc = Mips::BEQZC;
450 break;
451 case Mips::BNEC:
452 NewOpc = Mips::BNEZC;
453 break;
454 case Mips::BGEC:
455 NewOpc = Mips::BGEZC;
456 break;
457 case Mips::BLTC:
458 NewOpc = Mips::BLTZC;
459 break;
Simon Dardis68a204d2016-07-26 10:25:07 +0000460 case Mips::BEQC64:
461 NewOpc = Mips::BEQZC64;
462 break;
463 case Mips::BNEC64:
464 NewOpc = Mips::BNEZC64;
465 break;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000466 }
467 }
468
Akira Hatanaka310e26a2013-05-13 17:57:42 +0000469 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
470
Simon Dardisd9d41f52016-04-05 12:50:29 +0000471 // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
472 // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
473 // implicit operand as copying the implicit operations of the instructio we're
474 // looking at will give us the correct flags.
475 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
476 NewOpc == Mips::JIALC64) {
477
478 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
479 MIB->RemoveOperand(0);
480
481 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
Diana Picus116bbab2017-01-13 09:58:52 +0000482 MIB.add(I->getOperand(J));
Simon Dardisd9d41f52016-04-05 12:50:29 +0000483 }
484
485 MIB.addImm(0);
486
Simon Dardisd9d41f52016-04-05 12:50:29 +0000487 } else {
Simon Dardisd9d41f52016-04-05 12:50:29 +0000488 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
Simon Dardis4893aff2016-08-16 17:16:11 +0000489 if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
490 continue;
491
Diana Picus116bbab2017-01-13 09:58:52 +0000492 MIB.add(I->getOperand(J));
Simon Dardisd9d41f52016-04-05 12:50:29 +0000493 }
494 }
495
496 MIB.copyImplicitOps(*I);
Akira Hatanaka310e26a2013-05-13 17:57:42 +0000497
498 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
499 return MIB;
500}
Petar Jovanovic9bff3b72017-03-31 14:31:55 +0000501
502bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
503 unsigned &SrcOpIdx2) const {
504 assert(!MI.isBundle() &&
505 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
506
507 const MCInstrDesc &MCID = MI.getDesc();
508 if (!MCID.isCommutable())
509 return false;
510
511 switch (MI.getOpcode()) {
512 case Mips::DPADD_U_H:
513 case Mips::DPADD_U_W:
514 case Mips::DPADD_U_D:
515 case Mips::DPADD_S_H:
516 case Mips::DPADD_S_W:
517 case Mips::DPADD_S_D: {
518 // The first operand is both input and output, so it should not commute
519 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
520 return false;
521
522 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
523 return false;
524 return true;
525 }
526 }
527 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
528}