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gerrit-public.fairphone.software / toolchain / llvm-project / d7d8fe0e9ca53feb5bca3f53208acad4195f90c0 / . / llvm / lib / Target / NVPTX / NVPTXISelLowering.cpp
blob: b324cdb7d667d159a094cee6c96709c0d57f1bae [file] [log] [blame]
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1//
2// The LLVM Compiler Infrastructure
3//
4// This file is distributed under the University of Illinois Open Source
5// License. See LICENSE.TXT for details.
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]14#include "NVPTXISelLowering.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]15#include "NVPTX.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]16#include "NVPTXTargetMachine.h"
17#include "NVPTXTargetObjectFile.h"
18#include "NVPTXUtilities.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]24#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
Chandler Carruth219b89b2014-03-04 11:01:28 +0000[diff] [blame]25#include "llvm/IR/CallSite.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/GlobalValue.h"
29#include "llvm/IR/IntrinsicInst.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/IR/Module.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]32#include "llvm/MC/MCSectionELF.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]37#include <sstream>
38
39#undef DEBUG_TYPE
40#define DEBUG_TYPE "nvptx-lower"
41
42using namespace llvm;
43
44static unsigned int uniqueCallSite = 0;
45
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]46static cl::opt<bool> sched4reg(
47 "nvptx-sched4reg",
48 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]49
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]50static bool IsPTXVectorType(MVT VT) {
51 switch (VT.SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]52 default:
53 return false;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]54 case MVT::v2i1:
55 case MVT::v4i1:
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]56 case MVT::v2i8:
57 case MVT::v4i8:
58 case MVT::v2i16:
59 case MVT::v4i16:
60 case MVT::v2i32:
61 case MVT::v4i32:
62 case MVT::v2i64:
63 case MVT::v2f32:
64 case MVT::v4f32:
65 case MVT::v2f64:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]66 return true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]67 }
68}
69
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]70/// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
71/// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
72/// into their primitive components.
73/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
74/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
75/// LowerCall, and LowerReturn.
76static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
77 SmallVectorImpl<EVT> &ValueVTs,
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]78 SmallVectorImpl<uint64_t> *Offsets = nullptr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]79 uint64_t StartingOffset = 0) {
80 SmallVector<EVT, 16> TempVTs;
81 SmallVector<uint64_t, 16> TempOffsets;
82
83 ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
84 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
85 EVT VT = TempVTs[i];
86 uint64_t Off = TempOffsets[i];
87 if (VT.isVector())
88 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
89 ValueVTs.push_back(VT.getVectorElementType());
90 if (Offsets)
91 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
92 }
93 else {
94 ValueVTs.push_back(VT);
95 if (Offsets)
96 Offsets->push_back(Off);
97 }
98 }
99}
100
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]101// NVPTXTargetLowering Constructor.
102NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]103 : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
104 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]105
106 // always lower memset, memcpy, and memmove intrinsics to load/store
107 // instructions, rather
108 // then generating calls to memset, mempcy or memmove.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]109 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
110 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
111 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]112
113 setBooleanContents(ZeroOrNegativeOneBooleanContent);
Justin Holewinskid7d8fe02014-06-27 18:35:42 +0000[diff] [blame^]114 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]115
116 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
117 // condition branches.
118 setJumpIsExpensive(true);
119
120 // By default, use the Source scheduling
121 if (sched4reg)
122 setSchedulingPreference(Sched::RegPressure);
123 else
124 setSchedulingPreference(Sched::Source);
125
126 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]127 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
128 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
129 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
130 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
131 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
132
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]133 // Operations not directly supported by NVPTX.
Tom Stellard3787b122014-06-10 16:01:29 +0000[diff] [blame]134 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
135 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
136 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
137 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
138 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
139 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
140 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]141 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
142 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
143 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
144 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
145 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
146 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
147 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
Justin Holewinski318c6252013-07-01 12:58:56 +0000[diff] [blame]148 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
149 // For others we will expand to a SHL/SRA pair.
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]155
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame]156 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
157 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
158 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
159 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
160 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
161 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
162
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]163 if (nvptxSubtarget.hasROT64()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]164 setOperationAction(ISD::ROTL, MVT::i64, Legal);
165 setOperationAction(ISD::ROTR, MVT::i64, Legal);
166 } else {
167 setOperationAction(ISD::ROTL, MVT::i64, Expand);
168 setOperationAction(ISD::ROTR, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]169 }
170 if (nvptxSubtarget.hasROT32()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]171 setOperationAction(ISD::ROTL, MVT::i32, Legal);
172 setOperationAction(ISD::ROTR, MVT::i32, Legal);
173 } else {
174 setOperationAction(ISD::ROTL, MVT::i32, Expand);
175 setOperationAction(ISD::ROTR, MVT::i32, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]176 }
177
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]178 setOperationAction(ISD::ROTL, MVT::i16, Expand);
179 setOperationAction(ISD::ROTR, MVT::i16, Expand);
180 setOperationAction(ISD::ROTL, MVT::i8, Expand);
181 setOperationAction(ISD::ROTR, MVT::i8, Expand);
182 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
183 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
184 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]185
186 // Indirect branch is not supported.
187 // This also disables Jump Table creation.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]188 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
189 setOperationAction(ISD::BRIND, MVT::Other, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]190
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]191 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
192 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]193
194 // We want to legalize constant related memmove and memcopy
195 // intrinsics.
196 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
197
198 // Turn FP extload into load/fextend
199 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
200 // Turn FP truncstore into trunc + store.
201 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
202
203 // PTX does not support load / store predicate registers
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]204 setOperationAction(ISD::LOAD, MVT::i1, Custom);
205 setOperationAction(ISD::STORE, MVT::i1, Custom);
206
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]207 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
208 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]209 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
210 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
211 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
212 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
213
214 // This is legal in NVPTX
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]215 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
216 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]217
218 // TRAP can be lowered to PTX trap
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]219 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]220
Justin Holewinski51cb1342013-07-01 12:59:04 +0000[diff] [blame]221 setOperationAction(ISD::ADDC, MVT::i64, Expand);
222 setOperationAction(ISD::ADDE, MVT::i64, Expand);
223
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]224 // Register custom handling for vector loads/stores
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]225 for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
226 ++i) {
227 MVT VT = (MVT::SimpleValueType) i;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]228 if (IsPTXVectorType(VT)) {
229 setOperationAction(ISD::LOAD, VT, Custom);
230 setOperationAction(ISD::STORE, VT, Custom);
231 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
232 }
233 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]234
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]235 // Custom handling for i8 intrinsics
236 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
237
Justin Holewinskidc372df2013-06-28 17:58:07 +0000[diff] [blame]238 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
239 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
240 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
241 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
243 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
244 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
245 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
248 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
249 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
250 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
251 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
252 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
253
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame]254 // We have some custom DAG combine patterns for these nodes
255 setTargetDAGCombine(ISD::ADD);
256 setTargetDAGCombine(ISD::AND);
257 setTargetDAGCombine(ISD::FADD);
258 setTargetDAGCombine(ISD::MUL);
259 setTargetDAGCombine(ISD::SHL);
260
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]261 // Now deduce the information based on the above mentioned
262 // actions
263 computeRegisterProperties();
264}
265
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]266const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
267 switch (Opcode) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]268 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]269 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]270 case NVPTXISD::CALL:
271 return "NVPTXISD::CALL";
272 case NVPTXISD::RET_FLAG:
273 return "NVPTXISD::RET_FLAG";
274 case NVPTXISD::Wrapper:
275 return "NVPTXISD::Wrapper";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]276 case NVPTXISD::DeclareParam:
277 return "NVPTXISD::DeclareParam";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]278 case NVPTXISD::DeclareScalarParam:
279 return "NVPTXISD::DeclareScalarParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]280 case NVPTXISD::DeclareRet:
281 return "NVPTXISD::DeclareRet";
282 case NVPTXISD::DeclareRetParam:
283 return "NVPTXISD::DeclareRetParam";
284 case NVPTXISD::PrintCall:
285 return "NVPTXISD::PrintCall";
286 case NVPTXISD::LoadParam:
287 return "NVPTXISD::LoadParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]288 case NVPTXISD::LoadParamV2:
289 return "NVPTXISD::LoadParamV2";
290 case NVPTXISD::LoadParamV4:
291 return "NVPTXISD::LoadParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]292 case NVPTXISD::StoreParam:
293 return "NVPTXISD::StoreParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]294 case NVPTXISD::StoreParamV2:
295 return "NVPTXISD::StoreParamV2";
296 case NVPTXISD::StoreParamV4:
297 return "NVPTXISD::StoreParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]298 case NVPTXISD::StoreParamS32:
299 return "NVPTXISD::StoreParamS32";
300 case NVPTXISD::StoreParamU32:
301 return "NVPTXISD::StoreParamU32";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]302 case NVPTXISD::CallArgBegin:
303 return "NVPTXISD::CallArgBegin";
304 case NVPTXISD::CallArg:
305 return "NVPTXISD::CallArg";
306 case NVPTXISD::LastCallArg:
307 return "NVPTXISD::LastCallArg";
308 case NVPTXISD::CallArgEnd:
309 return "NVPTXISD::CallArgEnd";
310 case NVPTXISD::CallVoid:
311 return "NVPTXISD::CallVoid";
312 case NVPTXISD::CallVal:
313 return "NVPTXISD::CallVal";
314 case NVPTXISD::CallSymbol:
315 return "NVPTXISD::CallSymbol";
316 case NVPTXISD::Prototype:
317 return "NVPTXISD::Prototype";
318 case NVPTXISD::MoveParam:
319 return "NVPTXISD::MoveParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]320 case NVPTXISD::StoreRetval:
321 return "NVPTXISD::StoreRetval";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]322 case NVPTXISD::StoreRetvalV2:
323 return "NVPTXISD::StoreRetvalV2";
324 case NVPTXISD::StoreRetvalV4:
325 return "NVPTXISD::StoreRetvalV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]326 case NVPTXISD::PseudoUseParam:
327 return "NVPTXISD::PseudoUseParam";
328 case NVPTXISD::RETURN:
329 return "NVPTXISD::RETURN";
330 case NVPTXISD::CallSeqBegin:
331 return "NVPTXISD::CallSeqBegin";
332 case NVPTXISD::CallSeqEnd:
333 return "NVPTXISD::CallSeqEnd";
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]334 case NVPTXISD::CallPrototype:
335 return "NVPTXISD::CallPrototype";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]336 case NVPTXISD::LoadV2:
337 return "NVPTXISD::LoadV2";
338 case NVPTXISD::LoadV4:
339 return "NVPTXISD::LoadV4";
340 case NVPTXISD::LDGV2:
341 return "NVPTXISD::LDGV2";
342 case NVPTXISD::LDGV4:
343 return "NVPTXISD::LDGV4";
344 case NVPTXISD::LDUV2:
345 return "NVPTXISD::LDUV2";
346 case NVPTXISD::LDUV4:
347 return "NVPTXISD::LDUV4";
348 case NVPTXISD::StoreV2:
349 return "NVPTXISD::StoreV2";
350 case NVPTXISD::StoreV4:
351 return "NVPTXISD::StoreV4";
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame]352 case NVPTXISD::FUN_SHFL_CLAMP:
353 return "NVPTXISD::FUN_SHFL_CLAMP";
354 case NVPTXISD::FUN_SHFR_CLAMP:
355 return "NVPTXISD::FUN_SHFR_CLAMP";
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame]356 case NVPTXISD::IMAD:
357 return "NVPTXISD::IMAD";
358 case NVPTXISD::MUL_WIDE_SIGNED:
359 return "NVPTXISD::MUL_WIDE_SIGNED";
360 case NVPTXISD::MUL_WIDE_UNSIGNED:
361 return "NVPTXISD::MUL_WIDE_UNSIGNED";
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]362 case NVPTXISD::Tex1DFloatI32: return "NVPTXISD::Tex1DFloatI32";
363 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
364 case NVPTXISD::Tex1DFloatFloatLevel:
365 return "NVPTXISD::Tex1DFloatFloatLevel";
366 case NVPTXISD::Tex1DFloatFloatGrad:
367 return "NVPTXISD::Tex1DFloatFloatGrad";
368 case NVPTXISD::Tex1DI32I32: return "NVPTXISD::Tex1DI32I32";
369 case NVPTXISD::Tex1DI32Float: return "NVPTXISD::Tex1DI32Float";
370 case NVPTXISD::Tex1DI32FloatLevel:
371 return "NVPTXISD::Tex1DI32FloatLevel";
372 case NVPTXISD::Tex1DI32FloatGrad:
373 return "NVPTXISD::Tex1DI32FloatGrad";
374 case NVPTXISD::Tex1DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
375 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
376 case NVPTXISD::Tex1DArrayFloatFloatLevel:
377 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
378 case NVPTXISD::Tex1DArrayFloatFloatGrad:
379 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
380 case NVPTXISD::Tex1DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
381 case NVPTXISD::Tex1DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
382 case NVPTXISD::Tex1DArrayI32FloatLevel:
383 return "NVPTXISD::Tex2DArrayI32FloatLevel";
384 case NVPTXISD::Tex1DArrayI32FloatGrad:
385 return "NVPTXISD::Tex2DArrayI32FloatGrad";
386 case NVPTXISD::Tex2DFloatI32: return "NVPTXISD::Tex2DFloatI32";
387 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
388 case NVPTXISD::Tex2DFloatFloatLevel:
389 return "NVPTXISD::Tex2DFloatFloatLevel";
390 case NVPTXISD::Tex2DFloatFloatGrad:
391 return "NVPTXISD::Tex2DFloatFloatGrad";
392 case NVPTXISD::Tex2DI32I32: return "NVPTXISD::Tex2DI32I32";
393 case NVPTXISD::Tex2DI32Float: return "NVPTXISD::Tex2DI32Float";
394 case NVPTXISD::Tex2DI32FloatLevel:
395 return "NVPTXISD::Tex2DI32FloatLevel";
396 case NVPTXISD::Tex2DI32FloatGrad:
397 return "NVPTXISD::Tex2DI32FloatGrad";
398 case NVPTXISD::Tex2DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
399 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
400 case NVPTXISD::Tex2DArrayFloatFloatLevel:
401 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
402 case NVPTXISD::Tex2DArrayFloatFloatGrad:
403 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
404 case NVPTXISD::Tex2DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
405 case NVPTXISD::Tex2DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
406 case NVPTXISD::Tex2DArrayI32FloatLevel:
407 return "NVPTXISD::Tex2DArrayI32FloatLevel";
408 case NVPTXISD::Tex2DArrayI32FloatGrad:
409 return "NVPTXISD::Tex2DArrayI32FloatGrad";
410 case NVPTXISD::Tex3DFloatI32: return "NVPTXISD::Tex3DFloatI32";
411 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
412 case NVPTXISD::Tex3DFloatFloatLevel:
413 return "NVPTXISD::Tex3DFloatFloatLevel";
414 case NVPTXISD::Tex3DFloatFloatGrad:
415 return "NVPTXISD::Tex3DFloatFloatGrad";
416 case NVPTXISD::Tex3DI32I32: return "NVPTXISD::Tex3DI32I32";
417 case NVPTXISD::Tex3DI32Float: return "NVPTXISD::Tex3DI32Float";
418 case NVPTXISD::Tex3DI32FloatLevel:
419 return "NVPTXISD::Tex3DI32FloatLevel";
420 case NVPTXISD::Tex3DI32FloatGrad:
421 return "NVPTXISD::Tex3DI32FloatGrad";
422
423 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
424 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
425 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
426 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
427 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
428 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
429 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
430 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
431 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
432
433 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
434 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
435 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
436 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
437 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
438 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
439 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
440 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
441 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
442
443 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
444 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
445 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
446 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
447 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
448 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
449 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
450 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
451 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
452
453 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
454 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
455 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
456 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
457 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
458 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
459 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
460 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
461 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
462
463 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
464 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
465 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
466 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
467 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
468 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
469 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
470 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
471 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]472 }
473}
474
Matt Arsenaultf751d622014-03-31 20:54:58 +0000[diff] [blame]475bool NVPTXTargetLowering::shouldSplitVectorType(EVT VT) const {
476 return VT.getScalarType() == MVT::i1;
Justin Holewinskibc451192012-11-29 14:26:24 +0000[diff] [blame]477}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]478
479SDValue
480NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]481 SDLoc dl(Op);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]482 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
483 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
484 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
485}
486
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]487std::string
488NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
489 const SmallVectorImpl<ISD::OutputArg> &Outs,
490 unsigned retAlignment,
491 const ImmutableCallSite *CS) const {
492
493 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
494 assert(isABI && "Non-ABI compilation is not supported");
495 if (!isABI)
496 return "";
497
498 std::stringstream O;
499 O << "prototype_" << uniqueCallSite << " : .callprototype ";
500
501 if (retTy->getTypeID() == Type::VoidTyID) {
502 O << "()";
503 } else {
504 O << "(";
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]505 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]506 unsigned size = 0;
507 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
508 size = ITy->getBitWidth();
509 if (size < 32)
510 size = 32;
511 } else {
512 assert(retTy->isFloatingPointTy() &&
513 "Floating point type expected here");
514 size = retTy->getPrimitiveSizeInBits();
515 }
516
517 O << ".param .b" << size << " _";
518 } else if (isa<PointerType>(retTy)) {
519 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
520 } else {
521 if ((retTy->getTypeID() == Type::StructTyID) || isa<VectorType>(retTy)) {
522 SmallVector<EVT, 16> vtparts;
523 ComputeValueVTs(*this, retTy, vtparts);
524 unsigned totalsz = 0;
525 for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
526 unsigned elems = 1;
527 EVT elemtype = vtparts[i];
528 if (vtparts[i].isVector()) {
529 elems = vtparts[i].getVectorNumElements();
530 elemtype = vtparts[i].getVectorElementType();
531 }
532 // TODO: no need to loop
533 for (unsigned j = 0, je = elems; j != je; ++j) {
534 unsigned sz = elemtype.getSizeInBits();
535 if (elemtype.isInteger() && (sz < 8))
536 sz = 8;
537 totalsz += sz / 8;
538 }
539 }
540 O << ".param .align " << retAlignment << " .b8 _[" << totalsz << "]";
541 } else {
542 assert(false && "Unknown return type");
543 }
544 }
545 O << ") ";
546 }
547 O << "_ (";
548
549 bool first = true;
550 MVT thePointerTy = getPointerTy();
551
552 unsigned OIdx = 0;
553 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
554 Type *Ty = Args[i].Ty;
555 if (!first) {
556 O << ", ";
557 }
558 first = false;
559
560 if (Outs[OIdx].Flags.isByVal() == false) {
561 if (Ty->isAggregateType() || Ty->isVectorTy()) {
562 unsigned align = 0;
563 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
564 const DataLayout *TD = getDataLayout();
565 // +1 because index 0 is reserved for return type alignment
566 if (!llvm::getAlign(*CallI, i + 1, align))
567 align = TD->getABITypeAlignment(Ty);
568 unsigned sz = TD->getTypeAllocSize(Ty);
569 O << ".param .align " << align << " .b8 ";
570 O << "_";
571 O << "[" << sz << "]";
572 // update the index for Outs
573 SmallVector<EVT, 16> vtparts;
574 ComputeValueVTs(*this, Ty, vtparts);
575 if (unsigned len = vtparts.size())
576 OIdx += len - 1;
577 continue;
578 }
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]579 // i8 types in IR will be i16 types in SDAG
580 assert((getValueType(Ty) == Outs[OIdx].VT ||
581 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]582 "type mismatch between callee prototype and arguments");
583 // scalar type
584 unsigned sz = 0;
585 if (isa<IntegerType>(Ty)) {
586 sz = cast<IntegerType>(Ty)->getBitWidth();
587 if (sz < 32)
588 sz = 32;
589 } else if (isa<PointerType>(Ty))
590 sz = thePointerTy.getSizeInBits();
591 else
592 sz = Ty->getPrimitiveSizeInBits();
593 O << ".param .b" << sz << " ";
594 O << "_";
595 continue;
596 }
597 const PointerType *PTy = dyn_cast<PointerType>(Ty);
598 assert(PTy && "Param with byval attribute should be a pointer type");
599 Type *ETy = PTy->getElementType();
600
601 unsigned align = Outs[OIdx].Flags.getByValAlign();
602 unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
603 O << ".param .align " << align << " .b8 ";
604 O << "_";
605 O << "[" << sz << "]";
606 }
607 O << ");";
608 return O.str();
609}
610
611unsigned
612NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
613 const ImmutableCallSite *CS,
614 Type *Ty,
615 unsigned Idx) const {
616 const DataLayout *TD = getDataLayout();
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]617 unsigned Align = 0;
618 const Value *DirectCallee = CS->getCalledFunction();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]619
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]620 if (!DirectCallee) {
621 // We don't have a direct function symbol, but that may be because of
622 // constant cast instructions in the call.
623 const Instruction *CalleeI = CS->getInstruction();
624 assert(CalleeI && "Call target is not a function or derived value?");
625
626 // With bitcast'd call targets, the instruction will be the call
627 if (isa<CallInst>(CalleeI)) {
628 // Check if we have call alignment metadata
629 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
630 return Align;
631
632 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
633 // Ignore any bitcast instructions
634 while(isa<ConstantExpr>(CalleeV)) {
635 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
636 if (!CE->isCast())
637 break;
638 // Look through the bitcast
639 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
640 }
641
642 // We have now looked past all of the bitcasts. Do we finally have a
643 // Function?
644 if (isa<Function>(CalleeV))
645 DirectCallee = CalleeV;
646 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]647 }
648
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]649 // Check for function alignment information if we found that the
650 // ultimate target is a Function
651 if (DirectCallee)
652 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
653 return Align;
654
655 // Call is indirect or alignment information is not available, fall back to
656 // the ABI type alignment
657 return TD->getABITypeAlignment(Ty);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]658}
659
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]660SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
661 SmallVectorImpl<SDValue> &InVals) const {
662 SelectionDAG &DAG = CLI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]663 SDLoc dl = CLI.DL;
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]664 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
665 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
666 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]667 SDValue Chain = CLI.Chain;
668 SDValue Callee = CLI.Callee;
669 bool &isTailCall = CLI.IsTailCall;
Saleem Abdulrasool9f664c12014-05-17 21:50:01 +0000[diff] [blame]670 ArgListTy &Args = CLI.getArgs();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]671 Type *retTy = CLI.RetTy;
672 ImmutableCallSite *CS = CLI.CS;
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]673
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]674 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]675 assert(isABI && "Non-ABI compilation is not supported");
676 if (!isABI)
677 return Chain;
678 const DataLayout *TD = getDataLayout();
679 MachineFunction &MF = DAG.getMachineFunction();
680 const Function *F = MF.getFunction();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]681
682 SDValue tempChain = Chain;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]683 Chain =
684 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
685 dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]686 SDValue InFlag = Chain.getValue(1);
687
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]688 unsigned paramCount = 0;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]689 // Args.size() and Outs.size() need not match.
690 // Outs.size() will be larger
691 // * if there is an aggregate argument with multiple fields (each field
692 // showing up separately in Outs)
693 // * if there is a vector argument with more than typical vector-length
694 // elements (generally if more than 4) where each vector element is
695 // individually present in Outs.
696 // So a different index should be used for indexing into Outs/OutVals.
697 // See similar issue in LowerFormalArguments.
698 unsigned OIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]699 // Declare the .params or .reg need to pass values
700 // to the function
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]701 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
702 EVT VT = Outs[OIdx].VT;
703 Type *Ty = Args[i].Ty;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]704
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]705 if (Outs[OIdx].Flags.isByVal() == false) {
706 if (Ty->isAggregateType()) {
707 // aggregate
708 SmallVector<EVT, 16> vtparts;
709 ComputeValueVTs(*this, Ty, vtparts);
710
711 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
712 // declare .param .align <align> .b8 .param<n>[<size>];
713 unsigned sz = TD->getTypeAllocSize(Ty);
714 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
715 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
716 DAG.getConstant(paramCount, MVT::i32),
717 DAG.getConstant(sz, MVT::i32), InFlag };
718 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]719 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]720 InFlag = Chain.getValue(1);
721 unsigned curOffset = 0;
722 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
723 unsigned elems = 1;
724 EVT elemtype = vtparts[j];
725 if (vtparts[j].isVector()) {
726 elems = vtparts[j].getVectorNumElements();
727 elemtype = vtparts[j].getVectorElementType();
728 }
729 for (unsigned k = 0, ke = elems; k != ke; ++k) {
730 unsigned sz = elemtype.getSizeInBits();
731 if (elemtype.isInteger() && (sz < 8))
732 sz = 8;
733 SDValue StVal = OutVals[OIdx];
734 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]735 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]736 }
737 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
738 SDValue CopyParamOps[] = { Chain,
739 DAG.getConstant(paramCount, MVT::i32),
740 DAG.getConstant(curOffset, MVT::i32),
741 StVal, InFlag };
742 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]743 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]744 elemtype, MachinePointerInfo());
745 InFlag = Chain.getValue(1);
746 curOffset += sz / 8;
747 ++OIdx;
748 }
749 }
750 if (vtparts.size() > 0)
751 --OIdx;
752 ++paramCount;
753 continue;
754 }
755 if (Ty->isVectorTy()) {
756 EVT ObjectVT = getValueType(Ty);
757 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
758 // declare .param .align <align> .b8 .param<n>[<size>];
759 unsigned sz = TD->getTypeAllocSize(Ty);
760 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
761 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
762 DAG.getConstant(paramCount, MVT::i32),
763 DAG.getConstant(sz, MVT::i32), InFlag };
764 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]765 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]766 InFlag = Chain.getValue(1);
767 unsigned NumElts = ObjectVT.getVectorNumElements();
768 EVT EltVT = ObjectVT.getVectorElementType();
769 EVT MemVT = EltVT;
770 bool NeedExtend = false;
771 if (EltVT.getSizeInBits() < 16) {
772 NeedExtend = true;
773 EltVT = MVT::i16;
774 }
775
776 // V1 store
777 if (NumElts == 1) {
778 SDValue Elt = OutVals[OIdx++];
779 if (NeedExtend)
780 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
781
782 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
783 SDValue CopyParamOps[] = { Chain,
784 DAG.getConstant(paramCount, MVT::i32),
785 DAG.getConstant(0, MVT::i32), Elt,
786 InFlag };
787 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]788 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]789 MemVT, MachinePointerInfo());
790 InFlag = Chain.getValue(1);
791 } else if (NumElts == 2) {
792 SDValue Elt0 = OutVals[OIdx++];
793 SDValue Elt1 = OutVals[OIdx++];
794 if (NeedExtend) {
795 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
796 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
797 }
798
799 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
800 SDValue CopyParamOps[] = { Chain,
801 DAG.getConstant(paramCount, MVT::i32),
802 DAG.getConstant(0, MVT::i32), Elt0, Elt1,
803 InFlag };
804 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]805 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]806 MemVT, MachinePointerInfo());
807 InFlag = Chain.getValue(1);
808 } else {
809 unsigned curOffset = 0;
810 // V4 stores
811 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
812 // the
813 // vector will be expanded to a power of 2 elements, so we know we can
814 // always round up to the next multiple of 4 when creating the vector
815 // stores.
816 // e.g. 4 elem => 1 st.v4
817 // 6 elem => 2 st.v4
818 // 8 elem => 2 st.v4
819 // 11 elem => 3 st.v4
820 unsigned VecSize = 4;
821 if (EltVT.getSizeInBits() == 64)
822 VecSize = 2;
823
824 // This is potentially only part of a vector, so assume all elements
825 // are packed together.
826 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
827
828 for (unsigned i = 0; i < NumElts; i += VecSize) {
829 // Get values
830 SDValue StoreVal;
831 SmallVector<SDValue, 8> Ops;
832 Ops.push_back(Chain);
833 Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
834 Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
835
836 unsigned Opc = NVPTXISD::StoreParamV2;
837
838 StoreVal = OutVals[OIdx++];
839 if (NeedExtend)
840 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
841 Ops.push_back(StoreVal);
842
843 if (i + 1 < NumElts) {
844 StoreVal = OutVals[OIdx++];
845 if (NeedExtend)
846 StoreVal =
847 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
848 } else {
849 StoreVal = DAG.getUNDEF(EltVT);
850 }
851 Ops.push_back(StoreVal);
852
853 if (VecSize == 4) {
854 Opc = NVPTXISD::StoreParamV4;
855 if (i + 2 < NumElts) {
856 StoreVal = OutVals[OIdx++];
857 if (NeedExtend)
858 StoreVal =
859 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
860 } else {
861 StoreVal = DAG.getUNDEF(EltVT);
862 }
863 Ops.push_back(StoreVal);
864
865 if (i + 3 < NumElts) {
866 StoreVal = OutVals[OIdx++];
867 if (NeedExtend)
868 StoreVal =
869 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
870 } else {
871 StoreVal = DAG.getUNDEF(EltVT);
872 }
873 Ops.push_back(StoreVal);
874 }
875
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]876 Ops.push_back(InFlag);
877
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]878 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]879 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
880 MemVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]881 InFlag = Chain.getValue(1);
882 curOffset += PerStoreOffset;
883 }
884 }
885 ++paramCount;
886 --OIdx;
887 continue;
888 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]889 // Plain scalar
890 // for ABI, declare .param .b<size> .param<n>;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]891 unsigned sz = VT.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]892 bool needExtend = false;
893 if (VT.isInteger()) {
894 if (sz < 16)
895 needExtend = true;
896 if (sz < 32)
897 sz = 32;
898 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]899 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
900 SDValue DeclareParamOps[] = { Chain,
901 DAG.getConstant(paramCount, MVT::i32),
902 DAG.getConstant(sz, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]903 DAG.getConstant(0, MVT::i32), InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]904 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]905 DeclareParamOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]906 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]907 SDValue OutV = OutVals[OIdx];
908 if (needExtend) {
909 // zext/sext i1 to i16
910 unsigned opc = ISD::ZERO_EXTEND;
911 if (Outs[OIdx].Flags.isSExt())
912 opc = ISD::SIGN_EXTEND;
913 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
914 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]915 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
916 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]917 DAG.getConstant(0, MVT::i32), OutV, InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]918
919 unsigned opcode = NVPTXISD::StoreParam;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]920 if (Outs[OIdx].Flags.isZExt())
921 opcode = NVPTXISD::StoreParamU32;
922 else if (Outs[OIdx].Flags.isSExt())
923 opcode = NVPTXISD::StoreParamS32;
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]924 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]925 VT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]926
927 InFlag = Chain.getValue(1);
928 ++paramCount;
929 continue;
930 }
931 // struct or vector
932 SmallVector<EVT, 16> vtparts;
933 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]934 assert(PTy && "Type of a byval parameter should be pointer");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]935 ComputeValueVTs(*this, PTy->getElementType(), vtparts);
936
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]937 // declare .param .align <align> .b8 .param<n>[<size>];
938 unsigned sz = Outs[OIdx].Flags.getByValSize();
939 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
940 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
941 // so we don't need to worry about natural alignment or not.
942 // See TargetLowering::LowerCallTo().
943 SDValue DeclareParamOps[] = {
944 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
945 DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
946 InFlag
947 };
948 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]949 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]950 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]951 unsigned curOffset = 0;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]952 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]953 unsigned elems = 1;
954 EVT elemtype = vtparts[j];
955 if (vtparts[j].isVector()) {
956 elems = vtparts[j].getVectorNumElements();
957 elemtype = vtparts[j].getVectorElementType();
958 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]959 for (unsigned k = 0, ke = elems; k != ke; ++k) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]960 unsigned sz = elemtype.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]961 if (elemtype.isInteger() && (sz < 8))
962 sz = 8;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]963 SDValue srcAddr =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]964 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]965 DAG.getConstant(curOffset, getPointerTy()));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]966 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
967 MachinePointerInfo(), false, false, false,
968 0);
969 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]970 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]971 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]972 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
973 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]974 DAG.getConstant(curOffset, MVT::i32), theVal,
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]975 InFlag };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]976 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]977 CopyParamOps, elemtype,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]978 MachinePointerInfo());
979
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]980 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]981 curOffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]982 }
983 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]984 ++paramCount;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]985 }
986
987 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
988 unsigned retAlignment = 0;
989
990 // Handle Result
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]991 if (Ins.size() > 0) {
992 SmallVector<EVT, 16> resvtparts;
993 ComputeValueVTs(*this, retTy, resvtparts);
994
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]995 // Declare
996 // .param .align 16 .b8 retval0[<size-in-bytes>], or
997 // .param .b<size-in-bits> retval0
998 unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]999 if (retTy->isSingleValueType()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1000 // Scalar needs to be at least 32bit wide
1001 if (resultsz < 32)
1002 resultsz = 32;
1003 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1004 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
1005 DAG.getConstant(resultsz, MVT::i32),
1006 DAG.getConstant(0, MVT::i32), InFlag };
1007 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1008 DeclareRetOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1009 InFlag = Chain.getValue(1);
1010 } else {
1011 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1012 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1013 SDValue DeclareRetOps[] = { Chain,
1014 DAG.getConstant(retAlignment, MVT::i32),
1015 DAG.getConstant(resultsz / 8, MVT::i32),
1016 DAG.getConstant(0, MVT::i32), InFlag };
1017 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1018 DeclareRetOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1019 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1020 }
1021 }
1022
1023 if (!Func) {
1024 // This is indirect function call case : PTX requires a prototype of the
1025 // form
1026 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1027 // to be emitted, and the label has to used as the last arg of call
1028 // instruction.
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]1029 // The prototype is embedded in a string and put as the operand for a
1030 // CallPrototype SDNode which will print out to the value of the string.
1031 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1032 std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
1033 const char *ProtoStr =
1034 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1035 SDValue ProtoOps[] = {
1036 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1037 };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1038 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1039 InFlag = Chain.getValue(1);
1040 }
1041 // Op to just print "call"
1042 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1043 SDValue PrintCallOps[] = {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1044 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1045 };
1046 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1047 dl, PrintCallVTs, PrintCallOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1048 InFlag = Chain.getValue(1);
1049
1050 // Ops to print out the function name
1051 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1052 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1053 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1054 InFlag = Chain.getValue(1);
1055
1056 // Ops to print out the param list
1057 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1058 SDValue CallArgBeginOps[] = { Chain, InFlag };
1059 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1060 CallArgBeginOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1061 InFlag = Chain.getValue(1);
1062
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1063 for (unsigned i = 0, e = paramCount; i != e; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1064 unsigned opcode;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1065 if (i == (e - 1))
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1066 opcode = NVPTXISD::LastCallArg;
1067 else
1068 opcode = NVPTXISD::CallArg;
1069 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1070 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1071 DAG.getConstant(i, MVT::i32), InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1072 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1073 InFlag = Chain.getValue(1);
1074 }
1075 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1076 SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1077 InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1078 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1079 InFlag = Chain.getValue(1);
1080
1081 if (!Func) {
1082 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1083 SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1084 InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1085 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1086 InFlag = Chain.getValue(1);
1087 }
1088
1089 // Generate loads from param memory/moves from registers for result
1090 if (Ins.size() > 0) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1091 unsigned resoffset = 0;
1092 if (retTy && retTy->isVectorTy()) {
1093 EVT ObjectVT = getValueType(retTy);
1094 unsigned NumElts = ObjectVT.getVectorNumElements();
1095 EVT EltVT = ObjectVT.getVectorElementType();
Benjamin Kramer3cc579a2013-06-29 22:51:12 +0000[diff] [blame]1096 assert(nvTM->getTargetLowering()->getNumRegisters(F->getContext(),
1097 ObjectVT) == NumElts &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1098 "Vector was not scalarized");
1099 unsigned sz = EltVT.getSizeInBits();
1100 bool needTruncate = sz < 16 ? true : false;
1101
1102 if (NumElts == 1) {
1103 // Just a simple load
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1104 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1105 if (needTruncate) {
1106 // If loading i1 result, generate
1107 // load i16
1108 // trunc i16 to i1
1109 LoadRetVTs.push_back(MVT::i16);
1110 } else
1111 LoadRetVTs.push_back(EltVT);
1112 LoadRetVTs.push_back(MVT::Other);
1113 LoadRetVTs.push_back(MVT::Glue);
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1114 SmallVector<SDValue, 4> LoadRetOps;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1115 LoadRetOps.push_back(Chain);
1116 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1117 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1118 LoadRetOps.push_back(InFlag);
1119 SDValue retval = DAG.getMemIntrinsicNode(
1120 NVPTXISD::LoadParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1121 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1122 Chain = retval.getValue(1);
1123 InFlag = retval.getValue(2);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1124 SDValue Ret0 = retval;
1125 if (needTruncate)
1126 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1127 InVals.push_back(Ret0);
1128 } else if (NumElts == 2) {
1129 // LoadV2
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1130 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1131 if (needTruncate) {
1132 // If loading i1 result, generate
1133 // load i16
1134 // trunc i16 to i1
1135 LoadRetVTs.push_back(MVT::i16);
1136 LoadRetVTs.push_back(MVT::i16);
1137 } else {
1138 LoadRetVTs.push_back(EltVT);
1139 LoadRetVTs.push_back(EltVT);
1140 }
1141 LoadRetVTs.push_back(MVT::Other);
1142 LoadRetVTs.push_back(MVT::Glue);
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1143 SmallVector<SDValue, 4> LoadRetOps;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1144 LoadRetOps.push_back(Chain);
1145 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1146 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1147 LoadRetOps.push_back(InFlag);
1148 SDValue retval = DAG.getMemIntrinsicNode(
1149 NVPTXISD::LoadParamV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1150 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1151 Chain = retval.getValue(2);
1152 InFlag = retval.getValue(3);
1153 SDValue Ret0 = retval.getValue(0);
1154 SDValue Ret1 = retval.getValue(1);
1155 if (needTruncate) {
1156 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1157 InVals.push_back(Ret0);
1158 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1159 InVals.push_back(Ret1);
1160 } else {
1161 InVals.push_back(Ret0);
1162 InVals.push_back(Ret1);
1163 }
1164 } else {
1165 // Split into N LoadV4
1166 unsigned Ofst = 0;
1167 unsigned VecSize = 4;
1168 unsigned Opc = NVPTXISD::LoadParamV4;
1169 if (EltVT.getSizeInBits() == 64) {
1170 VecSize = 2;
1171 Opc = NVPTXISD::LoadParamV2;
1172 }
1173 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1174 for (unsigned i = 0; i < NumElts; i += VecSize) {
1175 SmallVector<EVT, 8> LoadRetVTs;
1176 if (needTruncate) {
1177 // If loading i1 result, generate
1178 // load i16
1179 // trunc i16 to i1
1180 for (unsigned j = 0; j < VecSize; ++j)
1181 LoadRetVTs.push_back(MVT::i16);
1182 } else {
1183 for (unsigned j = 0; j < VecSize; ++j)
1184 LoadRetVTs.push_back(EltVT);
1185 }
1186 LoadRetVTs.push_back(MVT::Other);
1187 LoadRetVTs.push_back(MVT::Glue);
1188 SmallVector<SDValue, 4> LoadRetOps;
1189 LoadRetOps.push_back(Chain);
1190 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1191 LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
1192 LoadRetOps.push_back(InFlag);
1193 SDValue retval = DAG.getMemIntrinsicNode(
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1194 Opc, dl, DAG.getVTList(LoadRetVTs),
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1195 LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1196 if (VecSize == 2) {
1197 Chain = retval.getValue(2);
1198 InFlag = retval.getValue(3);
1199 } else {
1200 Chain = retval.getValue(4);
1201 InFlag = retval.getValue(5);
1202 }
1203
1204 for (unsigned j = 0; j < VecSize; ++j) {
1205 if (i + j >= NumElts)
1206 break;
1207 SDValue Elt = retval.getValue(j);
1208 if (needTruncate)
1209 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1210 InVals.push_back(Elt);
1211 }
1212 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1213 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1214 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1215 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1216 SmallVector<EVT, 16> VTs;
1217 ComputePTXValueVTs(*this, retTy, VTs);
1218 assert(VTs.size() == Ins.size() && "Bad value decomposition");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1219 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1220 unsigned sz = VTs[i].getSizeInBits();
1221 bool needTruncate = sz < 8 ? true : false;
1222 if (VTs[i].isInteger() && (sz < 8))
1223 sz = 8;
1224
1225 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1226 EVT TheLoadType = VTs[i];
1227 if (retTy->isIntegerTy() &&
1228 TD->getTypeAllocSizeInBits(retTy) < 32) {
1229 // This is for integer types only, and specifically not for
1230 // aggregates.
1231 LoadRetVTs.push_back(MVT::i32);
1232 TheLoadType = MVT::i32;
1233 } else if (sz < 16) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1234 // If loading i1/i8 result, generate
1235 // load i8 (-> i16)
1236 // trunc i16 to i1/i8
1237 LoadRetVTs.push_back(MVT::i16);
1238 } else
1239 LoadRetVTs.push_back(Ins[i].VT);
1240 LoadRetVTs.push_back(MVT::Other);
1241 LoadRetVTs.push_back(MVT::Glue);
1242
1243 SmallVector<SDValue, 4> LoadRetOps;
1244 LoadRetOps.push_back(Chain);
1245 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1246 LoadRetOps.push_back(DAG.getConstant(resoffset, MVT::i32));
1247 LoadRetOps.push_back(InFlag);
1248 SDValue retval = DAG.getMemIntrinsicNode(
1249 NVPTXISD::LoadParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1250 DAG.getVTList(LoadRetVTs), LoadRetOps,
1251 TheLoadType, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1252 Chain = retval.getValue(1);
1253 InFlag = retval.getValue(2);
1254 SDValue Ret0 = retval.getValue(0);
1255 if (needTruncate)
1256 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1257 InVals.push_back(Ret0);
1258 resoffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1259 }
1260 }
1261 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1262
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1263 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
1264 DAG.getIntPtrConstant(uniqueCallSite + 1, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +0000[diff] [blame]1265 InFlag, dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1266 uniqueCallSite++;
1267
1268 // set isTailCall to false for now, until we figure out how to express
1269 // tail call optimization in PTX
1270 isTailCall = false;
1271 return Chain;
1272}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1273
1274// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1275// (see LegalizeDAG.cpp). This is slow and uses local memory.
1276// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1277SDValue
1278NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1279 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1280 SDLoc dl(Node);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1281 SmallVector<SDValue, 8> Ops;
1282 unsigned NumOperands = Node->getNumOperands();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1283 for (unsigned i = 0; i < NumOperands; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1284 SDValue SubOp = Node->getOperand(i);
1285 EVT VVT = SubOp.getNode()->getValueType(0);
1286 EVT EltVT = VVT.getVectorElementType();
1287 unsigned NumSubElem = VVT.getVectorNumElements();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1288 for (unsigned j = 0; j < NumSubElem; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1289 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1290 DAG.getIntPtrConstant(j)));
1291 }
1292 }
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1293 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1294}
1295
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame]1296/// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1297/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1298/// amount, or
1299/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1300/// amount.
1301SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1302 SelectionDAG &DAG) const {
1303 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1304 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1305
1306 EVT VT = Op.getValueType();
1307 unsigned VTBits = VT.getSizeInBits();
1308 SDLoc dl(Op);
1309 SDValue ShOpLo = Op.getOperand(0);
1310 SDValue ShOpHi = Op.getOperand(1);
1311 SDValue ShAmt = Op.getOperand(2);
1312 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1313
1314 if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
1315
1316 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1317 // {dHi, dLo} = {aHi, aLo} >> Amt
1318 // dHi = aHi >> Amt
1319 // dLo = shf.r.clamp aLo, aHi, Amt
1320
1321 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1322 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1323 ShAmt);
1324
1325 SDValue Ops[2] = { Lo, Hi };
1326 return DAG.getMergeValues(Ops, dl);
1327 }
1328 else {
1329
1330 // {dHi, dLo} = {aHi, aLo} >> Amt
1331 // - if (Amt>=size) then
1332 // dLo = aHi >> (Amt-size)
1333 // dHi = aHi >> Amt (this is either all 0 or all 1)
1334 // else
1335 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1336 // dHi = aHi >> Amt
1337
1338 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1339 DAG.getConstant(VTBits, MVT::i32), ShAmt);
1340 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1341 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1342 DAG.getConstant(VTBits, MVT::i32));
1343 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1344 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1345 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1346
1347 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1348 DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
1349 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1350 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1351
1352 SDValue Ops[2] = { Lo, Hi };
1353 return DAG.getMergeValues(Ops, dl);
1354 }
1355}
1356
1357/// LowerShiftLeftParts - Lower SHL_PARTS, which
1358/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1359/// amount, or
1360/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1361/// amount.
1362SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1363 SelectionDAG &DAG) const {
1364 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1365 assert(Op.getOpcode() == ISD::SHL_PARTS);
1366
1367 EVT VT = Op.getValueType();
1368 unsigned VTBits = VT.getSizeInBits();
1369 SDLoc dl(Op);
1370 SDValue ShOpLo = Op.getOperand(0);
1371 SDValue ShOpHi = Op.getOperand(1);
1372 SDValue ShAmt = Op.getOperand(2);
1373
1374 if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
1375
1376 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1377 // {dHi, dLo} = {aHi, aLo} << Amt
1378 // dHi = shf.l.clamp aLo, aHi, Amt
1379 // dLo = aLo << Amt
1380
1381 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1382 ShAmt);
1383 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1384
1385 SDValue Ops[2] = { Lo, Hi };
1386 return DAG.getMergeValues(Ops, dl);
1387 }
1388 else {
1389
1390 // {dHi, dLo} = {aHi, aLo} << Amt
1391 // - if (Amt>=size) then
1392 // dLo = aLo << Amt (all 0)
1393 // dLo = aLo << (Amt-size)
1394 // else
1395 // dLo = aLo << Amt
1396 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1397
1398 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1399 DAG.getConstant(VTBits, MVT::i32), ShAmt);
1400 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1401 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1402 DAG.getConstant(VTBits, MVT::i32));
1403 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1404 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1405 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1406
1407 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1408 DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
1409 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1410 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1411
1412 SDValue Ops[2] = { Lo, Hi };
1413 return DAG.getMergeValues(Ops, dl);
1414 }
1415}
1416
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1417SDValue
1418NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1419 switch (Op.getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1420 case ISD::RETURNADDR:
1421 return SDValue();
1422 case ISD::FRAMEADDR:
1423 return SDValue();
1424 case ISD::GlobalAddress:
1425 return LowerGlobalAddress(Op, DAG);
1426 case ISD::INTRINSIC_W_CHAIN:
1427 return Op;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1428 case ISD::BUILD_VECTOR:
1429 case ISD::EXTRACT_SUBVECTOR:
1430 return Op;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1431 case ISD::CONCAT_VECTORS:
1432 return LowerCONCAT_VECTORS(Op, DAG);
1433 case ISD::STORE:
1434 return LowerSTORE(Op, DAG);
1435 case ISD::LOAD:
1436 return LowerLOAD(Op, DAG);
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame]1437 case ISD::SHL_PARTS:
1438 return LowerShiftLeftParts(Op, DAG);
1439 case ISD::SRA_PARTS:
1440 case ISD::SRL_PARTS:
1441 return LowerShiftRightParts(Op, DAG);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1442 default:
David Blaikie891d0a32012-05-04 22:34:16 +0000[diff] [blame]1443 llvm_unreachable("Custom lowering not defined for operation");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1444 }
1445}
1446
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1447SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1448 if (Op.getValueType() == MVT::i1)
1449 return LowerLOADi1(Op, DAG);
1450 else
1451 return SDValue();
1452}
1453
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1454// v = ld i1* addr
1455// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1456// v1 = ld i8* addr (-> i16)
1457// v = trunc i16 to i1
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1458SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1459 SDNode *Node = Op.getNode();
1460 LoadSDNode *LD = cast<LoadSDNode>(Node);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1461 SDLoc dl(Node);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1462 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1463 assert(Node->getValueType(0) == MVT::i1 &&
1464 "Custom lowering for i1 load only");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1465 SDValue newLD =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1466 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1467 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1468 LD->isInvariant(), LD->getAlignment());
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1469 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1470 // The legalizer (the caller) is expecting two values from the legalized
1471 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1472 // in LegalizeDAG.cpp which also uses MergeValues.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1473 SDValue Ops[] = { result, LD->getChain() };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1474 return DAG.getMergeValues(Ops, dl);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1475}
1476
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1477SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1478 EVT ValVT = Op.getOperand(1).getValueType();
1479 if (ValVT == MVT::i1)
1480 return LowerSTOREi1(Op, DAG);
1481 else if (ValVT.isVector())
1482 return LowerSTOREVector(Op, DAG);
1483 else
1484 return SDValue();
1485}
1486
1487SDValue
1488NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1489 SDNode *N = Op.getNode();
1490 SDValue Val = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1491 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1492 EVT ValVT = Val.getValueType();
1493
1494 if (ValVT.isVector()) {
1495 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1496 // legal. We can (and should) split that into 2 stores of <2 x double> here
1497 // but I'm leaving that as a TODO for now.
1498 if (!ValVT.isSimple())
1499 return SDValue();
1500 switch (ValVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1501 default:
1502 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1503 case MVT::v2i8:
1504 case MVT::v2i16:
1505 case MVT::v2i32:
1506 case MVT::v2i64:
1507 case MVT::v2f32:
1508 case MVT::v2f64:
1509 case MVT::v4i8:
1510 case MVT::v4i16:
1511 case MVT::v4i32:
1512 case MVT::v4f32:
1513 // This is a "native" vector type
1514 break;
1515 }
1516
1517 unsigned Opcode = 0;
1518 EVT EltVT = ValVT.getVectorElementType();
1519 unsigned NumElts = ValVT.getVectorNumElements();
1520
1521 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1522 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]1523 // stored type to i16 and propagate the "real" type as the memory type.
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1524 bool NeedExt = false;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1525 if (EltVT.getSizeInBits() < 16)
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1526 NeedExt = true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1527
1528 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1529 default:
1530 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1531 case 2:
1532 Opcode = NVPTXISD::StoreV2;
1533 break;
1534 case 4: {
1535 Opcode = NVPTXISD::StoreV4;
1536 break;
1537 }
1538 }
1539
1540 SmallVector<SDValue, 8> Ops;
1541
1542 // First is the chain
1543 Ops.push_back(N->getOperand(0));
1544
1545 // Then the split values
1546 for (unsigned i = 0; i < NumElts; ++i) {
1547 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1548 DAG.getIntPtrConstant(i));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1549 if (NeedExt)
1550 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1551 Ops.push_back(ExtVal);
1552 }
1553
1554 // Then any remaining arguments
1555 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1556 Ops.push_back(N->getOperand(i));
1557 }
1558
1559 MemSDNode *MemSD = cast<MemSDNode>(N);
1560
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1561 SDValue NewSt = DAG.getMemIntrinsicNode(
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1562 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1563 MemSD->getMemoryVT(), MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1564
1565 //return DCI.CombineTo(N, NewSt, true);
1566 return NewSt;
1567 }
1568
1569 return SDValue();
1570}
1571
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1572// st i1 v, addr
1573// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1574// v1 = zxt v to i16
1575// st.u8 i16, addr
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1576SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1577 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1578 SDLoc dl(Node);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1579 StoreSDNode *ST = cast<StoreSDNode>(Node);
1580 SDValue Tmp1 = ST->getChain();
1581 SDValue Tmp2 = ST->getBasePtr();
1582 SDValue Tmp3 = ST->getValue();
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1583 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1584 unsigned Alignment = ST->getAlignment();
1585 bool isVolatile = ST->isVolatile();
1586 bool isNonTemporal = ST->isNonTemporal();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1587 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1588 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1589 ST->getPointerInfo(), MVT::i8, isNonTemporal,
1590 isVolatile, Alignment);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1591 return Result;
1592}
1593
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1594SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
1595 int idx, EVT v) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1596 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
1597 std::stringstream suffix;
1598 suffix << idx;
1599 *name += suffix.str();
1600 return DAG.getTargetExternalSymbol(name->c_str(), v);
1601}
1602
1603SDValue
1604NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
Justin Holewinskia2a63d22013-08-06 14:13:27 +0000[diff] [blame]1605 std::string ParamSym;
1606 raw_string_ostream ParamStr(ParamSym);
1607
1608 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
1609 ParamStr.flush();
1610
1611 std::string *SavedStr =
1612 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
1613 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1614}
1615
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1616SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1617 return getExtSymb(DAG, ".HLPPARAM", idx);
1618}
1619
1620// Check to see if the kernel argument is image*_t or sampler_t
1621
1622bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1623 static const char *const specialTypes[] = { "struct._image2d_t",
1624 "struct._image3d_t",
1625 "struct._sampler_t" };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1626
1627 const Type *Ty = arg->getType();
1628 const PointerType *PTy = dyn_cast<PointerType>(Ty);
1629
1630 if (!PTy)
1631 return false;
1632
1633 if (!context)
1634 return false;
1635
1636 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
Justin Holewinskifb711152012-12-05 20:50:28 +0000[diff] [blame]1637 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1638
Craig Toppere4260f92012-05-24 04:22:05 +0000[diff] [blame]1639 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1640 if (TypeName == specialTypes[i])
1641 return true;
1642
1643 return false;
1644}
1645
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1646SDValue NVPTXTargetLowering::LowerFormalArguments(
1647 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1648 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1649 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1650 MachineFunction &MF = DAG.getMachineFunction();
Micah Villmowcdfe20b2012-10-08 16:38:25 +0000[diff] [blame]1651 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1652
1653 const Function *F = MF.getFunction();
Bill Wendlinge94d8432012-12-07 23:16:57 +0000[diff] [blame]1654 const AttributeSet &PAL = F->getAttributes();
Eric Christopher2ecb77e2014-06-27 03:45:49 +0000[diff] [blame]1655 const TargetLowering *TLI = DAG.getTarget().getTargetLowering();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1656
1657 SDValue Root = DAG.getRoot();
1658 std::vector<SDValue> OutChains;
1659
1660 bool isKernel = llvm::isKernelFunction(*F);
1661 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1662 assert(isABI && "Non-ABI compilation is not supported");
1663 if (!isABI)
1664 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1665
1666 std::vector<Type *> argTypes;
1667 std::vector<const Argument *> theArgs;
1668 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1669 I != E; ++I) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1670 theArgs.push_back(I);
1671 argTypes.push_back(I->getType());
1672 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1673 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
1674 // Ins.size() will be larger
1675 // * if there is an aggregate argument with multiple fields (each field
1676 // showing up separately in Ins)
1677 // * if there is a vector argument with more than typical vector-length
1678 // elements (generally if more than 4) where each vector element is
1679 // individually present in Ins.
1680 // So a different index should be used for indexing into Ins.
1681 // See similar issue in LowerCall.
1682 unsigned InsIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1683
1684 int idx = 0;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1685 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1686 Type *Ty = argTypes[i];
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1687
1688 // If the kernel argument is image*_t or sampler_t, convert it to
1689 // a i32 constant holding the parameter position. This can later
1690 // matched in the AsmPrinter to output the correct mangled name.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1691 if (isImageOrSamplerVal(
1692 theArgs[i],
1693 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1694 : nullptr))) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1695 assert(isKernel && "Only kernels can have image/sampler params");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1696 InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1697 continue;
1698 }
1699
1700 if (theArgs[i]->use_empty()) {
1701 // argument is dead
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1702 if (Ty->isAggregateType()) {
1703 SmallVector<EVT, 16> vtparts;
1704
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1705 ComputePTXValueVTs(*this, Ty, vtparts);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1706 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1707 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1708 ++parti) {
1709 EVT partVT = vtparts[parti];
1710 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, partVT));
1711 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1712 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1713 if (vtparts.size() > 0)
1714 --InsIdx;
1715 continue;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1716 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1717 if (Ty->isVectorTy()) {
1718 EVT ObjectVT = getValueType(Ty);
1719 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
1720 for (unsigned parti = 0; parti < NumRegs; ++parti) {
1721 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
1722 ++InsIdx;
1723 }
1724 if (NumRegs > 0)
1725 --InsIdx;
1726 continue;
1727 }
1728 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1729 continue;
1730 }
1731
1732 // In the following cases, assign a node order of "idx+1"
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1733 // to newly created nodes. The SDNodes for params have to
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1734 // appear in the same order as their order of appearance
1735 // in the original function. "idx+1" holds that order.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1736 if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1737 if (Ty->isAggregateType()) {
1738 SmallVector<EVT, 16> vtparts;
1739 SmallVector<uint64_t, 16> offsets;
1740
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1741 // NOTE: Here, we lose the ability to issue vector loads for vectors
1742 // that are a part of a struct. This should be investigated in the
1743 // future.
1744 ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1745 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1746 bool aggregateIsPacked = false;
1747 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
1748 aggregateIsPacked = STy->isPacked();
1749
1750 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1751 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1752 ++parti) {
1753 EVT partVT = vtparts[parti];
1754 Value *srcValue = Constant::getNullValue(
1755 PointerType::get(partVT.getTypeForEVT(F->getContext()),
1756 llvm::ADDRESS_SPACE_PARAM));
1757 SDValue srcAddr =
1758 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1759 DAG.getConstant(offsets[parti], getPointerTy()));
1760 unsigned partAlign =
1761 aggregateIsPacked ? 1
1762 : TD->getABITypeAlignment(
1763 partVT.getTypeForEVT(F->getContext()));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1764 SDValue p;
1765 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
1766 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1767 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1768 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1769 MachinePointerInfo(srcValue), partVT, false,
1770 false, partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1771 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1772 p = DAG.getLoad(partVT, dl, Root, srcAddr,
1773 MachinePointerInfo(srcValue), false, false, false,
1774 partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1775 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1776 if (p.getNode())
1777 p.getNode()->setIROrder(idx + 1);
1778 InVals.push_back(p);
1779 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1780 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1781 if (vtparts.size() > 0)
1782 --InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1783 continue;
1784 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1785 if (Ty->isVectorTy()) {
1786 EVT ObjectVT = getValueType(Ty);
Justin Holewinskiaaaf2892013-06-25 12:22:21 +0000[diff] [blame]1787 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1788 unsigned NumElts = ObjectVT.getVectorNumElements();
1789 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
1790 "Vector was not scalarized");
1791 unsigned Ofst = 0;
1792 EVT EltVT = ObjectVT.getVectorElementType();
1793
1794 // V1 load
1795 // f32 = load ...
1796 if (NumElts == 1) {
1797 // We only have one element, so just directly load it
1798 Value *SrcValue = Constant::getNullValue(PointerType::get(
1799 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1800 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1801 DAG.getConstant(Ofst, getPointerTy()));
1802 SDValue P = DAG.getLoad(
1803 EltVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1804 false, true,
1805 TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
1806 if (P.getNode())
1807 P.getNode()->setIROrder(idx + 1);
1808
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1809 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1810 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1811 InVals.push_back(P);
1812 Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
1813 ++InsIdx;
1814 } else if (NumElts == 2) {
1815 // V2 load
1816 // f32,f32 = load ...
1817 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
1818 Value *SrcValue = Constant::getNullValue(PointerType::get(
1819 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1820 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1821 DAG.getConstant(Ofst, getPointerTy()));
1822 SDValue P = DAG.getLoad(
1823 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1824 false, true,
1825 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1826 if (P.getNode())
1827 P.getNode()->setIROrder(idx + 1);
1828
1829 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1830 DAG.getIntPtrConstant(0));
1831 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1832 DAG.getIntPtrConstant(1));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1833
1834 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1835 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
1836 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1837 }
1838
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1839 InVals.push_back(Elt0);
1840 InVals.push_back(Elt1);
1841 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1842 InsIdx += 2;
1843 } else {
1844 // V4 loads
1845 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1846 // the
1847 // vector will be expanded to a power of 2 elements, so we know we can
1848 // always round up to the next multiple of 4 when creating the vector
1849 // loads.
1850 // e.g. 4 elem => 1 ld.v4
1851 // 6 elem => 2 ld.v4
1852 // 8 elem => 2 ld.v4
1853 // 11 elem => 3 ld.v4
1854 unsigned VecSize = 4;
1855 if (EltVT.getSizeInBits() == 64) {
1856 VecSize = 2;
1857 }
1858 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1859 for (unsigned i = 0; i < NumElts; i += VecSize) {
1860 Value *SrcValue = Constant::getNullValue(
1861 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
1862 llvm::ADDRESS_SPACE_PARAM));
1863 SDValue SrcAddr =
1864 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1865 DAG.getConstant(Ofst, getPointerTy()));
1866 SDValue P = DAG.getLoad(
1867 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1868 false, true,
1869 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1870 if (P.getNode())
1871 P.getNode()->setIROrder(idx + 1);
1872
1873 for (unsigned j = 0; j < VecSize; ++j) {
1874 if (i + j >= NumElts)
1875 break;
1876 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1877 DAG.getIntPtrConstant(j));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1878 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1879 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1880 InVals.push_back(Elt);
1881 }
1882 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1883 }
Justin Holewinski4f5bc9b2013-11-11 19:28:16 +0000[diff] [blame]1884 InsIdx += NumElts;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1885 }
1886
1887 if (NumElts > 0)
1888 --InsIdx;
1889 continue;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1890 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1891 // A plain scalar.
1892 EVT ObjectVT = getValueType(Ty);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1893 // If ABI, load from the param symbol
1894 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1895 Value *srcValue = Constant::getNullValue(PointerType::get(
1896 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1897 SDValue p;
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1898 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
1899 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1900 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1901 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1902 MachinePointerInfo(srcValue), ObjectVT, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1903 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1904 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1905 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
1906 MachinePointerInfo(srcValue), false, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1907 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1908 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1909 if (p.getNode())
1910 p.getNode()->setIROrder(idx + 1);
1911 InVals.push_back(p);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1912 continue;
1913 }
1914
1915 // Param has ByVal attribute
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1916 // Return MoveParam(param symbol).
1917 // Ideally, the param symbol can be returned directly,
1918 // but when SDNode builder decides to use it in a CopyToReg(),
1919 // machine instruction fails because TargetExternalSymbol
1920 // (not lowered) is target dependent, and CopyToReg assumes
1921 // the source is lowered.
1922 EVT ObjectVT = getValueType(Ty);
1923 assert(ObjectVT == Ins[InsIdx].VT &&
1924 "Ins type did not match function type");
1925 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1926 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
1927 if (p.getNode())
1928 p.getNode()->setIROrder(idx + 1);
1929 if (isKernel)
1930 InVals.push_back(p);
1931 else {
1932 SDValue p2 = DAG.getNode(
1933 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
1934 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
1935 InVals.push_back(p2);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1936 }
1937 }
1938
1939 // Clang will check explicit VarArg and issue error if any. However, Clang
1940 // will let code with
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1941 // implicit var arg like f() pass. See bug 617733.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1942 // We treat this case as if the arg list is empty.
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1943 // if (F.isVarArg()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1944 // assert(0 && "VarArg not supported yet!");
1945 //}
1946
1947 if (!OutChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1948 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1949
1950 return Chain;
1951}
1952
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1953
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1954SDValue
1955NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1956 bool isVarArg,
1957 const SmallVectorImpl<ISD::OutputArg> &Outs,
1958 const SmallVectorImpl<SDValue> &OutVals,
1959 SDLoc dl, SelectionDAG &DAG) const {
1960 MachineFunction &MF = DAG.getMachineFunction();
1961 const Function *F = MF.getFunction();
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1962 Type *RetTy = F->getReturnType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1963 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1964
1965 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1966 assert(isABI && "Non-ABI compilation is not supported");
1967 if (!isABI)
1968 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1969
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1970 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1971 // If we have a vector type, the OutVals array will be the scalarized
1972 // components and we have combine them into 1 or more vector stores.
1973 unsigned NumElts = VTy->getNumElements();
1974 assert(NumElts == Outs.size() && "Bad scalarization of return value");
1975
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1976 // const_cast can be removed in later LLVM versions
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1977 EVT EltVT = getValueType(RetTy).getVectorElementType();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1978 bool NeedExtend = false;
1979 if (EltVT.getSizeInBits() < 16)
1980 NeedExtend = true;
1981
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1982 // V1 store
1983 if (NumElts == 1) {
1984 SDValue StoreVal = OutVals[0];
1985 // We only have one element, so just directly store it
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1986 if (NeedExtend)
1987 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1988 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
1989 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1990 DAG.getVTList(MVT::Other), Ops,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1991 EltVT, MachinePointerInfo());
1992
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1993 } else if (NumElts == 2) {
1994 // V2 store
1995 SDValue StoreVal0 = OutVals[0];
1996 SDValue StoreVal1 = OutVals[1];
1997
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1998 if (NeedExtend) {
1999 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2000 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2001 }
2002
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2003 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
2004 StoreVal1 };
2005 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2006 DAG.getVTList(MVT::Other), Ops,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2007 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2008 } else {
2009 // V4 stores
2010 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2011 // vector will be expanded to a power of 2 elements, so we know we can
2012 // always round up to the next multiple of 4 when creating the vector
2013 // stores.
2014 // e.g. 4 elem => 1 st.v4
2015 // 6 elem => 2 st.v4
2016 // 8 elem => 2 st.v4
2017 // 11 elem => 3 st.v4
2018
2019 unsigned VecSize = 4;
2020 if (OutVals[0].getValueType().getSizeInBits() == 64)
2021 VecSize = 2;
2022
2023 unsigned Offset = 0;
2024
2025 EVT VecVT =
2026 EVT::getVectorVT(F->getContext(), OutVals[0].getValueType(), VecSize);
2027 unsigned PerStoreOffset =
2028 TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2029
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2030 for (unsigned i = 0; i < NumElts; i += VecSize) {
2031 // Get values
2032 SDValue StoreVal;
2033 SmallVector<SDValue, 8> Ops;
2034 Ops.push_back(Chain);
2035 Ops.push_back(DAG.getConstant(Offset, MVT::i32));
2036 unsigned Opc = NVPTXISD::StoreRetvalV2;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2037 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2038
2039 StoreVal = OutVals[i];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2040 if (NeedExtend)
2041 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2042 Ops.push_back(StoreVal);
2043
2044 if (i + 1 < NumElts) {
2045 StoreVal = OutVals[i + 1];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2046 if (NeedExtend)
2047 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2048 } else {
2049 StoreVal = DAG.getUNDEF(ExtendedVT);
2050 }
2051 Ops.push_back(StoreVal);
2052
2053 if (VecSize == 4) {
2054 Opc = NVPTXISD::StoreRetvalV4;
2055 if (i + 2 < NumElts) {
2056 StoreVal = OutVals[i + 2];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2057 if (NeedExtend)
2058 StoreVal =
2059 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2060 } else {
2061 StoreVal = DAG.getUNDEF(ExtendedVT);
2062 }
2063 Ops.push_back(StoreVal);
2064
2065 if (i + 3 < NumElts) {
2066 StoreVal = OutVals[i + 3];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2067 if (NeedExtend)
2068 StoreVal =
2069 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2070 } else {
2071 StoreVal = DAG.getUNDEF(ExtendedVT);
2072 }
2073 Ops.push_back(StoreVal);
2074 }
2075
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2076 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2077 Chain =
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2078 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2079 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2080 Offset += PerStoreOffset;
2081 }
2082 }
2083 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2084 SmallVector<EVT, 16> ValVTs;
2085 // const_cast is necessary since we are still using an LLVM version from
2086 // before the type system re-write.
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2087 ComputePTXValueVTs(*this, RetTy, ValVTs);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2088 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2089
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2090 unsigned SizeSoFar = 0;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2091 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2092 SDValue theVal = OutVals[i];
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2093 EVT TheValType = theVal.getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2094 unsigned numElems = 1;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2095 if (TheValType.isVector())
2096 numElems = TheValType.getVectorNumElements();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2097 for (unsigned j = 0, je = numElems; j != je; ++j) {
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2098 SDValue TmpVal = theVal;
2099 if (TheValType.isVector())
2100 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2101 TheValType.getVectorElementType(), TmpVal,
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2102 DAG.getIntPtrConstant(j));
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2103 EVT TheStoreType = ValVTs[i];
2104 if (RetTy->isIntegerTy() &&
2105 TD->getTypeAllocSizeInBits(RetTy) < 32) {
2106 // The following zero-extension is for integer types only, and
2107 // specifically not for aggregates.
2108 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2109 TheStoreType = MVT::i32;
2110 }
2111 else if (TmpVal.getValueType().getSizeInBits() < 16)
2112 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2113
2114 SDValue Ops[] = { Chain, DAG.getConstant(SizeSoFar, MVT::i32), TmpVal };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2115 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2116 DAG.getVTList(MVT::Other), Ops,
2117 TheStoreType,
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2118 MachinePointerInfo());
2119 if(TheValType.isVector())
2120 SizeSoFar +=
2121 TheStoreType.getVectorElementType().getStoreSizeInBits() / 8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2122 else
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2123 SizeSoFar += TheStoreType.getStoreSizeInBits()/8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2124 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2125 }
2126 }
2127
2128 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2129}
2130
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2131
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2132void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2133 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2134 SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2135 if (Constraint.length() > 1)
2136 return;
2137 else
2138 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2139}
2140
2141// NVPTX suuport vector of legal types of any length in Intrinsics because the
2142// NVPTX specific type legalizer
2143// will legalize them to the PTX supported length.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2144bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2145 if (isTypeLegal(VT))
2146 return true;
2147 if (VT.isVector()) {
2148 MVT eVT = VT.getVectorElementType();
2149 if (isTypeLegal(eVT))
2150 return true;
2151 }
2152 return false;
2153}
2154
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2155static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2156 switch (Intrinsic) {
2157 default:
2158 return 0;
2159
2160 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2161 return NVPTXISD::Tex1DFloatI32;
2162 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2163 return NVPTXISD::Tex1DFloatFloat;
2164 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2165 return NVPTXISD::Tex1DFloatFloatLevel;
2166 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2167 return NVPTXISD::Tex1DFloatFloatGrad;
2168 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2169 return NVPTXISD::Tex1DI32I32;
2170 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2171 return NVPTXISD::Tex1DI32Float;
2172 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2173 return NVPTXISD::Tex1DI32FloatLevel;
2174 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2175 return NVPTXISD::Tex1DI32FloatGrad;
2176
2177 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2178 return NVPTXISD::Tex1DArrayFloatI32;
2179 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2180 return NVPTXISD::Tex1DArrayFloatFloat;
2181 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2182 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2183 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2184 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2185 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2186 return NVPTXISD::Tex1DArrayI32I32;
2187 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2188 return NVPTXISD::Tex1DArrayI32Float;
2189 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2190 return NVPTXISD::Tex1DArrayI32FloatLevel;
2191 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2192 return NVPTXISD::Tex1DArrayI32FloatGrad;
2193
2194 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2195 return NVPTXISD::Tex2DFloatI32;
2196 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2197 return NVPTXISD::Tex2DFloatFloat;
2198 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2199 return NVPTXISD::Tex2DFloatFloatLevel;
2200 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2201 return NVPTXISD::Tex2DFloatFloatGrad;
2202 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2203 return NVPTXISD::Tex2DI32I32;
2204 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2205 return NVPTXISD::Tex2DI32Float;
2206 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2207 return NVPTXISD::Tex2DI32FloatLevel;
2208 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2209 return NVPTXISD::Tex2DI32FloatGrad;
2210
2211 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2212 return NVPTXISD::Tex2DArrayFloatI32;
2213 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2214 return NVPTXISD::Tex2DArrayFloatFloat;
2215 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2216 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2217 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2218 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2219 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2220 return NVPTXISD::Tex2DArrayI32I32;
2221 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2222 return NVPTXISD::Tex2DArrayI32Float;
2223 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2224 return NVPTXISD::Tex2DArrayI32FloatLevel;
2225 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2226 return NVPTXISD::Tex2DArrayI32FloatGrad;
2227
2228 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2229 return NVPTXISD::Tex3DFloatI32;
2230 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2231 return NVPTXISD::Tex3DFloatFloat;
2232 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2233 return NVPTXISD::Tex3DFloatFloatLevel;
2234 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2235 return NVPTXISD::Tex3DFloatFloatGrad;
2236 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2237 return NVPTXISD::Tex3DI32I32;
2238 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2239 return NVPTXISD::Tex3DI32Float;
2240 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2241 return NVPTXISD::Tex3DI32FloatLevel;
2242 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32:
2243 return NVPTXISD::Tex3DI32FloatGrad;
2244 }
2245}
2246
2247static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2248 switch (Intrinsic) {
2249 default:
2250 return 0;
2251 case Intrinsic::nvvm_suld_1d_i8_trap:
2252 return NVPTXISD::Suld1DI8Trap;
2253 case Intrinsic::nvvm_suld_1d_i16_trap:
2254 return NVPTXISD::Suld1DI16Trap;
2255 case Intrinsic::nvvm_suld_1d_i32_trap:
2256 return NVPTXISD::Suld1DI32Trap;
2257 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2258 return NVPTXISD::Suld1DV2I8Trap;
2259 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2260 return NVPTXISD::Suld1DV2I16Trap;
2261 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2262 return NVPTXISD::Suld1DV2I32Trap;
2263 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2264 return NVPTXISD::Suld1DV4I8Trap;
2265 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2266 return NVPTXISD::Suld1DV4I16Trap;
2267 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2268 return NVPTXISD::Suld1DV4I32Trap;
2269 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2270 return NVPTXISD::Suld1DArrayI8Trap;
2271 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2272 return NVPTXISD::Suld1DArrayI16Trap;
2273 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2274 return NVPTXISD::Suld1DArrayI32Trap;
2275 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2276 return NVPTXISD::Suld1DArrayV2I8Trap;
2277 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2278 return NVPTXISD::Suld1DArrayV2I16Trap;
2279 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2280 return NVPTXISD::Suld1DArrayV2I32Trap;
2281 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2282 return NVPTXISD::Suld1DArrayV4I8Trap;
2283 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2284 return NVPTXISD::Suld1DArrayV4I16Trap;
2285 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2286 return NVPTXISD::Suld1DArrayV4I32Trap;
2287 case Intrinsic::nvvm_suld_2d_i8_trap:
2288 return NVPTXISD::Suld2DI8Trap;
2289 case Intrinsic::nvvm_suld_2d_i16_trap:
2290 return NVPTXISD::Suld2DI16Trap;
2291 case Intrinsic::nvvm_suld_2d_i32_trap:
2292 return NVPTXISD::Suld2DI32Trap;
2293 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2294 return NVPTXISD::Suld2DV2I8Trap;
2295 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2296 return NVPTXISD::Suld2DV2I16Trap;
2297 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2298 return NVPTXISD::Suld2DV2I32Trap;
2299 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2300 return NVPTXISD::Suld2DV4I8Trap;
2301 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2302 return NVPTXISD::Suld2DV4I16Trap;
2303 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2304 return NVPTXISD::Suld2DV4I32Trap;
2305 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2306 return NVPTXISD::Suld2DArrayI8Trap;
2307 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2308 return NVPTXISD::Suld2DArrayI16Trap;
2309 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2310 return NVPTXISD::Suld2DArrayI32Trap;
2311 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2312 return NVPTXISD::Suld2DArrayV2I8Trap;
2313 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2314 return NVPTXISD::Suld2DArrayV2I16Trap;
2315 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2316 return NVPTXISD::Suld2DArrayV2I32Trap;
2317 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2318 return NVPTXISD::Suld2DArrayV4I8Trap;
2319 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2320 return NVPTXISD::Suld2DArrayV4I16Trap;
2321 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2322 return NVPTXISD::Suld2DArrayV4I32Trap;
2323 case Intrinsic::nvvm_suld_3d_i8_trap:
2324 return NVPTXISD::Suld3DI8Trap;
2325 case Intrinsic::nvvm_suld_3d_i16_trap:
2326 return NVPTXISD::Suld3DI16Trap;
2327 case Intrinsic::nvvm_suld_3d_i32_trap:
2328 return NVPTXISD::Suld3DI32Trap;
2329 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2330 return NVPTXISD::Suld3DV2I8Trap;
2331 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2332 return NVPTXISD::Suld3DV2I16Trap;
2333 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2334 return NVPTXISD::Suld3DV2I32Trap;
2335 case Intrinsic::nvvm_suld_3d_v4i8_trap:
2336 return NVPTXISD::Suld3DV4I8Trap;
2337 case Intrinsic::nvvm_suld_3d_v4i16_trap:
2338 return NVPTXISD::Suld3DV4I16Trap;
2339 case Intrinsic::nvvm_suld_3d_v4i32_trap:
2340 return NVPTXISD::Suld3DV4I32Trap;
2341 }
2342}
2343
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2344// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
2345// TgtMemIntrinsic
2346// because we need the information that is only available in the "Value" type
2347// of destination
2348// pointer. In particular, the address space information.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2349bool NVPTXTargetLowering::getTgtMemIntrinsic(
2350 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2351 switch (Intrinsic) {
2352 default:
2353 return false;
2354
2355 case Intrinsic::nvvm_atomic_load_add_f32:
2356 Info.opc = ISD::INTRINSIC_W_CHAIN;
2357 Info.memVT = MVT::f32;
2358 Info.ptrVal = I.getArgOperand(0);
2359 Info.offset = 0;
2360 Info.vol = 0;
2361 Info.readMem = true;
2362 Info.writeMem = true;
2363 Info.align = 0;
2364 return true;
2365
2366 case Intrinsic::nvvm_atomic_load_inc_32:
2367 case Intrinsic::nvvm_atomic_load_dec_32:
2368 Info.opc = ISD::INTRINSIC_W_CHAIN;
2369 Info.memVT = MVT::i32;
2370 Info.ptrVal = I.getArgOperand(0);
2371 Info.offset = 0;
2372 Info.vol = 0;
2373 Info.readMem = true;
2374 Info.writeMem = true;
2375 Info.align = 0;
2376 return true;
2377
2378 case Intrinsic::nvvm_ldu_global_i:
2379 case Intrinsic::nvvm_ldu_global_f:
2380 case Intrinsic::nvvm_ldu_global_p:
2381
2382 Info.opc = ISD::INTRINSIC_W_CHAIN;
2383 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2384 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2385 else if (Intrinsic == Intrinsic::nvvm_ldu_global_p)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2386 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2387 else
2388 Info.memVT = MVT::f32;
2389 Info.ptrVal = I.getArgOperand(0);
2390 Info.offset = 0;
2391 Info.vol = 0;
2392 Info.readMem = true;
2393 Info.writeMem = false;
2394 Info.align = 0;
2395 return true;
2396
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2397 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2398 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2399 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2400 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2401 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2402 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2403 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2404 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2405 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2406 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2407 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2408 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2409 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2410 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2411 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2412 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2413 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2414 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2415 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2416 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32: {
2417 Info.opc = getOpcForTextureInstr(Intrinsic);
2418 Info.memVT = MVT::f32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2419 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2420 Info.offset = 0;
2421 Info.vol = 0;
2422 Info.readMem = true;
2423 Info.writeMem = false;
2424 Info.align = 16;
2425 return true;
2426 }
2427 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2428 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2429 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2430 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2431 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2432 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2433 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2434 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2435 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2436 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2437 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2438 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2439 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2440 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2441 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2442 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2443 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2444 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2445 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2446 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32: {
2447 Info.opc = getOpcForTextureInstr(Intrinsic);
2448 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2449 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2450 Info.offset = 0;
2451 Info.vol = 0;
2452 Info.readMem = true;
2453 Info.writeMem = false;
2454 Info.align = 16;
2455 return true;
2456 }
2457 case Intrinsic::nvvm_suld_1d_i8_trap:
2458 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2459 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2460 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2461 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2462 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2463 case Intrinsic::nvvm_suld_2d_i8_trap:
2464 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2465 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2466 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2467 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2468 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2469 case Intrinsic::nvvm_suld_3d_i8_trap:
2470 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2471 case Intrinsic::nvvm_suld_3d_v4i8_trap: {
2472 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2473 Info.memVT = MVT::i8;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2474 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2475 Info.offset = 0;
2476 Info.vol = 0;
2477 Info.readMem = true;
2478 Info.writeMem = false;
2479 Info.align = 16;
2480 return true;
2481 }
2482 case Intrinsic::nvvm_suld_1d_i16_trap:
2483 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2484 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2485 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2486 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2487 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2488 case Intrinsic::nvvm_suld_2d_i16_trap:
2489 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2490 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2491 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2492 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2493 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2494 case Intrinsic::nvvm_suld_3d_i16_trap:
2495 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2496 case Intrinsic::nvvm_suld_3d_v4i16_trap: {
2497 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2498 Info.memVT = MVT::i16;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2499 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2500 Info.offset = 0;
2501 Info.vol = 0;
2502 Info.readMem = true;
2503 Info.writeMem = false;
2504 Info.align = 16;
2505 return true;
2506 }
2507 case Intrinsic::nvvm_suld_1d_i32_trap:
2508 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2509 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2510 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2511 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2512 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2513 case Intrinsic::nvvm_suld_2d_i32_trap:
2514 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2515 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2516 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2517 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2518 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2519 case Intrinsic::nvvm_suld_3d_i32_trap:
2520 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2521 case Intrinsic::nvvm_suld_3d_v4i32_trap: {
2522 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2523 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2524 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2525 Info.offset = 0;
2526 Info.vol = 0;
2527 Info.readMem = true;
2528 Info.writeMem = false;
2529 Info.align = 16;
2530 return true;
2531 }
2532
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2533 }
2534 return false;
2535}
2536
2537/// isLegalAddressingMode - Return true if the addressing mode represented
2538/// by AM is legal for this target, for a load/store of the specified type.
2539/// Used to guide target specific optimizations, like loop strength reduction
2540/// (LoopStrengthReduce.cpp) and memory optimization for address mode
2541/// (CodeGenPrepare.cpp)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2542bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2543 Type *Ty) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2544
2545 // AddrMode - This represents an addressing mode of:
2546 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2547 //
2548 // The legal address modes are
2549 // - [avar]
2550 // - [areg]
2551 // - [areg+immoff]
2552 // - [immAddr]
2553
2554 if (AM.BaseGV) {
2555 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
2556 return false;
2557 return true;
2558 }
2559
2560 switch (AM.Scale) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2561 case 0: // "r", "r+i" or "i" is allowed
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2562 break;
2563 case 1:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2564 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2565 return false;
2566 // Otherwise we have r+i.
2567 break;
2568 default:
2569 // No scale > 1 is allowed
2570 return false;
2571 }
2572 return true;
2573}
2574
2575//===----------------------------------------------------------------------===//
2576// NVPTX Inline Assembly Support
2577//===----------------------------------------------------------------------===//
2578
2579/// getConstraintType - Given a constraint letter, return the type of
2580/// constraint it is for this target.
2581NVPTXTargetLowering::ConstraintType
2582NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
2583 if (Constraint.size() == 1) {
2584 switch (Constraint[0]) {
2585 default:
2586 break;
2587 case 'r':
2588 case 'h':
2589 case 'c':
2590 case 'l':
2591 case 'f':
2592 case 'd':
2593 case '0':
2594 case 'N':
2595 return C_RegisterClass;
2596 }
2597 }
2598 return TargetLowering::getConstraintType(Constraint);
2599}
2600
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2601std::pair<unsigned, const TargetRegisterClass *>
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2602NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Chad Rosier295bd432013-06-22 18:37:38 +0000[diff] [blame]2603 MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2604 if (Constraint.size() == 1) {
2605 switch (Constraint[0]) {
2606 case 'c':
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2607 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2608 case 'h':
2609 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
2610 case 'r':
2611 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
2612 case 'l':
2613 case 'N':
2614 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
2615 case 'f':
2616 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
2617 case 'd':
2618 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
2619 }
2620 }
2621 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2622}
2623
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2624/// getFunctionAlignment - Return the Log2 alignment of this function.
2625unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
2626 return 4;
2627}
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2628
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame]2629//===----------------------------------------------------------------------===//
2630// NVPTX DAG Combining
2631//===----------------------------------------------------------------------===//
2632
2633extern unsigned FMAContractLevel;
2634
2635/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
2636/// operands N0 and N1. This is a helper for PerformADDCombine that is
2637/// called with the default operands, and if that fails, with commuted
2638/// operands.
2639static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
2640 TargetLowering::DAGCombinerInfo &DCI,
2641 const NVPTXSubtarget &Subtarget,
2642 CodeGenOpt::Level OptLevel) {
2643 SelectionDAG &DAG = DCI.DAG;
2644 // Skip non-integer, non-scalar case
2645 EVT VT=N0.getValueType();
2646 if (VT.isVector())
2647 return SDValue();
2648
2649 // fold (add (mul a, b), c) -> (mad a, b, c)
2650 //
2651 if (N0.getOpcode() == ISD::MUL) {
2652 assert (VT.isInteger());
2653 // For integer:
2654 // Since integer multiply-add costs the same as integer multiply
2655 // but is more costly than integer add, do the fusion only when
2656 // the mul is only used in the add.
2657 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
2658 !N0.getNode()->hasOneUse())
2659 return SDValue();
2660
2661 // Do the folding
2662 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
2663 N0.getOperand(0), N0.getOperand(1), N1);
2664 }
2665 else if (N0.getOpcode() == ISD::FMUL) {
2666 if (VT == MVT::f32 || VT == MVT::f64) {
2667 if (FMAContractLevel == 0)
2668 return SDValue();
2669
2670 // For floating point:
2671 // Do the fusion only when the mul has less than 5 uses and all
2672 // are add.
2673 // The heuristic is that if a use is not an add, then that use
2674 // cannot be fused into fma, therefore mul is still needed anyway.
2675 // If there are more than 4 uses, even if they are all add, fusing
2676 // them will increase register pressue.
2677 //
2678 int numUses = 0;
2679 int nonAddCount = 0;
2680 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2681 UE = N0.getNode()->use_end();
2682 UI != UE; ++UI) {
2683 numUses++;
2684 SDNode *User = *UI;
2685 if (User->getOpcode() != ISD::FADD)
2686 ++nonAddCount;
2687 }
2688 if (numUses >= 5)
2689 return SDValue();
2690 if (nonAddCount) {
2691 int orderNo = N->getIROrder();
2692 int orderNo2 = N0.getNode()->getIROrder();
2693 // simple heuristics here for considering potential register
2694 // pressure, the logics here is that the differnce are used
2695 // to measure the distance between def and use, the longer distance
2696 // more likely cause register pressure.
2697 if (orderNo - orderNo2 < 500)
2698 return SDValue();
2699
2700 // Now, check if at least one of the FMUL's operands is live beyond the node N,
2701 // which guarantees that the FMA will not increase register pressure at node N.
2702 bool opIsLive = false;
2703 const SDNode *left = N0.getOperand(0).getNode();
2704 const SDNode *right = N0.getOperand(1).getNode();
2705
2706 if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
2707 opIsLive = true;
2708
2709 if (!opIsLive)
2710 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
2711 SDNode *User = *UI;
2712 int orderNo3 = User->getIROrder();
2713 if (orderNo3 > orderNo) {
2714 opIsLive = true;
2715 break;
2716 }
2717 }
2718
2719 if (!opIsLive)
2720 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
2721 SDNode *User = *UI;
2722 int orderNo3 = User->getIROrder();
2723 if (orderNo3 > orderNo) {
2724 opIsLive = true;
2725 break;
2726 }
2727 }
2728
2729 if (!opIsLive)
2730 return SDValue();
2731 }
2732
2733 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
2734 N0.getOperand(0), N0.getOperand(1), N1);
2735 }
2736 }
2737
2738 return SDValue();
2739}
2740
2741/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2742///
2743static SDValue PerformADDCombine(SDNode *N,
2744 TargetLowering::DAGCombinerInfo &DCI,
2745 const NVPTXSubtarget &Subtarget,
2746 CodeGenOpt::Level OptLevel) {
2747 SDValue N0 = N->getOperand(0);
2748 SDValue N1 = N->getOperand(1);
2749
2750 // First try with the default operand order.
2751 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
2752 OptLevel);
2753 if (Result.getNode())
2754 return Result;
2755
2756 // If that didn't work, try again with the operands commuted.
2757 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
2758}
2759
2760static SDValue PerformANDCombine(SDNode *N,
2761 TargetLowering::DAGCombinerInfo &DCI) {
2762 // The type legalizer turns a vector load of i8 values into a zextload to i16
2763 // registers, optionally ANY_EXTENDs it (if target type is integer),
2764 // and ANDs off the high 8 bits. Since we turn this load into a
2765 // target-specific DAG node, the DAG combiner fails to eliminate these AND
2766 // nodes. Do that here.
2767 SDValue Val = N->getOperand(0);
2768 SDValue Mask = N->getOperand(1);
2769
2770 if (isa<ConstantSDNode>(Val)) {
2771 std::swap(Val, Mask);
2772 }
2773
2774 SDValue AExt;
2775 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
2776 if (Val.getOpcode() == ISD::ANY_EXTEND) {
2777 AExt = Val;
2778 Val = Val->getOperand(0);
2779 }
2780
2781 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
2782 Val = Val->getOperand(0);
2783 }
2784
2785 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
2786 Val->getOpcode() == NVPTXISD::LoadV4) {
2787 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
2788 if (!MaskCnst) {
2789 // Not an AND with a constant
2790 return SDValue();
2791 }
2792
2793 uint64_t MaskVal = MaskCnst->getZExtValue();
2794 if (MaskVal != 0xff) {
2795 // Not an AND that chops off top 8 bits
2796 return SDValue();
2797 }
2798
2799 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
2800 if (!Mem) {
2801 // Not a MemSDNode?!?
2802 return SDValue();
2803 }
2804
2805 EVT MemVT = Mem->getMemoryVT();
2806 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
2807 // We only handle the i8 case
2808 return SDValue();
2809 }
2810
2811 unsigned ExtType =
2812 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
2813 getZExtValue();
2814 if (ExtType == ISD::SEXTLOAD) {
2815 // If for some reason the load is a sextload, the and is needed to zero
2816 // out the high 8 bits
2817 return SDValue();
2818 }
2819
2820 bool AddTo = false;
2821 if (AExt.getNode() != 0) {
2822 // Re-insert the ext as a zext.
2823 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2824 AExt.getValueType(), Val);
2825 AddTo = true;
2826 }
2827
2828 // If we get here, the AND is unnecessary. Just replace it with the load
2829 DCI.CombineTo(N, Val, AddTo);
2830 }
2831
2832 return SDValue();
2833}
2834
2835enum OperandSignedness {
2836 Signed = 0,
2837 Unsigned,
2838 Unknown
2839};
2840
2841/// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
2842/// that can be demoted to \p OptSize bits without loss of information. The
2843/// signedness of the operand, if determinable, is placed in \p S.
2844static bool IsMulWideOperandDemotable(SDValue Op,
2845 unsigned OptSize,
2846 OperandSignedness &S) {
2847 S = Unknown;
2848
2849 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
2850 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2851 EVT OrigVT = Op.getOperand(0).getValueType();
2852 if (OrigVT.getSizeInBits() == OptSize) {
2853 S = Signed;
2854 return true;
2855 }
2856 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2857 EVT OrigVT = Op.getOperand(0).getValueType();
2858 if (OrigVT.getSizeInBits() == OptSize) {
2859 S = Unsigned;
2860 return true;
2861 }
2862 }
2863
2864 return false;
2865}
2866
2867/// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
2868/// be demoted to \p OptSize bits without loss of information. If the operands
2869/// contain a constant, it should appear as the RHS operand. The signedness of
2870/// the operands is placed in \p IsSigned.
2871static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
2872 unsigned OptSize,
2873 bool &IsSigned) {
2874
2875 OperandSignedness LHSSign;
2876
2877 // The LHS operand must be a demotable op
2878 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
2879 return false;
2880
2881 // We should have been able to determine the signedness from the LHS
2882 if (LHSSign == Unknown)
2883 return false;
2884
2885 IsSigned = (LHSSign == Signed);
2886
2887 // The RHS can be a demotable op or a constant
2888 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
2889 APInt Val = CI->getAPIntValue();
2890 if (LHSSign == Unsigned) {
2891 if (Val.isIntN(OptSize)) {
2892 return true;
2893 }
2894 return false;
2895 } else {
2896 if (Val.isSignedIntN(OptSize)) {
2897 return true;
2898 }
2899 return false;
2900 }
2901 } else {
2902 OperandSignedness RHSSign;
2903 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
2904 return false;
2905
2906 if (LHSSign != RHSSign)
2907 return false;
2908
2909 return true;
2910 }
2911}
2912
2913/// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
2914/// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
2915/// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
2916/// amount.
2917static SDValue TryMULWIDECombine(SDNode *N,
2918 TargetLowering::DAGCombinerInfo &DCI) {
2919 EVT MulType = N->getValueType(0);
2920 if (MulType != MVT::i32 && MulType != MVT::i64) {
2921 return SDValue();
2922 }
2923
2924 unsigned OptSize = MulType.getSizeInBits() >> 1;
2925 SDValue LHS = N->getOperand(0);
2926 SDValue RHS = N->getOperand(1);
2927
2928 // Canonicalize the multiply so the constant (if any) is on the right
2929 if (N->getOpcode() == ISD::MUL) {
2930 if (isa<ConstantSDNode>(LHS)) {
2931 std::swap(LHS, RHS);
2932 }
2933 }
2934
2935 // If we have a SHL, determine the actual multiply amount
2936 if (N->getOpcode() == ISD::SHL) {
2937 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
2938 if (!ShlRHS) {
2939 return SDValue();
2940 }
2941
2942 APInt ShiftAmt = ShlRHS->getAPIntValue();
2943 unsigned BitWidth = MulType.getSizeInBits();
2944 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
2945 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
2946 RHS = DCI.DAG.getConstant(MulVal, MulType);
2947 } else {
2948 return SDValue();
2949 }
2950 }
2951
2952 bool Signed;
2953 // Verify that our operands are demotable
2954 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
2955 return SDValue();
2956 }
2957
2958 EVT DemotedVT;
2959 if (MulType == MVT::i32) {
2960 DemotedVT = MVT::i16;
2961 } else {
2962 DemotedVT = MVT::i32;
2963 }
2964
2965 // Truncate the operands to the correct size. Note that these are just for
2966 // type consistency and will (likely) be eliminated in later phases.
2967 SDValue TruncLHS =
2968 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
2969 SDValue TruncRHS =
2970 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
2971
2972 unsigned Opc;
2973 if (Signed) {
2974 Opc = NVPTXISD::MUL_WIDE_SIGNED;
2975 } else {
2976 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
2977 }
2978
2979 return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
2980}
2981
2982/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
2983static SDValue PerformMULCombine(SDNode *N,
2984 TargetLowering::DAGCombinerInfo &DCI,
2985 CodeGenOpt::Level OptLevel) {
2986 if (OptLevel > 0) {
2987 // Try mul.wide combining at OptLevel > 0
2988 SDValue Ret = TryMULWIDECombine(N, DCI);
2989 if (Ret.getNode())
2990 return Ret;
2991 }
2992
2993 return SDValue();
2994}
2995
2996/// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
2997static SDValue PerformSHLCombine(SDNode *N,
2998 TargetLowering::DAGCombinerInfo &DCI,
2999 CodeGenOpt::Level OptLevel) {
3000 if (OptLevel > 0) {
3001 // Try mul.wide combining at OptLevel > 0
3002 SDValue Ret = TryMULWIDECombine(N, DCI);
3003 if (Ret.getNode())
3004 return Ret;
3005 }
3006
3007 return SDValue();
3008}
3009
3010SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
3011 DAGCombinerInfo &DCI) const {
3012 // FIXME: Get this from the DAG somehow
3013 CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
3014 switch (N->getOpcode()) {
3015 default: break;
3016 case ISD::ADD:
3017 case ISD::FADD:
3018 return PerformADDCombine(N, DCI, nvptxSubtarget, OptLevel);
3019 case ISD::MUL:
3020 return PerformMULCombine(N, DCI, OptLevel);
3021 case ISD::SHL:
3022 return PerformSHLCombine(N, DCI, OptLevel);
3023 case ISD::AND:
3024 return PerformANDCombine(N, DCI);
3025 }
3026 return SDValue();
3027}
3028
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3029/// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
3030static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3031 SmallVectorImpl<SDValue> &Results) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3032 EVT ResVT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]3033 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3034
3035 assert(ResVT.isVector() && "Vector load must have vector type");
3036
3037 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
3038 // legal. We can (and should) split that into 2 loads of <2 x double> here
3039 // but I'm leaving that as a TODO for now.
3040 assert(ResVT.isSimple() && "Can only handle simple types");
3041 switch (ResVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3042 default:
3043 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3044 case MVT::v2i8:
3045 case MVT::v2i16:
3046 case MVT::v2i32:
3047 case MVT::v2i64:
3048 case MVT::v2f32:
3049 case MVT::v2f64:
3050 case MVT::v4i8:
3051 case MVT::v4i16:
3052 case MVT::v4i32:
3053 case MVT::v4f32:
3054 // This is a "native" vector type
3055 break;
3056 }
3057
3058 EVT EltVT = ResVT.getVectorElementType();
3059 unsigned NumElts = ResVT.getVectorNumElements();
3060
3061 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
3062 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]3063 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3064 bool NeedTrunc = false;
3065 if (EltVT.getSizeInBits() < 16) {
3066 EltVT = MVT::i16;
3067 NeedTrunc = true;
3068 }
3069
3070 unsigned Opcode = 0;
3071 SDVTList LdResVTs;
3072
3073 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3074 default:
3075 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3076 case 2:
3077 Opcode = NVPTXISD::LoadV2;
3078 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
3079 break;
3080 case 4: {
3081 Opcode = NVPTXISD::LoadV4;
3082 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]3083 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3084 break;
3085 }
3086 }
3087
3088 SmallVector<SDValue, 8> OtherOps;
3089
3090 // Copy regular operands
3091 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
3092 OtherOps.push_back(N->getOperand(i));
3093
3094 LoadSDNode *LD = cast<LoadSDNode>(N);
3095
3096 // The select routine does not have access to the LoadSDNode instance, so
3097 // pass along the extension information
3098 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
3099
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3100 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
3101 LD->getMemoryVT(),
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3102 LD->getMemOperand());
3103
3104 SmallVector<SDValue, 4> ScalarRes;
3105
3106 for (unsigned i = 0; i < NumElts; ++i) {
3107 SDValue Res = NewLD.getValue(i);
3108 if (NeedTrunc)
3109 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
3110 ScalarRes.push_back(Res);
3111 }
3112
3113 SDValue LoadChain = NewLD.getValue(NumElts);
3114
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]3115 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3116
3117 Results.push_back(BuildVec);
3118 Results.push_back(LoadChain);
3119}
3120
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3121static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3122 SmallVectorImpl<SDValue> &Results) {
3123 SDValue Chain = N->getOperand(0);
3124 SDValue Intrin = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]3125 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3126
3127 // Get the intrinsic ID
3128 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3129 switch (IntrinNo) {
3130 default:
3131 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3132 case Intrinsic::nvvm_ldg_global_i:
3133 case Intrinsic::nvvm_ldg_global_f:
3134 case Intrinsic::nvvm_ldg_global_p:
3135 case Intrinsic::nvvm_ldu_global_i:
3136 case Intrinsic::nvvm_ldu_global_f:
3137 case Intrinsic::nvvm_ldu_global_p: {
3138 EVT ResVT = N->getValueType(0);
3139
3140 if (ResVT.isVector()) {
3141 // Vector LDG/LDU
3142
3143 unsigned NumElts = ResVT.getVectorNumElements();
3144 EVT EltVT = ResVT.getVectorElementType();
3145
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3146 // Since LDU/LDG are target nodes, we cannot rely on DAG type
3147 // legalization.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3148 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]3149 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3150 bool NeedTrunc = false;
3151 if (EltVT.getSizeInBits() < 16) {
3152 EltVT = MVT::i16;
3153 NeedTrunc = true;
3154 }
3155
3156 unsigned Opcode = 0;
3157 SDVTList LdResVTs;
3158
3159 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3160 default:
3161 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3162 case 2:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3163 switch (IntrinNo) {
3164 default:
3165 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3166 case Intrinsic::nvvm_ldg_global_i:
3167 case Intrinsic::nvvm_ldg_global_f:
3168 case Intrinsic::nvvm_ldg_global_p:
3169 Opcode = NVPTXISD::LDGV2;
3170 break;
3171 case Intrinsic::nvvm_ldu_global_i:
3172 case Intrinsic::nvvm_ldu_global_f:
3173 case Intrinsic::nvvm_ldu_global_p:
3174 Opcode = NVPTXISD::LDUV2;
3175 break;
3176 }
3177 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
3178 break;
3179 case 4: {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3180 switch (IntrinNo) {
3181 default:
3182 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3183 case Intrinsic::nvvm_ldg_global_i:
3184 case Intrinsic::nvvm_ldg_global_f:
3185 case Intrinsic::nvvm_ldg_global_p:
3186 Opcode = NVPTXISD::LDGV4;
3187 break;
3188 case Intrinsic::nvvm_ldu_global_i:
3189 case Intrinsic::nvvm_ldu_global_f:
3190 case Intrinsic::nvvm_ldu_global_p:
3191 Opcode = NVPTXISD::LDUV4;
3192 break;
3193 }
3194 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]3195 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3196 break;
3197 }
3198 }
3199
3200 SmallVector<SDValue, 8> OtherOps;
3201
3202 // Copy regular operands
3203
3204 OtherOps.push_back(Chain); // Chain
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3205 // Skip operand 1 (intrinsic ID)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3206 // Others
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3207 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
3208 OtherOps.push_back(N->getOperand(i));
3209
3210 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
3211
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3212 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
3213 MemSD->getMemoryVT(),
3214 MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3215
3216 SmallVector<SDValue, 4> ScalarRes;
3217
3218 for (unsigned i = 0; i < NumElts; ++i) {
3219 SDValue Res = NewLD.getValue(i);
3220 if (NeedTrunc)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3221 Res =
3222 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3223 ScalarRes.push_back(Res);
3224 }
3225
3226 SDValue LoadChain = NewLD.getValue(NumElts);
3227
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3228 SDValue BuildVec =
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]3229 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3230
3231 Results.push_back(BuildVec);
3232 Results.push_back(LoadChain);
3233 } else {
3234 // i8 LDG/LDU
3235 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
3236 "Custom handling of non-i8 ldu/ldg?");
3237
3238 // Just copy all operands as-is
3239 SmallVector<SDValue, 4> Ops;
3240 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
3241 Ops.push_back(N->getOperand(i));
3242
3243 // Force output to i16
3244 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
3245
3246 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
3247
3248 // We make sure the memory type is i8, which will be used during isel
3249 // to select the proper instruction.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3250 SDValue NewLD =
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3251 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
3252 MVT::i8, MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3253
Justin Holewinskie8c93e32013-07-01 12:58:48 +0000[diff] [blame]3254 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
3255 NewLD.getValue(0)));
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3256 Results.push_back(NewLD.getValue(1));
3257 }
3258 }
3259 }
3260}
3261
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3262void NVPTXTargetLowering::ReplaceNodeResults(
3263 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3264 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3265 default:
3266 report_fatal_error("Unhandled custom legalization");
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3267 case ISD::LOAD:
3268 ReplaceLoadVector(N, DAG, Results);
3269 return;
3270 case ISD::INTRINSIC_W_CHAIN:
3271 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
3272 return;
3273 }
3274}
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]3275
3276// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
3277void NVPTXSection::anchor() {}
3278
3279NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
3280 delete TextSection;
3281 delete DataSection;
3282 delete BSSSection;
3283 delete ReadOnlySection;
3284
3285 delete StaticCtorSection;
3286 delete StaticDtorSection;
3287 delete LSDASection;
3288 delete EHFrameSection;
3289 delete DwarfAbbrevSection;
3290 delete DwarfInfoSection;
3291 delete DwarfLineSection;
3292 delete DwarfFrameSection;
3293 delete DwarfPubTypesSection;
3294 delete DwarfDebugInlineSection;
3295 delete DwarfStrSection;
3296 delete DwarfLocSection;
3297 delete DwarfARangesSection;
3298 delete DwarfRangesSection;
3299 delete DwarfMacroInfoSection;
3300}