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gerrit-public.fairphone.software / toolchain / llvm-project / df43e6862918eba86dd8b608bc2ae202225092dc / . / llvm / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 0239cabe9e52824409cc97357642864b031e8c4f [file] [log] [blame]
Brendon Cahoon55bdeb72015-04-27 14:16:43 +0000[diff] [blame]1
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]2//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]3//
4// The LLVM Compiler Infrastructure
5//
6// This file is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the Hexagon implementation of the TargetInstrInfo class.
12//
13//===----------------------------------------------------------------------===//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]15#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
16#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]17
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]18#include "HexagonRegisterInfo.h"
Brendon Cahoon6f358372012-02-08 18:25:47 +0000[diff] [blame]19#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]20#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +0000[diff] [blame]21#include "llvm/Target/TargetFrameLowering.h"
22#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]23
24#define GET_INSTRINFO_HEADER
25#include "HexagonGenInstrInfo.inc"
26
27namespace llvm {
28
Patrik Hagglund8d09a6c2014-03-15 09:11:41 +0000[diff] [blame]29struct EVT;
Eric Christopher234a1ec2015-03-12 06:07:16 +0000[diff] [blame]30class HexagonSubtarget;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]31class HexagonInstrInfo : public HexagonGenInstrInfo {
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]32 virtual void anchor();
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]33 const HexagonRegisterInfo RI;
Bill Wendling4a7a4082013-06-07 06:19:56 +0000[diff] [blame]34 const HexagonSubtarget &Subtarget;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]35
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]36public:
Brendon Cahoondf43e682015-05-08 16:16:29 +0000[diff] [blame^]37 typedef unsigned Opcode_t;
38
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]39 explicit HexagonInstrInfo(HexagonSubtarget &ST);
40
41 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
42 /// such, whenever a client has an instance of instruction info, it should
43 /// always be able to get register info as well (through this method).
44 ///
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]45 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]46
47 /// isLoadFromStackSlot - If the specified machine instruction is a direct
48 /// load from a stack slot, return the virtual or physical register number of
49 /// the destination along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than loading from the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]52 unsigned isLoadFromStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]54
55 /// isStoreToStackSlot - If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]60 unsigned isStoreToStackSlot(const MachineInstr *MI,
61 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]62
63
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]64 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
65 MachineBasicBlock *&FBB,
66 SmallVectorImpl<MachineOperand> &Cond,
67 bool AllowModify) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]68
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]69 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]70
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
72 MachineBasicBlock *FBB,
73 const SmallVectorImpl<MachineOperand> &Cond,
74 DebugLoc DL) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]75
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]76 bool analyzeCompare(const MachineInstr *MI,
77 unsigned &SrcReg, unsigned &SrcReg2,
78 int &Mask, int &Value) const override;
Krzysztof Parzyszekcfe285e2013-02-11 20:04:29 +0000[diff] [blame]79
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]80 void copyPhysReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator I, DebugLoc DL,
82 unsigned DestReg, unsigned SrcReg,
83 bool KillSrc) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]84
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]85 void storeRegToStackSlot(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI,
87 unsigned SrcReg, bool isKill, int FrameIndex,
88 const TargetRegisterClass *RC,
89 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]90
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]91 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
92 SmallVectorImpl<MachineOperand> &Addr,
93 const TargetRegisterClass *RC,
94 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]95
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]96 void loadRegFromStackSlot(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MBBI,
98 unsigned DestReg, int FrameIndex,
99 const TargetRegisterClass *RC,
100 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]101
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]102 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
103 SmallVectorImpl<MachineOperand> &Addr,
104 const TargetRegisterClass *RC,
105 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]106
Colin LeMahieu7b1799c2015-03-09 22:05:21 +0000[diff] [blame]107 /// expandPostRAPseudo - This function is called for all pseudo instructions
108 /// that remain after register allocation. Many pseudo instructions are
109 /// created to help register allocation. This is the place to convert them
110 /// into real instructions. The target can edit MI in place, or it can insert
111 /// new instructions and erase MI. The function should return true if
112 /// anything was changed.
113 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
114
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]115 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
116 ArrayRef<unsigned> Ops,
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]117 int FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]118
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]119 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
120 ArrayRef<unsigned> Ops,
121 MachineInstr *LoadMI) const override {
Craig Toppere73658d2014-04-28 04:05:08 +0000[diff] [blame]122 return nullptr;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]123 }
124
125 unsigned createVR(MachineFunction* MF, MVT VT) const;
126
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]127 bool isBranch(const MachineInstr *MI) const;
128 bool isPredicable(MachineInstr *MI) const override;
129 bool PredicateInstruction(MachineInstr *MI,
130 const SmallVectorImpl<MachineOperand> &Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]131
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]132 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
133 unsigned ExtraPredCycles,
134 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]135
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]136 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
137 unsigned NumTCycles, unsigned ExtraTCycles,
138 MachineBasicBlock &FMBB,
139 unsigned NumFCycles, unsigned ExtraFCycles,
140 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]141
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]142 bool isPredicated(const MachineInstr *MI) const override;
143 bool isPredicated(unsigned Opcode) const;
144 bool isPredicatedTrue(const MachineInstr *MI) const;
145 bool isPredicatedTrue(unsigned Opcode) const;
146 bool isPredicatedNew(const MachineInstr *MI) const;
147 bool isPredicatedNew(unsigned Opcode) const;
148 bool DefinesPredicate(MachineInstr *MI,
149 std::vector<MachineOperand> &Pred) const override;
150 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
151 const SmallVectorImpl<MachineOperand> &Pred2) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]152
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]153 bool
154 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]155
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]156 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
157 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]158
Eric Christopher143f02c2014-10-09 01:59:35 +0000[diff] [blame]159 DFAPacketizer *
160 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
Andrew Trickd06df962012-02-01 22:13:57 +0000[diff] [blame]161
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]162 bool isSchedulingBoundary(const MachineInstr *MI,
163 const MachineBasicBlock *MBB,
164 const MachineFunction &MF) const override;
Krzysztof Parzyszek05902162015-04-22 17:51:26 +0000[diff] [blame]165 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]166 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
167 bool isMemOp(const MachineInstr *MI) const;
168 bool isSpillPredRegOp(const MachineInstr *MI) const;
169 bool isU6_3Immediate(const int value) const;
170 bool isU6_2Immediate(const int value) const;
171 bool isU6_1Immediate(const int value) const;
172 bool isU6_0Immediate(const int value) const;
173 bool isS4_3Immediate(const int value) const;
174 bool isS4_2Immediate(const int value) const;
175 bool isS4_1Immediate(const int value) const;
176 bool isS4_0Immediate(const int value) const;
177 bool isS12_Immediate(const int value) const;
178 bool isU6_Immediate(const int value) const;
179 bool isS8_Immediate(const int value) const;
180 bool isS6_Immediate(const int value) const;
181
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]182 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
183 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]184 bool isConditionalALU32 (const MachineInstr* MI) const;
185 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]186 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Vermaf1214a82013-03-05 18:51:42 +0000[diff] [blame]187 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma84c47102013-05-06 18:49:23 +0000[diff] [blame]188 bool isNewValue(const MachineInstr* MI) const;
Brendon Cahoondf43e682015-05-08 16:16:29 +0000[diff] [blame^]189 bool isNewValue(Opcode_t Opcode) const;
Jyotsna Vermaa46059b2013-03-28 19:44:04 +0000[diff] [blame]190 bool isDotNewInst(const MachineInstr* MI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000[diff] [blame]191 int GetDotOldOp(const int opc) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]192 int GetDotNewOp(const MachineInstr* MI) const;
Jyotsna Verma00681dc2013-05-09 19:16:07 +0000[diff] [blame]193 int GetDotNewPredOp(MachineInstr *MI,
194 const MachineBranchProbabilityInfo
195 *MBPI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000[diff] [blame]196 bool mayBeNewStore(const MachineInstr* MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]197 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]198 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]199 bool isExtendable(const MachineInstr* MI) const;
200 bool isExtended(const MachineInstr* MI) const;
201 bool isPostIncrement(const MachineInstr* MI) const;
202 bool isNewValueStore(const MachineInstr* MI) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]203 bool isNewValueStore(unsigned Opcode) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]204 bool isNewValueJump(const MachineInstr* MI) const;
Brendon Cahoondf43e682015-05-08 16:16:29 +0000[diff] [blame^]205 bool isNewValueJump(Opcode_t Opcode) const;
Sirish Pande4bd20c52012-05-12 05:10:30 +0000[diff] [blame]206 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]207
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]208
209 void immediateExtend(MachineInstr *MI) const;
Brendon Cahoon55bdeb72015-04-27 14:16:43 +0000[diff] [blame]210 bool isConstExtended(const MachineInstr *MI) const;
211 unsigned getSize(const MachineInstr *MI) const;
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]212 int getDotNewPredJumpOp(MachineInstr *MI,
213 const MachineBranchProbabilityInfo *MBPI) const;
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]214 unsigned getAddrMode(const MachineInstr* MI) const;
215 bool isOperandExtended(const MachineInstr *MI,
216 unsigned short OperandNum) const;
217 unsigned short getCExtOpNum(const MachineInstr *MI) const;
218 int getMinValue(const MachineInstr *MI) const;
219 int getMaxValue(const MachineInstr *MI) const;
220 bool NonExtEquivalentExists (const MachineInstr *MI) const;
221 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]222 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
Brendon Cahoondf43e682015-05-08 16:16:29 +0000[diff] [blame^]223 bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const;
224 bool isEndLoopN(Opcode_t Opcode) const;
225 bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
226 unsigned &PredReg, unsigned &PredRegPos,
227 unsigned &PredRegFlags) const;
Krzysztof Parzyszekc05dff12015-03-31 13:35:12 +0000[diff] [blame]228 int getCondOpcode(int Opc, bool sense) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]229
230};
231
232}
233
234#endif