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gerrit-public.fairphone.software / toolchain / llvm-project / e5147247b8cea11e06225e1ee27a5ed4af57824f / . / llvm / lib / Target / AMDGPU / DSInstructions.td
blob: 8dad3e83e0499d42bcf211750261452451ef5aab [file] [log] [blame]
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
13
14 let SubtargetPredicate = isGCN;
15
16 let LGKM_CNT = 1;
17 let DS = 1;
Matt Arsenault10c17ca2016-10-06 10:13:23 +0000[diff] [blame]18 let Size = 8;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
21
22 // Most instruction load and store data, so set this as the default.
23 let mayLoad = 1;
24 let mayStore = 1;
25
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
28
29 let isPseudo = 1;
30 let isCodeGenOnly = 1;
31
32 let AsmMatchConverter = "cvtDS";
33
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
36
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
39 bits<1> has_vdst = 1;
40 bits<1> has_addr = 1;
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
43
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
47
48 bits<1> has_gds = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50}
51
52class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
54 Enc64 {
55
56 let isPseudo = 0;
57 let isCodeGenOnly = 0;
58
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
62
63 // encoding fields
64 bits<8> vdst;
65 bits<1> gds;
66 bits<8> addr;
67 bits<8> data0;
68 bits<8> data1;
69 bits<8> offset0;
70 bits<8> offset1;
71
72 bits<16> offset;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
75}
76
77
78// DS Pseudo instructions
79
80class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
81: DS_Pseudo<opName,
82 (outs),
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
86
87 let has_data1 = 0;
88 let has_vdst = 0;
89}
90
91class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName,
92 (outs),
93 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
94 "$addr $offset0$offset1$gds"> {
95
96 let has_data0 = 0;
97 let has_data1 = 0;
98 let has_vdst = 0;
99 let has_offset = 0;
100 let AsmMatchConverter = "cvtDSOffset01";
101}
102
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]103class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]104: DS_Pseudo<opName,
105 (outs),
106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107 "$addr, $data0, $data1"#"$offset"#"$gds">,
108 AtomicNoRet<opName, 0> {
109
110 let has_vdst = 0;
111}
112
113class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
114: DS_Pseudo<opName,
115 (outs),
116 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
117 offset0:$offset0, offset1:$offset1, gds:$gds),
118 "$addr, $data0, $data1$offset0$offset1$gds"> {
119
120 let has_vdst = 0;
121 let has_offset = 0;
122 let AsmMatchConverter = "cvtDSOffset01";
123}
124
125class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
126: DS_Pseudo<opName,
127 (outs rc:$vdst),
128 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0$offset$gds"> {
130
131 let hasPostISelHook = 1;
132 let has_data1 = 0;
133}
134
135class DS_1A2D_RET<string opName,
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]136 RegisterClass rc = VGPR_32,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]137 RegisterClass src = rc>
138: DS_Pseudo<opName,
139 (outs rc:$vdst),
140 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
141 "$vdst, $addr, $data0, $data1$offset$gds"> {
142
143 let hasPostISelHook = 1;
144}
145
146class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
147: DS_Pseudo<opName,
148 (outs rc:$vdst),
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]149 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]150 "$vdst, $addr$offset$gds"> {
151
152 let has_data0 = 0;
153 let has_data1 = 0;
154}
155
156class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
157: DS_Pseudo<opName,
158 (outs rc:$vdst),
159 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
160 "$vdst, $addr$offset0$offset1$gds"> {
161
162 let has_offset = 0;
163 let has_data0 = 0;
164 let has_data1 = 0;
165 let AsmMatchConverter = "cvtDSOffset01";
166}
167
168class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
169 (outs VGPR_32:$vdst),
170 (ins VGPR_32:$addr, offset:$offset),
171 "$vdst, $addr$offset gds"> {
172
173 let has_data0 = 0;
174 let has_data1 = 0;
175 let has_gds = 0;
176 let gdsValue = 1;
Artem Tamazov43b61562017-02-03 12:47:30 +0000[diff] [blame]177 let AsmMatchConverter = "cvtDSGds";
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]178}
179
180class DS_0A_RET <string opName> : DS_Pseudo<opName,
181 (outs VGPR_32:$vdst),
182 (ins offset:$offset, gds:$gds),
183 "$vdst$offset$gds"> {
184
185 let mayLoad = 1;
186 let mayStore = 1;
187
188 let has_addr = 0;
189 let has_data0 = 0;
190 let has_data1 = 0;
191}
192
193class DS_1A <string opName> : DS_Pseudo<opName,
194 (outs),
195 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
196 "$addr$offset$gds"> {
197
198 let mayLoad = 1;
199 let mayStore = 1;
200
201 let has_vdst = 0;
202 let has_data0 = 0;
203 let has_data1 = 0;
204}
205
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]206class DS_GWS <string opName, dag ins, string asmOps>
207: DS_Pseudo<opName, (outs), ins, asmOps> {
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]208
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]209 let has_vdst = 0;
210 let has_addr = 0;
211 let has_data0 = 0;
212 let has_data1 = 0;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]213
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]214 let has_gds = 0;
215 let gdsValue = 1;
216 let AsmMatchConverter = "cvtDSGds";
217}
218
219class DS_GWS_0D <string opName>
220: DS_GWS<opName,
221 (ins offset:$offset, gds:$gds), "$offset gds">;
222
223class DS_GWS_1D <string opName>
224: DS_GWS<opName,
225 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
226
227 let has_data0 = 1;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]228}
229
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]230class DS_VOID <string opName> : DS_Pseudo<opName,
231 (outs), (ins), ""> {
232 let mayLoad = 0;
233 let mayStore = 0;
234 let hasSideEffects = 1;
235 let UseNamedOperandTable = 0;
236 let AsmMatchConverter = "";
237
238 let has_vdst = 0;
239 let has_addr = 0;
240 let has_data0 = 0;
241 let has_data1 = 0;
242 let has_offset = 0;
243 let has_offset0 = 0;
244 let has_offset1 = 0;
245 let has_gds = 0;
246}
247
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]248class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
249: DS_Pseudo<opName,
250 (outs VGPR_32:$vdst),
251 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
252 "$vdst, $addr, $data0$offset",
253 [(set i32:$vdst,
254 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
255
256 let mayLoad = 0;
257 let mayStore = 0;
258 let isConvergent = 1;
259
260 let has_data1 = 0;
261 let has_gds = 0;
262}
263
264def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
265def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
266def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
267def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
268def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
269def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
270def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
271def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
272def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
273def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
274def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
275def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]276def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]277def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
278def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]279
280let mayLoad = 0 in {
281def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
282def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
283def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
284def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
285def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
286}
287
288def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
289def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
290def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]291
292def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
293def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
294def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
295def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
296def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
297def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
298def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
299def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
300def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
301def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
302def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
303def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
304def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
305let mayLoad = 0 in {
306def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
307def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
308def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
309}
310def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
311def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
312def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
313def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
314
315def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
316 AtomicNoRet<"ds_add_u32", 1>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]317def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
318 AtomicNoRet<"ds_add_f32", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]319def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
320 AtomicNoRet<"ds_sub_u32", 1>;
321def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
322 AtomicNoRet<"ds_rsub_u32", 1>;
323def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
324 AtomicNoRet<"ds_inc_u32", 1>;
325def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
326 AtomicNoRet<"ds_dec_u32", 1>;
327def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
328 AtomicNoRet<"ds_min_i32", 1>;
329def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
330 AtomicNoRet<"ds_max_i32", 1>;
331def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
332 AtomicNoRet<"ds_min_u32", 1>;
333def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
334 AtomicNoRet<"ds_max_u32", 1>;
335def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
336 AtomicNoRet<"ds_and_b32", 1>;
337def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
338 AtomicNoRet<"ds_or_b32", 1>;
339def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
340 AtomicNoRet<"ds_xor_b32", 1>;
341def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
342 AtomicNoRet<"ds_mskor_b32", 1>;
343def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
344 AtomicNoRet<"ds_cmpst_b32", 1>;
345def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
346 AtomicNoRet<"ds_cmpst_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]347def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]348 AtomicNoRet<"ds_min_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]349def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]350 AtomicNoRet<"ds_max_f32", 1>;
351
352def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
353 AtomicNoRet<"", 1>;
354def DS_WRXCHG2_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
355 AtomicNoRet<"", 1>;
356def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
357 AtomicNoRet<"", 1>;
358
359def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
360 AtomicNoRet<"ds_add_u64", 1>;
361def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
362 AtomicNoRet<"ds_sub_u64", 1>;
363def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
364 AtomicNoRet<"ds_rsub_u64", 1>;
365def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
366 AtomicNoRet<"ds_inc_u64", 1>;
367def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
368 AtomicNoRet<"ds_dec_u64", 1>;
369def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
370 AtomicNoRet<"ds_min_i64", 1>;
371def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
372 AtomicNoRet<"ds_max_i64", 1>;
373def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
374 AtomicNoRet<"ds_min_u64", 1>;
375def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
376 AtomicNoRet<"ds_max_u64", 1>;
377def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
378 AtomicNoRet<"ds_and_b64", 1>;
379def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
380 AtomicNoRet<"ds_or_b64", 1>;
381def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
382 AtomicNoRet<"ds_xor_b64", 1>;
383def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
384 AtomicNoRet<"ds_mskor_b64", 1>;
385def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
386 AtomicNoRet<"ds_cmpst_b64", 1>;
387def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
388 AtomicNoRet<"ds_cmpst_f64", 1>;
389def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
390 AtomicNoRet<"ds_min_f64", 1>;
391def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
392 AtomicNoRet<"ds_max_f64", 1>;
393
394def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
395 AtomicNoRet<"ds_wrxchg_b64", 1>;
396def DS_WRXCHG2_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
397 AtomicNoRet<"ds_wrxchg2_b64", 1>;
398def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
399 AtomicNoRet<"ds_wrxchg2st64_b64", 1>;
400
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]401def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
402def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
403def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
404def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
405def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]406
407def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
408def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
409def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
410def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
411def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
412def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
413def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
414def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
415def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]416def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]417def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
418def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
419def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
420def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
421
422def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
423def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
424def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
425def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
426def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
427def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
428def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
429def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
430def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
431def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
432def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
433def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
434def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
435def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
436
437def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">;
438def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">;
439
440let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
441def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
442}
443
444let mayStore = 0 in {
445def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
446def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
447def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
448def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
449def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
450def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
451
452def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
453def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
454
455def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
456def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
457}
458
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]459def DS_CONSUME : DS_0A_RET<"ds_consume">;
460def DS_APPEND : DS_0A_RET<"ds_append">;
461def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]462
463//===----------------------------------------------------------------------===//
464// Instruction definitions for CI and newer.
465//===----------------------------------------------------------------------===//
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]466
467let SubtargetPredicate = isCIVI in {
468
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]469def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
470
471def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
472 AtomicNoRet<"", 1>;
473
474def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]475
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]476let mayStore = 0 in {
477def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
478def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
479} // End mayStore = 0
480
481let mayLoad = 0 in {
482def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
483def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
484} // End mayLoad = 0
485
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]486def DS_NOP : DS_VOID<"ds_nop">;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]487
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]488} // let SubtargetPredicate = isCIVI
489
490//===----------------------------------------------------------------------===//
491// Instruction definitions for VI and newer.
492//===----------------------------------------------------------------------===//
493
494let SubtargetPredicate = isVI in {
495
496let Uses = [EXEC] in {
497def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
498 int_amdgcn_ds_permute>;
499def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
500 int_amdgcn_ds_bpermute>;
501}
502
503} // let SubtargetPredicate = isVI
504
505//===----------------------------------------------------------------------===//
506// DS Patterns
507//===----------------------------------------------------------------------===//
508
509let Predicates = [isGCN] in {
510
511def : Pat <
512 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
513 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
514>;
515
516class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
517 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
518 (inst $ptr, (as_i16imm $offset), (i1 0))
519>;
520
521def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
522def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]523def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
524def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
525def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]526def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
527def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]528def : DSReadPat <DS_READ_U16, i16, si_load_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]529def : DSReadPat <DS_READ_B32, i32, si_load_local>;
530
531let AddedComplexity = 100 in {
532
533def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
534
535} // End AddedComplexity = 100
536
537def : Pat <
538 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
539 i8:$offset1))),
540 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
541>;
542
543class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
544 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
545 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
546>;
547
548def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
549def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]550def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
551def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]552def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
553
554let AddedComplexity = 100 in {
555
556def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
557} // End AddedComplexity = 100
558
559def : Pat <
560 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
561 i8:$offset1)),
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]562 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
563 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]564 (i1 0))
565>;
566
567class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
568 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
569 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
570>;
571
572class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
573 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
574 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
575>;
576
577
578// 32-bit atomics.
579def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
580def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
581def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
582def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
583def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
584def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
585def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
586def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
587def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
588def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
589def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
590def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
591def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
592
593// 64-bit atomics.
594def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
595def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
596def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
597def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
598def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
599def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
600def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
601def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
602def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
603def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
604def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
605def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
606
607def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
608
609} // let Predicates = [isGCN]
610
611//===----------------------------------------------------------------------===//
612// Real instructions
613//===----------------------------------------------------------------------===//
614
615//===----------------------------------------------------------------------===//
616// SIInstructions.td
617//===----------------------------------------------------------------------===//
618
619class DS_Real_si <bits<8> op, DS_Pseudo ds> :
620 DS_Real <ds>,
621 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
622 let AssemblerPredicates=[isSICI];
623 let DecoderNamespace="SICI";
624
625 // encoding
626 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
627 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
628 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
629 let Inst{25-18} = op;
630 let Inst{31-26} = 0x36; // ds prefix
631 let Inst{39-32} = !if(ds.has_addr, addr, 0);
632 let Inst{47-40} = !if(ds.has_data0, data0, 0);
633 let Inst{55-48} = !if(ds.has_data1, data1, 0);
634 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
635}
636
637def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
638def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
639def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
640def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
641def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
642def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
643def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
644def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
645def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
646def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
647def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
648def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
649def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
650def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
651def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
652def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
653def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
654def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
655def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
656def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]657def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]658def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
659def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
660def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
661def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
662def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
663def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
664def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
665def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
666def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
667def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
668def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
669def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
670def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
671def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
672def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
673def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
674def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
675def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
676def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
677def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
678def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
679def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
680def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
681def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
682def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
683def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
684def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
685
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]686// These instruction are CI/VI only
687def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
688def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
689def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]690
691def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
692def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
693def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
694def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
695def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
696def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
697def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
698def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
699def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
700def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
701def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
702def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
703def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
704def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
705def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
706def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
707def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
708def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
709def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
710def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
711def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
712def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
713def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
714def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
715def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
716def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
717def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
718def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
719def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
720def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
721def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
722
723def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
724def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
725def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
726def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
727def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
728def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
729def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
730def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
731def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
732def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
733def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
734def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
735def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
736def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
737def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
738def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
739def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
740def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
741def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
742def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
743
744def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
745def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
746def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
747
748def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
749def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
750def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
751def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
752def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
753def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
754def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
755def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
756def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
757def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
758def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
759def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
760def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
761
762def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
763def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
764
765def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
766def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
767def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
768def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
769def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
770def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
771def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
772def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
773def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
774def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
775def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
776def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
777def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
778
779def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
780def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]781def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
782def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
783def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
784def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]785
786//===----------------------------------------------------------------------===//
787// VIInstructions.td
788//===----------------------------------------------------------------------===//
789
790class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
791 DS_Real <ds>,
792 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
793 let AssemblerPredicates = [isVI];
794 let DecoderNamespace="VI";
795
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]796 // encoding
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]797 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
798 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
799 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
800 let Inst{24-17} = op;
801 let Inst{31-26} = 0x36; // ds prefix
802 let Inst{39-32} = !if(ds.has_addr, addr, 0);
803 let Inst{47-40} = !if(ds.has_data0, data0, 0);
804 let Inst{55-48} = !if(ds.has_data1, data1, 0);
805 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
806}
807
808def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
809def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
810def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
811def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
812def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
813def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
814def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
815def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
816def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
817def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
818def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
819def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
820def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
821def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
822def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
823def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
824def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
825def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
826def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
827def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]828def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]829def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]830def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
831def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
832def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
833def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
834def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]835def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
836def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
837def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
838def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
839def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
840def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
841def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
842def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
843def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
844def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
845def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
846def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
847def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
848def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
849def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
850def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
851def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
852def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
853def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
854def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
855def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
856def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]857def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]858def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]859def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
860def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
861def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
862def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
863def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
864def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
865def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]866def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
867def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
868def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]869def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
870def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
871def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
872
873def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
874def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
875def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
876def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
877def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
878def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
879def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
880def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
881def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
882def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
883def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
884def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
885def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
886def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
887def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
888def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
889def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
890def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
891def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
892def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
893
894def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
895def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
896def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
897def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
898def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
899def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
900def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
901def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
902def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
903def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
904def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
905def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
906def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
907def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
908def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
909def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame^]910def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
911def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]912def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
913def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
914def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
915def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
916
917def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
918def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
919def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
920
921def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
922def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
923def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
924def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
925def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
926def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
927def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
928def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
929def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
930def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
931def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
932def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
933def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
934def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
935def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
936def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
937def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
938def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
939def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
940def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
941def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
942def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
943def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
944def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
945def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
946def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
947def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
948def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
949def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
950def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]951def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
952def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
953def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
954def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;