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gerrit-public.fairphone.software / toolchain / llvm-project / eac54473dd4e3aa703ef166111be2b68f3586097 / . / llvm / lib / Target / ARM / ARMScheduleA9.td
blob: d06ad7d6691d17c15f78dfecc5353f72512220bf [file] [log] [blame]
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1//=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]2//
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]7//
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM Cortex A9 processors.
11//
12//===----------------------------------------------------------------------===//
13
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]14// ===---------------------------------------------------------------------===//
15// This section contains legacy support for itineraries. This is
16// required until SD and PostRA schedulers are replaced by MachineScheduler.
17
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]18//
19// Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
20// Reference Manual".
21//
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]22// Functional units
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]23def A9_Issue0 : FuncUnit; // Issue 0
24def A9_Issue1 : FuncUnit; // Issue 1
25def A9_Branch : FuncUnit; // Branch
26def A9_ALU0 : FuncUnit; // ALU / MUL pipeline 0
27def A9_ALU1 : FuncUnit; // ALU pipeline 1
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]28def A9_AGU : FuncUnit; // Address generation unit for ld / st
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]29def A9_NPipe : FuncUnit; // NEON pipeline
30def A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]31def A9_LSUnit : FuncUnit; // L/S Unit
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]32def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
33def A9_DRegsN : FuncUnit; // FP register set, NEON side
34
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]35// Bypasses
36def A9_LdBypass : Bypass;
37
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]38def CortexA9Itineraries : ProcessorItineraries<
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]39 [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]40 A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]41 [A9_LdBypass], [
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]42 // Two fully-pipelined integer ALU pipelines
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]43
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]44 //
45 // Move instructions, unconditional
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]46 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
48 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
49 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
50 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
51 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
52 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
53 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
54 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
55 InstrStage<1, [A9_ALU0, A9_ALU1]>,
56 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Evan Chengb8b0ad82011-01-20 08:34:58 +0000[diff] [blame]57 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
58 InstrStage<1, [A9_ALU0, A9_ALU1]>,
59 InstrStage<1, [A9_ALU0, A9_ALU1]>,
60 InstrStage<1, [A9_ALU0, A9_ALU1]>], [3]>,
61 InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
62 InstrStage<1, [A9_ALU0, A9_ALU1]>,
63 InstrStage<1, [A9_ALU0, A9_ALU1]>,
64 InstrStage<1, [A9_MUX0], 0>,
65 InstrStage<1, [A9_AGU], 0>,
66 InstrStage<1, [A9_LSUnit]>], [5]>,
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]67 //
68 // MVN instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]69 InstrItinData<IIC_iMVNi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
70 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]71 [1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]72 InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
73 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]74 [1, 1], [NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]75 InstrItinData<IIC_iMVNsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
76 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]77 [2, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]78 InstrItinData<IIC_iMVNsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
79 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]80 [3, 1, 1]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]81 //
82 // No operand cycles
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]83 InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
84 InstrStage<1, [A9_ALU0, A9_ALU1]>]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]85 //
86 // Binary Instructions that produce a result
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]87 InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
88 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]89 [1, 1], [NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]90 InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
91 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]92 [1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]93 InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
94 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]95 [2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]96 InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
97 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]98 [2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]99 InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
100 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]101 [3, 1, 1, 1],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]102 [NoBypass, A9_LdBypass, NoBypass, NoBypass]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]103 //
Evan Chengc35d7bb2010-09-29 00:27:46 +0000[diff] [blame]104 // Bitwise Instructions that produce a result
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]105 InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
106 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
107 InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
108 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
109 InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
110 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
111 InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
112 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Evan Chengc35d7bb2010-09-29 00:27:46 +0000[diff] [blame]113 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]114 // Unary Instructions that produce a result
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]115
116 // CLZ, RBIT, etc.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]117 InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
118 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]119
120 // BFC, BFI, UBFX, SBFX
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]121 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
122 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]123
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]124 //
Evan Cheng62d626c2010-09-25 00:49:35 +0000[diff] [blame]125 // Zero and sign extension instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]126 InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
127 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>,
128 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
129 InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>,
130 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
131 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Evan Cheng62d626c2010-09-25 00:49:35 +0000[diff] [blame]132 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]133 // Compare instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]134 InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
135 InstrStage<1, [A9_ALU0, A9_ALU1]>],
136 [1], [A9_LdBypass]>,
137 InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
138 InstrStage<1, [A9_ALU0, A9_ALU1]>],
139 [1, 1], [A9_LdBypass, A9_LdBypass]>,
Andrew Trick163a2442011-01-04 00:32:57 +0000[diff] [blame]140 InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
141 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]142 [1, 1], [A9_LdBypass, NoBypass]>,
143 InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
144 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]145 [1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]146 //
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]147 // Test instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]148 InstrItinData<IIC_iTSTi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
149 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
150 InstrItinData<IIC_iTSTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
151 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
152 InstrItinData<IIC_iTSTsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
153 InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>,
154 InstrItinData<IIC_iTSTsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
155 InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]156 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]157 // Move instructions, conditional
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]158 // FIXME: Correctly model the extra input dep on the destination.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]159 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
160 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
161 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
162 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
163 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
164 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
165 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
166 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
Evan Cheng79ff5232010-11-13 05:14:20 +0000[diff] [blame]167 InstrItinData<IIC_iCMOVix2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
168 InstrStage<1, [A9_ALU0, A9_ALU1]>,
169 InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
170 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]171
172 // Integer multiply pipeline
173 //
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]174 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
175 InstrStage<2, [A9_ALU0]>], [3, 1, 1]>,
176 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
177 InstrStage<2, [A9_ALU0]>],
178 [3, 1, 1, 1]>,
179 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
180 InstrStage<2, [A9_ALU0]>], [4, 1, 1]>,
181 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
182 InstrStage<2, [A9_ALU0]>],
183 [4, 1, 1, 1]>,
184 InstrItinData<IIC_iMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
185 InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>,
186 InstrItinData<IIC_iMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
187 InstrStage<3, [A9_ALU0]>],
188 [4, 5, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]189 // Integer load pipeline
190 // FIXME: The timings are some rough approximations
191 //
192 // Immediate offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]193 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]194 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]195 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]196 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]197 [3, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]198 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]199 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]200 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]201 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]202 [4, 1], [A9_LdBypass]>,
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]204 InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]205 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]206 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]207 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]208 [3, 3, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]209 //
210 // Register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]211 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]212 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]213 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]214 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]215 [3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]216 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]217 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]218 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]219 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]220 [4, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]221 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]222 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]223 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]224 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]225 [3, 3, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]226 //
227 // Scaled register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]228 InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]229 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]230 InstrStage<1, [A9_AGU], 0>,
231 InstrStage<1, [A9_LSUnit], 0>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]232 [4, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]233 InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]234 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]235 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]236 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]237 [5, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]238 //
239 // Immediate offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]240 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]241 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]242 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]243 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]244 [3, 2, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]245 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]246 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]247 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]248 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]249 [4, 3, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]250 //
251 // Register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]252 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]253 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]254 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]255 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]256 [3, 2, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]257 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]258 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]259 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]260 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]261 [4, 3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]262 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]263 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]264 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]265 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]266 [3, 3, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]267 //
268 // Scaled register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]269 InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]270 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]271 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]272 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]273 [4, 3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]274 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]275 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]276 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]277 InstrStage<1, [A9_LSUnit]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]278 [5, 4, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]279 //
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]280 // Load multiple, def is the 5th operand.
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]281 // FIXME: This assumes 3 to 4 registers.
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]282 InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]283 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]284 InstrStage<2, [A9_AGU], 1>,
285 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]286 [1, 1, 1, 1, 3],
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]287 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
288 -1>, // dynamic uops
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]289 //
290 // Load multiple + update, defs are the 1st and 5th operands.
291 InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
292 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]293 InstrStage<2, [A9_AGU], 1>,
294 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]295 [2, 1, 1, 1, 3],
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]296 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
297 -1>, // dynamic uops
Evan Cheng722cd122010-09-08 22:57:08 +0000[diff] [blame]298 //
299 // Load multiple plus branch
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]300 InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]301 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]302 InstrStage<1, [A9_AGU], 1>,
303 InstrStage<2, [A9_LSUnit]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]304 InstrStage<1, [A9_Branch]>],
305 [1, 2, 1, 1, 3],
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]306 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
307 -1>, // dynamic uops
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]308 //
309 // Pop, def is the 3rd operand.
310 InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
311 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]312 InstrStage<2, [A9_AGU], 1>,
313 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]314 [1, 1, 3],
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]315 [NoBypass, NoBypass, A9_LdBypass],
316 -1>, // dynamic uops
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]317 //
318 // Pop + branch, def is the 3rd operand.
319 InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
320 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]321 InstrStage<2, [A9_AGU], 1>,
322 InstrStage<2, [A9_LSUnit]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]323 InstrStage<1, [A9_Branch]>],
324 [1, 1, 3],
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]325 [NoBypass, NoBypass, A9_LdBypass],
326 -1>, // dynamic uops
Evan Chenge37da032010-09-24 22:41:41 +0000[diff] [blame]327 //
328 // iLoadi + iALUr for t2LDRpci_pic.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]329 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]330 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]331 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]332 InstrStage<1, [A9_LSUnit]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]333 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]334 [2, 1]>,
Evan Chenge37da032010-09-24 22:41:41 +0000[diff] [blame]335
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]336 // Integer store pipeline
337 ///
338 // Immediate offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]339 InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]340 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]341 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]342 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]343 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]344 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]345 InstrStage<2, [A9_AGU], 1>,
346 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]348 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]349 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]350 InstrStage<2, [A9_AGU], 1>,
351 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]352 //
353 // Register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]354 InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]355 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]356 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]357 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]358 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]359 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]360 InstrStage<2, [A9_AGU], 1>,
361 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]362 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]363 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]364 InstrStage<2, [A9_AGU], 1>,
365 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]366 //
367 // Scaled register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]368 InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
369 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]370 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]371 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]372 InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]373 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]374 InstrStage<2, [A9_AGU], 1>,
375 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]376 //
377 // Immediate offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]378 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
379 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]380 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]381 InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]382 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]383 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]384 InstrStage<2, [A9_AGU], 1>,
385 InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]386 //
387 // Register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]388 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
389 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]390 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]391 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]392 [2, 1, 1, 1]>,
393 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]394 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]395 InstrStage<2, [A9_AGU], 1>,
396 InstrStage<1, [A9_LSUnit]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]397 [3, 1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]398 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
399 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]400 InstrStage<2, [A9_AGU], 1>,
401 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]402 [3, 1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]403 //
404 // Scaled register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]405 InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
406 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]407 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]408 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]409 [2, 1, 1, 1]>,
410 InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
411 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]412 InstrStage<2, [A9_AGU], 1>,
413 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]414 [3, 1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]415 //
416 // Store multiple
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]417 InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]418 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]419 InstrStage<1, [A9_AGU], 0>,
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]420 InstrStage<2, [A9_LSUnit]>],
421 [], [], -1>, // dynamic uops
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]422 //
423 // Store multiple + update
424 InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
425 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]426 InstrStage<1, [A9_AGU], 0>,
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]427 InstrStage<2, [A9_LSUnit]>],
428 [2], [], -1>, // dynamic uops
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]429 //
430 // Preload
431 InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>,
432
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]433 // Branch
434 //
435 // no delay slots, so the latency of a branch is unimportant
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]436 InstrItinData<IIC_Br , [InstrStage<1, [A9_Issue0], 0>,
437 InstrStage<1, [A9_Issue1], 0>,
438 InstrStage<1, [A9_Branch]>]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]439
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]440 // VFP and NEON shares the same register file. This means that every VFP
441 // instruction should wait for full completion of the consecutive NEON
442 // instruction and vice-versa. We model this behavior with two artificial FUs:
443 // DRegsVFP and DRegsVFP.
444 //
445 // Every VFP instruction:
446 // - Acquires DRegsVFP resource for 1 cycle
447 // - Reserves DRegsN resource for the whole duration (including time to
448 // register file writeback!).
449 // Every NEON instruction does the same but with FUs swapped.
450 //
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]451 // Since the reserved FU cannot be acquired, this models precisely
452 // "cross-domain" stalls.
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]453
454 // VFP
455 // Issue through integer pipeline, and execute in NEON unit.
456
457 // FP Special Register to Integer Register File Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]458 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]459 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]460 InstrStage<1, [A9_DRegsVFP], 0, Required>,
461 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng99cce362010-10-29 23:16:55 +0000[diff] [blame]462 InstrStage<1, [A9_NPipe]>],
463 [1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]464 //
465 // Single-precision FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]466 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
467 InstrStage<1, [A9_MUX0], 0>,
468 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]469 // Extra latency cycles since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]470 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]471 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]472 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]473 //
474 // Double-precision FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]475 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
476 InstrStage<1, [A9_MUX0], 0>,
477 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]478 // Extra latency cycles since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]479 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]480 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]481 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]482
483 //
484 // Single-precision FP Compare
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]485 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
486 InstrStage<1, [A9_MUX0], 0>,
487 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]488 // Extra latency cycles since wbck is 4 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]489 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]490 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]491 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]492 //
493 // Double-precision FP Compare
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]494 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
495 InstrStage<1, [A9_MUX0], 0>,
496 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]497 // Extra latency cycles since wbck is 4 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]498 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]499 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]500 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]501 //
502 // Single to Double FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]503 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]504 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]505 InstrStage<1, [A9_DRegsVFP], 0, Required>,
506 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]507 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]508 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]509 //
510 // Double to Single FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]511 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]512 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]513 InstrStage<1, [A9_DRegsVFP], 0, Required>,
514 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]515 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]516 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]517
518 //
519 // Single to Half FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]520 InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]521 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]522 InstrStage<1, [A9_DRegsVFP], 0, Required>,
523 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]524 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]525 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]526 //
527 // Half to Single FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]528 InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]529 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]530 InstrStage<1, [A9_DRegsVFP], 0, Required>,
531 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]532 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]533 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]534
535 //
536 // Single-Precision FP to Integer Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]537 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]538 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]539 InstrStage<1, [A9_DRegsVFP], 0, Required>,
540 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]541 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]542 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]543 //
544 // Double-Precision FP to Integer Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]545 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]546 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]547 InstrStage<1, [A9_DRegsVFP], 0, Required>,
548 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]549 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]550 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]551 //
552 // Integer to Single-Precision FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]553 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]554 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]555 InstrStage<1, [A9_DRegsVFP], 0, Required>,
556 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]557 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]558 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]559 //
560 // Integer to Double-Precision FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]561 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]562 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]563 InstrStage<1, [A9_DRegsVFP], 0, Required>,
564 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]565 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]566 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]567 //
568 // Single-precision FP ALU
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]569 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]570 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]571 InstrStage<1, [A9_DRegsVFP], 0, Required>,
572 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]573 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]574 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]575 //
576 // Double-precision FP ALU
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]577 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]578 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]579 InstrStage<1, [A9_DRegsVFP], 0, Required>,
580 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]581 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]582 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]583 //
584 // Single-precision FP Multiply
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]585 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]586 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]587 InstrStage<1, [A9_DRegsVFP], 0, Required>,
588 InstrStage<6, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]589 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]590 [5, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]591 //
592 // Double-precision FP Multiply
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]593 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]594 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]595 InstrStage<1, [A9_DRegsVFP], 0, Required>,
596 InstrStage<7, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]597 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]598 [6, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]599 //
600 // Single-precision FP MAC
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]601 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]602 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]603 InstrStage<1, [A9_DRegsVFP], 0, Required>,
604 InstrStage<9, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]605 InstrStage<1, [A9_NPipe]>],
Evan Chengff310732010-10-28 06:47:08 +0000[diff] [blame]606 [8, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]607 //
608 // Double-precision FP MAC
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]609 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]610 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]611 InstrStage<1, [A9_DRegsVFP], 0, Required>,
612 InstrStage<10, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]613 InstrStage<2, [A9_NPipe]>],
Evan Chengff310732010-10-28 06:47:08 +0000[diff] [blame]614 [9, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]615 //
Evan Chengaca6c822012-04-11 00:13:00 +0000[diff] [blame]616 // Single-precision Fused FP MAC
617 InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
618 InstrStage<1, [A9_MUX0], 0>,
619 InstrStage<1, [A9_DRegsVFP], 0, Required>,
620 InstrStage<9, [A9_DRegsN], 0, Reserved>,
621 InstrStage<1, [A9_NPipe]>],
622 [8, 1, 1, 1]>,
623 //
624 // Double-precision Fused FP MAC
625 InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
626 InstrStage<1, [A9_MUX0], 0>,
627 InstrStage<1, [A9_DRegsVFP], 0, Required>,
628 InstrStage<10, [A9_DRegsN], 0, Reserved>,
629 InstrStage<2, [A9_NPipe]>],
630 [9, 1, 1, 1]>,
631 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]632 // Single-precision FP DIV
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]633 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]634 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]635 InstrStage<1, [A9_DRegsVFP], 0, Required>,
636 InstrStage<16, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]637 InstrStage<10, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]638 [15, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]639 //
640 // Double-precision FP DIV
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]641 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]642 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]643 InstrStage<1, [A9_DRegsVFP], 0, Required>,
644 InstrStage<26, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]645 InstrStage<20, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]646 [25, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]647 //
648 // Single-precision FP SQRT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]649 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]650 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]651 InstrStage<1, [A9_DRegsVFP], 0, Required>,
652 InstrStage<18, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]653 InstrStage<13, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]654 [17, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]655 //
656 // Double-precision FP SQRT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]657 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]658 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]659 InstrStage<1, [A9_DRegsVFP], 0, Required>,
660 InstrStage<33, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]661 InstrStage<28, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]662 [32, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]663
664 //
665 // Integer to Single-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]666 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
667 InstrStage<1, [A9_MUX0], 0>,
668 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]669 // Extra 1 latency cycle since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]670 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]671 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]672 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]673 //
674 // Integer to Double-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]675 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
676 InstrStage<1, [A9_MUX0], 0>,
677 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]678 // Extra 1 latency cycle since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]679 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]680 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]681 [1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]682 //
683 // Single-precision to Integer Move
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]684 //
685 // On A9 move-from-VFP is free to issue with no stall if other VFP
686 // operations are in flight. I assume it still can't dual-issue though.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]687 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]688 InstrStage<1, [A9_MUX0], 0>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]689 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]690 //
691 // Double-precision to Integer Move
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]692 //
693 // On A9 move-from-VFP is free to issue with no stall if other VFP
694 // operations are in flight. I assume it still can't dual-issue though.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]695 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]696 InstrStage<1, [A9_MUX0], 0>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]697 [2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]698 //
699 // Single-precision FP Load
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]700 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]701 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]702 InstrStage<1, [A9_DRegsVFP], 0, Required>,
703 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]704 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]705 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]706 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]707 //
708 // Double-precision FP Load
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]709 // FIXME: Result latency is 1 if address is 64-bit aligned.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]710 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]711 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]712 InstrStage<1, [A9_DRegsVFP], 0, Required>,
713 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]714 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]715 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]716 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]717 //
718 // FP Load Multiple
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]720 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]721 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]722 InstrStage<1, [A9_DRegsVFP], 0, Required>,
723 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]724 InstrStage<1, [A9_NPipe], 0>,
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]725 InstrStage<2, [A9_LSUnit]>],
726 [1, 1, 1, 1], [], -1>, // dynamic uops
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]727 //
728 // FP Load Multiple + update
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]729 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]730 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]731 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]732 InstrStage<1, [A9_DRegsVFP], 0, Required>,
733 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]734 InstrStage<1, [A9_NPipe], 0>,
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]735 InstrStage<2, [A9_LSUnit]>],
736 [2, 1, 1, 1], [], -1>, // dynamic uops
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]737 //
738 // Single-precision FP Store
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]739 InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]740 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]741 InstrStage<1, [A9_DRegsVFP], 0, Required>,
742 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]743 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]744 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]745 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]746 //
747 // Double-precision FP Store
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]748 InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]749 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]750 InstrStage<1, [A9_DRegsVFP], 0, Required>,
751 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]752 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]753 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]754 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]755 //
756 // FP Store Multiple
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]757 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]758 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]759 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]760 InstrStage<1, [A9_DRegsVFP], 0, Required>,
761 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]762 InstrStage<1, [A9_NPipe], 0>,
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]763 InstrStage<2, [A9_LSUnit]>],
764 [1, 1, 1, 1], [], -1>, // dynamic uops
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]765 //
766 // FP Store Multiple + update
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]767 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]768 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]769 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]770 InstrStage<1, [A9_DRegsVFP], 0, Required>,
771 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]772 InstrStage<1, [A9_NPipe], 0>,
Andrew Trickf161e392012-07-02 18:10:42 +0000[diff] [blame]773 InstrStage<2, [A9_LSUnit]>],
774 [2, 1, 1, 1], [], -1>, // dynamic uops
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]775 // NEON
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]776 // VLD1
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]777 InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]778 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]779 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]780 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
781 InstrStage<1, [A9_NPipe], 0>,
782 InstrStage<1, [A9_LSUnit]>],
783 [1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]784 // VLD1x2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]785 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]786 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]787 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]788 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
789 InstrStage<1, [A9_NPipe], 0>,
790 InstrStage<1, [A9_LSUnit]>],
791 [1, 1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]792 // VLD1x3
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]793 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]794 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]795 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]796 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
797 InstrStage<2, [A9_NPipe], 0>,
798 InstrStage<2, [A9_LSUnit]>],
799 [1, 1, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]800 // VLD1x4
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]801 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]802 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]803 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]804 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
805 InstrStage<2, [A9_NPipe], 0>,
806 InstrStage<2, [A9_LSUnit]>],
807 [1, 1, 2, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]808 // VLD1u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]809 InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]810 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]811 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]812 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
813 InstrStage<1, [A9_NPipe], 0>,
814 InstrStage<1, [A9_LSUnit]>],
815 [1, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]816 // VLD1x2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]817 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]818 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]819 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]820 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
821 InstrStage<1, [A9_NPipe], 0>,
822 InstrStage<1, [A9_LSUnit]>],
823 [1, 1, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]824 // VLD1x3u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]825 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]826 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]827 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]828 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
829 InstrStage<2, [A9_NPipe], 0>,
830 InstrStage<2, [A9_LSUnit]>],
831 [1, 1, 2, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]832 // VLD1x4u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]833 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]834 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]835 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]836 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
837 InstrStage<2, [A9_NPipe], 0>,
838 InstrStage<2, [A9_LSUnit]>],
839 [1, 1, 2, 2, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]840 //
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame]841 // VLD1ln
842 InstrItinData<IIC_VLD1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
843 InstrStage<1, [A9_MUX0], 0>,
844 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]845 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
846 InstrStage<2, [A9_NPipe], 0>,
847 InstrStage<2, [A9_LSUnit]>],
848 [3, 1, 1, 1]>,
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame]849 //
850 // VLD1lnu
851 InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
852 InstrStage<1, [A9_MUX0], 0>,
853 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]854 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
855 InstrStage<2, [A9_NPipe], 0>,
856 InstrStage<2, [A9_LSUnit]>],
857 [3, 2, 1, 1, 1, 1]>,
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame]858 //
Bob Wilsonc92eea02010-11-27 06:35:16 +0000[diff] [blame]859 // VLD1dup
860 InstrItinData<IIC_VLD1dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
861 InstrStage<1, [A9_MUX0], 0>,
862 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]863 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
864 InstrStage<1, [A9_NPipe], 0>,
865 InstrStage<1, [A9_LSUnit]>],
866 [2, 1]>,
Bob Wilsonc92eea02010-11-27 06:35:16 +0000[diff] [blame]867 //
868 // VLD1dupu
869 InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
870 InstrStage<1, [A9_MUX0], 0>,
871 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]872 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
873 InstrStage<1, [A9_NPipe], 0>,
874 InstrStage<1, [A9_LSUnit]>],
875 [2, 2, 1, 1]>,
Bob Wilsonc92eea02010-11-27 06:35:16 +0000[diff] [blame]876 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]877 // VLD2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]878 InstrItinData<IIC_VLD2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
879 InstrStage<1, [A9_MUX0], 0>,
880 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]881 // Extra latency cycles since wbck is 7 cycles
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]882 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
883 InstrStage<1, [A9_NPipe], 0>,
884 InstrStage<1, [A9_LSUnit]>],
885 [2, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]886 //
887 // VLD2x2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]888 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]889 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]890 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]891 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
892 InstrStage<2, [A9_NPipe], 0>,
893 InstrStage<2, [A9_LSUnit]>],
894 [2, 3, 2, 3, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]895 //
896 // VLD2ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]897 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]898 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]899 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]900 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
901 InstrStage<2, [A9_NPipe], 0>,
902 InstrStage<2, [A9_LSUnit]>],
903 [3, 3, 1, 1, 1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]904 //
905 // VLD2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]906 InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
907 InstrStage<1, [A9_MUX0], 0>,
908 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]909 // Extra latency cycles since wbck is 7 cycles
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]910 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
911 InstrStage<1, [A9_NPipe], 0>,
912 InstrStage<1, [A9_LSUnit]>],
913 [2, 2, 2, 1, 1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]914 //
915 // VLD2x2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]916 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]917 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]918 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]919 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
920 InstrStage<2, [A9_NPipe], 0>,
921 InstrStage<2, [A9_LSUnit]>],
922 [2, 3, 2, 3, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]923 //
924 // VLD2lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]925 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]926 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]927 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]928 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
929 InstrStage<2, [A9_NPipe], 0>,
930 InstrStage<2, [A9_LSUnit]>],
931 [3, 3, 2, 1, 1, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]932 //
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]933 // VLD2dup
934 InstrItinData<IIC_VLD2dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
935 InstrStage<1, [A9_MUX0], 0>,
936 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]937 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
938 InstrStage<1, [A9_NPipe], 0>,
939 InstrStage<1, [A9_LSUnit]>],
940 [2, 2, 1]>,
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]941 //
942 // VLD2dupu
943 InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
944 InstrStage<1, [A9_MUX0], 0>,
945 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]946 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
947 InstrStage<1, [A9_NPipe], 0>,
948 InstrStage<1, [A9_LSUnit]>],
949 [2, 2, 2, 1, 1]>,
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]950 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]951 // VLD3
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]952 InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]953 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]954 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]955 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
956 InstrStage<3, [A9_NPipe], 0>,
957 InstrStage<3, [A9_LSUnit]>],
958 [3, 3, 4, 1]>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]959 //
960 // VLD3ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]961 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]962 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]963 InstrStage<1, [A9_DRegsN], 0, Required>,
964 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]965 InstrStage<5, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]966 InstrStage<5, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]967 [5, 5, 6, 1, 1, 1, 1, 2]>,
968 //
969 // VLD3u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]970 InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]971 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]972 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]973 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
974 InstrStage<3, [A9_NPipe], 0>,
975 InstrStage<3, [A9_LSUnit]>],
976 [3, 3, 4, 2, 1]>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]977 //
978 // VLD3lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]979 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]980 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]981 InstrStage<1, [A9_DRegsN], 0, Required>,
982 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]983 InstrStage<5, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]984 InstrStage<5, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]985 [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]986 //
Bob Wilson77ab1652010-11-29 19:35:29 +0000[diff] [blame]987 // VLD3dup
988 InstrItinData<IIC_VLD3dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
989 InstrStage<1, [A9_MUX0], 0>,
990 InstrStage<1, [A9_DRegsN], 0, Required>,
991 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
992 InstrStage<3, [A9_NPipe], 0>,
993 InstrStage<3, [A9_LSUnit]>],
994 [3, 3, 4, 1]>,
995 //
996 // VLD3dupu
997 InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
998 InstrStage<1, [A9_MUX0], 0>,
999 InstrStage<1, [A9_DRegsN], 0, Required>,
1000 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1001 InstrStage<3, [A9_NPipe], 0>,
1002 InstrStage<3, [A9_LSUnit]>],
1003 [3, 3, 4, 2, 1, 1]>,
1004 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1005 // VLD4
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1006 InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1007 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1008 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1009 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
1010 InstrStage<3, [A9_NPipe], 0>,
1011 InstrStage<3, [A9_LSUnit]>],
1012 [3, 3, 4, 4, 1]>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1013 //
1014 // VLD4ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1015 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1016 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1017 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1018 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
1019 InstrStage<4, [A9_NPipe], 0>,
1020 InstrStage<4, [A9_LSUnit]>],
1021 [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1022 //
1023 // VLD4u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1024 InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1025 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1026 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1027 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
1028 InstrStage<3, [A9_NPipe], 0>,
1029 InstrStage<3, [A9_LSUnit]>],
1030 [3, 3, 4, 4, 2, 1]>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1031 //
1032 // VLD4lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1033 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1034 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1035 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1036 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
1037 InstrStage<4, [A9_NPipe], 0>,
1038 InstrStage<4, [A9_LSUnit]>],
1039 [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1040 //
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000[diff] [blame]1041 // VLD4dup
1042 InstrItinData<IIC_VLD4dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1043 InstrStage<1, [A9_MUX0], 0>,
1044 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1045 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1046 InstrStage<2, [A9_NPipe], 0>,
1047 InstrStage<2, [A9_LSUnit]>],
1048 [2, 2, 3, 3, 1]>,
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000[diff] [blame]1049 //
1050 // VLD4dupu
1051 InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1052 InstrStage<1, [A9_MUX0], 0>,
1053 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1054 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1055 InstrStage<2, [A9_NPipe], 0>,
1056 InstrStage<2, [A9_LSUnit]>],
1057 [2, 2, 3, 3, 2, 1, 1]>,
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000[diff] [blame]1058 //
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1059 // VST1
1060 InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1061 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1062 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1063 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1064 InstrStage<1, [A9_NPipe], 0>,
1065 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1066 [1, 1, 1]>,
1067 //
1068 // VST1x2
1069 InstrItinData<IIC_VST1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1070 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1071 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1072 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1073 InstrStage<1, [A9_NPipe], 0>,
1074 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1075 [1, 1, 1, 1]>,
1076 //
1077 // VST1x3
1078 InstrItinData<IIC_VST1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1079 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1080 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1081 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1082 InstrStage<2, [A9_NPipe], 0>,
1083 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1084 [1, 1, 1, 1, 2]>,
1085 //
1086 // VST1x4
1087 InstrItinData<IIC_VST1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1088 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1089 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1090 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1091 InstrStage<2, [A9_NPipe], 0>,
1092 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1093 [1, 1, 1, 1, 2, 2]>,
1094 //
1095 // VST1u
1096 InstrItinData<IIC_VST1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1097 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1098 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1099 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1100 InstrStage<1, [A9_NPipe], 0>,
1101 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1102 [2, 1, 1, 1, 1]>,
1103 //
1104 // VST1x2u
1105 InstrItinData<IIC_VST1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1106 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1107 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1108 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1109 InstrStage<1, [A9_NPipe], 0>,
1110 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1111 [2, 1, 1, 1, 1, 1]>,
1112 //
1113 // VST1x3u
1114 InstrItinData<IIC_VST1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1115 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1116 InstrStage<1, [A9_DRegsN], 0, Required>,
1117 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1118 InstrStage<2, [A9_NPipe], 0>,
1119 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1120 [2, 1, 1, 1, 1, 1, 2]>,
1121 //
1122 // VST1x4u
1123 InstrItinData<IIC_VST1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1124 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1125 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1126 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1127 InstrStage<2, [A9_NPipe], 0>,
1128 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1129 [2, 1, 1, 1, 1, 1, 2, 2]>,
1130 //
Bob Wilsond80b29d2010-11-02 21:18:25 +0000[diff] [blame]1131 // VST1ln
1132 InstrItinData<IIC_VST1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1133 InstrStage<1, [A9_MUX0], 0>,
1134 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1135 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1136 InstrStage<1, [A9_NPipe], 0>,
1137 InstrStage<1, [A9_LSUnit]>],
Bob Wilsond80b29d2010-11-02 21:18:25 +0000[diff] [blame]1138 [1, 1, 1]>,
1139 //
1140 // VST1lnu
1141 InstrItinData<IIC_VST1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1142 InstrStage<1, [A9_MUX0], 0>,
1143 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1144 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1145 InstrStage<1, [A9_NPipe], 0>,
1146 InstrStage<1, [A9_LSUnit]>],
Bob Wilsond80b29d2010-11-02 21:18:25 +0000[diff] [blame]1147 [2, 1, 1, 1, 1]>,
1148 //
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1149 // VST2
1150 InstrItinData<IIC_VST2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1151 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1152 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1153 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1154 InstrStage<1, [A9_NPipe], 0>,
1155 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1156 [1, 1, 1, 1]>,
1157 //
1158 // VST2x2
1159 InstrItinData<IIC_VST2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1160 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1161 InstrStage<1, [A9_DRegsN], 0, Required>,
1162 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1163 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1164 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1165 [1, 1, 1, 1, 2, 2]>,
1166 //
1167 // VST2u
1168 InstrItinData<IIC_VST2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1169 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1170 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1171 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1172 InstrStage<1, [A9_NPipe], 0>,
1173 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1174 [2, 1, 1, 1, 1, 1]>,
1175 //
1176 // VST2x2u
1177 InstrItinData<IIC_VST2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1178 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1179 InstrStage<1, [A9_DRegsN], 0, Required>,
1180 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1181 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1182 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1183 [2, 1, 1, 1, 1, 1, 2, 2]>,
1184 //
1185 // VST2ln
1186 InstrItinData<IIC_VST2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1187 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1188 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1189 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1190 InstrStage<1, [A9_NPipe], 0>,
1191 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1192 [1, 1, 1, 1]>,
1193 //
1194 // VST2lnu
1195 InstrItinData<IIC_VST2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1196 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1197 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1198 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1199 InstrStage<1, [A9_NPipe], 0>,
1200 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1201 [2, 1, 1, 1, 1, 1]>,
1202 //
1203 // VST3
1204 InstrItinData<IIC_VST3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1205 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1206 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1207 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1208 InstrStage<2, [A9_NPipe], 0>,
1209 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1210 [1, 1, 1, 1, 2]>,
1211 //
1212 // VST3u
1213 InstrItinData<IIC_VST3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1214 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1215 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1216 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1217 InstrStage<2, [A9_NPipe], 0>,
1218 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1219 [2, 1, 1, 1, 1, 1, 2]>,
1220 //
1221 // VST3ln
1222 InstrItinData<IIC_VST3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1223 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1224 InstrStage<1, [A9_DRegsN], 0, Required>,
1225 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1226 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1227 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1228 [1, 1, 1, 1, 2]>,
1229 //
1230 // VST3lnu
1231 InstrItinData<IIC_VST3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1232 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1233 InstrStage<1, [A9_DRegsN], 0, Required>,
1234 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1235 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1236 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1237 [2, 1, 1, 1, 1, 1, 2]>,
1238 //
1239 // VST4
1240 InstrItinData<IIC_VST4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1241 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1242 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1243 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1244 InstrStage<2, [A9_NPipe], 0>,
1245 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1246 [1, 1, 1, 1, 2, 2]>,
1247 //
1248 // VST4u
1249 InstrItinData<IIC_VST4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1250 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1251 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1252 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1253 InstrStage<2, [A9_NPipe], 0>,
1254 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1255 [2, 1, 1, 1, 1, 1, 2, 2]>,
1256 //
1257 // VST4ln
1258 InstrItinData<IIC_VST4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1259 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1260 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1261 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1262 InstrStage<2, [A9_NPipe], 0>,
1263 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1264 [1, 1, 1, 1, 2, 2]>,
1265 //
1266 // VST4lnu
1267 InstrItinData<IIC_VST4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1268 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1269 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1270 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1271 InstrStage<2, [A9_NPipe], 0>,
1272 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1273 [2, 1, 1, 1, 1, 1, 2, 2]>,
1274
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1275 //
1276 // Double-register Integer Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1277 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1278 InstrStage<1, [A9_MUX0], 0>,
1279 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1280 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1281 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1282 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1283 [4, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1284 //
1285 // Quad-register Integer Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1286 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1287 InstrStage<1, [A9_MUX0], 0>,
1288 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1289 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1290 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1291 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1292 [4, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1293 //
1294 // Double-register Integer Q-Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1295 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1296 InstrStage<1, [A9_MUX0], 0>,
1297 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1298 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1299 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1300 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1301 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1302 //
1303 // Quad-register Integer CountQ-Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1304 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1305 InstrStage<1, [A9_MUX0], 0>,
1306 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1307 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1308 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1309 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1310 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1311 //
1312 // Double-register Integer Binary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1313 InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1314 InstrStage<1, [A9_MUX0], 0>,
1315 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1316 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1317 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1318 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1319 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1320 //
1321 // Quad-register Integer Binary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1322 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1323 InstrStage<1, [A9_MUX0], 0>,
1324 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1325 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1326 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1327 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1328 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1329 //
1330 // Double-register Integer Subtract
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1331 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1332 InstrStage<1, [A9_MUX0], 0>,
1333 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1334 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1335 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1336 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1337 [3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1338 //
1339 // Quad-register Integer Subtract
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1340 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1341 InstrStage<1, [A9_MUX0], 0>,
1342 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1343 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1344 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1345 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1346 [3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1347 //
1348 // Double-register Integer Shift
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1349 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1350 InstrStage<1, [A9_MUX0], 0>,
1351 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1352 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1353 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1354 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1355 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1356 //
1357 // Quad-register Integer Shift
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1358 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1359 InstrStage<1, [A9_MUX0], 0>,
1360 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1361 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1362 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1363 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1364 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1365 //
1366 // Double-register Integer Shift (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1367 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1368 InstrStage<1, [A9_MUX0], 0>,
1369 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1370 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1371 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1372 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1373 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1374 //
1375 // Quad-register Integer Shift (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1376 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1377 InstrStage<1, [A9_MUX0], 0>,
1378 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1379 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1380 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1381 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1382 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1383 //
1384 // Double-register Integer Binary (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1385 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1386 InstrStage<1, [A9_MUX0], 0>,
1387 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1388 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1389 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1390 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1391 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1392 //
1393 // Quad-register Integer Binary (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1394 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1395 InstrStage<1, [A9_MUX0], 0>,
1396 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1397 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1398 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1399 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1400 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1401 //
1402 // Double-register Integer Subtract (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1403 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1404 InstrStage<1, [A9_MUX0], 0>,
1405 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1406 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1407 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1408 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1409 [4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1410 //
1411 // Quad-register Integer Subtract (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1412 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1413 InstrStage<1, [A9_MUX0], 0>,
1414 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1415 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1416 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1417 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1418 [4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1419
1420 //
1421 // Double-register Integer Count
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1422 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1423 InstrStage<1, [A9_MUX0], 0>,
1424 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1425 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1426 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1427 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1428 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1429 //
1430 // Quad-register Integer Count
1431 // Result written in N3, but that is relative to the last cycle of multicycle,
1432 // so we use 4 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1433 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1434 InstrStage<1, [A9_MUX0], 0>,
1435 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1436 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1437 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1438 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1439 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1440 //
1441 // Double-register Absolute Difference and Accumulate
Evan Cheng7f3e9152010-12-08 23:01:18 +0000[diff] [blame]1442 InstrItinData<IIC_VABAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1443 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1444 InstrStage<1, [A9_DRegsN], 0, Required>,
1445 // Extra latency cycles since wbck is 6 cycles
Evan Cheng7f3e9152010-12-08 23:01:18 +0000[diff] [blame]1446 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1447 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1448 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1449 //
1450 // Quad-register Absolute Difference and Accumulate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1451 InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1452 InstrStage<1, [A9_MUX0], 0>,
1453 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1454 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1455 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1456 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1457 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1458 //
1459 // Double-register Integer Pair Add Long
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1460 InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1461 InstrStage<1, [A9_MUX0], 0>,
1462 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1463 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1464 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1465 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1466 [6, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1467 //
1468 // Quad-register Integer Pair Add Long
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1469 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1470 InstrStage<1, [A9_MUX0], 0>,
1471 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1472 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1473 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1474 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1475 [6, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1476
1477 //
1478 // Double-register Integer Multiply (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1479 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1480 InstrStage<1, [A9_MUX0], 0>,
1481 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1482 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1483 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1484 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1485 [6, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1486 //
1487 // Quad-register Integer Multiply (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1488 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1489 InstrStage<1, [A9_MUX0], 0>,
1490 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1491 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1492 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1493 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1494 [7, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1495
1496 //
1497 // Double-register Integer Multiply (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1498 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1499 InstrStage<1, [A9_MUX0], 0>,
1500 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1501 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1502 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1503 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1504 [7, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1505 //
1506 // Quad-register Integer Multiply (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1507 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1508 InstrStage<1, [A9_MUX0], 0>,
1509 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1510 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1511 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1512 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1513 [9, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1514 //
1515 // Double-register Integer Multiply-Accumulate (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1516 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1517 InstrStage<1, [A9_MUX0], 0>,
1518 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1519 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1520 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1521 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1522 [6, 3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1523 //
1524 // Double-register Integer Multiply-Accumulate (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1525 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1526 InstrStage<1, [A9_MUX0], 0>,
1527 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1528 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1529 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1530 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1531 [7, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1532 //
1533 // Quad-register Integer Multiply-Accumulate (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1534 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1535 InstrStage<1, [A9_MUX0], 0>,
1536 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1537 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1538 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1539 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1540 [7, 3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1541 //
1542 // Quad-register Integer Multiply-Accumulate (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1543 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1544 InstrStage<1, [A9_MUX0], 0>,
1545 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1546 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1547 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1548 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1549 [9, 3, 2, 1]>,
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1550
1551 //
1552 // Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1553 InstrItinData<IIC_VMOV, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1554 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1555 InstrStage<1, [A9_DRegsN], 0, Required>,
1556 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1557 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1558 [1,1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1559 //
1560 // Move Immediate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1561 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1562 InstrStage<1, [A9_MUX0], 0>,
1563 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1564 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1565 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1566 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1567 [3]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1568 //
1569 // Double-register Permute Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1570 InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1571 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1572 InstrStage<1, [A9_DRegsN], 0, Required>,
1573 // Extra latency cycles since wbck is 6 cycles
1574 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1575 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1576 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1577 //
1578 // Quad-register Permute Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1579 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1580 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1581 InstrStage<1, [A9_DRegsN], 0, Required>,
1582 // Extra latency cycles since wbck is 6 cycles
1583 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1584 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1585 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1586 //
1587 // Integer to Single-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1588 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1589 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1590 InstrStage<1, [A9_DRegsN], 0, Required>,
1591 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1592 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]1593 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1594 //
1595 // Integer to Double-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1596 InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1597 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1598 InstrStage<1, [A9_DRegsN], 0, Required>,
1599 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1600 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]1601 [1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1602 //
1603 // Single-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1604 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1605 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1606 InstrStage<1, [A9_DRegsN], 0, Required>,
1607 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1608 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1609 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1610 //
1611 // Double-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1612 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1613 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1614 InstrStage<1, [A9_DRegsN], 0, Required>,
1615 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1616 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1617 [2, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1618 //
1619 // Integer to Lane Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1620 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1621 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1622 InstrStage<1, [A9_DRegsN], 0, Required>,
1623 InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1624 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1625 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1626
1627 //
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1628 // Vector narrow move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1629 InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1630 InstrStage<1, [A9_MUX0], 0>,
1631 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1632 // Extra latency cycles since wbck is 6 cycles
1633 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1634 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1635 [3, 1]>,
1636 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1637 // Double-register FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1638 InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1639 InstrStage<1, [A9_MUX0], 0>,
1640 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1641 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1642 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1643 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1644 [5, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1645 //
1646 // Quad-register FP Unary
1647 // Result written in N5, but that is relative to the last cycle of multicycle,
1648 // so we use 6 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1649 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1650 InstrStage<1, [A9_MUX0], 0>,
1651 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1652 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1653 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1654 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1655 [6, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1656 //
1657 // Double-register FP Binary
1658 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1659 // optimistic.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1660 InstrItinData<IIC_VBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1661 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1662 InstrStage<1, [A9_DRegsN], 0, Required>,
1663 // Extra latency cycles since wbck is 6 cycles
1664 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1665 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1666 [5, 2, 2]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1667
1668 //
1669 // VPADD, etc.
1670 InstrItinData<IIC_VPBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1671 InstrStage<1, [A9_MUX0], 0>,
1672 InstrStage<1, [A9_DRegsN], 0, Required>,
1673 // Extra latency cycles since wbck is 6 cycles
1674 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1675 InstrStage<1, [A9_NPipe]>],
1676 [5, 1, 1]>,
1677 //
1678 // Double-register FP VMUL
1679 InstrItinData<IIC_VFMULD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1680 InstrStage<1, [A9_MUX0], 0>,
1681 InstrStage<1, [A9_DRegsN], 0, Required>,
1682 // Extra latency cycles since wbck is 6 cycles
1683 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1684 InstrStage<1, [A9_NPipe]>],
1685 [5, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1686 //
1687 // Quad-register FP Binary
1688 // Result written in N5, but that is relative to the last cycle of multicycle,
1689 // so we use 6 for those cases
1690 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1691 // optimistic.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1692 InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1693 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1694 InstrStage<1, [A9_DRegsN], 0, Required>,
1695 // Extra latency cycles since wbck is 7 cycles
1696 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1697 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1698 [6, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1699 //
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1700 // Quad-register FP VMUL
1701 InstrItinData<IIC_VFMULQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1702 InstrStage<1, [A9_MUX0], 0>,
1703 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1704 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1705 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1706 InstrStage<1, [A9_NPipe]>],
1707 [6, 2, 1]>,
1708 //
1709 // Double-register FP Multiple-Accumulate
1710 InstrItinData<IIC_VMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1711 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1712 InstrStage<1, [A9_DRegsN], 0, Required>,
1713 // Extra latency cycles since wbck is 7 cycles
1714 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1715 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1716 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1717 //
1718 // Quad-register FP Multiple-Accumulate
1719 // Result written in N9, but that is relative to the last cycle of multicycle,
1720 // so we use 10 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1721 InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1722 InstrStage<1, [A9_MUX0], 0>,
1723 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1724 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1725 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1726 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1727 [8, 4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1728 //
Evan Chengaca6c822012-04-11 00:13:00 +0000[diff] [blame]1729 // Double-register Fused FP Multiple-Accumulate
1730 InstrItinData<IIC_VFMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1731 InstrStage<1, [A9_MUX0], 0>,
1732 InstrStage<1, [A9_DRegsN], 0, Required>,
1733 // Extra latency cycles since wbck is 7 cycles
1734 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1735 InstrStage<2, [A9_NPipe]>],
1736 [6, 3, 2, 1]>,
1737 //
1738 // Quad-register Fused FP Multiple-Accumulate
1739 // Result written in N9, but that is relative to the last cycle of multicycle,
1740 // so we use 10 for those cases
1741 InstrItinData<IIC_VFMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1742 InstrStage<1, [A9_MUX0], 0>,
1743 InstrStage<1, [A9_DRegsN], 0, Required>,
1744 // Extra latency cycles since wbck is 9 cycles
1745 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1746 InstrStage<4, [A9_NPipe]>],
1747 [8, 4, 2, 1]>,
1748 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1749 // Double-register Reciprical Step
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1750 InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1751 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1752 InstrStage<1, [A9_DRegsN], 0, Required>,
1753 // Extra latency cycles since wbck is 10 cycles
1754 InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
1755 InstrStage<1, [A9_NPipe]>],
1756 [9, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1757 //
1758 // Quad-register Reciprical Step
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1759 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1760 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1761 InstrStage<1, [A9_DRegsN], 0, Required>,
1762 // Extra latency cycles since wbck is 11 cycles
1763 InstrStage<12, [A9_DRegsVFP], 0, Reserved>,
1764 InstrStage<2, [A9_NPipe]>],
1765 [10, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1766 //
1767 // Double-register Permute
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1768 InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1769 InstrStage<1, [A9_MUX0], 0>,
1770 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1771 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1772 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1773 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1774 [2, 2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1775 //
1776 // Quad-register Permute
1777 // Result written in N2, but that is relative to the last cycle of multicycle,
1778 // so we use 3 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1779 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1780 InstrStage<1, [A9_MUX0], 0>,
1781 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1782 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1783 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1784 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1785 [3, 3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1786 //
1787 // Quad-register Permute (3 cycle issue)
1788 // Result written in N2, but that is relative to the last cycle of multicycle,
1789 // so we use 4 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1790 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1791 InstrStage<1, [A9_MUX0], 0>,
1792 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1793 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1794 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1795 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1796 [4, 4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1797
1798 //
1799 // Double-register VEXT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1800 InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1801 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1802 InstrStage<1, [A9_DRegsN], 0, Required>,
1803 // Extra latency cycles since wbck is 6 cycles
1804 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1805 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1806 [2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1807 //
1808 // Quad-register VEXT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1809 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1810 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1811 InstrStage<1, [A9_DRegsN], 0, Required>,
1812 // Extra latency cycles since wbck is 7 cycles
1813 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1814 InstrStage<2, [A9_NPipe]>],
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1815 [3, 1, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1816 //
1817 // VTB
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1818 InstrItinData<IIC_VTB1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1819 InstrStage<1, [A9_MUX0], 0>,
1820 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1821 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1822 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1823 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1824 [3, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1825 InstrItinData<IIC_VTB2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1826 InstrStage<1, [A9_MUX0], 0>,
1827 InstrStage<2, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1828 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1829 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1830 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1831 [3, 2, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1832 InstrItinData<IIC_VTB3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1833 InstrStage<1, [A9_MUX0], 0>,
1834 InstrStage<2, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1835 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1836 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1837 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1838 [4, 2, 2, 3, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1839 InstrItinData<IIC_VTB4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1840 InstrStage<1, [A9_MUX0], 0>,
1841 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1842 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1843 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1844 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1845 [4, 2, 2, 3, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1846 //
1847 // VTBX
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1848 InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1849 InstrStage<1, [A9_MUX0], 0>,
1850 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1851 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1852 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1853 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1854 [3, 1, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1855 InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1856 InstrStage<1, [A9_MUX0], 0>,
1857 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1858 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1859 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1860 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1861 [3, 1, 2, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1862 InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1863 InstrStage<1, [A9_MUX0], 0>,
1864 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1865 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1866 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1867 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1868 [4, 1, 2, 2, 3, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1869 InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1870 InstrStage<1, [A9_MUX0], 0>,
1871 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1872 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1873 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1874 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1875 [4, 1, 2, 2, 3, 3, 1]>
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1876]>;
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]1877
1878// ===---------------------------------------------------------------------===//
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1879// The following definitions describe the simpler per-operand machine model.
1880// This works with MachineScheduler and will eventually replace itineraries.
1881
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]1882
1883// Cortex-A9 machine model for scheduling and other instruction cost heuristics.
1884def CortexA9Model : SchedMachineModel {
1885 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
1886 let MinLatency = 0; // Data dependencies are allowed within dispatch groups.
1887 let LoadLatency = 2; // Optimistic load latency assuming bypass.
1888 // This is overriden by OperandCycles if the
1889 // Itineraries are queried instead.
Andrew Trick9f0b95f2013-01-09 03:36:49 +0000[diff] [blame]1890 let ILPWindow = 10; // Don't reschedule small blocks to hide
1891 // latency. Minimum latency requirements are already
1892 // modeled strictly by reserving resources.
Andrew Trick352abc12012-08-08 02:44:16 +0000[diff] [blame]1893 let MispredictPenalty = 8; // Based on estimate of pipeline depth.
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]1894
1895 let Itineraries = CortexA9Itineraries;
1896}
1897
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1898//===----------------------------------------------------------------------===//
1899// Define each kind of processor resource and number available.
Andrew Trick87255e32012-07-07 04:00:00 +0000[diff] [blame]1900
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]1901let SchedModel = CortexA9Model in {
1902
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1903def A9UnitALU : ProcResource<2>;
1904def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
1905def A9UnitAGU : ProcResource<1>;
1906def A9UnitLS : ProcResource<1>;
1907def A9UnitFP : ProcResource<1> { let Buffered = 0; }
1908def A9UnitB : ProcResource<1>;
1909
1910//===----------------------------------------------------------------------===//
1911// Define scheduler read/write types with their resources and latency on A9.
1912
1913// Consume an issue slot, but no processor resources. This is useful when all
1914// other writes associated with the operand have NumMicroOps = 0.
1915def A9WriteIssue : SchedWriteRes<[]> { let Latency = 0; }
1916
1917// Write an integer register.
1918def A9WriteI : SchedWriteRes<[A9UnitALU]>;
1919// Write an integer shifted-by register
1920def A9WriteIsr : SchedWriteRes<[A9UnitALU]> { let Latency = 2; }
1921
1922// Basic ALU.
Arnold Schwaighoferfb6b9f42013-04-05 05:01:06 +0000[diff] [blame]1923def A9WriteALU : SchedWriteRes<[A9UnitALU]>;
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1924// ALU with operand shifted by immediate.
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]1925def : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; }
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1926// ALU with operand shifted by register.
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]1927def A9WriteALUsr : SchedWriteRes<[A9UnitALU]> { let Latency = 3; }
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1928
1929// Multiplication
1930def A9WriteM : SchedWriteRes<[A9UnitMul, A9UnitMul]> { let Latency = 4; }
1931def A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5;
1932 let NumMicroOps = 0; }
1933def A9WriteM16 : SchedWriteRes<[A9UnitMul]> { let Latency = 3; }
1934def A9WriteM16Hi : SchedWriteRes<[A9UnitMul]> { let Latency = 4;
1935 let NumMicroOps = 0; }
1936
1937// Floating-point
1938// Only one FP or AGU instruction may issue per cycle. We model this
1939// by having FP instructions consume the AGU resource.
1940def A9WriteF : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; }
1941def A9WriteFMov : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; }
1942def A9WriteFMulS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; }
1943def A9WriteFMulD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; }
1944def A9WriteFMAS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 8; }
1945def A9WriteFMAD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; }
Andrew Trick99cc7f62012-09-21 05:06:40 +0000[diff] [blame]1946def A9WriteFDivS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 15; }
1947def A9WriteFDivD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 25; }
1948def A9WriteFSqrtS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 17; }
1949def A9WriteFSqrtD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 32; }
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1950
1951// NEON has an odd mix of latencies. Simply name the write types by latency.
Andrew Trick99cc7f62012-09-21 05:06:40 +0000[diff] [blame]1952def A9WriteV1 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; }
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]1953def A9WriteV2 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 2; }
1954def A9WriteV3 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 3; }
1955def A9WriteV4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; }
1956def A9WriteV5 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; }
1957def A9WriteV6 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; }
1958def A9WriteV7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 7; }
1959def A9WriteV9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; }
1960def A9WriteV10 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 10; }
1961
1962// Reserve A9UnitFP for 2 consecutive cycles.
1963def A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
1964 let Latency = 4;
1965 let ResourceCycles = [2];
1966}
1967def A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
1968 let Latency = 7;
1969 let ResourceCycles = [2];
1970}
1971def A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
1972 let Latency = 9;
1973 let ResourceCycles = [2];
1974}
1975
1976// Branches don't have a def operand but still consume resources.
1977def A9WriteB : SchedWriteRes<[A9UnitB]>;
1978
1979// Address generation.
1980def A9WriteAdr : SchedWriteRes<[A9UnitAGU]> { let NumMicroOps = 0; }
1981
1982// Load Integer.
1983def A9WriteL : SchedWriteRes<[A9UnitLS]> { let Latency = 3; }
1984// Load the upper 32-bits using the same micro-op.
1985def A9WriteLHi : SchedWriteRes<[]> { let Latency = 3;
1986 let NumMicroOps = 0; }
1987// Offset shifted by register.
1988def A9WriteLsi : SchedWriteRes<[A9UnitLS]> { let Latency = 4; }
1989// Load (and zero extend) a byte.
1990def A9WriteLb : SchedWriteRes<[A9UnitLS]> { let Latency = 4; }
1991def A9WriteLbsi : SchedWriteRes<[A9UnitLS]> { let Latency = 5; }
1992
1993// Load or Store Float, aligned.
1994def A9WriteLSfp : SchedWriteRes<[A9UnitLS, A9UnitFP]> { let Latency = 1; }
1995
1996// Store Integer.
1997def A9WriteS : SchedWriteRes<[A9UnitLS]>;
1998
1999//===----------------------------------------------------------------------===//
2000// Define resources dynamically for load multiple variants.
2001
2002// Define helpers for extra latency without consuming resources.
2003def A9WriteCycle1 : SchedWriteRes<[]> { let Latency = 1; let NumMicroOps = 0; }
2004foreach NumCycles = 2-8 in {
2005def A9WriteCycle#NumCycles : WriteSequence<[A9WriteCycle1], NumCycles>;
2006} // foreach NumCycles
2007
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2008// Define address generation sequences and predicates for 8 flavors of LDMs.
2009foreach NumAddr = 1-8 in {
2010
2011// Define A9WriteAdr1-8 as a sequence of A9WriteAdr with additive
2012// latency for instructions that generate multiple loads or stores.
2013def A9WriteAdr#NumAddr : WriteSequence<[A9WriteAdr], NumAddr>;
2014
2015// Define a predicate to select the LDM based on number of memory addresses.
2016def A9LMAdr#NumAddr#Pred :
2017 SchedPredicate<"TII->getNumLDMAddresses(MI) == "#NumAddr>;
2018
2019} // foreach NumAddr
2020
2021// Fall-back for unknown LDMs.
2022def A9LMUnknownPred : SchedPredicate<"TII->getNumLDMAddresses(MI) == 0">;
2023
2024// LDM/VLDM/VLDn address generation latency & resources.
2025// Dynamically select the A9WriteAdrN sequence using a predicate.
2026def A9WriteLMAdr : SchedWriteVariant<[
2027 SchedVar<A9LMAdr1Pred, [A9WriteAdr1]>,
2028 SchedVar<A9LMAdr2Pred, [A9WriteAdr2]>,
2029 SchedVar<A9LMAdr3Pred, [A9WriteAdr3]>,
2030 SchedVar<A9LMAdr4Pred, [A9WriteAdr4]>,
2031 SchedVar<A9LMAdr5Pred, [A9WriteAdr5]>,
2032 SchedVar<A9LMAdr6Pred, [A9WriteAdr6]>,
2033 SchedVar<A9LMAdr7Pred, [A9WriteAdr7]>,
2034 SchedVar<A9LMAdr8Pred, [A9WriteAdr8]>,
2035 // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
2036 SchedVar<A9LMUnknownPred, [A9WriteAdr2]>]>;
2037
2038// Define LDM Resources.
2039// These take no issue resource, so they can be combined with other
2040// writes like WriteB.
2041// A9WriteLMLo takes a single LS resource and 2 cycles.
2042def A9WriteLMLo : SchedWriteRes<[A9UnitLS]> { let Latency = 2;
2043 let NumMicroOps = 0; }
2044// Assuming aligned access, the upper half of each pair is free with
2045// the same latency.
2046def A9WriteLMHi : SchedWriteRes<[]> { let Latency = 2;
2047 let NumMicroOps = 0; }
2048// Each A9WriteL#N variant adds N cycles of latency without consuming
2049// additional resources.
2050foreach NumAddr = 1-8 in {
2051def A9WriteL#NumAddr : WriteSequence<
2052 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2053def A9WriteL#NumAddr#Hi : WriteSequence<
2054 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2055}
2056
2057//===----------------------------------------------------------------------===//
2058// LDM: Load multiple into 32-bit integer registers.
2059
2060// A9WriteLM variants expand into a pair of writes for each 64-bit
2061// value loaded. When the number of registers is odd, the last
2062// A9WriteLnHi is naturally ignored because the instruction has no
2063// following def operands. These variants take no issue resource, so
2064// they may need to be part of a WriteSequence that includes A9WriteIssue.
2065def A9WriteLM : SchedWriteVariant<[
2066 SchedVar<A9LMAdr1Pred, [A9WriteL1, A9WriteL1Hi]>,
2067 SchedVar<A9LMAdr2Pred, [A9WriteL1, A9WriteL1Hi,
2068 A9WriteL2, A9WriteL2Hi]>,
2069 SchedVar<A9LMAdr3Pred, [A9WriteL1, A9WriteL1Hi,
2070 A9WriteL2, A9WriteL2Hi,
2071 A9WriteL3, A9WriteL3Hi]>,
2072 SchedVar<A9LMAdr4Pred, [A9WriteL1, A9WriteL1Hi,
2073 A9WriteL2, A9WriteL2Hi,
2074 A9WriteL3, A9WriteL3Hi,
2075 A9WriteL4, A9WriteL4Hi]>,
2076 SchedVar<A9LMAdr5Pred, [A9WriteL1, A9WriteL1Hi,
2077 A9WriteL2, A9WriteL2Hi,
2078 A9WriteL3, A9WriteL3Hi,
2079 A9WriteL4, A9WriteL4Hi,
2080 A9WriteL5, A9WriteL5Hi]>,
2081 SchedVar<A9LMAdr6Pred, [A9WriteL1, A9WriteL1Hi,
2082 A9WriteL2, A9WriteL2Hi,
2083 A9WriteL3, A9WriteL3Hi,
2084 A9WriteL4, A9WriteL4Hi,
2085 A9WriteL5, A9WriteL5Hi,
2086 A9WriteL6, A9WriteL6Hi]>,
2087 SchedVar<A9LMAdr7Pred, [A9WriteL1, A9WriteL1Hi,
2088 A9WriteL2, A9WriteL2Hi,
2089 A9WriteL3, A9WriteL3Hi,
2090 A9WriteL4, A9WriteL4Hi,
2091 A9WriteL5, A9WriteL5Hi,
2092 A9WriteL6, A9WriteL6Hi,
2093 A9WriteL7, A9WriteL7Hi]>,
2094 SchedVar<A9LMAdr8Pred, [A9WriteL1, A9WriteL1Hi,
2095 A9WriteL2, A9WriteL2Hi,
2096 A9WriteL3, A9WriteL3Hi,
2097 A9WriteL4, A9WriteL4Hi,
2098 A9WriteL5, A9WriteL5Hi,
2099 A9WriteL6, A9WriteL6Hi,
2100 A9WriteL7, A9WriteL7Hi,
2101 A9WriteL8, A9WriteL8Hi]>,
2102 // For unknown LDMs, define the maximum number of writes, but only
2103 // make the first two consume resources.
2104 SchedVar<A9LMUnknownPred, [A9WriteL1, A9WriteL1Hi,
2105 A9WriteL2, A9WriteL2Hi,
2106 A9WriteL3Hi, A9WriteL3Hi,
2107 A9WriteL4Hi, A9WriteL4Hi,
2108 A9WriteL5Hi, A9WriteL5Hi,
2109 A9WriteL6Hi, A9WriteL6Hi,
2110 A9WriteL7Hi, A9WriteL7Hi,
2111 A9WriteL8Hi, A9WriteL8Hi]>]> {
2112 let Variadic = 1;
2113}
2114
2115//===----------------------------------------------------------------------===//
2116// VFP Load/Store Multiple Variants, and NEON VLDn/VSTn support.
2117
2118// A9WriteLfpOp is the same as A9WriteLSfp but takes no issue resources
2119// so can be used in WriteSequences for in single-issue instructions that
2120// encapsulate multiple loads.
2121def A9WriteLfpOp : SchedWriteRes<[A9UnitLS, A9UnitFP]> {
2122 let Latency = 1;
2123 let NumMicroOps = 0;
2124}
2125
2126foreach NumAddr = 1-8 in {
2127
2128// Helper for A9WriteLfp1-8: A sequence of fp loads with no micro-ops.
2129def A9WriteLfp#NumAddr#Seq : WriteSequence<[A9WriteLfpOp], NumAddr>;
2130
2131// A9WriteLfp1-8 definitions are statically expanded into a sequence of
2132// A9WriteLfpOps with additive latency that takes a single issue slot.
2133// Used directly to describe NEON VLDn.
2134def A9WriteLfp#NumAddr : WriteSequence<
2135 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2136
2137// A9WriteLfp1-8Mov adds a cycle of latency and FP resource for
2138// permuting loaded values.
2139def A9WriteLfp#NumAddr#Mov : WriteSequence<
2140 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2141
2142} // foreach NumAddr
2143
2144// Define VLDM/VSTM PreRA resources.
2145// A9WriteLMfpPreRA are dynamically expanded into the correct
2146// A9WriteLfp1-8 sequence based on a predicate. This supports the
2147// preRA VLDM variants in which all 64-bit loads are written to the
2148// same tuple of either single or double precision registers.
2149def A9WriteLMfpPreRA : SchedWriteVariant<[
2150 SchedVar<A9LMAdr1Pred, [A9WriteLfp1]>,
2151 SchedVar<A9LMAdr2Pred, [A9WriteLfp2]>,
2152 SchedVar<A9LMAdr3Pred, [A9WriteLfp3]>,
2153 SchedVar<A9LMAdr4Pred, [A9WriteLfp4]>,
2154 SchedVar<A9LMAdr5Pred, [A9WriteLfp5]>,
2155 SchedVar<A9LMAdr6Pred, [A9WriteLfp6]>,
2156 SchedVar<A9LMAdr7Pred, [A9WriteLfp7]>,
2157 SchedVar<A9LMAdr8Pred, [A9WriteLfp8]>,
2158 // For unknown VLDM/VSTM PreRA, assume 2xS registers.
2159 SchedVar<A9LMUnknownPred, [A9WriteLfp2]>]>;
2160
2161// Define VLDM/VSTM PostRA Resources.
2162// A9WriteLMfpLo takes a LS and FP resource and one issue slot but no latency.
2163def A9WriteLMfpLo : SchedWriteRes<[A9UnitLS, A9UnitFP]> { let Latency = 0; }
2164
2165foreach NumAddr = 1-8 in {
2166
2167// Each A9WriteL#N variant adds N cycles of latency without consuming
2168// additional resources.
2169def A9WriteLMfp#NumAddr : WriteSequence<
2170 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2171
2172// Assuming aligned access, the upper half of each pair is free with
2173// the same latency.
2174def A9WriteLMfp#NumAddr#Hi : WriteSequence<
2175 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2176
2177} // foreach NumAddr
2178
2179// VLDM PostRA Variants. These variants expand A9WriteLMfpPostRA into a
2180// pair of writes for each 64-bit data loaded. When the number of
2181// registers is odd, the last WriteLMfpnHi is naturally ignored because
2182// the instruction has no following def operands.
2183def A9WriteLMfpPostRA : SchedWriteVariant<[
2184 SchedVar<A9LMAdr1Pred, [A9WriteLMfp1, A9WriteLMfp1Hi]>,
2185 SchedVar<A9LMAdr2Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2186 A9WriteLMfp2, A9WriteLMfp2Hi]>,
2187 SchedVar<A9LMAdr3Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2188 A9WriteLMfp2, A9WriteLMfp2Hi,
2189 A9WriteLMfp3, A9WriteLMfp3Hi]>,
2190 SchedVar<A9LMAdr4Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2191 A9WriteLMfp2, A9WriteLMfp2Hi,
2192 A9WriteLMfp3, A9WriteLMfp3Hi,
2193 A9WriteLMfp4, A9WriteLMfp4Hi]>,
2194 SchedVar<A9LMAdr5Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2195 A9WriteLMfp2, A9WriteLMfp2Hi,
2196 A9WriteLMfp3, A9WriteLMfp3Hi,
2197 A9WriteLMfp4, A9WriteLMfp4Hi,
2198 A9WriteLMfp5, A9WriteLMfp5Hi]>,
2199 SchedVar<A9LMAdr6Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2200 A9WriteLMfp2, A9WriteLMfp2Hi,
2201 A9WriteLMfp3, A9WriteLMfp3Hi,
2202 A9WriteLMfp4, A9WriteLMfp4Hi,
2203 A9WriteLMfp5, A9WriteLMfp5Hi,
2204 A9WriteLMfp6, A9WriteLMfp6Hi]>,
2205 SchedVar<A9LMAdr7Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2206 A9WriteLMfp2, A9WriteLMfp2Hi,
2207 A9WriteLMfp3, A9WriteLMfp3Hi,
2208 A9WriteLMfp4, A9WriteLMfp4Hi,
2209 A9WriteLMfp5, A9WriteLMfp5Hi,
2210 A9WriteLMfp6, A9WriteLMfp6Hi,
2211 A9WriteLMfp7, A9WriteLMfp7Hi]>,
2212 SchedVar<A9LMAdr8Pred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2213 A9WriteLMfp2, A9WriteLMfp2Hi,
2214 A9WriteLMfp3, A9WriteLMfp3Hi,
2215 A9WriteLMfp4, A9WriteLMfp4Hi,
2216 A9WriteLMfp5, A9WriteLMfp5Hi,
2217 A9WriteLMfp6, A9WriteLMfp6Hi,
2218 A9WriteLMfp7, A9WriteLMfp7Hi,
2219 A9WriteLMfp8, A9WriteLMfp8Hi]>,
2220 // For unknown LDMs, define the maximum number of writes, but only
2221 // make the first two consume resources.
2222 SchedVar<A9LMUnknownPred, [A9WriteLMfp1, A9WriteLMfp1Hi,
2223 A9WriteLMfp2, A9WriteLMfp2Hi,
2224 A9WriteLMfp3Hi, A9WriteLMfp3Hi,
2225 A9WriteLMfp4Hi, A9WriteLMfp4Hi,
2226 A9WriteLMfp5Hi, A9WriteLMfp5Hi,
2227 A9WriteLMfp6Hi, A9WriteLMfp6Hi,
2228 A9WriteLMfp7Hi, A9WriteLMfp7Hi,
2229 A9WriteLMfp8Hi, A9WriteLMfp8Hi]>]> {
2230 let Variadic = 1;
2231}
2232
2233// Distinguish between our multiple MI-level forms of the same
2234// VLDM/VSTM instructions.
2235def A9PreRA : SchedPredicate<
2236 "TargetRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg())">;
2237def A9PostRA : SchedPredicate<
2238 "TargetRegisterInfo::isPhysicalRegister(MI->getOperand(0).getReg())">;
2239
2240// VLDM represents all destination registers as a single register
2241// tuple, unlike LDM. So the number of write operands is not variadic.
2242def A9WriteLMfp : SchedWriteVariant<[
2243 SchedVar<A9PreRA, [A9WriteLMfpPreRA]>,
2244 SchedVar<A9PostRA, [A9WriteLMfpPostRA]>]>;
2245
2246//===----------------------------------------------------------------------===//
2247// Resources for other (non LDM/VLDM) Variants.
2248
2249// These mov immediate writers are unconditionally expanded with
2250// additive latency.
2251def A9WriteI2 : WriteSequence<[A9WriteI, A9WriteI]>;
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2252def A9WriteI2pc : WriteSequence<[A9WriteI, A9WriteI, WriteALU]>;
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2253def A9WriteI2ld : WriteSequence<[A9WriteI, A9WriteI, A9WriteL]>;
2254
2255// Some ALU operations can read loaded integer values one cycle early.
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2256def A9ReadALU : SchedReadAdvance<1,
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2257 [A9WriteL, A9WriteLHi, A9WriteLsi, A9WriteLb, A9WriteLbsi,
2258 A9WriteL1, A9WriteL2, A9WriteL3, A9WriteL4,
2259 A9WriteL5, A9WriteL6, A9WriteL7, A9WriteL8,
2260 A9WriteL1Hi, A9WriteL2Hi, A9WriteL3Hi, A9WriteL4Hi,
2261 A9WriteL5Hi, A9WriteL6Hi, A9WriteL7Hi, A9WriteL8Hi]>;
2262
2263// Read types for operands that are unconditionally read in cycle N
2264// after the instruction issues, decreases producer latency by N-1.
2265def A9Read2 : SchedReadAdvance<1>;
2266def A9Read3 : SchedReadAdvance<2>;
2267def A9Read4 : SchedReadAdvance<3>;
2268
2269//===----------------------------------------------------------------------===//
2270// Map itinerary classes to scheduler read/write resources per operand.
2271//
2272// For ARM, we piggyback scheduler resources on the Itinerary classes
2273// to avoid perturbing the existing instruction definitions.
2274
2275// This table follows the ARM Cortex-A9 Technical Reference Manuals,
2276// mostly in order.
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2277
Arnold Schwaighofer57142852013-06-06 19:30:21 +0000[diff] [blame]2278def :ItinRW<[WriteALU], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2279 IIC_iMVNi,IIC_iMVNsi,
2280 IIC_iCMOVi,IIC_iCMOVr,IIC_iCMOVsi]>;
Arnold Schwaighofer57142852013-06-06 19:30:21 +0000[diff] [blame]2281def :ItinRW<[WriteALU, A9ReadALU],[IIC_iMVNr]>;
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2282def :ItinRW<[A9WriteIsr], [IIC_iMOVsr,IIC_iMVNsr,IIC_iCMOVsr]>;
2283
2284def :ItinRW<[A9WriteI2], [IIC_iMOVix2,IIC_iCMOVix2]>;
2285def :ItinRW<[A9WriteI2pc], [IIC_iMOVix2addpc]>;
2286def :ItinRW<[A9WriteI2ld], [IIC_iMOVix2ld]>;
2287
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2288def :ItinRW<[WriteALU], [IIC_iBITi,IIC_iBITr,IIC_iUNAr,IIC_iTSTi,IIC_iTSTr]>;
Arnold Schwaighoferfb6b9f42013-04-05 05:01:06 +0000[diff] [blame]2289def :ItinRW<[WriteALU, A9ReadALU], [IIC_iALUi, IIC_iCMPi, IIC_iCMPsi]>;
2290def :ItinRW<[WriteALU, A9ReadALU, A9ReadALU],[IIC_iALUr,IIC_iCMPr]>;
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2291def :ItinRW<[WriteALUsi], [IIC_iBITsi,IIC_iUNAsi,IIC_iEXTr,IIC_iTSTsi]>;
Arnold Schwaighoferfb6b9f42013-04-05 05:01:06 +0000[diff] [blame]2292def :ItinRW<[WriteALUsi, A9ReadALU], [IIC_iALUsi]>;
2293def :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2294def :ItinRW<[A9WriteALUsr], [IIC_iBITsr,IIC_iTSTsr,IIC_iEXTAr,IIC_iEXTAsr]>;
Arnold Schwaighoferfb6b9f42013-04-05 05:01:06 +0000[diff] [blame]2295def :ItinRW<[A9WriteALUsr, A9ReadALU], [IIC_iALUsr,IIC_iCMPsr]>;
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2296
2297// A9WriteHi ignored for MUL32.
2298def :ItinRW<[A9WriteM, A9WriteMHi], [IIC_iMUL32,IIC_iMAC32,
2299 IIC_iMUL64,IIC_iMAC64]>;
2300// FIXME: SMLALxx needs itin classes
2301def :ItinRW<[A9WriteM16, A9WriteM16Hi], [IIC_iMUL16,IIC_iMAC16]>;
2302
2303// TODO: For floating-point ops, we model the pipeline forwarding
2304// latencies here. WAW latencies are sometimes longer.
2305
2306def :ItinRW<[A9WriteFMov], [IIC_fpSTAT, IIC_fpMOVIS, IIC_fpMOVID, IIC_fpMOVSI,
2307 IIC_fpUNA32, IIC_fpUNA64,
2308 IIC_fpCMP32, IIC_fpCMP64]>;
2309def :ItinRW<[A9WriteFMov, A9WriteFMov], [IIC_fpMOVDI]>;
2310def :ItinRW<[A9WriteF], [IIC_fpCVTSD, IIC_fpCVTDS, IIC_fpCVTSH, IIC_fpCVTHS,
2311 IIC_fpCVTIS, IIC_fpCVTID, IIC_fpCVTSI, IIC_fpCVTDI,
2312 IIC_fpALU32, IIC_fpALU64]>;
2313def :ItinRW<[A9WriteFMulS], [IIC_fpMUL32]>;
2314def :ItinRW<[A9WriteFMulD], [IIC_fpMUL64]>;
2315def :ItinRW<[A9WriteFMAS], [IIC_fpMAC32]>;
2316def :ItinRW<[A9WriteFMAD], [IIC_fpMAC64]>;
2317def :ItinRW<[A9WriteFDivS], [IIC_fpDIV32]>;
2318def :ItinRW<[A9WriteFDivD], [IIC_fpDIV64]>;
2319def :ItinRW<[A9WriteFSqrtS], [IIC_fpSQRT32]>;
2320def :ItinRW<[A9WriteFSqrtD], [IIC_fpSQRT64]>;
2321
2322def :ItinRW<[A9WriteB], [IIC_Br]>;
2323
2324// A9 PLD is processed in a dedicated unit.
2325def :ItinRW<[], [IIC_Preload]>;
2326
2327// Note: We must assume that loads are aligned, since the machine
2328// model cannot know this statically and A9 ignores alignment hints.
2329
2330// A9WriteAdr consumes AGU regardless address writeback. But it's
2331// latency is only relevant for users of an updated address.
2332def :ItinRW<[A9WriteL, A9WriteAdr], [IIC_iLoad_i,IIC_iLoad_r,
2333 IIC_iLoad_iu,IIC_iLoad_ru]>;
2334def :ItinRW<[A9WriteLsi, A9WriteAdr], [IIC_iLoad_si,IIC_iLoad_siu]>;
2335def :ItinRW<[A9WriteLb, A9WriteAdr2], [IIC_iLoad_bh_i,IIC_iLoad_bh_r,
2336 IIC_iLoad_bh_iu,IIC_iLoad_bh_ru]>;
2337def :ItinRW<[A9WriteLbsi, A9WriteAdr2], [IIC_iLoad_bh_si,IIC_iLoad_bh_siu]>;
2338def :ItinRW<[A9WriteL, A9WriteLHi, A9WriteAdr], [IIC_iLoad_d_i,IIC_iLoad_d_r,
2339 IIC_iLoad_d_ru]>;
2340// Store either has no def operands, or the one def for address writeback.
2341def :ItinRW<[A9WriteAdr, A9WriteS], [IIC_iStore_i, IIC_iStore_r,
2342 IIC_iStore_iu, IIC_iStore_ru,
2343 IIC_iStore_d_i, IIC_iStore_d_r,
2344 IIC_iStore_d_ru]>;
2345def :ItinRW<[A9WriteAdr2, A9WriteS], [IIC_iStore_si, IIC_iStore_siu,
2346 IIC_iStore_bh_i, IIC_iStore_bh_r,
2347 IIC_iStore_bh_iu, IIC_iStore_bh_ru]>;
2348def :ItinRW<[A9WriteAdr3, A9WriteS], [IIC_iStore_bh_si, IIC_iStore_bh_siu]>;
2349
2350// A9WriteML will be expanded into a separate write for each def
2351// operand. Address generation consumes resources, but A9WriteLMAdr
2352// is listed after all def operands, so has no effective latency.
2353//
2354// Note: A9WriteLM expands into an even number of def operands. The
2355// actual number of def operands may be less by one.
2356def :ItinRW<[A9WriteLM, A9WriteLMAdr, A9WriteIssue], [IIC_iLoad_m, IIC_iPop]>;
2357
2358// Load multiple with address writeback has an extra def operand in
2359// front of the loaded registers.
2360//
2361// Reuse the load-multiple variants for store-multiple because the
2362// resources are identical, For stores only the address writeback
2363// has a def operand so the WriteL latencies are unused.
2364def :ItinRW<[A9WriteLMAdr, A9WriteLM, A9WriteIssue], [IIC_iLoad_mu,
2365 IIC_iStore_m,
2366 IIC_iStore_mu]>;
2367def :ItinRW<[A9WriteLM, A9WriteLMAdr, A9WriteB], [IIC_iLoad_mBr, IIC_iPop_Br]>;
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2368def :ItinRW<[A9WriteL, A9WriteAdr, WriteALU], [IIC_iLoadiALU]>;
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2369
2370def :ItinRW<[A9WriteLSfp, A9WriteAdr], [IIC_fpLoad32, IIC_fpLoad64]>;
2371
2372def :ItinRW<[A9WriteLMfp, A9WriteLMAdr], [IIC_fpLoad_m]>;
2373def :ItinRW<[A9WriteLMAdr, A9WriteLMfp], [IIC_fpLoad_mu]>;
2374def :ItinRW<[A9WriteAdr, A9WriteLSfp], [IIC_fpStore32, IIC_fpStore64,
2375 IIC_fpStore_m, IIC_fpStore_mu]>;
2376
2377// Note: Unlike VLDM, VLD1 expects the writeback operand after the
2378// normal writes.
2379def :ItinRW<[A9WriteLfp1, A9WriteAdr1], [IIC_VLD1, IIC_VLD1u,
2380 IIC_VLD1x2, IIC_VLD1x2u]>;
2381def :ItinRW<[A9WriteLfp2, A9WriteAdr2], [IIC_VLD1x3, IIC_VLD1x3u,
2382 IIC_VLD1x4, IIC_VLD1x4u,
2383 IIC_VLD4dup, IIC_VLD4dupu]>;
2384def :ItinRW<[A9WriteLfp1Mov, A9WriteAdr1], [IIC_VLD1dup, IIC_VLD1dupu,
2385 IIC_VLD2, IIC_VLD2u,
2386 IIC_VLD2dup, IIC_VLD2dupu]>;
2387def :ItinRW<[A9WriteLfp2Mov, A9WriteAdr1], [IIC_VLD1ln, IIC_VLD1lnu,
2388 IIC_VLD2x2, IIC_VLD2x2u,
2389 IIC_VLD2ln, IIC_VLD2lnu]>;
2390def :ItinRW<[A9WriteLfp3Mov, A9WriteAdr3], [IIC_VLD3, IIC_VLD3u,
2391 IIC_VLD3dup, IIC_VLD3dupu]>;
2392def :ItinRW<[A9WriteLfp4Mov, A9WriteAdr4], [IIC_VLD4, IIC_VLD4u,
2393 IIC_VLD4ln, IIC_VLD4lnu]>;
2394def :ItinRW<[A9WriteLfp5Mov, A9WriteAdr5], [IIC_VLD3ln, IIC_VLD3lnu]>;
2395
2396// Vector stores use similar resources to vector loads, so use the
2397// same write types. The address write must be first for stores with
2398// address writeback.
2399def :ItinRW<[A9WriteAdr1, A9WriteLfp1], [IIC_VST1, IIC_VST1u,
2400 IIC_VST1x2, IIC_VST1x2u,
2401 IIC_VST1ln, IIC_VST1lnu,
2402 IIC_VST2, IIC_VST2u,
2403 IIC_VST2x2, IIC_VST2x2u,
2404 IIC_VST2ln, IIC_VST2lnu]>;
2405def :ItinRW<[A9WriteAdr2, A9WriteLfp2], [IIC_VST1x3, IIC_VST1x3u,
2406 IIC_VST1x4, IIC_VST1x4u,
2407 IIC_VST3, IIC_VST3u,
2408 IIC_VST3ln, IIC_VST3lnu,
2409 IIC_VST4, IIC_VST4u,
2410 IIC_VST4ln, IIC_VST4lnu]>;
2411
2412// NEON moves.
2413def :ItinRW<[A9WriteV2], [IIC_VMOVSI, IIC_VMOVDI, IIC_VMOVD, IIC_VMOVQ]>;
2414def :ItinRW<[A9WriteV1], [IIC_VMOV, IIC_VMOVIS, IIC_VMOVID]>;
2415def :ItinRW<[A9WriteV3], [IIC_VMOVISL, IIC_VMOVN]>;
2416
2417// NEON integer arithmetic
2418//
2419// VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
2420def :ItinRW<[A9WriteV3, A9Read2, A9Read2], [IIC_VBINiD, IIC_VBINiQ]>;
2421// VSUB/VMVN/VCLSD/VCLZD/VCNTD
2422def :ItinRW<[A9WriteV3, A9Read2], [IIC_VSUBiD, IIC_VSUBiQ, IIC_VCNTiD]>;
2423// VADDL/VSUBL/VNEG are mapped later under IIC_SHLi.
2424// ...
2425// VHADD/VRHADD/VQADD/VTST/VADH/VRADH
2426def :ItinRW<[A9WriteV4, A9Read2, A9Read2], [IIC_VBINi4D, IIC_VBINi4Q]>;
2427// VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
2428def :ItinRW<[A9WriteV4, A9Read2], [IIC_VSUBi4D, IIC_VSUBi4Q]>;
2429// VQNEG/VQABS
2430def :ItinRW<[A9WriteV4], [IIC_VQUNAiD, IIC_VQUNAiQ]>;
2431// VABS
2432def :ItinRW<[A9WriteV4, A9Read2], [IIC_VUNAiD, IIC_VUNAiQ]>;
2433// VPADD/VPADDL are mapped later under IIC_SHLi.
2434// ...
2435// VCLSQ/VCLZQ/VCNTQ, takes two cycles.
2436def :ItinRW<[A9Write2V4, A9Read3], [IIC_VCNTiQ]>;
2437// VMOVimm/VMVNimm/VORRimm/VBICimm
2438def :ItinRW<[A9WriteV3], [IIC_VMOVImm]>;
2439def :ItinRW<[A9WriteV6, A9Read3, A9Read2], [IIC_VABAD, IIC_VABAQ]>;
2440def :ItinRW<[A9WriteV6, A9Read3], [IIC_VPALiD, IIC_VPALiQ]>;
2441
2442// NEON integer multiply
2443//
2444// Note: these don't quite match the timing docs, but they do match
2445// the original A9 itinerary.
2446def :ItinRW<[A9WriteV6, A9Read2, A9Read2], [IIC_VMULi16D]>;
2447def :ItinRW<[A9WriteV7, A9Read2, A9Read2], [IIC_VMULi16Q]>;
2448def :ItinRW<[A9Write2V7, A9Read2], [IIC_VMULi32D]>;
2449def :ItinRW<[A9Write2V9, A9Read2], [IIC_VMULi32Q]>;
2450def :ItinRW<[A9WriteV6, A9Read3, A9Read2, A9Read2], [IIC_VMACi16D]>;
2451def :ItinRW<[A9WriteV7, A9Read3, A9Read2, A9Read2], [IIC_VMACi16Q]>;
2452def :ItinRW<[A9Write2V7, A9Read3, A9Read2], [IIC_VMACi32D]>;
2453def :ItinRW<[A9Write2V9, A9Read3, A9Read2], [IIC_VMACi32Q]>;
2454
2455// NEON integer shift
2456// TODO: Q,Q,Q shifts should actually reserve FP for 2 cycles.
2457def :ItinRW<[A9WriteV3], [IIC_VSHLiD, IIC_VSHLiQ]>;
2458def :ItinRW<[A9WriteV4], [IIC_VSHLi4D, IIC_VSHLi4Q]>;
2459
2460// NEON permute
2461def :ItinRW<[A9WriteV2], [IIC_VPERMD, IIC_VPERMQ, IIC_VEXTD]>;
2462def :ItinRW<[A9WriteV3, A9WriteV4, ReadDefault, A9Read2],
2463 [IIC_VPERMQ3, IIC_VEXTQ]>;
2464def :ItinRW<[A9WriteV3, A9Read2], [IIC_VTB1]>;
2465def :ItinRW<[A9WriteV3, A9Read2, A9Read2], [IIC_VTB2]>;
2466def :ItinRW<[A9WriteV4, A9Read2, A9Read2, A9Read3], [IIC_VTB3]>;
2467def :ItinRW<[A9WriteV4, A9Read2, A9Read2, A9Read3, A9Read3], [IIC_VTB4]>;
2468def :ItinRW<[A9WriteV3, ReadDefault, A9Read2], [IIC_VTBX1]>;
2469def :ItinRW<[A9WriteV3, ReadDefault, A9Read2, A9Read2], [IIC_VTBX2]>;
2470def :ItinRW<[A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3], [IIC_VTBX3]>;
2471def :ItinRW<[A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3, A9Read3],
2472 [IIC_VTBX4]>;
2473
2474// NEON floating-point
2475def :ItinRW<[A9WriteV5, A9Read2, A9Read2], [IIC_VBIND]>;
2476def :ItinRW<[A9WriteV6, A9Read2, A9Read2], [IIC_VBINQ]>;
2477def :ItinRW<[A9WriteV5, A9Read2], [IIC_VUNAD, IIC_VFMULD]>;
2478def :ItinRW<[A9WriteV6, A9Read2], [IIC_VUNAQ, IIC_VFMULQ]>;
2479def :ItinRW<[A9WriteV9, A9Read3, A9Read2], [IIC_VMACD, IIC_VFMACD]>;
2480def :ItinRW<[A9WriteV10, A9Read3, A9Read2], [IIC_VMACQ, IIC_VFMACQ]>;
2481def :ItinRW<[A9WriteV9, A9Read2, A9Read2], [IIC_VRECSD]>;
2482def :ItinRW<[A9WriteV10, A9Read2, A9Read2], [IIC_VRECSQ]>;
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2483
2484// Map SchedRWs that are identical for cortexa9 to existing resources.
Arnold Schwaighoferfb6b9f42013-04-05 05:01:06 +0000[diff] [blame]2485def : SchedAlias<WriteALU, A9WriteALU>;
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2486def : SchedAlias<WriteALUsr, A9WriteALUsr>;
2487def : SchedAlias<WriteALUSsr, A9WriteALUsr>;
2488def : SchedAlias<ReadALU, A9ReadALU>;
2489def : SchedAlias<ReadALUsr, A9ReadALU>;
Arnold Schwaighofer57142852013-06-06 19:30:21 +0000[diff] [blame]2490def : InstRW< [WriteALU],
2491 (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr",
2492 "BICrr")>;
2493def : InstRW< [WriteALUsi], (instregex "ANDrsi", "ORRrsi", "EORrsi", "BICrsi")>;
2494def : InstRW< [WriteALUsr], (instregex "ANDrsr", "ORRrsr", "EORrsr", "BICrsr")>;
2495
Arnold Schwaighofer6793aeb2013-04-01 13:07:05 +0000[diff] [blame]2496
Arnold Schwaighoferfb6b9f42013-04-05 05:01:06 +0000[diff] [blame]2497def : SchedAlias<WriteCMP, A9WriteALU>;
2498def : SchedAlias<WriteCMPsi, A9WriteALU>;
2499def : SchedAlias<WriteCMPsr, A9WriteALU>;
Arnold Schwaighofer57142852013-06-06 19:30:21 +0000[diff] [blame]2500
2501def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi",
2502 "MOVCCsr")>;
2503def : InstRW< [WriteALU, A9ReadALU], (instregex "MVNr")>;
2504def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm",
2505 "MOV_ga_dyn")>;
2506def : InstRW< [A9WriteI2pc], (instregex "MOV_ga_pcrel")>;
2507def : InstRW< [A9WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>;
2508
2509def : InstRW< [WriteALU], (instregex "SEL")>;
2510
2511def : InstRW< [WriteALUsi], (instregex "BFC", "BFI", "UBFX", "SBFX")>;
2512
2513def : InstRW< [A9WriteM],
2514 (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS",
2515 "SMMLA", "SMMLAR", "SMMLS", "SMMLSR")>;
2516def : InstRW< [A9WriteM, A9WriteMHi],
2517 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
2518 "UMAAL", "SMLALv5", "UMLALv5", "UMAALv5", "SMLALBB", "SMLALBT", "SMLALTB",
2519 "SMLALTT")>;
2520// FIXME: These instructions used to have NoItinerary. Just copied the one from above.
2521def : InstRW< [A9WriteM, A9WriteMHi],
2522 (instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX",
2523 "SMLSLD", "SMLLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
2524
2525def : InstRW<[A9WriteM16, A9WriteM16Hi],
2526 (instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT")>;
2527def : InstRW<[A9WriteM16, A9WriteM16Hi],
2528 (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLAWB", "SMLAWT")>;
2529
2530def : InstRW<[A9WriteL], (instregex "LDRi12", "PICLDR$")>;
2531def : InstRW<[A9WriteLsi], (instregex "LDRrs")>;
2532def : InstRW<[A9WriteLb],
2533 (instregex "LDRBi12", "PICLDRH", "PICLDRB", "PICLDRSH", "PICLDRSB",
2534 "LDRH", "LDRSH", "LDRSB")>;
2535def : InstRW<[A9WriteLbsi], (instregex "LDRrs")>;
2536
Arnold Schwaighofer2773f1d2013-06-05 16:06:11 +0000[diff] [blame]2537def : WriteRes<WriteDiv, []> { let Latency = 0; }
2538
2539def : WriteRes<WriteBr, [A9UnitB]>;
2540def : WriteRes<WriteBrL, [A9UnitB]>;
2541def : WriteRes<WriteBrTbl, [A9UnitB]>;
2542def : WriteRes<WritePreLd, []>;
2543def : SchedAlias<WriteCvtFP, A9WriteF>;
Arnold Schwaighofereac54472013-06-06 20:26:18 +0000[diff] [blame^]2544def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
Andrew Trick985dc0d2012-09-14 18:31:58 +0000[diff] [blame]2545} // SchedModel = CortexA9Model