blob: 4e978e4044a3b81e6ae0f35af8fc171bc2684c41 [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010032#include "i915_trace.h"
Jesse Barnes652c3932009-08-17 13:31:43 -070033#include "intel_drv.h"
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Eric Anholt673a3942008-07-30 12:06:12 -070035#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include <linux/pci.h>
Zhenyu Wangf8f235e2010-08-27 11:08:57 +080037#include <linux/intel-gtt.h>
Eric Anholt673a3942008-07-30 12:06:12 -070038
Daniel Vetter0108a3e2010-08-07 11:01:21 +010039static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
Daniel Vetterba3d8d72010-02-11 22:37:04 +010040
41static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
42 bool pipelined);
Eric Anholte47c68e2008-11-14 13:35:19 -080043static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
44static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080045static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
46 int write);
47static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 uint64_t offset,
49 uint64_t size);
50static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Chris Wilson2cf34d72010-09-14 13:03:28 +010051static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
52 bool interruptible);
Jesse Barnesde151cf2008-11-12 10:03:55 -080053static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54 unsigned alignment);
Jesse Barnesde151cf2008-11-12 10:03:55 -080055static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +100056static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
57 struct drm_i915_gem_pwrite *args,
58 struct drm_file *file_priv);
Chris Wilsonbe726152010-07-23 23:18:50 +010059static void i915_gem_free_object_tail(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070060
Chris Wilson31169712009-09-14 16:50:28 +010061static LIST_HEAD(shrink_list);
62static DEFINE_SPINLOCK(shrink_list_lock);
63
Chris Wilson7d1c4802010-08-07 21:45:03 +010064static inline bool
65i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
66{
67 return obj_priv->gtt_space &&
68 !obj_priv->active &&
69 obj_priv->pin_count == 0;
70}
71
Jesse Barnes79e53942008-11-07 14:24:08 -080072int i915_gem_do_init(struct drm_device *dev, unsigned long start,
73 unsigned long end)
74{
75 drm_i915_private_t *dev_priv = dev->dev_private;
76
77 if (start >= end ||
78 (start & (PAGE_SIZE - 1)) != 0 ||
79 (end & (PAGE_SIZE - 1)) != 0) {
80 return -EINVAL;
81 }
82
83 drm_mm_init(&dev_priv->mm.gtt_space, start,
84 end - start);
85
86 dev->gtt_total = (uint32_t) (end - start);
87
88 return 0;
89}
Keith Packard6dbe2772008-10-14 21:41:13 -070090
Eric Anholt673a3942008-07-30 12:06:12 -070091int
92i915_gem_init_ioctl(struct drm_device *dev, void *data,
93 struct drm_file *file_priv)
94{
Eric Anholt673a3942008-07-30 12:06:12 -070095 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080096 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070097
98 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080099 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -0700100 mutex_unlock(&dev->struct_mutex);
101
Jesse Barnes79e53942008-11-07 14:24:08 -0800102 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700103}
104
Eric Anholt5a125c32008-10-22 21:40:13 -0700105int
106i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
107 struct drm_file *file_priv)
108{
Eric Anholt5a125c32008-10-22 21:40:13 -0700109 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -0700110
111 if (!(dev->driver->driver_features & DRIVER_GEM))
112 return -ENODEV;
113
114 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -0800115 args->aper_available_size = (args->aper_size -
116 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700117
118 return 0;
119}
120
Eric Anholt673a3942008-07-30 12:06:12 -0700121
122/**
123 * Creates a new mm object and returns a handle to it.
124 */
125int
126i915_gem_create_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file_priv)
128{
129 struct drm_i915_gem_create *args = data;
130 struct drm_gem_object *obj;
Pekka Paalanena1a2d1d2009-08-23 12:40:55 +0300131 int ret;
132 u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700133
134 args->size = roundup(args->size, PAGE_SIZE);
135
136 /* Allocate the new object */
Daniel Vetterac52bc52010-04-09 19:05:06 +0000137 obj = i915_gem_alloc_object(dev, args->size);
Eric Anholt673a3942008-07-30 12:06:12 -0700138 if (obj == NULL)
139 return -ENOMEM;
140
141 ret = drm_gem_handle_create(file_priv, obj, &handle);
Chris Wilson1dfd9752010-09-06 14:44:14 +0100142 if (ret) {
143 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700144 return ret;
Chris Wilson1dfd9752010-09-06 14:44:14 +0100145 }
146
147 /* Sink the floating reference from kref_init(handlecount) */
148 drm_gem_object_handle_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700149
150 args->handle = handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700151 return 0;
152}
153
Eric Anholt40123c12009-03-09 13:42:30 -0700154static inline int
Eric Anholteb014592009-03-10 11:44:52 -0700155fast_shmem_read(struct page **pages,
156 loff_t page_base, int page_offset,
157 char __user *data,
158 int length)
159{
160 char __iomem *vaddr;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200161 int unwritten;
Eric Anholteb014592009-03-10 11:44:52 -0700162
163 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
164 if (vaddr == NULL)
165 return -ENOMEM;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200166 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
Eric Anholteb014592009-03-10 11:44:52 -0700167 kunmap_atomic(vaddr, KM_USER0);
168
Florian Mickler2bc43b52009-04-06 22:55:41 +0200169 if (unwritten)
170 return -EFAULT;
171
172 return 0;
Eric Anholteb014592009-03-10 11:44:52 -0700173}
174
Eric Anholt280b7132009-03-12 16:56:27 -0700175static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
176{
177 drm_i915_private_t *dev_priv = obj->dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +0100178 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt280b7132009-03-12 16:56:27 -0700179
180 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
181 obj_priv->tiling_mode != I915_TILING_NONE;
182}
183
Chris Wilson99a03df2010-05-27 14:15:34 +0100184static inline void
Eric Anholt40123c12009-03-09 13:42:30 -0700185slow_shmem_copy(struct page *dst_page,
186 int dst_offset,
187 struct page *src_page,
188 int src_offset,
189 int length)
190{
191 char *dst_vaddr, *src_vaddr;
192
Chris Wilson99a03df2010-05-27 14:15:34 +0100193 dst_vaddr = kmap(dst_page);
194 src_vaddr = kmap(src_page);
Eric Anholt40123c12009-03-09 13:42:30 -0700195
196 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
197
Chris Wilson99a03df2010-05-27 14:15:34 +0100198 kunmap(src_page);
199 kunmap(dst_page);
Eric Anholt40123c12009-03-09 13:42:30 -0700200}
201
Chris Wilson99a03df2010-05-27 14:15:34 +0100202static inline void
Eric Anholt280b7132009-03-12 16:56:27 -0700203slow_shmem_bit17_copy(struct page *gpu_page,
204 int gpu_offset,
205 struct page *cpu_page,
206 int cpu_offset,
207 int length,
208 int is_read)
209{
210 char *gpu_vaddr, *cpu_vaddr;
211
212 /* Use the unswizzled path if this page isn't affected. */
213 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
214 if (is_read)
215 return slow_shmem_copy(cpu_page, cpu_offset,
216 gpu_page, gpu_offset, length);
217 else
218 return slow_shmem_copy(gpu_page, gpu_offset,
219 cpu_page, cpu_offset, length);
220 }
221
Chris Wilson99a03df2010-05-27 14:15:34 +0100222 gpu_vaddr = kmap(gpu_page);
223 cpu_vaddr = kmap(cpu_page);
Eric Anholt280b7132009-03-12 16:56:27 -0700224
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
227 */
228 while (length > 0) {
229 int cacheline_end = ALIGN(gpu_offset + 1, 64);
230 int this_length = min(cacheline_end - gpu_offset, length);
231 int swizzled_gpu_offset = gpu_offset ^ 64;
232
233 if (is_read) {
234 memcpy(cpu_vaddr + cpu_offset,
235 gpu_vaddr + swizzled_gpu_offset,
236 this_length);
237 } else {
238 memcpy(gpu_vaddr + swizzled_gpu_offset,
239 cpu_vaddr + cpu_offset,
240 this_length);
241 }
242 cpu_offset += this_length;
243 gpu_offset += this_length;
244 length -= this_length;
245 }
246
Chris Wilson99a03df2010-05-27 14:15:34 +0100247 kunmap(cpu_page);
248 kunmap(gpu_page);
Eric Anholt280b7132009-03-12 16:56:27 -0700249}
250
Eric Anholt673a3942008-07-30 12:06:12 -0700251/**
Eric Anholteb014592009-03-10 11:44:52 -0700252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
255 */
256static int
257i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
258 struct drm_i915_gem_pread *args,
259 struct drm_file *file_priv)
260{
Daniel Vetter23010e42010-03-08 13:35:02 +0100261 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700262 ssize_t remain;
263 loff_t offset, page_base;
264 char __user *user_data;
265 int page_offset, page_length;
266 int ret;
267
268 user_data = (char __user *) (uintptr_t) args->data_ptr;
269 remain = args->size;
270
271 mutex_lock(&dev->struct_mutex);
272
Chris Wilson4bdadb92010-01-27 13:36:32 +0000273 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholteb014592009-03-10 11:44:52 -0700274 if (ret != 0)
275 goto fail_unlock;
276
277 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
278 args->size);
279 if (ret != 0)
280 goto fail_put_pages;
281
Daniel Vetter23010e42010-03-08 13:35:02 +0100282 obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700283 offset = args->offset;
284
285 while (remain > 0) {
286 /* Operation in this page
287 *
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
291 */
292 page_base = (offset & ~(PAGE_SIZE-1));
293 page_offset = offset & (PAGE_SIZE-1);
294 page_length = remain;
295 if ((page_offset + remain) > PAGE_SIZE)
296 page_length = PAGE_SIZE - page_offset;
297
298 ret = fast_shmem_read(obj_priv->pages,
299 page_base, page_offset,
300 user_data, page_length);
301 if (ret)
302 goto fail_put_pages;
303
304 remain -= page_length;
305 user_data += page_length;
306 offset += page_length;
307 }
308
309fail_put_pages:
310 i915_gem_object_put_pages(obj);
311fail_unlock:
312 mutex_unlock(&dev->struct_mutex);
313
314 return ret;
315}
316
Chris Wilson07f73f62009-09-14 16:50:30 +0100317static int
318i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
319{
320 int ret;
321
Chris Wilson4bdadb92010-01-27 13:36:32 +0000322 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
Chris Wilson07f73f62009-09-14 16:50:30 +0100323
324 /* If we've insufficient memory to map in the pages, attempt
325 * to make some space by throwing out some old buffers.
326 */
327 if (ret == -ENOMEM) {
328 struct drm_device *dev = obj->dev;
Chris Wilson07f73f62009-09-14 16:50:30 +0100329
Daniel Vetter0108a3e2010-08-07 11:01:21 +0100330 ret = i915_gem_evict_something(dev, obj->size,
331 i915_gem_get_gtt_alignment(obj));
Chris Wilson07f73f62009-09-14 16:50:30 +0100332 if (ret)
333 return ret;
334
Chris Wilson4bdadb92010-01-27 13:36:32 +0000335 ret = i915_gem_object_get_pages(obj, 0);
Chris Wilson07f73f62009-09-14 16:50:30 +0100336 }
337
338 return ret;
339}
340
Eric Anholteb014592009-03-10 11:44:52 -0700341/**
342 * This is the fallback shmem pread path, which allocates temporary storage
343 * in kernel space to copy_to_user into outside of the struct_mutex, so we
344 * can copy out of the object's backing pages while holding the struct mutex
345 * and not take page faults.
346 */
347static int
348i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
349 struct drm_i915_gem_pread *args,
350 struct drm_file *file_priv)
351{
Daniel Vetter23010e42010-03-08 13:35:02 +0100352 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700353 struct mm_struct *mm = current->mm;
354 struct page **user_pages;
355 ssize_t remain;
356 loff_t offset, pinned_pages, i;
357 loff_t first_data_page, last_data_page, num_pages;
358 int shmem_page_index, shmem_page_offset;
359 int data_page_index, data_page_offset;
360 int page_length;
361 int ret;
362 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700363 int do_bit17_swizzling;
Eric Anholteb014592009-03-10 11:44:52 -0700364
365 remain = args->size;
366
367 /* Pin the user pages containing the data. We can't fault while
368 * holding the struct mutex, yet we want to hold it while
369 * dereferencing the user data.
370 */
371 first_data_page = data_ptr / PAGE_SIZE;
372 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
373 num_pages = last_data_page - first_data_page + 1;
374
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700375 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholteb014592009-03-10 11:44:52 -0700376 if (user_pages == NULL)
377 return -ENOMEM;
378
379 down_read(&mm->mmap_sem);
380 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
Eric Anholte5e9ecd2009-04-07 16:01:22 -0700381 num_pages, 1, 0, user_pages, NULL);
Eric Anholteb014592009-03-10 11:44:52 -0700382 up_read(&mm->mmap_sem);
383 if (pinned_pages < num_pages) {
384 ret = -EFAULT;
385 goto fail_put_user_pages;
386 }
387
Eric Anholt280b7132009-03-12 16:56:27 -0700388 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
389
Eric Anholteb014592009-03-10 11:44:52 -0700390 mutex_lock(&dev->struct_mutex);
391
Chris Wilson07f73f62009-09-14 16:50:30 +0100392 ret = i915_gem_object_get_pages_or_evict(obj);
393 if (ret)
Eric Anholteb014592009-03-10 11:44:52 -0700394 goto fail_unlock;
395
396 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
397 args->size);
398 if (ret != 0)
399 goto fail_put_pages;
400
Daniel Vetter23010e42010-03-08 13:35:02 +0100401 obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700402 offset = args->offset;
403
404 while (remain > 0) {
405 /* Operation in this page
406 *
407 * shmem_page_index = page number within shmem file
408 * shmem_page_offset = offset within page in shmem file
409 * data_page_index = page number in get_user_pages return
410 * data_page_offset = offset with data_page_index page.
411 * page_length = bytes to copy for this page
412 */
413 shmem_page_index = offset / PAGE_SIZE;
414 shmem_page_offset = offset & ~PAGE_MASK;
415 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
416 data_page_offset = data_ptr & ~PAGE_MASK;
417
418 page_length = remain;
419 if ((shmem_page_offset + page_length) > PAGE_SIZE)
420 page_length = PAGE_SIZE - shmem_page_offset;
421 if ((data_page_offset + page_length) > PAGE_SIZE)
422 page_length = PAGE_SIZE - data_page_offset;
423
Eric Anholt280b7132009-03-12 16:56:27 -0700424 if (do_bit17_swizzling) {
Chris Wilson99a03df2010-05-27 14:15:34 +0100425 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
Eric Anholt280b7132009-03-12 16:56:27 -0700426 shmem_page_offset,
Chris Wilson99a03df2010-05-27 14:15:34 +0100427 user_pages[data_page_index],
428 data_page_offset,
429 page_length,
430 1);
431 } else {
432 slow_shmem_copy(user_pages[data_page_index],
433 data_page_offset,
434 obj_priv->pages[shmem_page_index],
435 shmem_page_offset,
436 page_length);
Eric Anholt280b7132009-03-12 16:56:27 -0700437 }
Eric Anholteb014592009-03-10 11:44:52 -0700438
439 remain -= page_length;
440 data_ptr += page_length;
441 offset += page_length;
442 }
443
444fail_put_pages:
445 i915_gem_object_put_pages(obj);
446fail_unlock:
447 mutex_unlock(&dev->struct_mutex);
448fail_put_user_pages:
449 for (i = 0; i < pinned_pages; i++) {
450 SetPageDirty(user_pages[i]);
451 page_cache_release(user_pages[i]);
452 }
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700453 drm_free_large(user_pages);
Eric Anholteb014592009-03-10 11:44:52 -0700454
455 return ret;
456}
457
Eric Anholt673a3942008-07-30 12:06:12 -0700458/**
459 * Reads data from the object referenced by handle.
460 *
461 * On error, the contents of *data are undefined.
462 */
463int
464i915_gem_pread_ioctl(struct drm_device *dev, void *data,
465 struct drm_file *file_priv)
466{
467 struct drm_i915_gem_pread *args = data;
468 struct drm_gem_object *obj;
469 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -0700470 int ret;
471
472 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
473 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +0100474 return -ENOENT;
Daniel Vetter23010e42010-03-08 13:35:02 +0100475 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700476
477 /* Bounds check source.
478 *
479 * XXX: This could use review for overflow issues...
480 */
481 if (args->offset > obj->size || args->size > obj->size ||
482 args->offset + args->size > obj->size) {
Luca Barbieribc9025b2010-02-09 05:49:12 +0000483 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700484 return -EINVAL;
485 }
486
Eric Anholt280b7132009-03-12 16:56:27 -0700487 if (i915_gem_object_needs_bit17_swizzle(obj)) {
Eric Anholteb014592009-03-10 11:44:52 -0700488 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
Eric Anholt280b7132009-03-12 16:56:27 -0700489 } else {
490 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
491 if (ret != 0)
492 ret = i915_gem_shmem_pread_slow(dev, obj, args,
493 file_priv);
494 }
Eric Anholt673a3942008-07-30 12:06:12 -0700495
Luca Barbieribc9025b2010-02-09 05:49:12 +0000496 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700497
Eric Anholteb014592009-03-10 11:44:52 -0700498 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700499}
500
Keith Packard0839ccb2008-10-30 19:38:48 -0700501/* This is the fast write path which cannot handle
502 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700503 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700504
Keith Packard0839ccb2008-10-30 19:38:48 -0700505static inline int
506fast_user_write(struct io_mapping *mapping,
507 loff_t page_base, int page_offset,
508 char __user *user_data,
509 int length)
510{
511 char *vaddr_atomic;
512 unsigned long unwritten;
513
Chris Wilsonfca3ec02010-08-04 14:34:24 +0100514 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
Keith Packard0839ccb2008-10-30 19:38:48 -0700515 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
516 user_data, length);
Chris Wilsonfca3ec02010-08-04 14:34:24 +0100517 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
Keith Packard0839ccb2008-10-30 19:38:48 -0700518 if (unwritten)
519 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700520 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700521}
522
523/* Here's the write path which can sleep for
524 * page faults
525 */
526
Chris Wilsonab34c222010-05-27 14:15:35 +0100527static inline void
Eric Anholt3de09aa2009-03-09 09:42:23 -0700528slow_kernel_write(struct io_mapping *mapping,
529 loff_t gtt_base, int gtt_offset,
530 struct page *user_page, int user_offset,
531 int length)
Keith Packard0839ccb2008-10-30 19:38:48 -0700532{
Chris Wilsonab34c222010-05-27 14:15:35 +0100533 char __iomem *dst_vaddr;
534 char *src_vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700535
Chris Wilsonab34c222010-05-27 14:15:35 +0100536 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
537 src_vaddr = kmap(user_page);
538
539 memcpy_toio(dst_vaddr + gtt_offset,
540 src_vaddr + user_offset,
541 length);
542
543 kunmap(user_page);
544 io_mapping_unmap(dst_vaddr);
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700545}
546
Eric Anholt40123c12009-03-09 13:42:30 -0700547static inline int
548fast_shmem_write(struct page **pages,
549 loff_t page_base, int page_offset,
550 char __user *data,
551 int length)
552{
553 char __iomem *vaddr;
Dave Airlied0088772009-03-28 20:29:48 -0400554 unsigned long unwritten;
Eric Anholt40123c12009-03-09 13:42:30 -0700555
556 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
557 if (vaddr == NULL)
558 return -ENOMEM;
Dave Airlied0088772009-03-28 20:29:48 -0400559 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
Eric Anholt40123c12009-03-09 13:42:30 -0700560 kunmap_atomic(vaddr, KM_USER0);
561
Dave Airlied0088772009-03-28 20:29:48 -0400562 if (unwritten)
563 return -EFAULT;
Eric Anholt40123c12009-03-09 13:42:30 -0700564 return 0;
565}
566
Eric Anholt3de09aa2009-03-09 09:42:23 -0700567/**
568 * This is the fast pwrite path, where we copy the data directly from the
569 * user into the GTT, uncached.
570 */
Eric Anholt673a3942008-07-30 12:06:12 -0700571static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700572i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
573 struct drm_i915_gem_pwrite *args,
574 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700575{
Daniel Vetter23010e42010-03-08 13:35:02 +0100576 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Keith Packard0839ccb2008-10-30 19:38:48 -0700577 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700578 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700579 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700580 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700581 int page_offset, page_length;
582 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700583
584 user_data = (char __user *) (uintptr_t) args->data_ptr;
585 remain = args->size;
586 if (!access_ok(VERIFY_READ, user_data, remain))
587 return -EFAULT;
588
589
590 mutex_lock(&dev->struct_mutex);
591 ret = i915_gem_object_pin(obj, 0);
592 if (ret) {
593 mutex_unlock(&dev->struct_mutex);
594 return ret;
595 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800596 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700597 if (ret)
598 goto fail;
599
Daniel Vetter23010e42010-03-08 13:35:02 +0100600 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700601 offset = obj_priv->gtt_offset + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700602
603 while (remain > 0) {
604 /* Operation in this page
605 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700606 * page_base = page offset within aperture
607 * page_offset = offset within page
608 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700609 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700610 page_base = (offset & ~(PAGE_SIZE-1));
611 page_offset = offset & (PAGE_SIZE-1);
612 page_length = remain;
613 if ((page_offset + remain) > PAGE_SIZE)
614 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700615
Keith Packard0839ccb2008-10-30 19:38:48 -0700616 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
617 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700618
Keith Packard0839ccb2008-10-30 19:38:48 -0700619 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700620 * source page isn't available. Return the error and we'll
621 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700622 */
Eric Anholt3de09aa2009-03-09 09:42:23 -0700623 if (ret)
624 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700625
Keith Packard0839ccb2008-10-30 19:38:48 -0700626 remain -= page_length;
627 user_data += page_length;
628 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700629 }
Eric Anholt673a3942008-07-30 12:06:12 -0700630
631fail:
632 i915_gem_object_unpin(obj);
633 mutex_unlock(&dev->struct_mutex);
634
635 return ret;
636}
637
Eric Anholt3de09aa2009-03-09 09:42:23 -0700638/**
639 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
640 * the memory and maps it using kmap_atomic for copying.
641 *
642 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
643 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
644 */
Eric Anholt3043c602008-10-02 12:24:47 -0700645static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700646i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
647 struct drm_i915_gem_pwrite *args,
648 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700649{
Daniel Vetter23010e42010-03-08 13:35:02 +0100650 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700651 drm_i915_private_t *dev_priv = dev->dev_private;
652 ssize_t remain;
653 loff_t gtt_page_base, offset;
654 loff_t first_data_page, last_data_page, num_pages;
655 loff_t pinned_pages, i;
656 struct page **user_pages;
657 struct mm_struct *mm = current->mm;
658 int gtt_page_offset, data_page_offset, data_page_index, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700659 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700660 uint64_t data_ptr = args->data_ptr;
661
662 remain = args->size;
663
664 /* Pin the user pages containing the data. We can't fault while
665 * holding the struct mutex, and all of the pwrite implementations
666 * want to hold it while dereferencing the user data.
667 */
668 first_data_page = data_ptr / PAGE_SIZE;
669 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
670 num_pages = last_data_page - first_data_page + 1;
671
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700672 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt3de09aa2009-03-09 09:42:23 -0700673 if (user_pages == NULL)
674 return -ENOMEM;
675
676 down_read(&mm->mmap_sem);
677 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
678 num_pages, 0, 0, user_pages, NULL);
679 up_read(&mm->mmap_sem);
680 if (pinned_pages < num_pages) {
681 ret = -EFAULT;
682 goto out_unpin_pages;
683 }
684
685 mutex_lock(&dev->struct_mutex);
686 ret = i915_gem_object_pin(obj, 0);
687 if (ret)
688 goto out_unlock;
689
690 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
691 if (ret)
692 goto out_unpin_object;
693
Daniel Vetter23010e42010-03-08 13:35:02 +0100694 obj_priv = to_intel_bo(obj);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700695 offset = obj_priv->gtt_offset + args->offset;
696
697 while (remain > 0) {
698 /* Operation in this page
699 *
700 * gtt_page_base = page offset within aperture
701 * gtt_page_offset = offset within page in aperture
702 * data_page_index = page number in get_user_pages return
703 * data_page_offset = offset with data_page_index page.
704 * page_length = bytes to copy for this page
705 */
706 gtt_page_base = offset & PAGE_MASK;
707 gtt_page_offset = offset & ~PAGE_MASK;
708 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
709 data_page_offset = data_ptr & ~PAGE_MASK;
710
711 page_length = remain;
712 if ((gtt_page_offset + page_length) > PAGE_SIZE)
713 page_length = PAGE_SIZE - gtt_page_offset;
714 if ((data_page_offset + page_length) > PAGE_SIZE)
715 page_length = PAGE_SIZE - data_page_offset;
716
Chris Wilsonab34c222010-05-27 14:15:35 +0100717 slow_kernel_write(dev_priv->mm.gtt_mapping,
718 gtt_page_base, gtt_page_offset,
719 user_pages[data_page_index],
720 data_page_offset,
721 page_length);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700722
723 remain -= page_length;
724 offset += page_length;
725 data_ptr += page_length;
726 }
727
728out_unpin_object:
729 i915_gem_object_unpin(obj);
730out_unlock:
731 mutex_unlock(&dev->struct_mutex);
732out_unpin_pages:
733 for (i = 0; i < pinned_pages; i++)
734 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700735 drm_free_large(user_pages);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700736
737 return ret;
738}
739
Eric Anholt40123c12009-03-09 13:42:30 -0700740/**
741 * This is the fast shmem pwrite path, which attempts to directly
742 * copy_from_user into the kmapped pages backing the object.
743 */
Eric Anholt673a3942008-07-30 12:06:12 -0700744static int
Eric Anholt40123c12009-03-09 13:42:30 -0700745i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
746 struct drm_i915_gem_pwrite *args,
747 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700748{
Daniel Vetter23010e42010-03-08 13:35:02 +0100749 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700750 ssize_t remain;
751 loff_t offset, page_base;
752 char __user *user_data;
753 int page_offset, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700754 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700755
756 user_data = (char __user *) (uintptr_t) args->data_ptr;
757 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700758
759 mutex_lock(&dev->struct_mutex);
760
Chris Wilson4bdadb92010-01-27 13:36:32 +0000761 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholt40123c12009-03-09 13:42:30 -0700762 if (ret != 0)
763 goto fail_unlock;
764
Eric Anholte47c68e2008-11-14 13:35:19 -0800765 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt40123c12009-03-09 13:42:30 -0700766 if (ret != 0)
767 goto fail_put_pages;
Eric Anholt673a3942008-07-30 12:06:12 -0700768
Daniel Vetter23010e42010-03-08 13:35:02 +0100769 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700770 offset = args->offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700771 obj_priv->dirty = 1;
Eric Anholt673a3942008-07-30 12:06:12 -0700772
Eric Anholt40123c12009-03-09 13:42:30 -0700773 while (remain > 0) {
774 /* Operation in this page
775 *
776 * page_base = page offset within aperture
777 * page_offset = offset within page
778 * page_length = bytes to copy for this page
779 */
780 page_base = (offset & ~(PAGE_SIZE-1));
781 page_offset = offset & (PAGE_SIZE-1);
782 page_length = remain;
783 if ((page_offset + remain) > PAGE_SIZE)
784 page_length = PAGE_SIZE - page_offset;
785
786 ret = fast_shmem_write(obj_priv->pages,
787 page_base, page_offset,
788 user_data, page_length);
789 if (ret)
790 goto fail_put_pages;
791
792 remain -= page_length;
793 user_data += page_length;
794 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700795 }
796
Eric Anholt40123c12009-03-09 13:42:30 -0700797fail_put_pages:
798 i915_gem_object_put_pages(obj);
799fail_unlock:
Eric Anholt673a3942008-07-30 12:06:12 -0700800 mutex_unlock(&dev->struct_mutex);
801
Eric Anholt40123c12009-03-09 13:42:30 -0700802 return ret;
803}
804
805/**
806 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
807 * the memory and maps it using kmap_atomic for copying.
808 *
809 * This avoids taking mmap_sem for faulting on the user's address while the
810 * struct_mutex is held.
811 */
812static int
813i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
814 struct drm_i915_gem_pwrite *args,
815 struct drm_file *file_priv)
816{
Daniel Vetter23010e42010-03-08 13:35:02 +0100817 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700818 struct mm_struct *mm = current->mm;
819 struct page **user_pages;
820 ssize_t remain;
821 loff_t offset, pinned_pages, i;
822 loff_t first_data_page, last_data_page, num_pages;
823 int shmem_page_index, shmem_page_offset;
824 int data_page_index, data_page_offset;
825 int page_length;
826 int ret;
827 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700828 int do_bit17_swizzling;
Eric Anholt40123c12009-03-09 13:42:30 -0700829
830 remain = args->size;
831
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
835 */
836 first_data_page = data_ptr / PAGE_SIZE;
837 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
838 num_pages = last_data_page - first_data_page + 1;
839
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700840 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt40123c12009-03-09 13:42:30 -0700841 if (user_pages == NULL)
842 return -ENOMEM;
843
844 down_read(&mm->mmap_sem);
845 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
846 num_pages, 0, 0, user_pages, NULL);
847 up_read(&mm->mmap_sem);
848 if (pinned_pages < num_pages) {
849 ret = -EFAULT;
850 goto fail_put_user_pages;
851 }
852
Eric Anholt280b7132009-03-12 16:56:27 -0700853 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
854
Eric Anholt40123c12009-03-09 13:42:30 -0700855 mutex_lock(&dev->struct_mutex);
856
Chris Wilson07f73f62009-09-14 16:50:30 +0100857 ret = i915_gem_object_get_pages_or_evict(obj);
858 if (ret)
Eric Anholt40123c12009-03-09 13:42:30 -0700859 goto fail_unlock;
860
861 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
862 if (ret != 0)
863 goto fail_put_pages;
864
Daniel Vetter23010e42010-03-08 13:35:02 +0100865 obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700866 offset = args->offset;
867 obj_priv->dirty = 1;
868
869 while (remain > 0) {
870 /* Operation in this page
871 *
872 * shmem_page_index = page number within shmem file
873 * shmem_page_offset = offset within page in shmem file
874 * data_page_index = page number in get_user_pages return
875 * data_page_offset = offset with data_page_index page.
876 * page_length = bytes to copy for this page
877 */
878 shmem_page_index = offset / PAGE_SIZE;
879 shmem_page_offset = offset & ~PAGE_MASK;
880 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
881 data_page_offset = data_ptr & ~PAGE_MASK;
882
883 page_length = remain;
884 if ((shmem_page_offset + page_length) > PAGE_SIZE)
885 page_length = PAGE_SIZE - shmem_page_offset;
886 if ((data_page_offset + page_length) > PAGE_SIZE)
887 page_length = PAGE_SIZE - data_page_offset;
888
Eric Anholt280b7132009-03-12 16:56:27 -0700889 if (do_bit17_swizzling) {
Chris Wilson99a03df2010-05-27 14:15:34 +0100890 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
Eric Anholt280b7132009-03-12 16:56:27 -0700891 shmem_page_offset,
892 user_pages[data_page_index],
893 data_page_offset,
Chris Wilson99a03df2010-05-27 14:15:34 +0100894 page_length,
895 0);
896 } else {
897 slow_shmem_copy(obj_priv->pages[shmem_page_index],
898 shmem_page_offset,
899 user_pages[data_page_index],
900 data_page_offset,
901 page_length);
Eric Anholt280b7132009-03-12 16:56:27 -0700902 }
Eric Anholt40123c12009-03-09 13:42:30 -0700903
904 remain -= page_length;
905 data_ptr += page_length;
906 offset += page_length;
907 }
908
909fail_put_pages:
910 i915_gem_object_put_pages(obj);
911fail_unlock:
912 mutex_unlock(&dev->struct_mutex);
913fail_put_user_pages:
914 for (i = 0; i < pinned_pages; i++)
915 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700916 drm_free_large(user_pages);
Eric Anholt40123c12009-03-09 13:42:30 -0700917
918 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700919}
920
921/**
922 * Writes data to the object referenced by handle.
923 *
924 * On error, the contents of the buffer that were to be modified are undefined.
925 */
926int
927i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
928 struct drm_file *file_priv)
929{
930 struct drm_i915_gem_pwrite *args = data;
931 struct drm_gem_object *obj;
932 struct drm_i915_gem_object *obj_priv;
933 int ret = 0;
934
935 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
936 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +0100937 return -ENOENT;
Daniel Vetter23010e42010-03-08 13:35:02 +0100938 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700939
940 /* Bounds check destination.
941 *
942 * XXX: This could use review for overflow issues...
943 */
944 if (args->offset > obj->size || args->size > obj->size ||
945 args->offset + args->size > obj->size) {
Luca Barbieribc9025b2010-02-09 05:49:12 +0000946 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700947 return -EINVAL;
948 }
949
950 /* We can only do the GTT pwrite on untiled buffers, as otherwise
951 * it would end up going through the fenced access, and we'll get
952 * different detiling behavior between reading and writing.
953 * pread/pwrite currently are reading and writing from the CPU
954 * perspective, requiring manual detiling by the client.
955 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000956 if (obj_priv->phys_obj)
957 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
958 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
Chris Wilson9b8c4a02010-05-27 14:21:01 +0100959 dev->gtt_total != 0 &&
960 obj->write_domain != I915_GEM_DOMAIN_CPU) {
Eric Anholt3de09aa2009-03-09 09:42:23 -0700961 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
962 if (ret == -EFAULT) {
963 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
964 file_priv);
965 }
Eric Anholt280b7132009-03-12 16:56:27 -0700966 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
967 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
Eric Anholt40123c12009-03-09 13:42:30 -0700968 } else {
969 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
970 if (ret == -EFAULT) {
971 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
972 file_priv);
973 }
974 }
Eric Anholt673a3942008-07-30 12:06:12 -0700975
976#if WATCH_PWRITE
977 if (ret)
978 DRM_INFO("pwrite failed %d\n", ret);
979#endif
980
Luca Barbieribc9025b2010-02-09 05:49:12 +0000981 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700982
983 return ret;
984}
985
986/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800987 * Called when user space prepares to use an object with the CPU, either
988 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -0700989 */
990int
991i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *file_priv)
993{
Eric Anholta09ba7f2009-08-29 12:49:51 -0700994 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700995 struct drm_i915_gem_set_domain *args = data;
996 struct drm_gem_object *obj;
Jesse Barnes652c3932009-08-17 13:31:43 -0700997 struct drm_i915_gem_object *obj_priv;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800998 uint32_t read_domains = args->read_domains;
999 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07001000 int ret;
1001
1002 if (!(dev->driver->driver_features & DRIVER_GEM))
1003 return -ENODEV;
1004
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001005 /* Only handle setting domains to types used by the CPU. */
Chris Wilson21d509e2009-06-06 09:46:02 +01001006 if (write_domain & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001007 return -EINVAL;
1008
Chris Wilson21d509e2009-06-06 09:46:02 +01001009 if (read_domains & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001010 return -EINVAL;
1011
1012 /* Having something in the write domain implies it's in the read
1013 * domain, and only that read domain. Enforce that in the request.
1014 */
1015 if (write_domain != 0 && read_domains != write_domain)
1016 return -EINVAL;
1017
Eric Anholt673a3942008-07-30 12:06:12 -07001018 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1019 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001020 return -ENOENT;
Daniel Vetter23010e42010-03-08 13:35:02 +01001021 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001022
1023 mutex_lock(&dev->struct_mutex);
Jesse Barnes652c3932009-08-17 13:31:43 -07001024
1025 intel_mark_busy(dev, obj);
1026
Eric Anholt673a3942008-07-30 12:06:12 -07001027#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001028 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001029 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07001030#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001031 if (read_domains & I915_GEM_DOMAIN_GTT) {
1032 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -08001033
Eric Anholta09ba7f2009-08-29 12:49:51 -07001034 /* Update the LRU on the fence for the CPU access that's
1035 * about to occur.
1036 */
1037 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001038 struct drm_i915_fence_reg *reg =
1039 &dev_priv->fence_regs[obj_priv->fence_reg];
1040 list_move_tail(&reg->lru_list,
Eric Anholta09ba7f2009-08-29 12:49:51 -07001041 &dev_priv->mm.fence_list);
1042 }
1043
Eric Anholt02354392008-11-26 13:58:13 -08001044 /* Silently promote "you're not bound, there was nothing to do"
1045 * to success, since the client was just asking us to
1046 * make sure everything was done.
1047 */
1048 if (ret == -EINVAL)
1049 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001050 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -08001051 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001052 }
1053
Chris Wilson7d1c4802010-08-07 21:45:03 +01001054
1055 /* Maintain LRU order of "inactive" objects */
1056 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1057 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1058
Eric Anholt673a3942008-07-30 12:06:12 -07001059 drm_gem_object_unreference(obj);
1060 mutex_unlock(&dev->struct_mutex);
1061 return ret;
1062}
1063
1064/**
1065 * Called when user space has done writes to this buffer
1066 */
1067int
1068i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv)
1070{
1071 struct drm_i915_gem_sw_finish *args = data;
1072 struct drm_gem_object *obj;
1073 struct drm_i915_gem_object *obj_priv;
1074 int ret = 0;
1075
1076 if (!(dev->driver->driver_features & DRIVER_GEM))
1077 return -ENODEV;
1078
1079 mutex_lock(&dev->struct_mutex);
1080 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1081 if (obj == NULL) {
1082 mutex_unlock(&dev->struct_mutex);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001083 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07001084 }
1085
1086#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001087 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
Eric Anholt673a3942008-07-30 12:06:12 -07001088 __func__, args->handle, obj, obj->size);
1089#endif
Daniel Vetter23010e42010-03-08 13:35:02 +01001090 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001091
1092 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -08001093 if (obj_priv->pin_count)
1094 i915_gem_object_flush_cpu_write_domain(obj);
1095
Eric Anholt673a3942008-07-30 12:06:12 -07001096 drm_gem_object_unreference(obj);
1097 mutex_unlock(&dev->struct_mutex);
1098 return ret;
1099}
1100
1101/**
1102 * Maps the contents of an object, returning the address it is mapped
1103 * into.
1104 *
1105 * While the mapping holds a reference on the contents of the object, it doesn't
1106 * imply a ref on the object itself.
1107 */
1108int
1109i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1111{
1112 struct drm_i915_gem_mmap *args = data;
1113 struct drm_gem_object *obj;
1114 loff_t offset;
1115 unsigned long addr;
1116
1117 if (!(dev->driver->driver_features & DRIVER_GEM))
1118 return -ENODEV;
1119
1120 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1121 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001122 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07001123
1124 offset = args->offset;
1125
1126 down_write(&current->mm->mmap_sem);
1127 addr = do_mmap(obj->filp, 0, args->size,
1128 PROT_READ | PROT_WRITE, MAP_SHARED,
1129 args->offset);
1130 up_write(&current->mm->mmap_sem);
Luca Barbieribc9025b2010-02-09 05:49:12 +00001131 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001132 if (IS_ERR((void *)addr))
1133 return addr;
1134
1135 args->addr_ptr = (uint64_t) addr;
1136
1137 return 0;
1138}
1139
Jesse Barnesde151cf2008-11-12 10:03:55 -08001140/**
1141 * i915_gem_fault - fault a page into the GTT
1142 * vma: VMA in question
1143 * vmf: fault info
1144 *
1145 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146 * from userspace. The fault handler takes care of binding the object to
1147 * the GTT (if needed), allocating and programming a fence register (again,
1148 * only if needed based on whether the old reg is still valid or the object
1149 * is tiled) and inserting a new PTE into the faulting process.
1150 *
1151 * Note that the faulting process may involve evicting existing objects
1152 * from the GTT and/or fence registers to make room. So performance may
1153 * suffer if the GTT working set is large or there are few fence registers
1154 * left.
1155 */
1156int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1157{
1158 struct drm_gem_object *obj = vma->vm_private_data;
1159 struct drm_device *dev = obj->dev;
Chris Wilson7d1c4802010-08-07 21:45:03 +01001160 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001161 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001162 pgoff_t page_offset;
1163 unsigned long pfn;
1164 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001165 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001166
1167 /* We don't use vmf->pgoff since that has the fake offset */
1168 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1169 PAGE_SHIFT;
1170
1171 /* Now bind it into the GTT if needed */
1172 mutex_lock(&dev->struct_mutex);
1173 if (!obj_priv->gtt_space) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001174 ret = i915_gem_object_bind_to_gtt(obj, 0);
Chris Wilsonc7150892009-09-23 00:43:56 +01001175 if (ret)
1176 goto unlock;
Kristian Høgsberg07f4f3e2009-05-27 14:37:28 -04001177
Jesse Barnesde151cf2008-11-12 10:03:55 -08001178 ret = i915_gem_object_set_to_gtt_domain(obj, write);
Chris Wilsonc7150892009-09-23 00:43:56 +01001179 if (ret)
1180 goto unlock;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001181 }
1182
1183 /* Need a new fence register? */
Eric Anholta09ba7f2009-08-29 12:49:51 -07001184 if (obj_priv->tiling_mode != I915_TILING_NONE) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01001185 ret = i915_gem_object_get_fence_reg(obj, true);
Chris Wilsonc7150892009-09-23 00:43:56 +01001186 if (ret)
1187 goto unlock;
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001188 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001189
Chris Wilson7d1c4802010-08-07 21:45:03 +01001190 if (i915_gem_object_is_inactive(obj_priv))
1191 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192
Jesse Barnesde151cf2008-11-12 10:03:55 -08001193 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1194 page_offset;
1195
1196 /* Finally, remap it using the new GTT offset */
1197 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
Chris Wilsonc7150892009-09-23 00:43:56 +01001198unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001199 mutex_unlock(&dev->struct_mutex);
1200
1201 switch (ret) {
Chris Wilsonc7150892009-09-23 00:43:56 +01001202 case 0:
1203 case -ERESTARTSYS:
1204 return VM_FAULT_NOPAGE;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001205 case -ENOMEM:
1206 case -EAGAIN:
1207 return VM_FAULT_OOM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001208 default:
Chris Wilsonc7150892009-09-23 00:43:56 +01001209 return VM_FAULT_SIGBUS;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001210 }
1211}
1212
1213/**
1214 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215 * @obj: obj in question
1216 *
1217 * GEM memory mapping works by handing back to userspace a fake mmap offset
1218 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1219 * up the object based on the offset and sets up the various memory mapping
1220 * structures.
1221 *
1222 * This routine allocates and attaches a fake offset for @obj.
1223 */
1224static int
1225i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1226{
1227 struct drm_device *dev = obj->dev;
1228 struct drm_gem_mm *mm = dev->mm_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001229 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001230 struct drm_map_list *list;
Benjamin Herrenschmidtf77d3902009-02-02 16:55:46 +11001231 struct drm_local_map *map;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001232 int ret = 0;
1233
1234 /* Set the object up for mmap'ing */
1235 list = &obj->map_list;
Eric Anholt9a298b22009-03-24 12:23:04 -07001236 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001237 if (!list->map)
1238 return -ENOMEM;
1239
1240 map = list->map;
1241 map->type = _DRM_GEM;
1242 map->size = obj->size;
1243 map->handle = obj;
1244
1245 /* Get a DRM GEM mmap offset allocated... */
1246 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1247 obj->size / PAGE_SIZE, 0, 0);
1248 if (!list->file_offset_node) {
1249 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1250 ret = -ENOMEM;
1251 goto out_free_list;
1252 }
1253
1254 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1255 obj->size / PAGE_SIZE, 0);
1256 if (!list->file_offset_node) {
1257 ret = -ENOMEM;
1258 goto out_free_list;
1259 }
1260
1261 list->hash.key = list->file_offset_node->start;
1262 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1263 DRM_ERROR("failed to add to map hash\n");
Chris Wilson5618ca62009-12-02 15:15:30 +00001264 ret = -ENOMEM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001265 goto out_free_mm;
1266 }
1267
1268 /* By now we should be all set, any drm_mmap request on the offset
1269 * below will get to our mmap & fault handler */
1270 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1271
1272 return 0;
1273
1274out_free_mm:
1275 drm_mm_put_block(list->file_offset_node);
1276out_free_list:
Eric Anholt9a298b22009-03-24 12:23:04 -07001277 kfree(list->map);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001278
1279 return ret;
1280}
1281
Chris Wilson901782b2009-07-10 08:18:50 +01001282/**
1283 * i915_gem_release_mmap - remove physical page mappings
1284 * @obj: obj in question
1285 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001286 * Preserve the reservation of the mmapping with the DRM core code, but
Chris Wilson901782b2009-07-10 08:18:50 +01001287 * relinquish ownership of the pages back to the system.
1288 *
1289 * It is vital that we remove the page mapping if we have mapped a tiled
1290 * object through the GTT and then lose the fence register due to
1291 * resource pressure. Similarly if the object has been moved out of the
1292 * aperture, than pages mapped into userspace must be revoked. Removing the
1293 * mapping will then trigger a page fault on the next user access, allowing
1294 * fixup by i915_gem_fault().
1295 */
Eric Anholtd05ca302009-07-10 13:02:26 -07001296void
Chris Wilson901782b2009-07-10 08:18:50 +01001297i915_gem_release_mmap(struct drm_gem_object *obj)
1298{
1299 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson901782b2009-07-10 08:18:50 +01001301
1302 if (dev->dev_mapping)
1303 unmap_mapping_range(dev->dev_mapping,
1304 obj_priv->mmap_offset, obj->size, 1);
1305}
1306
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001307static void
1308i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1309{
1310 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001311 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001312 struct drm_gem_mm *mm = dev->mm_private;
1313 struct drm_map_list *list;
1314
1315 list = &obj->map_list;
1316 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1317
1318 if (list->file_offset_node) {
1319 drm_mm_put_block(list->file_offset_node);
1320 list->file_offset_node = NULL;
1321 }
1322
1323 if (list->map) {
Eric Anholt9a298b22009-03-24 12:23:04 -07001324 kfree(list->map);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001325 list->map = NULL;
1326 }
1327
1328 obj_priv->mmap_offset = 0;
1329}
1330
Jesse Barnesde151cf2008-11-12 10:03:55 -08001331/**
1332 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333 * @obj: object to check
1334 *
1335 * Return the required GTT alignment for an object, taking into account
1336 * potential fence register mapping if needed.
1337 */
1338static uint32_t
1339i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1340{
1341 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001343 int start, i;
1344
1345 /*
1346 * Minimum alignment is 4k (GTT page size), but might be greater
1347 * if a fence register is needed for the object.
1348 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001349 if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001350 return 4096;
1351
1352 /*
1353 * Previous chips need to be aligned to the size of the smallest
1354 * fence register that can contain the object.
1355 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001356 if (INTEL_INFO(dev)->gen == 3)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001357 start = 1024*1024;
1358 else
1359 start = 512*1024;
1360
1361 for (i = start; i < obj->size; i <<= 1)
1362 ;
1363
1364 return i;
1365}
1366
1367/**
1368 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1369 * @dev: DRM device
1370 * @data: GTT mapping ioctl data
1371 * @file_priv: GEM object info
1372 *
1373 * Simply returns the fake offset to userspace so it can mmap it.
1374 * The mmap call will end up in drm_gem_mmap(), which will set things
1375 * up so we can get faults in the handler above.
1376 *
1377 * The fault handler will take care of binding the object into the GTT
1378 * (since it may have been evicted to make room for something), allocating
1379 * a fence register, and mapping the appropriate aperture address into
1380 * userspace.
1381 */
1382int
1383i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1384 struct drm_file *file_priv)
1385{
1386 struct drm_i915_gem_mmap_gtt *args = data;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001387 struct drm_gem_object *obj;
1388 struct drm_i915_gem_object *obj_priv;
1389 int ret;
1390
1391 if (!(dev->driver->driver_features & DRIVER_GEM))
1392 return -ENODEV;
1393
1394 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1395 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001396 return -ENOENT;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001397
1398 mutex_lock(&dev->struct_mutex);
1399
Daniel Vetter23010e42010-03-08 13:35:02 +01001400 obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001401
Chris Wilsonab182822009-09-22 18:46:17 +01001402 if (obj_priv->madv != I915_MADV_WILLNEED) {
1403 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404 drm_gem_object_unreference(obj);
1405 mutex_unlock(&dev->struct_mutex);
1406 return -EINVAL;
1407 }
1408
1409
Jesse Barnesde151cf2008-11-12 10:03:55 -08001410 if (!obj_priv->mmap_offset) {
1411 ret = i915_gem_create_mmap_offset(obj);
Chris Wilson13af1062009-02-11 14:26:31 +00001412 if (ret) {
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001415 return ret;
Chris Wilson13af1062009-02-11 14:26:31 +00001416 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001417 }
1418
1419 args->offset = obj_priv->mmap_offset;
1420
Jesse Barnesde151cf2008-11-12 10:03:55 -08001421 /*
1422 * Pull it into the GTT so that we have a page list (makes the
1423 * initial fault faster and any subsequent flushing possible).
1424 */
1425 if (!obj_priv->agp_mem) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001426 ret = i915_gem_object_bind_to_gtt(obj, 0);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001427 if (ret) {
1428 drm_gem_object_unreference(obj);
1429 mutex_unlock(&dev->struct_mutex);
1430 return ret;
1431 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001432 }
1433
1434 drm_gem_object_unreference(obj);
1435 mutex_unlock(&dev->struct_mutex);
1436
1437 return 0;
1438}
1439
Ben Gamari6911a9b2009-04-02 11:24:54 -07001440void
Eric Anholt856fa192009-03-19 14:10:50 -07001441i915_gem_object_put_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001442{
Daniel Vetter23010e42010-03-08 13:35:02 +01001443 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001444 int page_count = obj->size / PAGE_SIZE;
1445 int i;
1446
Eric Anholt856fa192009-03-19 14:10:50 -07001447 BUG_ON(obj_priv->pages_refcount == 0);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001448 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
Eric Anholt856fa192009-03-19 14:10:50 -07001449
1450 if (--obj_priv->pages_refcount != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001451 return;
1452
Eric Anholt280b7132009-03-12 16:56:27 -07001453 if (obj_priv->tiling_mode != I915_TILING_NONE)
1454 i915_gem_object_save_bit_17_swizzle(obj);
1455
Chris Wilson3ef94da2009-09-14 16:50:29 +01001456 if (obj_priv->madv == I915_MADV_DONTNEED)
Chris Wilson13a05fd2009-09-20 23:03:19 +01001457 obj_priv->dirty = 0;
Chris Wilson3ef94da2009-09-14 16:50:29 +01001458
1459 for (i = 0; i < page_count; i++) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01001460 if (obj_priv->dirty)
1461 set_page_dirty(obj_priv->pages[i]);
1462
1463 if (obj_priv->madv == I915_MADV_WILLNEED)
Eric Anholt856fa192009-03-19 14:10:50 -07001464 mark_page_accessed(obj_priv->pages[i]);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001465
1466 page_cache_release(obj_priv->pages[i]);
1467 }
Eric Anholt673a3942008-07-30 12:06:12 -07001468 obj_priv->dirty = 0;
1469
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07001470 drm_free_large(obj_priv->pages);
Eric Anholt856fa192009-03-19 14:10:50 -07001471 obj_priv->pages = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001472}
1473
Daniel Vettere35a41d2010-02-11 22:13:59 +01001474static uint32_t
Daniel Vettera6910432010-02-02 17:08:37 +01001475i915_gem_next_request_seqno(struct drm_device *dev,
1476 struct intel_ring_buffer *ring)
Daniel Vettere35a41d2010-02-11 22:13:59 +01001477{
1478 drm_i915_private_t *dev_priv = dev->dev_private;
1479
Daniel Vettera6910432010-02-02 17:08:37 +01001480 ring->outstanding_lazy_request = true;
1481
Daniel Vettere35a41d2010-02-11 22:13:59 +01001482 return dev_priv->next_seqno;
1483}
1484
Eric Anholt673a3942008-07-30 12:06:12 -07001485static void
Daniel Vetter617dbe22010-02-11 22:16:02 +01001486i915_gem_object_move_to_active(struct drm_gem_object *obj,
Zou Nan hai852835f2010-05-21 09:08:56 +08001487 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001488{
1489 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001490 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetter617dbe22010-02-11 22:16:02 +01001491 uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1492
Zou Nan hai852835f2010-05-21 09:08:56 +08001493 BUG_ON(ring == NULL);
1494 obj_priv->ring = ring;
Eric Anholt673a3942008-07-30 12:06:12 -07001495
1496 /* Add a reference if we're newly entering the active list. */
1497 if (!obj_priv->active) {
1498 drm_gem_object_reference(obj);
1499 obj_priv->active = 1;
1500 }
Daniel Vettere35a41d2010-02-11 22:13:59 +01001501
Eric Anholt673a3942008-07-30 12:06:12 -07001502 /* Move from whatever list we were on to the tail of execution. */
Zou Nan hai852835f2010-05-21 09:08:56 +08001503 list_move_tail(&obj_priv->list, &ring->active_list);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001504 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001505}
1506
Eric Anholtce44b0e2008-11-06 16:00:31 -08001507static void
1508i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509{
1510 struct drm_device *dev = obj->dev;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001512 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001513
1514 BUG_ON(!obj_priv->active);
1515 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516 obj_priv->last_rendering_seqno = 0;
1517}
Eric Anholt673a3942008-07-30 12:06:12 -07001518
Chris Wilson963b4832009-09-20 23:03:54 +01001519/* Immediately discard the backing storage */
1520static void
1521i915_gem_object_truncate(struct drm_gem_object *obj)
1522{
Daniel Vetter23010e42010-03-08 13:35:02 +01001523 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001524 struct inode *inode;
Chris Wilson963b4832009-09-20 23:03:54 +01001525
Chris Wilsonae9fed62010-08-07 11:01:30 +01001526 /* Our goal here is to return as much of the memory as
1527 * is possible back to the system as we are called from OOM.
1528 * To do this we must instruct the shmfs to drop all of its
1529 * backing pages, *now*. Here we mirror the actions taken
1530 * when by shmem_delete_inode() to release the backing store.
1531 */
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001532 inode = obj->filp->f_path.dentry->d_inode;
Chris Wilsonae9fed62010-08-07 11:01:30 +01001533 truncate_inode_pages(inode->i_mapping, 0);
1534 if (inode->i_op->truncate_range)
1535 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001536
1537 obj_priv->madv = __I915_MADV_PURGED;
Chris Wilson963b4832009-09-20 23:03:54 +01001538}
1539
1540static inline int
1541i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1542{
1543 return obj_priv->madv == I915_MADV_DONTNEED;
1544}
1545
Eric Anholt673a3942008-07-30 12:06:12 -07001546static void
1547i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1548{
1549 struct drm_device *dev = obj->dev;
1550 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001551 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001552
1553 i915_verify_inactive(dev, __FILE__, __LINE__);
1554 if (obj_priv->pin_count != 0)
1555 list_del_init(&obj_priv->list);
1556 else
1557 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1558
Daniel Vetter99fcb762010-02-07 16:20:18 +01001559 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1560
Eric Anholtce44b0e2008-11-06 16:00:31 -08001561 obj_priv->last_rendering_seqno = 0;
Zou Nan hai852835f2010-05-21 09:08:56 +08001562 obj_priv->ring = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001563 if (obj_priv->active) {
1564 obj_priv->active = 0;
1565 drm_gem_object_unreference(obj);
1566 }
1567 i915_verify_inactive(dev, __FILE__, __LINE__);
1568}
1569
Chris Wilson92204342010-09-18 11:02:01 +01001570static void
Daniel Vetter63560392010-02-19 11:51:59 +01001571i915_gem_process_flushing_list(struct drm_device *dev,
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001572 uint32_t flush_domains,
Zou Nan hai852835f2010-05-21 09:08:56 +08001573 struct intel_ring_buffer *ring)
Daniel Vetter63560392010-02-19 11:51:59 +01001574{
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 struct drm_i915_gem_object *obj_priv, *next;
1577
1578 list_for_each_entry_safe(obj_priv, next,
1579 &dev_priv->mm.gpu_write_list,
1580 gpu_write_list) {
Daniel Vettera8089e82010-04-09 19:05:09 +00001581 struct drm_gem_object *obj = &obj_priv->base;
Daniel Vetter63560392010-02-19 11:51:59 +01001582
Chris Wilson2b6efaa2010-09-14 17:04:02 +01001583 if (obj->write_domain & flush_domains &&
1584 obj_priv->ring == ring) {
Daniel Vetter63560392010-02-19 11:51:59 +01001585 uint32_t old_write_domain = obj->write_domain;
1586
1587 obj->write_domain = 0;
1588 list_del_init(&obj_priv->gpu_write_list);
Daniel Vetter617dbe22010-02-11 22:16:02 +01001589 i915_gem_object_move_to_active(obj, ring);
Daniel Vetter63560392010-02-19 11:51:59 +01001590
1591 /* update the fence lru list */
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001592 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1593 struct drm_i915_fence_reg *reg =
1594 &dev_priv->fence_regs[obj_priv->fence_reg];
1595 list_move_tail(&reg->lru_list,
Daniel Vetter63560392010-02-19 11:51:59 +01001596 &dev_priv->mm.fence_list);
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001597 }
Daniel Vetter63560392010-02-19 11:51:59 +01001598
1599 trace_i915_gem_object_change_domain(obj,
1600 obj->read_domains,
1601 old_write_domain);
1602 }
1603 }
1604}
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001605
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001606uint32_t
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001607i915_add_request(struct drm_device *dev,
1608 struct drm_file *file_priv,
Chris Wilson8dc5d142010-08-12 12:36:12 +01001609 struct drm_i915_gem_request *request,
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001610 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001611{
1612 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtb9624422009-06-03 07:27:35 +00001613 struct drm_i915_file_private *i915_file_priv = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001614 uint32_t seqno;
1615 int was_empty;
Eric Anholt673a3942008-07-30 12:06:12 -07001616
Eric Anholtb9624422009-06-03 07:27:35 +00001617 if (file_priv != NULL)
1618 i915_file_priv = file_priv->driver_priv;
1619
Chris Wilson8dc5d142010-08-12 12:36:12 +01001620 if (request == NULL) {
1621 request = kzalloc(sizeof(*request), GFP_KERNEL);
1622 if (request == NULL)
1623 return 0;
1624 }
Eric Anholt673a3942008-07-30 12:06:12 -07001625
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001626 seqno = ring->add_request(dev, ring, file_priv, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001627
1628 request->seqno = seqno;
Zou Nan hai852835f2010-05-21 09:08:56 +08001629 request->ring = ring;
Eric Anholt673a3942008-07-30 12:06:12 -07001630 request->emitted_jiffies = jiffies;
Zou Nan hai852835f2010-05-21 09:08:56 +08001631 was_empty = list_empty(&ring->request_list);
1632 list_add_tail(&request->list, &ring->request_list);
1633
Eric Anholtb9624422009-06-03 07:27:35 +00001634 if (i915_file_priv) {
1635 list_add_tail(&request->client_list,
1636 &i915_file_priv->mm.request_list);
1637 } else {
1638 INIT_LIST_HEAD(&request->client_list);
1639 }
Eric Anholt673a3942008-07-30 12:06:12 -07001640
Ben Gamarif65d9422009-09-14 17:48:44 -04001641 if (!dev_priv->mm.suspended) {
Chris Wilsonb3b079d2010-09-13 23:44:34 +01001642 mod_timer(&dev_priv->hangcheck_timer,
1643 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
Ben Gamarif65d9422009-09-14 17:48:44 -04001644 if (was_empty)
Chris Wilsonb3b079d2010-09-13 23:44:34 +01001645 queue_delayed_work(dev_priv->wq,
1646 &dev_priv->mm.retire_work, HZ);
Ben Gamarif65d9422009-09-14 17:48:44 -04001647 }
Eric Anholt673a3942008-07-30 12:06:12 -07001648 return seqno;
1649}
1650
1651/**
1652 * Command execution barrier
1653 *
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1656 */
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001657static void
Zou Nan hai852835f2010-05-21 09:08:56 +08001658i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001659{
Eric Anholt673a3942008-07-30 12:06:12 -07001660 uint32_t flush_domains = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07001661
1662 /* The sampler always gets flushed on i965 (sigh) */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001663 if (INTEL_INFO(dev)->gen >= 4)
Eric Anholt673a3942008-07-30 12:06:12 -07001664 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
Zou Nan hai852835f2010-05-21 09:08:56 +08001665
1666 ring->flush(dev, ring,
1667 I915_GEM_DOMAIN_COMMAND, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07001668}
1669
1670/**
Eric Anholt673a3942008-07-30 12:06:12 -07001671 * Returns true if seq1 is later than seq2.
1672 */
Ben Gamari22be1722009-09-14 17:48:43 -04001673bool
Eric Anholt673a3942008-07-30 12:06:12 -07001674i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1675{
1676 return (int32_t)(seq1 - seq2) >= 0;
1677}
1678
1679uint32_t
Zou Nan hai852835f2010-05-21 09:08:56 +08001680i915_get_gem_seqno(struct drm_device *dev,
Zou Nan haid1b851f2010-05-21 09:08:57 +08001681 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001682{
Zou Nan hai852835f2010-05-21 09:08:56 +08001683 return ring->get_gem_seqno(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001684}
1685
Chris Wilson9375e442010-09-19 12:21:28 +01001686void i915_gem_reset_flushing_list(struct drm_device *dev)
1687{
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689
1690 while (!list_empty(&dev_priv->mm.flushing_list)) {
1691 struct drm_i915_gem_object *obj_priv;
1692
1693 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1694 struct drm_i915_gem_object,
1695 list);
1696
1697 obj_priv->base.write_domain = 0;
1698 i915_gem_object_move_to_inactive(&obj_priv->base);
1699 }
1700}
1701
Eric Anholt673a3942008-07-30 12:06:12 -07001702/**
1703 * This function clears the request list as sequence numbers are passed.
1704 */
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001705static void
1706i915_gem_retire_requests_ring(struct drm_device *dev,
1707 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001708{
1709 drm_i915_private_t *dev_priv = dev->dev_private;
1710 uint32_t seqno;
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001711 bool wedged;
Eric Anholt673a3942008-07-30 12:06:12 -07001712
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001713 if (!ring->status_page.page_addr ||
1714 list_empty(&ring->request_list))
Karsten Wiese6c0594a2009-02-23 15:07:57 +01001715 return;
1716
Zou Nan hai852835f2010-05-21 09:08:56 +08001717 seqno = i915_get_gem_seqno(dev, ring);
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001718 wedged = atomic_read(&dev_priv->mm.wedged);
Eric Anholt673a3942008-07-30 12:06:12 -07001719
Zou Nan hai852835f2010-05-21 09:08:56 +08001720 while (!list_empty(&ring->request_list)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001721 struct drm_i915_gem_request *request;
Eric Anholt673a3942008-07-30 12:06:12 -07001722
Zou Nan hai852835f2010-05-21 09:08:56 +08001723 request = list_first_entry(&ring->request_list,
Eric Anholt673a3942008-07-30 12:06:12 -07001724 struct drm_i915_gem_request,
1725 list);
Eric Anholt673a3942008-07-30 12:06:12 -07001726
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001727 if (!wedged && !i915_seqno_passed(seqno, request->seqno))
Eric Anholt673a3942008-07-30 12:06:12 -07001728 break;
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001729
1730 trace_i915_gem_request_retire(dev, request->seqno);
1731
1732 list_del(&request->list);
1733 list_del(&request->client_list);
1734 kfree(request);
1735 }
1736
1737 /* Move any buffers on the active list that are no longer referenced
1738 * by the ringbuffer to the flushing/inactive lists as appropriate.
1739 */
1740 while (!list_empty(&ring->active_list)) {
1741 struct drm_gem_object *obj;
1742 struct drm_i915_gem_object *obj_priv;
1743
1744 obj_priv = list_first_entry(&ring->active_list,
1745 struct drm_i915_gem_object,
1746 list);
1747
1748 if (!wedged &&
1749 !i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1750 break;
1751
1752 obj = &obj_priv->base;
1753
1754#if WATCH_LRU
1755 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1756 __func__, request->seqno, obj);
1757#endif
1758
1759 if (obj->write_domain != 0)
1760 i915_gem_object_move_to_flushing(obj);
1761 else
1762 i915_gem_object_move_to_inactive(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001763 }
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001764
1765 if (unlikely (dev_priv->trace_irq_seqno &&
1766 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001767 ring->user_irq_put(dev, ring);
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001768 dev_priv->trace_irq_seqno = 0;
1769 }
Eric Anholt673a3942008-07-30 12:06:12 -07001770}
1771
1772void
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001773i915_gem_retire_requests(struct drm_device *dev)
1774{
1775 drm_i915_private_t *dev_priv = dev->dev_private;
1776
Chris Wilsonbe726152010-07-23 23:18:50 +01001777 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1778 struct drm_i915_gem_object *obj_priv, *tmp;
1779
1780 /* We must be careful that during unbind() we do not
1781 * accidentally infinitely recurse into retire requests.
1782 * Currently:
1783 * retire -> free -> unbind -> wait -> retire_ring
1784 */
1785 list_for_each_entry_safe(obj_priv, tmp,
1786 &dev_priv->mm.deferred_free_list,
1787 list)
1788 i915_gem_free_object_tail(&obj_priv->base);
1789 }
1790
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001791 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1792 if (HAS_BSD(dev))
1793 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1794}
1795
Daniel Vetter75ef9da2010-08-21 00:25:16 +02001796static void
Eric Anholt673a3942008-07-30 12:06:12 -07001797i915_gem_retire_work_handler(struct work_struct *work)
1798{
1799 drm_i915_private_t *dev_priv;
1800 struct drm_device *dev;
1801
1802 dev_priv = container_of(work, drm_i915_private_t,
1803 mm.retire_work.work);
1804 dev = dev_priv->dev;
1805
1806 mutex_lock(&dev->struct_mutex);
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001807 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08001808
Keith Packard6dbe2772008-10-14 21:41:13 -07001809 if (!dev_priv->mm.suspended &&
Zou Nan haid1b851f2010-05-21 09:08:57 +08001810 (!list_empty(&dev_priv->render_ring.request_list) ||
1811 (HAS_BSD(dev) &&
1812 !list_empty(&dev_priv->bsd_ring.request_list))))
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07001813 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
Eric Anholt673a3942008-07-30 12:06:12 -07001814 mutex_unlock(&dev->struct_mutex);
1815}
1816
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001817int
Zou Nan hai852835f2010-05-21 09:08:56 +08001818i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001819 bool interruptible, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001820{
1821 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001822 u32 ier;
Eric Anholt673a3942008-07-30 12:06:12 -07001823 int ret = 0;
1824
1825 BUG_ON(seqno == 0);
1826
Daniel Vettere35a41d2010-02-11 22:13:59 +01001827 if (seqno == dev_priv->next_seqno) {
Chris Wilson8dc5d142010-08-12 12:36:12 +01001828 seqno = i915_add_request(dev, NULL, NULL, ring);
Daniel Vettere35a41d2010-02-11 22:13:59 +01001829 if (seqno == 0)
1830 return -ENOMEM;
1831 }
1832
Ben Gamariba1234d2009-09-14 17:48:47 -04001833 if (atomic_read(&dev_priv->mm.wedged))
Ben Gamariffed1d02009-09-14 17:48:41 -04001834 return -EIO;
1835
Zou Nan hai852835f2010-05-21 09:08:56 +08001836 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001837 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001838 ier = I915_READ(DEIER) | I915_READ(GTIER);
1839 else
1840 ier = I915_READ(IER);
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001841 if (!ier) {
1842 DRM_ERROR("something (likely vbetool) disabled "
1843 "interrupts, re-enabling\n");
1844 i915_driver_irq_preinstall(dev);
1845 i915_driver_irq_postinstall(dev);
1846 }
1847
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001848 trace_i915_gem_request_wait_begin(dev, seqno);
1849
Zou Nan hai852835f2010-05-21 09:08:56 +08001850 ring->waiting_gem_seqno = seqno;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001851 ring->user_irq_get(dev, ring);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001852 if (interruptible)
Zou Nan hai852835f2010-05-21 09:08:56 +08001853 ret = wait_event_interruptible(ring->irq_queue,
1854 i915_seqno_passed(
1855 ring->get_gem_seqno(dev, ring), seqno)
1856 || atomic_read(&dev_priv->mm.wedged));
Daniel Vetter48764bf2009-09-15 22:57:32 +02001857 else
Zou Nan hai852835f2010-05-21 09:08:56 +08001858 wait_event(ring->irq_queue,
1859 i915_seqno_passed(
1860 ring->get_gem_seqno(dev, ring), seqno)
1861 || atomic_read(&dev_priv->mm.wedged));
Daniel Vetter48764bf2009-09-15 22:57:32 +02001862
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001863 ring->user_irq_put(dev, ring);
Zou Nan hai852835f2010-05-21 09:08:56 +08001864 ring->waiting_gem_seqno = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001865
1866 trace_i915_gem_request_wait_end(dev, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001867 }
Ben Gamariba1234d2009-09-14 17:48:47 -04001868 if (atomic_read(&dev_priv->mm.wedged))
Eric Anholt673a3942008-07-30 12:06:12 -07001869 ret = -EIO;
1870
1871 if (ret && ret != -ERESTARTSYS)
Daniel Vetter8bff9172010-02-11 22:19:40 +01001872 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1873 __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1874 dev_priv->next_seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001875
1876 /* Directly dispatch request retiring. While we have the work queue
1877 * to handle this, the waiter on a request often wants an associated
1878 * buffer to have made it to the inactive list, and we would need
1879 * a separate wait queue to handle that.
1880 */
1881 if (ret == 0)
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001882 i915_gem_retire_requests_ring(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001883
1884 return ret;
1885}
1886
Daniel Vetter48764bf2009-09-15 22:57:32 +02001887/**
1888 * Waits for a sequence number to be signaled, and cleans up the
1889 * request and object lists appropriately for that event.
1890 */
1891static int
Zou Nan hai852835f2010-05-21 09:08:56 +08001892i915_wait_request(struct drm_device *dev, uint32_t seqno,
1893 struct intel_ring_buffer *ring)
Daniel Vetter48764bf2009-09-15 22:57:32 +02001894{
Zou Nan hai852835f2010-05-21 09:08:56 +08001895 return i915_do_wait_request(dev, seqno, 1, ring);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001896}
1897
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001898static void
Chris Wilson92204342010-09-18 11:02:01 +01001899i915_gem_flush_ring(struct drm_device *dev,
1900 struct intel_ring_buffer *ring,
1901 uint32_t invalidate_domains,
1902 uint32_t flush_domains)
1903{
1904 ring->flush(dev, ring, invalidate_domains, flush_domains);
1905 i915_gem_process_flushing_list(dev, flush_domains, ring);
1906}
1907
1908static void
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001909i915_gem_flush(struct drm_device *dev,
1910 uint32_t invalidate_domains,
Chris Wilson92204342010-09-18 11:02:01 +01001911 uint32_t flush_domains,
1912 uint32_t flush_rings)
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001913{
1914 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter8bff9172010-02-11 22:19:40 +01001915
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001916 if (flush_domains & I915_GEM_DOMAIN_CPU)
1917 drm_agp_chipset_flush(dev);
Daniel Vetter8bff9172010-02-11 22:19:40 +01001918
Chris Wilson92204342010-09-18 11:02:01 +01001919 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
1920 if (flush_rings & RING_RENDER)
1921 i915_gem_flush_ring(dev,
1922 &dev_priv->render_ring,
1923 invalidate_domains, flush_domains);
1924 if (flush_rings & RING_BSD)
1925 i915_gem_flush_ring(dev,
1926 &dev_priv->bsd_ring,
1927 invalidate_domains, flush_domains);
1928 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001929}
1930
Eric Anholt673a3942008-07-30 12:06:12 -07001931/**
1932 * Ensures that all rendering to the object has completed and the object is
1933 * safe to unbind from the GTT or access from the CPU.
1934 */
1935static int
Chris Wilson2cf34d72010-09-14 13:03:28 +01001936i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1937 bool interruptible)
Eric Anholt673a3942008-07-30 12:06:12 -07001938{
1939 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001940 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001941 int ret;
1942
Eric Anholte47c68e2008-11-14 13:35:19 -08001943 /* This function only exists to support waiting for existing rendering,
1944 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001945 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001946 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001947
1948 /* If there is rendering queued on the buffer being evicted, wait for
1949 * it.
1950 */
1951 if (obj_priv->active) {
1952#if WATCH_BUF
1953 DRM_INFO("%s: object %p wait for seqno %08x\n",
1954 __func__, obj, obj_priv->last_rendering_seqno);
1955#endif
Chris Wilson2cf34d72010-09-14 13:03:28 +01001956 ret = i915_do_wait_request(dev,
1957 obj_priv->last_rendering_seqno,
1958 interruptible,
1959 obj_priv->ring);
1960 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07001961 return ret;
1962 }
1963
1964 return 0;
1965}
1966
1967/**
1968 * Unbinds an object from the GTT aperture.
1969 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001970int
Eric Anholt673a3942008-07-30 12:06:12 -07001971i915_gem_object_unbind(struct drm_gem_object *obj)
1972{
1973 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001974 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001975 int ret = 0;
1976
1977#if WATCH_BUF
1978 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1979 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1980#endif
1981 if (obj_priv->gtt_space == NULL)
1982 return 0;
1983
1984 if (obj_priv->pin_count != 0) {
1985 DRM_ERROR("Attempting to unbind pinned buffer\n");
1986 return -EINVAL;
1987 }
1988
Eric Anholt5323fd02009-09-09 11:50:45 -07001989 /* blow away mappings if mapped through GTT */
1990 i915_gem_release_mmap(obj);
1991
Eric Anholt673a3942008-07-30 12:06:12 -07001992 /* Move the object to the CPU domain to ensure that
1993 * any possible CPU writes while it's not in the GTT
1994 * are flushed when we go to remap it. This will
1995 * also ensure that all pending GPU writes are finished
1996 * before we unbind.
1997 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001998 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Chris Wilson8dc17752010-07-23 23:18:51 +01001999 if (ret == -ERESTARTSYS)
Eric Anholt673a3942008-07-30 12:06:12 -07002000 return ret;
Chris Wilson8dc17752010-07-23 23:18:51 +01002001 /* Continue on if we fail due to EIO, the GPU is hung so we
2002 * should be safe and we need to cleanup or else we might
2003 * cause memory corruption through use-after-free.
2004 */
Eric Anholt673a3942008-07-30 12:06:12 -07002005
Daniel Vetter96b47b62009-12-15 17:50:00 +01002006 /* release the fence reg _after_ flushing */
2007 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2008 i915_gem_clear_fence_reg(obj);
2009
Eric Anholt673a3942008-07-30 12:06:12 -07002010 if (obj_priv->agp_mem != NULL) {
2011 drm_unbind_agp(obj_priv->agp_mem);
2012 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2013 obj_priv->agp_mem = NULL;
2014 }
2015
Eric Anholt856fa192009-03-19 14:10:50 -07002016 i915_gem_object_put_pages(obj);
Chris Wilsona32808c2009-09-20 21:29:47 +01002017 BUG_ON(obj_priv->pages_refcount);
Eric Anholt673a3942008-07-30 12:06:12 -07002018
2019 if (obj_priv->gtt_space) {
2020 atomic_dec(&dev->gtt_count);
2021 atomic_sub(obj->size, &dev->gtt_memory);
2022
2023 drm_mm_put_block(obj_priv->gtt_space);
2024 obj_priv->gtt_space = NULL;
2025 }
2026
2027 /* Remove ourselves from the LRU list if present. */
2028 if (!list_empty(&obj_priv->list))
2029 list_del_init(&obj_priv->list);
2030
Chris Wilson963b4832009-09-20 23:03:54 +01002031 if (i915_gem_object_is_purgeable(obj_priv))
2032 i915_gem_object_truncate(obj);
2033
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002034 trace_i915_gem_object_unbind(obj);
2035
Chris Wilson8dc17752010-07-23 23:18:51 +01002036 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002037}
2038
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002039int
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002040i915_gpu_idle(struct drm_device *dev)
2041{
2042 drm_i915_private_t *dev_priv = dev->dev_private;
2043 bool lists_empty;
Zou Nan hai852835f2010-05-21 09:08:56 +08002044 int ret;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002045
Zou Nan haid1b851f2010-05-21 09:08:57 +08002046 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2047 list_empty(&dev_priv->render_ring.active_list) &&
2048 (!HAS_BSD(dev) ||
2049 list_empty(&dev_priv->bsd_ring.active_list)));
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002050 if (lists_empty)
2051 return 0;
2052
2053 /* Flush everything onto the inactive list. */
Chris Wilson92204342010-09-18 11:02:01 +01002054 i915_gem_flush_ring(dev,
2055 &dev_priv->render_ring,
2056 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Daniel Vetter4fc6ee72010-02-11 22:53:20 +01002057
2058 ret = i915_wait_request(dev,
2059 i915_gem_next_request_seqno(dev, &dev_priv->render_ring),
2060 &dev_priv->render_ring);
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01002061 if (ret)
2062 return ret;
Zou Nan haid1b851f2010-05-21 09:08:57 +08002063
2064 if (HAS_BSD(dev)) {
Chris Wilson92204342010-09-18 11:02:01 +01002065 i915_gem_flush_ring(dev,
2066 &dev_priv->bsd_ring,
2067 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2068
Daniel Vetter4fc6ee72010-02-11 22:53:20 +01002069 ret = i915_wait_request(dev,
2070 i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring),
2071 &dev_priv->bsd_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002072 if (ret)
2073 return ret;
2074 }
2075
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01002076 return 0;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002077}
2078
Ben Gamari6911a9b2009-04-02 11:24:54 -07002079int
Chris Wilson4bdadb92010-01-27 13:36:32 +00002080i915_gem_object_get_pages(struct drm_gem_object *obj,
2081 gfp_t gfpmask)
Eric Anholt673a3942008-07-30 12:06:12 -07002082{
Daniel Vetter23010e42010-03-08 13:35:02 +01002083 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002084 int page_count, i;
2085 struct address_space *mapping;
2086 struct inode *inode;
2087 struct page *page;
Eric Anholt673a3942008-07-30 12:06:12 -07002088
Daniel Vetter778c3542010-05-13 11:49:44 +02002089 BUG_ON(obj_priv->pages_refcount
2090 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2091
Eric Anholt856fa192009-03-19 14:10:50 -07002092 if (obj_priv->pages_refcount++ != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002093 return 0;
2094
2095 /* Get the list of pages out of our struct file. They'll be pinned
2096 * at this point until we release them.
2097 */
2098 page_count = obj->size / PAGE_SIZE;
Eric Anholt856fa192009-03-19 14:10:50 -07002099 BUG_ON(obj_priv->pages != NULL);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07002100 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
Eric Anholt856fa192009-03-19 14:10:50 -07002101 if (obj_priv->pages == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002102 obj_priv->pages_refcount--;
Eric Anholt673a3942008-07-30 12:06:12 -07002103 return -ENOMEM;
2104 }
2105
2106 inode = obj->filp->f_path.dentry->d_inode;
2107 mapping = inode->i_mapping;
2108 for (i = 0; i < page_count; i++) {
Chris Wilson4bdadb92010-01-27 13:36:32 +00002109 page = read_cache_page_gfp(mapping, i,
Linus Torvalds985b8232010-07-02 10:04:42 +10002110 GFP_HIGHUSER |
Chris Wilson4bdadb92010-01-27 13:36:32 +00002111 __GFP_COLD |
Linus Torvaldscd9f0402010-07-18 09:44:37 -07002112 __GFP_RECLAIMABLE |
Chris Wilson4bdadb92010-01-27 13:36:32 +00002113 gfpmask);
Chris Wilson1f2b1012010-03-12 19:52:55 +00002114 if (IS_ERR(page))
2115 goto err_pages;
2116
Eric Anholt856fa192009-03-19 14:10:50 -07002117 obj_priv->pages[i] = page;
Eric Anholt673a3942008-07-30 12:06:12 -07002118 }
Eric Anholt280b7132009-03-12 16:56:27 -07002119
2120 if (obj_priv->tiling_mode != I915_TILING_NONE)
2121 i915_gem_object_do_bit_17_swizzle(obj);
2122
Eric Anholt673a3942008-07-30 12:06:12 -07002123 return 0;
Chris Wilson1f2b1012010-03-12 19:52:55 +00002124
2125err_pages:
2126 while (i--)
2127 page_cache_release(obj_priv->pages[i]);
2128
2129 drm_free_large(obj_priv->pages);
2130 obj_priv->pages = NULL;
2131 obj_priv->pages_refcount--;
2132 return PTR_ERR(page);
Eric Anholt673a3942008-07-30 12:06:12 -07002133}
2134
Eric Anholt4e901fd2009-10-26 16:44:17 -07002135static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2136{
2137 struct drm_gem_object *obj = reg->obj;
2138 struct drm_device *dev = obj->dev;
2139 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002140 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt4e901fd2009-10-26 16:44:17 -07002141 int regnum = obj_priv->fence_reg;
2142 uint64_t val;
2143
2144 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2145 0xfffff000) << 32;
2146 val |= obj_priv->gtt_offset & 0xfffff000;
2147 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2148 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2149
2150 if (obj_priv->tiling_mode == I915_TILING_Y)
2151 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2152 val |= I965_FENCE_REG_VALID;
2153
2154 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2155}
2156
Jesse Barnesde151cf2008-11-12 10:03:55 -08002157static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2158{
2159 struct drm_gem_object *obj = reg->obj;
2160 struct drm_device *dev = obj->dev;
2161 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002162 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002163 int regnum = obj_priv->fence_reg;
2164 uint64_t val;
2165
2166 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2167 0xfffff000) << 32;
2168 val |= obj_priv->gtt_offset & 0xfffff000;
2169 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2170 if (obj_priv->tiling_mode == I915_TILING_Y)
2171 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2172 val |= I965_FENCE_REG_VALID;
2173
2174 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2175}
2176
2177static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2178{
2179 struct drm_gem_object *obj = reg->obj;
2180 struct drm_device *dev = obj->dev;
2181 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002182 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002183 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08002184 int tile_width;
Eric Anholtdc529a42009-03-10 22:34:49 -07002185 uint32_t fence_reg, val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002186 uint32_t pitch_val;
2187
2188 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2189 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08002190 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002191 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002192 return;
2193 }
2194
Jesse Barnes0f973f22009-01-26 17:10:45 -08002195 if (obj_priv->tiling_mode == I915_TILING_Y &&
2196 HAS_128_BYTE_Y_TILING(dev))
2197 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002198 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08002199 tile_width = 512;
2200
2201 /* Note: pitch better be a power of two tile widths */
2202 pitch_val = obj_priv->stride / tile_width;
2203 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002204
Daniel Vetterc36a2a62010-04-17 15:12:03 +02002205 if (obj_priv->tiling_mode == I915_TILING_Y &&
2206 HAS_128_BYTE_Y_TILING(dev))
2207 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2208 else
2209 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2210
Jesse Barnesde151cf2008-11-12 10:03:55 -08002211 val = obj_priv->gtt_offset;
2212 if (obj_priv->tiling_mode == I915_TILING_Y)
2213 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2214 val |= I915_FENCE_SIZE_BITS(obj->size);
2215 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2216 val |= I830_FENCE_REG_VALID;
2217
Eric Anholtdc529a42009-03-10 22:34:49 -07002218 if (regnum < 8)
2219 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2220 else
2221 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2222 I915_WRITE(fence_reg, val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002223}
2224
2225static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2226{
2227 struct drm_gem_object *obj = reg->obj;
2228 struct drm_device *dev = obj->dev;
2229 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002231 int regnum = obj_priv->fence_reg;
2232 uint32_t val;
2233 uint32_t pitch_val;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002234 uint32_t fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002235
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002236 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
Jesse Barnesde151cf2008-11-12 10:03:55 -08002237 (obj_priv->gtt_offset & (obj->size - 1))) {
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002238 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002239 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002240 return;
2241 }
2242
Eric Anholte76a16d2009-05-26 17:44:56 -07002243 pitch_val = obj_priv->stride / 128;
2244 pitch_val = ffs(pitch_val) - 1;
2245 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2246
Jesse Barnesde151cf2008-11-12 10:03:55 -08002247 val = obj_priv->gtt_offset;
2248 if (obj_priv->tiling_mode == I915_TILING_Y)
2249 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002250 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2251 WARN_ON(fence_size_bits & ~0x00000f00);
2252 val |= fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002253 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2254 val |= I830_FENCE_REG_VALID;
2255
2256 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002257}
2258
Chris Wilson2cf34d72010-09-14 13:03:28 +01002259static int i915_find_fence_reg(struct drm_device *dev,
2260 bool interruptible)
Daniel Vetterae3db242010-02-19 11:51:58 +01002261{
2262 struct drm_i915_fence_reg *reg = NULL;
2263 struct drm_i915_gem_object *obj_priv = NULL;
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct drm_gem_object *obj = NULL;
2266 int i, avail, ret;
2267
2268 /* First try to find a free reg */
2269 avail = 0;
2270 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2271 reg = &dev_priv->fence_regs[i];
2272 if (!reg->obj)
2273 return i;
2274
Daniel Vetter23010e42010-03-08 13:35:02 +01002275 obj_priv = to_intel_bo(reg->obj);
Daniel Vetterae3db242010-02-19 11:51:58 +01002276 if (!obj_priv->pin_count)
2277 avail++;
2278 }
2279
2280 if (avail == 0)
2281 return -ENOSPC;
2282
2283 /* None available, try to steal one or wait for a user to finish */
2284 i = I915_FENCE_REG_NONE;
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002285 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2286 lru_list) {
2287 obj = reg->obj;
2288 obj_priv = to_intel_bo(obj);
Daniel Vetterae3db242010-02-19 11:51:58 +01002289
2290 if (obj_priv->pin_count)
2291 continue;
2292
2293 /* found one! */
2294 i = obj_priv->fence_reg;
2295 break;
2296 }
2297
2298 BUG_ON(i == I915_FENCE_REG_NONE);
2299
2300 /* We only have a reference on obj from the active list. put_fence_reg
2301 * might drop that one, causing a use-after-free in it. So hold a
2302 * private reference to obj like the other callers of put_fence_reg
2303 * (set_tiling ioctl) do. */
2304 drm_gem_object_reference(obj);
Chris Wilson2cf34d72010-09-14 13:03:28 +01002305 ret = i915_gem_object_put_fence_reg(obj, interruptible);
Daniel Vetterae3db242010-02-19 11:51:58 +01002306 drm_gem_object_unreference(obj);
2307 if (ret != 0)
2308 return ret;
2309
2310 return i;
2311}
2312
Jesse Barnesde151cf2008-11-12 10:03:55 -08002313/**
2314 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2315 * @obj: object to map through a fence reg
2316 *
2317 * When mapping objects through the GTT, userspace wants to be able to write
2318 * to them without having to worry about swizzling if the object is tiled.
2319 *
2320 * This function walks the fence regs looking for a free one for @obj,
2321 * stealing one if it can't find any.
2322 *
2323 * It then sets up the reg based on the object's properties: address, pitch
2324 * and tiling format.
2325 */
Chris Wilson8c4b8c32009-06-17 22:08:52 +01002326int
Chris Wilson2cf34d72010-09-14 13:03:28 +01002327i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2328 bool interruptible)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002329{
2330 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002331 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002332 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002333 struct drm_i915_fence_reg *reg = NULL;
Daniel Vetterae3db242010-02-19 11:51:58 +01002334 int ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002335
Eric Anholta09ba7f2009-08-29 12:49:51 -07002336 /* Just update our place in the LRU if our fence is getting used. */
2337 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002338 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2339 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07002340 return 0;
2341 }
2342
Jesse Barnesde151cf2008-11-12 10:03:55 -08002343 switch (obj_priv->tiling_mode) {
2344 case I915_TILING_NONE:
2345 WARN(1, "allocating a fence for non-tiled object?\n");
2346 break;
2347 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002348 if (!obj_priv->stride)
2349 return -EINVAL;
2350 WARN((obj_priv->stride & (512 - 1)),
2351 "object 0x%08x is X tiled but has non-512B pitch\n",
2352 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002353 break;
2354 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002355 if (!obj_priv->stride)
2356 return -EINVAL;
2357 WARN((obj_priv->stride & (128 - 1)),
2358 "object 0x%08x is Y tiled but has non-128B pitch\n",
2359 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002360 break;
2361 }
2362
Chris Wilson2cf34d72010-09-14 13:03:28 +01002363 ret = i915_find_fence_reg(dev, interruptible);
Daniel Vetterae3db242010-02-19 11:51:58 +01002364 if (ret < 0)
2365 return ret;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002366
Daniel Vetterae3db242010-02-19 11:51:58 +01002367 obj_priv->fence_reg = ret;
2368 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002369 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07002370
Jesse Barnesde151cf2008-11-12 10:03:55 -08002371 reg->obj = obj;
2372
Chris Wilsone259bef2010-09-17 00:32:02 +01002373 switch (INTEL_INFO(dev)->gen) {
2374 case 6:
Eric Anholt4e901fd2009-10-26 16:44:17 -07002375 sandybridge_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002376 break;
2377 case 5:
2378 case 4:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002379 i965_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002380 break;
2381 case 3:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002382 i915_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002383 break;
2384 case 2:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002385 i830_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002386 break;
2387 }
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002388
Daniel Vetterae3db242010-02-19 11:51:58 +01002389 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2390 obj_priv->tiling_mode);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002391
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002392 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002393}
2394
2395/**
2396 * i915_gem_clear_fence_reg - clear out fence register info
2397 * @obj: object to clear
2398 *
2399 * Zeroes out the fence register itself and clears out the associated
2400 * data structures in dev_priv and obj_priv.
2401 */
2402static void
2403i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2404{
2405 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002406 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002407 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002408 struct drm_i915_fence_reg *reg =
2409 &dev_priv->fence_regs[obj_priv->fence_reg];
Chris Wilsone259bef2010-09-17 00:32:02 +01002410 uint32_t fence_reg;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002411
Chris Wilsone259bef2010-09-17 00:32:02 +01002412 switch (INTEL_INFO(dev)->gen) {
2413 case 6:
Eric Anholt4e901fd2009-10-26 16:44:17 -07002414 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2415 (obj_priv->fence_reg * 8), 0);
Chris Wilsone259bef2010-09-17 00:32:02 +01002416 break;
2417 case 5:
2418 case 4:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002419 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
Chris Wilsone259bef2010-09-17 00:32:02 +01002420 break;
2421 case 3:
2422 if (obj_priv->fence_reg > 8)
2423 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
Eric Anholtdc529a42009-03-10 22:34:49 -07002424 else
Chris Wilsone259bef2010-09-17 00:32:02 +01002425 case 2:
2426 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
Eric Anholtdc529a42009-03-10 22:34:49 -07002427
2428 I915_WRITE(fence_reg, 0);
Chris Wilsone259bef2010-09-17 00:32:02 +01002429 break;
Eric Anholtdc529a42009-03-10 22:34:49 -07002430 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08002431
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002432 reg->obj = NULL;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002433 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002434 list_del_init(&reg->lru_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002435}
2436
Eric Anholt673a3942008-07-30 12:06:12 -07002437/**
Chris Wilson52dc7d32009-06-06 09:46:01 +01002438 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2439 * to the buffer to finish, and then resets the fence register.
2440 * @obj: tiled object holding a fence register.
Chris Wilson2cf34d72010-09-14 13:03:28 +01002441 * @bool: whether the wait upon the fence is interruptible
Chris Wilson52dc7d32009-06-06 09:46:01 +01002442 *
2443 * Zeroes out the fence register itself and clears out the associated
2444 * data structures in dev_priv and obj_priv.
2445 */
2446int
Chris Wilson2cf34d72010-09-14 13:03:28 +01002447i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2448 bool interruptible)
Chris Wilson52dc7d32009-06-06 09:46:01 +01002449{
2450 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01002451 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +01002452
2453 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2454 return 0;
2455
Daniel Vetter10ae9bd2010-02-01 13:59:17 +01002456 /* If we've changed tiling, GTT-mappings of the object
2457 * need to re-fault to ensure that the correct fence register
2458 * setup is in place.
2459 */
2460 i915_gem_release_mmap(obj);
2461
Chris Wilson52dc7d32009-06-06 09:46:01 +01002462 /* On the i915, GPU access to tiled buffers is via a fence,
2463 * therefore we must wait for any outstanding access to complete
2464 * before clearing the fence.
2465 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002466 if (INTEL_INFO(dev)->gen < 4) {
Chris Wilson52dc7d32009-06-06 09:46:01 +01002467 int ret;
2468
Chris Wilson2cf34d72010-09-14 13:03:28 +01002469 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
Chris Wilson0bc23aa2010-09-14 10:22:23 +01002470 if (ret)
2471 return ret;
2472
Chris Wilson2cf34d72010-09-14 13:03:28 +01002473 ret = i915_gem_object_wait_rendering(obj, interruptible);
Chris Wilson0bc23aa2010-09-14 10:22:23 +01002474 if (ret)
Chris Wilson52dc7d32009-06-06 09:46:01 +01002475 return ret;
2476 }
2477
Daniel Vetter4a726612010-02-01 13:59:16 +01002478 i915_gem_object_flush_gtt_write_domain(obj);
Chris Wilson0bc23aa2010-09-14 10:22:23 +01002479 i915_gem_clear_fence_reg(obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +01002480
2481 return 0;
2482}
2483
2484/**
Eric Anholt673a3942008-07-30 12:06:12 -07002485 * Finds free space in the GTT aperture and binds the object there.
2486 */
2487static int
2488i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2489{
2490 struct drm_device *dev = obj->dev;
2491 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002492 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002493 struct drm_mm_node *free_space;
Chris Wilson4bdadb92010-01-27 13:36:32 +00002494 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
Chris Wilson07f73f62009-09-14 16:50:30 +01002495 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002496
Chris Wilsonbb6baf72009-09-22 14:24:13 +01002497 if (obj_priv->madv != I915_MADV_WILLNEED) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01002498 DRM_ERROR("Attempting to bind a purgeable object\n");
2499 return -EINVAL;
2500 }
2501
Eric Anholt673a3942008-07-30 12:06:12 -07002502 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08002503 alignment = i915_gem_get_gtt_alignment(obj);
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002504 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002505 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2506 return -EINVAL;
2507 }
2508
Chris Wilson654fc602010-05-27 13:18:21 +01002509 /* If the object is bigger than the entire aperture, reject it early
2510 * before evicting everything in a vain attempt to find space.
2511 */
2512 if (obj->size > dev->gtt_total) {
2513 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2514 return -E2BIG;
2515 }
2516
Eric Anholt673a3942008-07-30 12:06:12 -07002517 search_free:
2518 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2519 obj->size, alignment, 0);
2520 if (free_space != NULL) {
2521 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2522 alignment);
Daniel Vetterdb3307a2010-07-02 15:02:12 +01002523 if (obj_priv->gtt_space != NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002524 obj_priv->gtt_offset = obj_priv->gtt_space->start;
Eric Anholt673a3942008-07-30 12:06:12 -07002525 }
2526 if (obj_priv->gtt_space == NULL) {
2527 /* If the gtt is empty and we're still having trouble
2528 * fitting our object in, we're out of memory.
2529 */
2530#if WATCH_LRU
2531 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2532#endif
Daniel Vetter0108a3e2010-08-07 11:01:21 +01002533 ret = i915_gem_evict_something(dev, obj->size, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01002534 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07002535 return ret;
Chris Wilson97311292009-09-21 00:22:34 +01002536
Eric Anholt673a3942008-07-30 12:06:12 -07002537 goto search_free;
2538 }
2539
2540#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02002541 DRM_INFO("Binding object of size %zd at 0x%08x\n",
Eric Anholt673a3942008-07-30 12:06:12 -07002542 obj->size, obj_priv->gtt_offset);
2543#endif
Chris Wilson4bdadb92010-01-27 13:36:32 +00002544 ret = i915_gem_object_get_pages(obj, gfpmask);
Eric Anholt673a3942008-07-30 12:06:12 -07002545 if (ret) {
2546 drm_mm_put_block(obj_priv->gtt_space);
2547 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002548
2549 if (ret == -ENOMEM) {
2550 /* first try to clear up some space from the GTT */
Daniel Vetter0108a3e2010-08-07 11:01:21 +01002551 ret = i915_gem_evict_something(dev, obj->size,
2552 alignment);
Chris Wilson07f73f62009-09-14 16:50:30 +01002553 if (ret) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002554 /* now try to shrink everyone else */
Chris Wilson4bdadb92010-01-27 13:36:32 +00002555 if (gfpmask) {
2556 gfpmask = 0;
2557 goto search_free;
Chris Wilson07f73f62009-09-14 16:50:30 +01002558 }
2559
2560 return ret;
2561 }
2562
2563 goto search_free;
2564 }
2565
Eric Anholt673a3942008-07-30 12:06:12 -07002566 return ret;
2567 }
2568
Eric Anholt673a3942008-07-30 12:06:12 -07002569 /* Create an AGP memory structure pointing at our pages, and bind it
2570 * into the GTT.
2571 */
2572 obj_priv->agp_mem = drm_agp_bind_pages(dev,
Eric Anholt856fa192009-03-19 14:10:50 -07002573 obj_priv->pages,
Chris Wilson07f73f62009-09-14 16:50:30 +01002574 obj->size >> PAGE_SHIFT,
Keith Packardba1eb1d2008-10-14 19:55:10 -07002575 obj_priv->gtt_offset,
2576 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07002577 if (obj_priv->agp_mem == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002578 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002579 drm_mm_put_block(obj_priv->gtt_space);
2580 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002581
Daniel Vetter0108a3e2010-08-07 11:01:21 +01002582 ret = i915_gem_evict_something(dev, obj->size, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01002583 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002584 return ret;
Chris Wilson07f73f62009-09-14 16:50:30 +01002585
2586 goto search_free;
Eric Anholt673a3942008-07-30 12:06:12 -07002587 }
2588 atomic_inc(&dev->gtt_count);
2589 atomic_add(obj->size, &dev->gtt_memory);
2590
Chris Wilsonbf1a1092010-08-07 11:01:20 +01002591 /* keep track of bounds object by adding it to the inactive list */
2592 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2593
Eric Anholt673a3942008-07-30 12:06:12 -07002594 /* Assert that the object is not currently in any GPU domain. As it
2595 * wasn't in the GTT, there shouldn't be any way it could have been in
2596 * a GPU cache
2597 */
Chris Wilson21d509e2009-06-06 09:46:02 +01002598 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2599 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
Eric Anholt673a3942008-07-30 12:06:12 -07002600
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002601 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2602
Eric Anholt673a3942008-07-30 12:06:12 -07002603 return 0;
2604}
2605
2606void
2607i915_gem_clflush_object(struct drm_gem_object *obj)
2608{
Daniel Vetter23010e42010-03-08 13:35:02 +01002609 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002610
2611 /* If we don't have a page list set up, then we're not pinned
2612 * to GPU, and we can ignore the cache flush because it'll happen
2613 * again at bind time.
2614 */
Eric Anholt856fa192009-03-19 14:10:50 -07002615 if (obj_priv->pages == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002616 return;
2617
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002618 trace_i915_gem_object_clflush(obj);
Eric Anholtcfa16a02009-05-26 18:46:16 -07002619
Eric Anholt856fa192009-03-19 14:10:50 -07002620 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002621}
2622
Eric Anholte47c68e2008-11-14 13:35:19 -08002623/** Flushes any GPU write domain for the object if it's dirty. */
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002624static int
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002625i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2626 bool pipelined)
Eric Anholte47c68e2008-11-14 13:35:19 -08002627{
2628 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002629 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002630
2631 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002632 return 0;
Eric Anholte47c68e2008-11-14 13:35:19 -08002633
2634 /* Queue the GPU write cache flushing we need. */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002635 old_write_domain = obj->write_domain;
Chris Wilson92204342010-09-18 11:02:01 +01002636 i915_gem_flush_ring(dev,
2637 to_intel_bo(obj)->ring,
2638 0, obj->write_domain);
Chris Wilson48b956c2010-09-14 12:50:34 +01002639 BUG_ON(obj->write_domain);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002640
2641 trace_i915_gem_object_change_domain(obj,
2642 obj->read_domains,
2643 old_write_domain);
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002644
2645 if (pipelined)
2646 return 0;
2647
Chris Wilson2cf34d72010-09-14 13:03:28 +01002648 return i915_gem_object_wait_rendering(obj, true);
Eric Anholte47c68e2008-11-14 13:35:19 -08002649}
2650
2651/** Flushes the GTT write domain for the object if it's dirty. */
2652static void
2653i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2654{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002655 uint32_t old_write_domain;
2656
Eric Anholte47c68e2008-11-14 13:35:19 -08002657 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2658 return;
2659
2660 /* No actual flushing is required for the GTT write domain. Writes
2661 * to it immediately go to main memory as far as we know, so there's
2662 * no chipset flush. It also doesn't land in render cache.
2663 */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002664 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002665 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002666
2667 trace_i915_gem_object_change_domain(obj,
2668 obj->read_domains,
2669 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002670}
2671
2672/** Flushes the CPU write domain for the object if it's dirty. */
2673static void
2674i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2675{
2676 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002677 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002678
2679 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2680 return;
2681
2682 i915_gem_clflush_object(obj);
2683 drm_agp_chipset_flush(dev);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002684 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002685 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002686
2687 trace_i915_gem_object_change_domain(obj,
2688 obj->read_domains,
2689 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002690}
2691
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002692/**
2693 * Moves a single object to the GTT read, and possibly write domain.
2694 *
2695 * This function returns when the move is complete, including waiting on
2696 * flushes to occur.
2697 */
Jesse Barnes79e53942008-11-07 14:24:08 -08002698int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002699i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2700{
Daniel Vetter23010e42010-03-08 13:35:02 +01002701 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002702 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002703 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002704
Eric Anholt02354392008-11-26 13:58:13 -08002705 /* Not valid to be called on unbound objects. */
2706 if (obj_priv->gtt_space == NULL)
2707 return -EINVAL;
2708
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002709 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08002710 if (ret != 0)
2711 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002712
Chris Wilson72133422010-09-13 23:56:38 +01002713 i915_gem_object_flush_cpu_write_domain(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002714
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002715 if (write) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01002716 ret = i915_gem_object_wait_rendering(obj, true);
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002717 if (ret)
2718 return ret;
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002719 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002720
Chris Wilson72133422010-09-13 23:56:38 +01002721 old_write_domain = obj->write_domain;
2722 old_read_domains = obj->read_domains;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002723
2724 /* It should now be out of any other write domains, and we can update
2725 * the domain values for our changes.
2726 */
2727 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2728 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002729 if (write) {
Chris Wilson72133422010-09-13 23:56:38 +01002730 obj->read_domains = I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002731 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002732 obj_priv->dirty = 1;
2733 }
2734
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002735 trace_i915_gem_object_change_domain(obj,
2736 old_read_domains,
2737 old_write_domain);
2738
Eric Anholte47c68e2008-11-14 13:35:19 -08002739 return 0;
2740}
2741
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002742/*
2743 * Prepare buffer for display plane. Use uninterruptible for possible flush
2744 * wait, as in modesetting process we're not supposed to be interrupted.
2745 */
2746int
Chris Wilson48b956c2010-09-14 12:50:34 +01002747i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2748 bool pipelined)
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002749{
Daniel Vetter23010e42010-03-08 13:35:02 +01002750 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002751 uint32_t old_read_domains;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002752 int ret;
2753
2754 /* Not valid to be called on unbound objects. */
2755 if (obj_priv->gtt_space == NULL)
2756 return -EINVAL;
2757
Chris Wilson48b956c2010-09-14 12:50:34 +01002758 ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
2759 if (ret)
Daniel Vettere35a41d2010-02-11 22:13:59 +01002760 return ret;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002761
Chris Wilsonb118c1e2010-05-27 13:18:14 +01002762 i915_gem_object_flush_cpu_write_domain(obj);
2763
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002764 old_read_domains = obj->read_domains;
Chris Wilsonb118c1e2010-05-27 13:18:14 +01002765 obj->read_domains = I915_GEM_DOMAIN_GTT;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002766
2767 trace_i915_gem_object_change_domain(obj,
2768 old_read_domains,
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002769 obj->write_domain);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002770
2771 return 0;
2772}
2773
Eric Anholte47c68e2008-11-14 13:35:19 -08002774/**
2775 * Moves a single object to the CPU read, and possibly write domain.
2776 *
2777 * This function returns when the move is complete, including waiting on
2778 * flushes to occur.
2779 */
2780static int
2781i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2782{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002783 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002784 int ret;
2785
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002786 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08002787 if (ret != 0)
2788 return ret;
2789
2790 i915_gem_object_flush_gtt_write_domain(obj);
2791
2792 /* If we have a partially-valid cache of the object in the CPU,
2793 * finish invalidating it and free the per-page flags.
2794 */
2795 i915_gem_object_set_to_full_cpu_read_domain(obj);
2796
Chris Wilson72133422010-09-13 23:56:38 +01002797 if (write) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01002798 ret = i915_gem_object_wait_rendering(obj, true);
Chris Wilson72133422010-09-13 23:56:38 +01002799 if (ret)
2800 return ret;
2801 }
2802
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002803 old_write_domain = obj->write_domain;
2804 old_read_domains = obj->read_domains;
2805
Eric Anholte47c68e2008-11-14 13:35:19 -08002806 /* Flush the CPU cache if it's still invalid. */
2807 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2808 i915_gem_clflush_object(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002809
2810 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2811 }
2812
2813 /* It should now be out of any other write domains, and we can update
2814 * the domain values for our changes.
2815 */
2816 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2817
2818 /* If we're writing through the CPU, then the GPU read domains will
2819 * need to be invalidated at next use.
2820 */
2821 if (write) {
2822 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2823 obj->write_domain = I915_GEM_DOMAIN_CPU;
2824 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002825
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002826 trace_i915_gem_object_change_domain(obj,
2827 old_read_domains,
2828 old_write_domain);
2829
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002830 return 0;
2831}
2832
Eric Anholt673a3942008-07-30 12:06:12 -07002833/*
2834 * Set the next domain for the specified object. This
2835 * may not actually perform the necessary flushing/invaliding though,
2836 * as that may want to be batched with other set_domain operations
2837 *
2838 * This is (we hope) the only really tricky part of gem. The goal
2839 * is fairly simple -- track which caches hold bits of the object
2840 * and make sure they remain coherent. A few concrete examples may
2841 * help to explain how it works. For shorthand, we use the notation
2842 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2843 * a pair of read and write domain masks.
2844 *
2845 * Case 1: the batch buffer
2846 *
2847 * 1. Allocated
2848 * 2. Written by CPU
2849 * 3. Mapped to GTT
2850 * 4. Read by GPU
2851 * 5. Unmapped from GTT
2852 * 6. Freed
2853 *
2854 * Let's take these a step at a time
2855 *
2856 * 1. Allocated
2857 * Pages allocated from the kernel may still have
2858 * cache contents, so we set them to (CPU, CPU) always.
2859 * 2. Written by CPU (using pwrite)
2860 * The pwrite function calls set_domain (CPU, CPU) and
2861 * this function does nothing (as nothing changes)
2862 * 3. Mapped by GTT
2863 * This function asserts that the object is not
2864 * currently in any GPU-based read or write domains
2865 * 4. Read by GPU
2866 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2867 * As write_domain is zero, this function adds in the
2868 * current read domains (CPU+COMMAND, 0).
2869 * flush_domains is set to CPU.
2870 * invalidate_domains is set to COMMAND
2871 * clflush is run to get data out of the CPU caches
2872 * then i915_dev_set_domain calls i915_gem_flush to
2873 * emit an MI_FLUSH and drm_agp_chipset_flush
2874 * 5. Unmapped from GTT
2875 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2876 * flush_domains and invalidate_domains end up both zero
2877 * so no flushing/invalidating happens
2878 * 6. Freed
2879 * yay, done
2880 *
2881 * Case 2: The shared render buffer
2882 *
2883 * 1. Allocated
2884 * 2. Mapped to GTT
2885 * 3. Read/written by GPU
2886 * 4. set_domain to (CPU,CPU)
2887 * 5. Read/written by CPU
2888 * 6. Read/written by GPU
2889 *
2890 * 1. Allocated
2891 * Same as last example, (CPU, CPU)
2892 * 2. Mapped to GTT
2893 * Nothing changes (assertions find that it is not in the GPU)
2894 * 3. Read/written by GPU
2895 * execbuffer calls set_domain (RENDER, RENDER)
2896 * flush_domains gets CPU
2897 * invalidate_domains gets GPU
2898 * clflush (obj)
2899 * MI_FLUSH and drm_agp_chipset_flush
2900 * 4. set_domain (CPU, CPU)
2901 * flush_domains gets GPU
2902 * invalidate_domains gets CPU
2903 * wait_rendering (obj) to make sure all drawing is complete.
2904 * This will include an MI_FLUSH to get the data from GPU
2905 * to memory
2906 * clflush (obj) to invalidate the CPU cache
2907 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2908 * 5. Read/written by CPU
2909 * cache lines are loaded and dirtied
2910 * 6. Read written by GPU
2911 * Same as last GPU access
2912 *
2913 * Case 3: The constant buffer
2914 *
2915 * 1. Allocated
2916 * 2. Written by CPU
2917 * 3. Read by GPU
2918 * 4. Updated (written) by CPU again
2919 * 5. Read by GPU
2920 *
2921 * 1. Allocated
2922 * (CPU, CPU)
2923 * 2. Written by CPU
2924 * (CPU, CPU)
2925 * 3. Read by GPU
2926 * (CPU+RENDER, 0)
2927 * flush_domains = CPU
2928 * invalidate_domains = RENDER
2929 * clflush (obj)
2930 * MI_FLUSH
2931 * drm_agp_chipset_flush
2932 * 4. Updated (written) by CPU again
2933 * (CPU, CPU)
2934 * flush_domains = 0 (no previous write domain)
2935 * invalidate_domains = 0 (no new read domains)
2936 * 5. Read by GPU
2937 * (CPU+RENDER, 0)
2938 * flush_domains = CPU
2939 * invalidate_domains = RENDER
2940 * clflush (obj)
2941 * MI_FLUSH
2942 * drm_agp_chipset_flush
2943 */
Keith Packardc0d90822008-11-20 23:11:08 -08002944static void
Eric Anholt8b0e3782009-02-19 14:40:50 -08002945i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002946{
2947 struct drm_device *dev = obj->dev;
Chris Wilson92204342010-09-18 11:02:01 +01002948 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002949 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002950 uint32_t invalidate_domains = 0;
2951 uint32_t flush_domains = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002952 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002953
Eric Anholt8b0e3782009-02-19 14:40:50 -08002954 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2955 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07002956
Jesse Barnes652c3932009-08-17 13:31:43 -07002957 intel_mark_busy(dev, obj);
2958
Eric Anholt673a3942008-07-30 12:06:12 -07002959#if WATCH_BUF
2960 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2961 __func__, obj,
Eric Anholt8b0e3782009-02-19 14:40:50 -08002962 obj->read_domains, obj->pending_read_domains,
2963 obj->write_domain, obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07002964#endif
2965 /*
2966 * If the object isn't moving to a new write domain,
2967 * let the object stay in multiple read domains
2968 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002969 if (obj->pending_write_domain == 0)
2970 obj->pending_read_domains |= obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07002971 else
2972 obj_priv->dirty = 1;
2973
2974 /*
2975 * Flush the current write domain if
2976 * the new read domains don't match. Invalidate
2977 * any read domains which differ from the old
2978 * write domain
2979 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002980 if (obj->write_domain &&
2981 obj->write_domain != obj->pending_read_domains) {
Eric Anholt673a3942008-07-30 12:06:12 -07002982 flush_domains |= obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08002983 invalidate_domains |=
2984 obj->pending_read_domains & ~obj->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07002985 }
2986 /*
2987 * Invalidate any read caches which may have
2988 * stale data. That is, any new read domains.
2989 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002990 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07002991 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2992#if WATCH_BUF
2993 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2994 __func__, flush_domains, invalidate_domains);
2995#endif
Eric Anholt673a3942008-07-30 12:06:12 -07002996 i915_gem_clflush_object(obj);
2997 }
2998
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002999 old_read_domains = obj->read_domains;
3000
Eric Anholtefbeed92009-02-19 14:54:51 -08003001 /* The actual obj->write_domain will be updated with
3002 * pending_write_domain after we emit the accumulated flush for all
3003 * of our domain changes in execbuffers (which clears objects'
3004 * write_domains). So if we have a current write domain that we
3005 * aren't changing, set pending_write_domain to that.
3006 */
3007 if (flush_domains == 0 && obj->pending_write_domain == 0)
3008 obj->pending_write_domain = obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003009 obj->read_domains = obj->pending_read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003010
3011 dev->invalidate_domains |= invalidate_domains;
3012 dev->flush_domains |= flush_domains;
Chris Wilson92204342010-09-18 11:02:01 +01003013 if (obj_priv->ring)
3014 dev_priv->mm.flush_rings |= obj_priv->ring->id;
Eric Anholt673a3942008-07-30 12:06:12 -07003015#if WATCH_BUF
3016 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3017 __func__,
3018 obj->read_domains, obj->write_domain,
3019 dev->invalidate_domains, dev->flush_domains);
3020#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003021
3022 trace_i915_gem_object_change_domain(obj,
3023 old_read_domains,
3024 obj->write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003025}
3026
3027/**
Eric Anholte47c68e2008-11-14 13:35:19 -08003028 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07003029 *
Eric Anholte47c68e2008-11-14 13:35:19 -08003030 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3031 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3032 */
3033static void
3034i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3035{
Daniel Vetter23010e42010-03-08 13:35:02 +01003036 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003037
3038 if (!obj_priv->page_cpu_valid)
3039 return;
3040
3041 /* If we're partially in the CPU read domain, finish moving it in.
3042 */
3043 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3044 int i;
3045
3046 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3047 if (obj_priv->page_cpu_valid[i])
3048 continue;
Eric Anholt856fa192009-03-19 14:10:50 -07003049 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholte47c68e2008-11-14 13:35:19 -08003050 }
Eric Anholte47c68e2008-11-14 13:35:19 -08003051 }
3052
3053 /* Free the page_cpu_valid mappings which are now stale, whether
3054 * or not we've got I915_GEM_DOMAIN_CPU.
3055 */
Eric Anholt9a298b22009-03-24 12:23:04 -07003056 kfree(obj_priv->page_cpu_valid);
Eric Anholte47c68e2008-11-14 13:35:19 -08003057 obj_priv->page_cpu_valid = NULL;
3058}
3059
3060/**
3061 * Set the CPU read domain on a range of the object.
3062 *
3063 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3064 * not entirely valid. The page_cpu_valid member of the object flags which
3065 * pages have been flushed, and will be respected by
3066 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3067 * of the whole object.
3068 *
3069 * This function returns when the move is complete, including waiting on
3070 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07003071 */
3072static int
Eric Anholte47c68e2008-11-14 13:35:19 -08003073i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3074 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07003075{
Daniel Vetter23010e42010-03-08 13:35:02 +01003076 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003077 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003078 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003079
Eric Anholte47c68e2008-11-14 13:35:19 -08003080 if (offset == 0 && size == obj->size)
3081 return i915_gem_object_set_to_cpu_domain(obj, 0);
3082
Daniel Vetterba3d8d72010-02-11 22:37:04 +01003083 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08003084 if (ret != 0)
3085 return ret;
3086 i915_gem_object_flush_gtt_write_domain(obj);
3087
3088 /* If we're already fully in the CPU read domain, we're done. */
3089 if (obj_priv->page_cpu_valid == NULL &&
3090 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07003091 return 0;
3092
Eric Anholte47c68e2008-11-14 13:35:19 -08003093 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3094 * newly adding I915_GEM_DOMAIN_CPU
3095 */
Eric Anholt673a3942008-07-30 12:06:12 -07003096 if (obj_priv->page_cpu_valid == NULL) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003097 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3098 GFP_KERNEL);
Eric Anholte47c68e2008-11-14 13:35:19 -08003099 if (obj_priv->page_cpu_valid == NULL)
3100 return -ENOMEM;
3101 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3102 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07003103
3104 /* Flush the cache on any pages that are still invalid from the CPU's
3105 * perspective.
3106 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003107 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3108 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07003109 if (obj_priv->page_cpu_valid[i])
3110 continue;
3111
Eric Anholt856fa192009-03-19 14:10:50 -07003112 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07003113
3114 obj_priv->page_cpu_valid[i] = 1;
3115 }
3116
Eric Anholte47c68e2008-11-14 13:35:19 -08003117 /* It should now be out of any other write domains, and we can update
3118 * the domain values for our changes.
3119 */
3120 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3121
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003122 old_read_domains = obj->read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003123 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3124
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003125 trace_i915_gem_object_change_domain(obj,
3126 old_read_domains,
3127 obj->write_domain);
3128
Eric Anholt673a3942008-07-30 12:06:12 -07003129 return 0;
3130}
3131
3132/**
Eric Anholt673a3942008-07-30 12:06:12 -07003133 * Pin an object to the GTT and evaluate the relocations landing in it.
3134 */
3135static int
3136i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3137 struct drm_file *file_priv,
Jesse Barnes76446ca2009-12-17 22:05:42 -05003138 struct drm_i915_gem_exec_object2 *entry,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003139 struct drm_i915_gem_relocation_entry *relocs)
Eric Anholt673a3942008-07-30 12:06:12 -07003140{
3141 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07003142 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01003143 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003144 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07003145 void __iomem *reloc_page;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003146 bool need_fence;
3147
3148 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3149 obj_priv->tiling_mode != I915_TILING_NONE;
3150
3151 /* Check fence reg constraints and rebind if necessary */
Chris Wilson808b24d2010-05-27 13:18:15 +01003152 if (need_fence &&
3153 !i915_gem_object_fence_offset_ok(obj,
3154 obj_priv->tiling_mode)) {
3155 ret = i915_gem_object_unbind(obj);
3156 if (ret)
3157 return ret;
3158 }
Eric Anholt673a3942008-07-30 12:06:12 -07003159
3160 /* Choose the GTT offset for our buffer and put it there. */
3161 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3162 if (ret)
3163 return ret;
3164
Jesse Barnes76446ca2009-12-17 22:05:42 -05003165 /*
3166 * Pre-965 chips need a fence register set up in order to
3167 * properly handle blits to/from tiled surfaces.
3168 */
3169 if (need_fence) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01003170 ret = i915_gem_object_get_fence_reg(obj, false);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003171 if (ret != 0) {
Jesse Barnes76446ca2009-12-17 22:05:42 -05003172 i915_gem_object_unpin(obj);
3173 return ret;
3174 }
3175 }
3176
Eric Anholt673a3942008-07-30 12:06:12 -07003177 entry->offset = obj_priv->gtt_offset;
3178
Eric Anholt673a3942008-07-30 12:06:12 -07003179 /* Apply the relocations, using the GTT aperture to avoid cache
3180 * flushing requirements.
3181 */
3182 for (i = 0; i < entry->relocation_count; i++) {
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003183 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003184 struct drm_gem_object *target_obj;
3185 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07003186 uint32_t reloc_val, reloc_offset;
3187 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07003188
Eric Anholt673a3942008-07-30 12:06:12 -07003189 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003190 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003191 if (target_obj == NULL) {
3192 i915_gem_object_unpin(obj);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01003193 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07003194 }
Daniel Vetter23010e42010-03-08 13:35:02 +01003195 target_obj_priv = to_intel_bo(target_obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003196
Chris Wilson8542a0b2009-09-09 21:15:15 +01003197#if WATCH_RELOC
3198 DRM_INFO("%s: obj %p offset %08x target %d "
3199 "read %08x write %08x gtt %08x "
3200 "presumed %08x delta %08x\n",
3201 __func__,
3202 obj,
3203 (int) reloc->offset,
3204 (int) reloc->target_handle,
3205 (int) reloc->read_domains,
3206 (int) reloc->write_domain,
3207 (int) target_obj_priv->gtt_offset,
3208 (int) reloc->presumed_offset,
3209 reloc->delta);
3210#endif
3211
Eric Anholt673a3942008-07-30 12:06:12 -07003212 /* The target buffer should have appeared before us in the
3213 * exec_object list, so it should have a GTT space bound by now.
3214 */
3215 if (target_obj_priv->gtt_space == NULL) {
3216 DRM_ERROR("No GTT space found for object %d\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003217 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003218 drm_gem_object_unreference(target_obj);
3219 i915_gem_object_unpin(obj);
3220 return -EINVAL;
3221 }
3222
Chris Wilson8542a0b2009-09-09 21:15:15 +01003223 /* Validate that the target is in a valid r/w GPU domain */
Daniel Vetter16edd552010-02-19 11:52:02 +01003224 if (reloc->write_domain & (reloc->write_domain - 1)) {
3225 DRM_ERROR("reloc with multiple write domains: "
3226 "obj %p target %d offset %d "
3227 "read %08x write %08x",
3228 obj, reloc->target_handle,
3229 (int) reloc->offset,
3230 reloc->read_domains,
3231 reloc->write_domain);
3232 return -EINVAL;
3233 }
Chris Wilson8542a0b2009-09-09 21:15:15 +01003234 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3235 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3236 DRM_ERROR("reloc with read/write CPU domains: "
3237 "obj %p target %d offset %d "
3238 "read %08x write %08x",
3239 obj, reloc->target_handle,
3240 (int) reloc->offset,
3241 reloc->read_domains,
3242 reloc->write_domain);
3243 drm_gem_object_unreference(target_obj);
3244 i915_gem_object_unpin(obj);
3245 return -EINVAL;
3246 }
3247 if (reloc->write_domain && target_obj->pending_write_domain &&
3248 reloc->write_domain != target_obj->pending_write_domain) {
3249 DRM_ERROR("Write domain conflict: "
3250 "obj %p target %d offset %d "
3251 "new %08x old %08x\n",
3252 obj, reloc->target_handle,
3253 (int) reloc->offset,
3254 reloc->write_domain,
3255 target_obj->pending_write_domain);
3256 drm_gem_object_unreference(target_obj);
3257 i915_gem_object_unpin(obj);
3258 return -EINVAL;
3259 }
3260
3261 target_obj->pending_read_domains |= reloc->read_domains;
3262 target_obj->pending_write_domain |= reloc->write_domain;
3263
3264 /* If the relocation already has the right value in it, no
3265 * more work needs to be done.
3266 */
3267 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3268 drm_gem_object_unreference(target_obj);
3269 continue;
3270 }
3271
3272 /* Check that the relocation address is valid... */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003273 if (reloc->offset > obj->size - 4) {
Eric Anholt673a3942008-07-30 12:06:12 -07003274 DRM_ERROR("Relocation beyond object bounds: "
3275 "obj %p target %d offset %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003276 obj, reloc->target_handle,
3277 (int) reloc->offset, (int) obj->size);
Eric Anholt673a3942008-07-30 12:06:12 -07003278 drm_gem_object_unreference(target_obj);
3279 i915_gem_object_unpin(obj);
3280 return -EINVAL;
3281 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003282 if (reloc->offset & 3) {
Eric Anholt673a3942008-07-30 12:06:12 -07003283 DRM_ERROR("Relocation not 4-byte aligned: "
3284 "obj %p target %d offset %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003285 obj, reloc->target_handle,
3286 (int) reloc->offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003287 drm_gem_object_unreference(target_obj);
3288 i915_gem_object_unpin(obj);
3289 return -EINVAL;
3290 }
3291
Chris Wilson8542a0b2009-09-09 21:15:15 +01003292 /* and points to somewhere within the target object. */
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003293 if (reloc->delta >= target_obj->size) {
3294 DRM_ERROR("Relocation beyond target object bounds: "
3295 "obj %p target %d delta %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003296 obj, reloc->target_handle,
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003297 (int) reloc->delta, (int) target_obj->size);
Chris Wilson491152b2009-02-11 14:26:32 +00003298 drm_gem_object_unreference(target_obj);
3299 i915_gem_object_unpin(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003300 return -EINVAL;
3301 }
3302
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003303 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3304 if (ret != 0) {
3305 drm_gem_object_unreference(target_obj);
3306 i915_gem_object_unpin(obj);
3307 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07003308 }
3309
3310 /* Map the page containing the relocation we're going to
3311 * perform.
3312 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003313 reloc_offset = obj_priv->gtt_offset + reloc->offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07003314 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3315 (reloc_offset &
Chris Wilsonfca3ec02010-08-04 14:34:24 +01003316 ~(PAGE_SIZE - 1)),
3317 KM_USER0);
Eric Anholt3043c602008-10-02 12:24:47 -07003318 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07003319 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003320 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
Eric Anholt673a3942008-07-30 12:06:12 -07003321
3322#if WATCH_BUF
3323 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003324 obj, (unsigned int) reloc->offset,
Eric Anholt673a3942008-07-30 12:06:12 -07003325 readl(reloc_entry), reloc_val);
3326#endif
3327 writel(reloc_val, reloc_entry);
Chris Wilsonfca3ec02010-08-04 14:34:24 +01003328 io_mapping_unmap_atomic(reloc_page, KM_USER0);
Eric Anholt673a3942008-07-30 12:06:12 -07003329
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003330 /* The updated presumed offset for this entry will be
3331 * copied back out to the user.
Eric Anholt673a3942008-07-30 12:06:12 -07003332 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003333 reloc->presumed_offset = target_obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003334
3335 drm_gem_object_unreference(target_obj);
3336 }
3337
Eric Anholt673a3942008-07-30 12:06:12 -07003338#if WATCH_BUF
3339 if (0)
3340 i915_gem_dump_object(obj, 128, __func__, ~0);
3341#endif
3342 return 0;
3343}
3344
Eric Anholt673a3942008-07-30 12:06:12 -07003345/* Throttle our rendering by waiting until the ring has completed our requests
3346 * emitted over 20 msec ago.
3347 *
Eric Anholtb9624422009-06-03 07:27:35 +00003348 * Note that if we were to use the current jiffies each time around the loop,
3349 * we wouldn't escape the function with any frames outstanding if the time to
3350 * render a frame was over 20ms.
3351 *
Eric Anholt673a3942008-07-30 12:06:12 -07003352 * This should get us reasonable parallelism between CPU and GPU but also
3353 * relatively low latency when blocking on a particular request to finish.
3354 */
3355static int
3356i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3357{
3358 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3359 int ret = 0;
Eric Anholtb9624422009-06-03 07:27:35 +00003360 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
Eric Anholt673a3942008-07-30 12:06:12 -07003361
3362 mutex_lock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003363 while (!list_empty(&i915_file_priv->mm.request_list)) {
3364 struct drm_i915_gem_request *request;
3365
3366 request = list_first_entry(&i915_file_priv->mm.request_list,
3367 struct drm_i915_gem_request,
3368 client_list);
3369
3370 if (time_after_eq(request->emitted_jiffies, recent_enough))
3371 break;
3372
Zou Nan hai852835f2010-05-21 09:08:56 +08003373 ret = i915_wait_request(dev, request->seqno, request->ring);
Eric Anholtb9624422009-06-03 07:27:35 +00003374 if (ret != 0)
3375 break;
3376 }
Eric Anholt673a3942008-07-30 12:06:12 -07003377 mutex_unlock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003378
Eric Anholt673a3942008-07-30 12:06:12 -07003379 return ret;
3380}
3381
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003382static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003383i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003384 uint32_t buffer_count,
3385 struct drm_i915_gem_relocation_entry **relocs)
3386{
3387 uint32_t reloc_count = 0, reloc_index = 0, i;
3388 int ret;
3389
3390 *relocs = NULL;
3391 for (i = 0; i < buffer_count; i++) {
3392 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3393 return -EINVAL;
3394 reloc_count += exec_list[i].relocation_count;
3395 }
3396
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003397 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
Jesse Barnes76446ca2009-12-17 22:05:42 -05003398 if (*relocs == NULL) {
3399 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003400 return -ENOMEM;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003401 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003402
3403 for (i = 0; i < buffer_count; i++) {
3404 struct drm_i915_gem_relocation_entry __user *user_relocs;
3405
3406 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3407
3408 ret = copy_from_user(&(*relocs)[reloc_index],
3409 user_relocs,
3410 exec_list[i].relocation_count *
3411 sizeof(**relocs));
3412 if (ret != 0) {
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003413 drm_free_large(*relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003414 *relocs = NULL;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003415 return -EFAULT;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003416 }
3417
3418 reloc_index += exec_list[i].relocation_count;
3419 }
3420
Florian Mickler2bc43b52009-04-06 22:55:41 +02003421 return 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003422}
3423
3424static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003425i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003426 uint32_t buffer_count,
3427 struct drm_i915_gem_relocation_entry *relocs)
3428{
3429 uint32_t reloc_count = 0, i;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003430 int ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003431
Chris Wilson93533c22010-01-31 10:40:48 +00003432 if (relocs == NULL)
3433 return 0;
3434
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003435 for (i = 0; i < buffer_count; i++) {
3436 struct drm_i915_gem_relocation_entry __user *user_relocs;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003437 int unwritten;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003438
3439 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3440
Florian Mickler2bc43b52009-04-06 22:55:41 +02003441 unwritten = copy_to_user(user_relocs,
3442 &relocs[reloc_count],
3443 exec_list[i].relocation_count *
3444 sizeof(*relocs));
3445
3446 if (unwritten) {
3447 ret = -EFAULT;
3448 goto err;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003449 }
3450
3451 reloc_count += exec_list[i].relocation_count;
3452 }
3453
Florian Mickler2bc43b52009-04-06 22:55:41 +02003454err:
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003455 drm_free_large(relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003456
3457 return ret;
3458}
3459
Chris Wilson83d60792009-06-06 09:45:57 +01003460static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003461i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
Chris Wilson83d60792009-06-06 09:45:57 +01003462 uint64_t exec_offset)
3463{
3464 uint32_t exec_start, exec_len;
3465
3466 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3467 exec_len = (uint32_t) exec->batch_len;
3468
3469 if ((exec_start | exec_len) & 0x7)
3470 return -EINVAL;
3471
3472 if (!exec_start)
3473 return -EINVAL;
3474
3475 return 0;
3476}
3477
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003478static int
3479i915_gem_wait_for_pending_flip(struct drm_device *dev,
3480 struct drm_gem_object **object_list,
3481 int count)
3482{
3483 drm_i915_private_t *dev_priv = dev->dev_private;
3484 struct drm_i915_gem_object *obj_priv;
3485 DEFINE_WAIT(wait);
3486 int i, ret = 0;
3487
3488 for (;;) {
3489 prepare_to_wait(&dev_priv->pending_flip_queue,
3490 &wait, TASK_INTERRUPTIBLE);
3491 for (i = 0; i < count; i++) {
Daniel Vetter23010e42010-03-08 13:35:02 +01003492 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003493 if (atomic_read(&obj_priv->pending_flip) > 0)
3494 break;
3495 }
3496 if (i == count)
3497 break;
3498
3499 if (!signal_pending(current)) {
3500 mutex_unlock(&dev->struct_mutex);
3501 schedule();
3502 mutex_lock(&dev->struct_mutex);
3503 continue;
3504 }
3505 ret = -ERESTARTSYS;
3506 break;
3507 }
3508 finish_wait(&dev_priv->pending_flip_queue, &wait);
3509
3510 return ret;
3511}
3512
Chris Wilson8dc5d142010-08-12 12:36:12 +01003513static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003514i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3515 struct drm_file *file_priv,
3516 struct drm_i915_gem_execbuffer2 *args,
3517 struct drm_i915_gem_exec_object2 *exec_list)
Eric Anholt673a3942008-07-30 12:06:12 -07003518{
3519 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003520 struct drm_gem_object **object_list = NULL;
3521 struct drm_gem_object *batch_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003522 struct drm_i915_gem_object *obj_priv;
Eric Anholt201361a2009-03-11 12:30:04 -07003523 struct drm_clip_rect *cliprects = NULL;
Chris Wilson93533c22010-01-31 10:40:48 +00003524 struct drm_i915_gem_relocation_entry *relocs = NULL;
Chris Wilson8dc5d142010-08-12 12:36:12 +01003525 struct drm_i915_gem_request *request = NULL;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003526 int ret = 0, ret2, i, pinned = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003527 uint64_t exec_offset;
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01003528 uint32_t seqno, reloc_index;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003529 int pin_tries, flips;
Eric Anholt673a3942008-07-30 12:06:12 -07003530
Zou Nan hai852835f2010-05-21 09:08:56 +08003531 struct intel_ring_buffer *ring = NULL;
3532
Eric Anholt673a3942008-07-30 12:06:12 -07003533#if WATCH_EXEC
3534 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3535 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3536#endif
Zou Nan haid1b851f2010-05-21 09:08:57 +08003537 if (args->flags & I915_EXEC_BSD) {
3538 if (!HAS_BSD(dev)) {
3539 DRM_ERROR("execbuf with wrong flag\n");
3540 return -EINVAL;
3541 }
3542 ring = &dev_priv->bsd_ring;
3543 } else {
3544 ring = &dev_priv->render_ring;
3545 }
3546
Eric Anholt4f481ed2008-09-10 14:22:49 -07003547 if (args->buffer_count < 1) {
3548 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3549 return -EINVAL;
3550 }
Eric Anholtc8e0f932009-11-22 03:49:37 +01003551 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003552 if (object_list == NULL) {
3553 DRM_ERROR("Failed to allocate object list for %d buffers\n",
Eric Anholt673a3942008-07-30 12:06:12 -07003554 args->buffer_count);
3555 ret = -ENOMEM;
3556 goto pre_mutex_err;
3557 }
Eric Anholt673a3942008-07-30 12:06:12 -07003558
Eric Anholt201361a2009-03-11 12:30:04 -07003559 if (args->num_cliprects != 0) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003560 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3561 GFP_KERNEL);
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003562 if (cliprects == NULL) {
3563 ret = -ENOMEM;
Eric Anholt201361a2009-03-11 12:30:04 -07003564 goto pre_mutex_err;
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003565 }
Eric Anholt201361a2009-03-11 12:30:04 -07003566
3567 ret = copy_from_user(cliprects,
3568 (struct drm_clip_rect __user *)
3569 (uintptr_t) args->cliprects_ptr,
3570 sizeof(*cliprects) * args->num_cliprects);
3571 if (ret != 0) {
3572 DRM_ERROR("copy %d cliprects failed: %d\n",
3573 args->num_cliprects, ret);
Dan Carpenterc877cdc2010-06-23 19:03:01 +02003574 ret = -EFAULT;
Eric Anholt201361a2009-03-11 12:30:04 -07003575 goto pre_mutex_err;
3576 }
3577 }
3578
Chris Wilson8dc5d142010-08-12 12:36:12 +01003579 request = kzalloc(sizeof(*request), GFP_KERNEL);
3580 if (request == NULL) {
3581 ret = -ENOMEM;
3582 goto pre_mutex_err;
3583 }
3584
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003585 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3586 &relocs);
3587 if (ret != 0)
3588 goto pre_mutex_err;
3589
Eric Anholt673a3942008-07-30 12:06:12 -07003590 mutex_lock(&dev->struct_mutex);
3591
3592 i915_verify_inactive(dev, __FILE__, __LINE__);
3593
Ben Gamariba1234d2009-09-14 17:48:47 -04003594 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07003595 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003596 ret = -EIO;
3597 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003598 }
3599
3600 if (dev_priv->mm.suspended) {
Eric Anholt673a3942008-07-30 12:06:12 -07003601 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003602 ret = -EBUSY;
3603 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003604 }
3605
Keith Packardac94a962008-11-20 23:30:27 -08003606 /* Look up object handles */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003607 flips = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003608 for (i = 0; i < args->buffer_count; i++) {
3609 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3610 exec_list[i].handle);
3611 if (object_list[i] == NULL) {
3612 DRM_ERROR("Invalid object handle %d at index %d\n",
3613 exec_list[i].handle, i);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003614 /* prevent error path from reading uninitialized data */
3615 args->buffer_count = i + 1;
Chris Wilsonbf79cb92010-08-04 14:19:46 +01003616 ret = -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07003617 goto err;
3618 }
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003619
Daniel Vetter23010e42010-03-08 13:35:02 +01003620 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003621 if (obj_priv->in_execbuffer) {
3622 DRM_ERROR("Object %p appears more than once in object list\n",
3623 object_list[i]);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003624 /* prevent error path from reading uninitialized data */
3625 args->buffer_count = i + 1;
Chris Wilsonbf79cb92010-08-04 14:19:46 +01003626 ret = -EINVAL;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003627 goto err;
3628 }
3629 obj_priv->in_execbuffer = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003630 flips += atomic_read(&obj_priv->pending_flip);
3631 }
3632
3633 if (flips > 0) {
3634 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3635 args->buffer_count);
3636 if (ret)
3637 goto err;
Keith Packardac94a962008-11-20 23:30:27 -08003638 }
Eric Anholt673a3942008-07-30 12:06:12 -07003639
Keith Packardac94a962008-11-20 23:30:27 -08003640 /* Pin and relocate */
3641 for (pin_tries = 0; ; pin_tries++) {
3642 ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003643 reloc_index = 0;
3644
Keith Packardac94a962008-11-20 23:30:27 -08003645 for (i = 0; i < args->buffer_count; i++) {
3646 object_list[i]->pending_read_domains = 0;
3647 object_list[i]->pending_write_domain = 0;
3648 ret = i915_gem_object_pin_and_relocate(object_list[i],
3649 file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003650 &exec_list[i],
3651 &relocs[reloc_index]);
Keith Packardac94a962008-11-20 23:30:27 -08003652 if (ret)
3653 break;
3654 pinned = i + 1;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003655 reloc_index += exec_list[i].relocation_count;
Keith Packardac94a962008-11-20 23:30:27 -08003656 }
3657 /* success */
3658 if (ret == 0)
3659 break;
3660
3661 /* error other than GTT full, or we've already tried again */
Chris Wilson2939e1f2009-06-06 09:46:03 +01003662 if (ret != -ENOSPC || pin_tries >= 1) {
Chris Wilson07f73f62009-09-14 16:50:30 +01003663 if (ret != -ERESTARTSYS) {
3664 unsigned long long total_size = 0;
Chris Wilson3d1cc472010-05-27 13:18:19 +01003665 int num_fences = 0;
3666 for (i = 0; i < args->buffer_count; i++) {
Chris Wilson43b27f42010-07-02 08:57:15 +01003667 obj_priv = to_intel_bo(object_list[i]);
Chris Wilson3d1cc472010-05-27 13:18:19 +01003668
Chris Wilson07f73f62009-09-14 16:50:30 +01003669 total_size += object_list[i]->size;
Chris Wilson3d1cc472010-05-27 13:18:19 +01003670 num_fences +=
3671 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3672 obj_priv->tiling_mode != I915_TILING_NONE;
3673 }
3674 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
Chris Wilson07f73f62009-09-14 16:50:30 +01003675 pinned+1, args->buffer_count,
Chris Wilson3d1cc472010-05-27 13:18:19 +01003676 total_size, num_fences,
3677 ret);
Chris Wilson07f73f62009-09-14 16:50:30 +01003678 DRM_ERROR("%d objects [%d pinned], "
3679 "%d object bytes [%d pinned], "
3680 "%d/%d gtt bytes\n",
3681 atomic_read(&dev->object_count),
3682 atomic_read(&dev->pin_count),
3683 atomic_read(&dev->object_memory),
3684 atomic_read(&dev->pin_memory),
3685 atomic_read(&dev->gtt_memory),
3686 dev->gtt_total);
3687 }
Eric Anholt673a3942008-07-30 12:06:12 -07003688 goto err;
3689 }
Keith Packardac94a962008-11-20 23:30:27 -08003690
3691 /* unpin all of our buffers */
3692 for (i = 0; i < pinned; i++)
3693 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08003694 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08003695
3696 /* evict everyone we can from the aperture */
3697 ret = i915_gem_evict_everything(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01003698 if (ret && ret != -ENOSPC)
Keith Packardac94a962008-11-20 23:30:27 -08003699 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07003700 }
3701
3702 /* Set the pending read domains for the batch buffer to COMMAND */
3703 batch_obj = object_list[args->buffer_count-1];
Chris Wilson5f26a2c2009-06-06 09:45:58 +01003704 if (batch_obj->pending_write_domain) {
3705 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3706 ret = -EINVAL;
3707 goto err;
3708 }
3709 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
Eric Anholt673a3942008-07-30 12:06:12 -07003710
Chris Wilson83d60792009-06-06 09:45:57 +01003711 /* Sanity check the batch buffer, prior to moving objects */
3712 exec_offset = exec_list[args->buffer_count - 1].offset;
3713 ret = i915_gem_check_execbuffer (args, exec_offset);
3714 if (ret != 0) {
3715 DRM_ERROR("execbuf with invalid offset/length\n");
3716 goto err;
3717 }
3718
Eric Anholt673a3942008-07-30 12:06:12 -07003719 i915_verify_inactive(dev, __FILE__, __LINE__);
3720
Keith Packard646f0f62008-11-20 23:23:03 -08003721 /* Zero the global flush/invalidate flags. These
3722 * will be modified as new domains are computed
3723 * for each object
3724 */
3725 dev->invalidate_domains = 0;
3726 dev->flush_domains = 0;
Chris Wilson92204342010-09-18 11:02:01 +01003727 dev_priv->mm.flush_rings = 0;
Keith Packard646f0f62008-11-20 23:23:03 -08003728
Eric Anholt673a3942008-07-30 12:06:12 -07003729 for (i = 0; i < args->buffer_count; i++) {
3730 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003731
Keith Packard646f0f62008-11-20 23:23:03 -08003732 /* Compute new gpu domains and update invalidate/flush */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003733 i915_gem_object_set_to_gpu_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003734 }
3735
3736 i915_verify_inactive(dev, __FILE__, __LINE__);
3737
Keith Packard646f0f62008-11-20 23:23:03 -08003738 if (dev->invalidate_domains | dev->flush_domains) {
3739#if WATCH_EXEC
3740 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3741 __func__,
3742 dev->invalidate_domains,
3743 dev->flush_domains);
3744#endif
3745 i915_gem_flush(dev,
3746 dev->invalidate_domains,
Chris Wilson92204342010-09-18 11:02:01 +01003747 dev->flush_domains,
3748 dev_priv->mm.flush_rings);
Daniel Vettera6910432010-02-02 17:08:37 +01003749 }
3750
3751 if (dev_priv->render_ring.outstanding_lazy_request) {
Chris Wilson8dc5d142010-08-12 12:36:12 +01003752 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring);
Daniel Vettera6910432010-02-02 17:08:37 +01003753 dev_priv->render_ring.outstanding_lazy_request = false;
3754 }
3755 if (dev_priv->bsd_ring.outstanding_lazy_request) {
Chris Wilson8dc5d142010-08-12 12:36:12 +01003756 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring);
Daniel Vettera6910432010-02-02 17:08:37 +01003757 dev_priv->bsd_ring.outstanding_lazy_request = false;
Keith Packard646f0f62008-11-20 23:23:03 -08003758 }
Eric Anholt673a3942008-07-30 12:06:12 -07003759
Eric Anholtefbeed92009-02-19 14:54:51 -08003760 for (i = 0; i < args->buffer_count; i++) {
3761 struct drm_gem_object *obj = object_list[i];
Daniel Vetter23010e42010-03-08 13:35:02 +01003762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003763 uint32_t old_write_domain = obj->write_domain;
Eric Anholtefbeed92009-02-19 14:54:51 -08003764
3765 obj->write_domain = obj->pending_write_domain;
Daniel Vetter99fcb762010-02-07 16:20:18 +01003766 if (obj->write_domain)
3767 list_move_tail(&obj_priv->gpu_write_list,
3768 &dev_priv->mm.gpu_write_list);
3769 else
3770 list_del_init(&obj_priv->gpu_write_list);
3771
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003772 trace_i915_gem_object_change_domain(obj,
3773 obj->read_domains,
3774 old_write_domain);
Eric Anholtefbeed92009-02-19 14:54:51 -08003775 }
3776
Eric Anholt673a3942008-07-30 12:06:12 -07003777 i915_verify_inactive(dev, __FILE__, __LINE__);
3778
3779#if WATCH_COHERENCY
3780 for (i = 0; i < args->buffer_count; i++) {
3781 i915_gem_object_check_coherency(object_list[i],
3782 exec_list[i].handle);
3783 }
3784#endif
3785
Eric Anholt673a3942008-07-30 12:06:12 -07003786#if WATCH_EXEC
Ben Gamari6911a9b2009-04-02 11:24:54 -07003787 i915_gem_dump_object(batch_obj,
Eric Anholt673a3942008-07-30 12:06:12 -07003788 args->batch_len,
3789 __func__,
3790 ~0);
3791#endif
3792
Eric Anholt673a3942008-07-30 12:06:12 -07003793 /* Exec the batchbuffer */
Zou Nan hai852835f2010-05-21 09:08:56 +08003794 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3795 cliprects, exec_offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003796 if (ret) {
3797 DRM_ERROR("dispatch failed %d\n", ret);
3798 goto err;
3799 }
3800
3801 /*
3802 * Ensure that the commands in the batch buffer are
3803 * finished before the interrupt fires
3804 */
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01003805 i915_retire_commands(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07003806
3807 i915_verify_inactive(dev, __FILE__, __LINE__);
3808
Daniel Vetter617dbe22010-02-11 22:16:02 +01003809 for (i = 0; i < args->buffer_count; i++) {
3810 struct drm_gem_object *obj = object_list[i];
3811 obj_priv = to_intel_bo(obj);
3812
3813 i915_gem_object_move_to_active(obj, ring);
3814#if WATCH_LRU
3815 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3816#endif
3817 }
3818
Eric Anholt673a3942008-07-30 12:06:12 -07003819 /*
3820 * Get a seqno representing the execution of the current buffer,
3821 * which we can wait on. We would like to mitigate these interrupts,
3822 * likely by only creating seqnos occasionally (so that we have
3823 * *some* interrupts representing completion of buffers that we can
3824 * wait on when trying to clear up gtt space).
3825 */
Chris Wilson8dc5d142010-08-12 12:36:12 +01003826 seqno = i915_add_request(dev, file_priv, request, ring);
3827 request = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07003828
Eric Anholt673a3942008-07-30 12:06:12 -07003829#if WATCH_LRU
3830 i915_dump_lru(dev, __func__);
3831#endif
3832
3833 i915_verify_inactive(dev, __FILE__, __LINE__);
3834
Eric Anholt673a3942008-07-30 12:06:12 -07003835err:
Julia Lawallaad87df2008-12-21 16:28:47 +01003836 for (i = 0; i < pinned; i++)
3837 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07003838
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003839 for (i = 0; i < args->buffer_count; i++) {
3840 if (object_list[i]) {
Daniel Vetter23010e42010-03-08 13:35:02 +01003841 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003842 obj_priv->in_execbuffer = false;
3843 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003844 drm_gem_object_unreference(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003845 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003846
Eric Anholt673a3942008-07-30 12:06:12 -07003847 mutex_unlock(&dev->struct_mutex);
3848
Chris Wilson93533c22010-01-31 10:40:48 +00003849pre_mutex_err:
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003850 /* Copy the updated relocations out regardless of current error
3851 * state. Failure to update the relocs would mean that the next
3852 * time userland calls execbuf, it would do so with presumed offset
3853 * state that didn't match the actual object state.
3854 */
3855 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3856 relocs);
3857 if (ret2 != 0) {
3858 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3859
3860 if (ret == 0)
3861 ret = ret2;
3862 }
3863
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003864 drm_free_large(object_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07003865 kfree(cliprects);
Chris Wilson8dc5d142010-08-12 12:36:12 +01003866 kfree(request);
Eric Anholt673a3942008-07-30 12:06:12 -07003867
3868 return ret;
3869}
3870
Jesse Barnes76446ca2009-12-17 22:05:42 -05003871/*
3872 * Legacy execbuffer just creates an exec2 list from the original exec object
3873 * list array and passes it to the real function.
3874 */
3875int
3876i915_gem_execbuffer(struct drm_device *dev, void *data,
3877 struct drm_file *file_priv)
3878{
3879 struct drm_i915_gem_execbuffer *args = data;
3880 struct drm_i915_gem_execbuffer2 exec2;
3881 struct drm_i915_gem_exec_object *exec_list = NULL;
3882 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3883 int ret, i;
3884
3885#if WATCH_EXEC
3886 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3887 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3888#endif
3889
3890 if (args->buffer_count < 1) {
3891 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3892 return -EINVAL;
3893 }
3894
3895 /* Copy in the exec list from userland */
3896 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3897 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3898 if (exec_list == NULL || exec2_list == NULL) {
3899 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3900 args->buffer_count);
3901 drm_free_large(exec_list);
3902 drm_free_large(exec2_list);
3903 return -ENOMEM;
3904 }
3905 ret = copy_from_user(exec_list,
3906 (struct drm_i915_relocation_entry __user *)
3907 (uintptr_t) args->buffers_ptr,
3908 sizeof(*exec_list) * args->buffer_count);
3909 if (ret != 0) {
3910 DRM_ERROR("copy %d exec entries failed %d\n",
3911 args->buffer_count, ret);
3912 drm_free_large(exec_list);
3913 drm_free_large(exec2_list);
3914 return -EFAULT;
3915 }
3916
3917 for (i = 0; i < args->buffer_count; i++) {
3918 exec2_list[i].handle = exec_list[i].handle;
3919 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3920 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3921 exec2_list[i].alignment = exec_list[i].alignment;
3922 exec2_list[i].offset = exec_list[i].offset;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003923 if (INTEL_INFO(dev)->gen < 4)
Jesse Barnes76446ca2009-12-17 22:05:42 -05003924 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3925 else
3926 exec2_list[i].flags = 0;
3927 }
3928
3929 exec2.buffers_ptr = args->buffers_ptr;
3930 exec2.buffer_count = args->buffer_count;
3931 exec2.batch_start_offset = args->batch_start_offset;
3932 exec2.batch_len = args->batch_len;
3933 exec2.DR1 = args->DR1;
3934 exec2.DR4 = args->DR4;
3935 exec2.num_cliprects = args->num_cliprects;
3936 exec2.cliprects_ptr = args->cliprects_ptr;
Zou Nan hai852835f2010-05-21 09:08:56 +08003937 exec2.flags = I915_EXEC_RENDER;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003938
3939 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3940 if (!ret) {
3941 /* Copy the new buffer offsets back to the user's exec list. */
3942 for (i = 0; i < args->buffer_count; i++)
3943 exec_list[i].offset = exec2_list[i].offset;
3944 /* ... and back out to userspace */
3945 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3946 (uintptr_t) args->buffers_ptr,
3947 exec_list,
3948 sizeof(*exec_list) * args->buffer_count);
3949 if (ret) {
3950 ret = -EFAULT;
3951 DRM_ERROR("failed to copy %d exec entries "
3952 "back to user (%d)\n",
3953 args->buffer_count, ret);
3954 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05003955 }
3956
3957 drm_free_large(exec_list);
3958 drm_free_large(exec2_list);
3959 return ret;
3960}
3961
3962int
3963i915_gem_execbuffer2(struct drm_device *dev, void *data,
3964 struct drm_file *file_priv)
3965{
3966 struct drm_i915_gem_execbuffer2 *args = data;
3967 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3968 int ret;
3969
3970#if WATCH_EXEC
3971 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3972 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3973#endif
3974
3975 if (args->buffer_count < 1) {
3976 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3977 return -EINVAL;
3978 }
3979
3980 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3981 if (exec2_list == NULL) {
3982 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3983 args->buffer_count);
3984 return -ENOMEM;
3985 }
3986 ret = copy_from_user(exec2_list,
3987 (struct drm_i915_relocation_entry __user *)
3988 (uintptr_t) args->buffers_ptr,
3989 sizeof(*exec2_list) * args->buffer_count);
3990 if (ret != 0) {
3991 DRM_ERROR("copy %d exec entries failed %d\n",
3992 args->buffer_count, ret);
3993 drm_free_large(exec2_list);
3994 return -EFAULT;
3995 }
3996
3997 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
3998 if (!ret) {
3999 /* Copy the new buffer offsets back to the user's exec list. */
4000 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4001 (uintptr_t) args->buffers_ptr,
4002 exec2_list,
4003 sizeof(*exec2_list) * args->buffer_count);
4004 if (ret) {
4005 ret = -EFAULT;
4006 DRM_ERROR("failed to copy %d exec entries "
4007 "back to user (%d)\n",
4008 args->buffer_count, ret);
4009 }
4010 }
4011
4012 drm_free_large(exec2_list);
4013 return ret;
4014}
4015
Eric Anholt673a3942008-07-30 12:06:12 -07004016int
4017i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4018{
4019 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01004020 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004021 int ret;
4022
Daniel Vetter778c3542010-05-13 11:49:44 +02004023 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4024
Eric Anholt673a3942008-07-30 12:06:12 -07004025 i915_verify_inactive(dev, __FILE__, __LINE__);
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004026
4027 if (obj_priv->gtt_space != NULL) {
4028 if (alignment == 0)
4029 alignment = i915_gem_get_gtt_alignment(obj);
4030 if (obj_priv->gtt_offset & (alignment - 1)) {
Chris Wilsonae7d49d2010-08-04 12:37:41 +01004031 WARN(obj_priv->pin_count,
4032 "bo is already pinned with incorrect alignment:"
4033 " offset=%x, req.alignment=%x\n",
4034 obj_priv->gtt_offset, alignment);
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004035 ret = i915_gem_object_unbind(obj);
4036 if (ret)
4037 return ret;
4038 }
4039 }
4040
Eric Anholt673a3942008-07-30 12:06:12 -07004041 if (obj_priv->gtt_space == NULL) {
4042 ret = i915_gem_object_bind_to_gtt(obj, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01004043 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07004044 return ret;
Chris Wilson22c344e2009-02-11 14:26:45 +00004045 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004046
Eric Anholt673a3942008-07-30 12:06:12 -07004047 obj_priv->pin_count++;
4048
4049 /* If the object is not active and not pending a flush,
4050 * remove it from the inactive list
4051 */
4052 if (obj_priv->pin_count == 1) {
4053 atomic_inc(&dev->pin_count);
4054 atomic_add(obj->size, &dev->pin_memory);
4055 if (!obj_priv->active &&
Chris Wilsonbf1a1092010-08-07 11:01:20 +01004056 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07004057 list_del_init(&obj_priv->list);
4058 }
4059 i915_verify_inactive(dev, __FILE__, __LINE__);
4060
4061 return 0;
4062}
4063
4064void
4065i915_gem_object_unpin(struct drm_gem_object *obj)
4066{
4067 struct drm_device *dev = obj->dev;
4068 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01004069 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004070
4071 i915_verify_inactive(dev, __FILE__, __LINE__);
4072 obj_priv->pin_count--;
4073 BUG_ON(obj_priv->pin_count < 0);
4074 BUG_ON(obj_priv->gtt_space == NULL);
4075
4076 /* If the object is no longer pinned, and is
4077 * neither active nor being flushed, then stick it on
4078 * the inactive list
4079 */
4080 if (obj_priv->pin_count == 0) {
4081 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01004082 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07004083 list_move_tail(&obj_priv->list,
4084 &dev_priv->mm.inactive_list);
4085 atomic_dec(&dev->pin_count);
4086 atomic_sub(obj->size, &dev->pin_memory);
4087 }
4088 i915_verify_inactive(dev, __FILE__, __LINE__);
4089}
4090
4091int
4092i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4093 struct drm_file *file_priv)
4094{
4095 struct drm_i915_gem_pin *args = data;
4096 struct drm_gem_object *obj;
4097 struct drm_i915_gem_object *obj_priv;
4098 int ret;
4099
4100 mutex_lock(&dev->struct_mutex);
4101
4102 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4103 if (obj == NULL) {
4104 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4105 args->handle);
4106 mutex_unlock(&dev->struct_mutex);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004107 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07004108 }
Daniel Vetter23010e42010-03-08 13:35:02 +01004109 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004110
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004111 if (obj_priv->madv != I915_MADV_WILLNEED) {
4112 DRM_ERROR("Attempting to pin a purgeable buffer\n");
Chris Wilson3ef94da2009-09-14 16:50:29 +01004113 drm_gem_object_unreference(obj);
4114 mutex_unlock(&dev->struct_mutex);
4115 return -EINVAL;
4116 }
4117
Jesse Barnes79e53942008-11-07 14:24:08 -08004118 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4119 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4120 args->handle);
Chris Wilson96dec612009-02-08 19:08:04 +00004121 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004122 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08004123 return -EINVAL;
4124 }
4125
4126 obj_priv->user_pin_count++;
4127 obj_priv->pin_filp = file_priv;
4128 if (obj_priv->user_pin_count == 1) {
4129 ret = i915_gem_object_pin(obj, args->alignment);
4130 if (ret != 0) {
4131 drm_gem_object_unreference(obj);
4132 mutex_unlock(&dev->struct_mutex);
4133 return ret;
4134 }
Eric Anholt673a3942008-07-30 12:06:12 -07004135 }
4136
4137 /* XXX - flush the CPU caches for pinned objects
4138 * as the X server doesn't manage domains yet
4139 */
Eric Anholte47c68e2008-11-14 13:35:19 -08004140 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004141 args->offset = obj_priv->gtt_offset;
4142 drm_gem_object_unreference(obj);
4143 mutex_unlock(&dev->struct_mutex);
4144
4145 return 0;
4146}
4147
4148int
4149i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4150 struct drm_file *file_priv)
4151{
4152 struct drm_i915_gem_pin *args = data;
4153 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08004154 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07004155
4156 mutex_lock(&dev->struct_mutex);
4157
4158 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4159 if (obj == NULL) {
4160 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4161 args->handle);
4162 mutex_unlock(&dev->struct_mutex);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004163 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07004164 }
4165
Daniel Vetter23010e42010-03-08 13:35:02 +01004166 obj_priv = to_intel_bo(obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08004167 if (obj_priv->pin_filp != file_priv) {
4168 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4169 args->handle);
4170 drm_gem_object_unreference(obj);
4171 mutex_unlock(&dev->struct_mutex);
4172 return -EINVAL;
4173 }
4174 obj_priv->user_pin_count--;
4175 if (obj_priv->user_pin_count == 0) {
4176 obj_priv->pin_filp = NULL;
4177 i915_gem_object_unpin(obj);
4178 }
Eric Anholt673a3942008-07-30 12:06:12 -07004179
4180 drm_gem_object_unreference(obj);
4181 mutex_unlock(&dev->struct_mutex);
4182 return 0;
4183}
4184
4185int
4186i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4187 struct drm_file *file_priv)
4188{
4189 struct drm_i915_gem_busy *args = data;
4190 struct drm_gem_object *obj;
4191 struct drm_i915_gem_object *obj_priv;
4192
Eric Anholt673a3942008-07-30 12:06:12 -07004193 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4194 if (obj == NULL) {
4195 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4196 args->handle);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004197 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07004198 }
4199
Chris Wilsonb1ce7862009-06-06 09:46:00 +01004200 mutex_lock(&dev->struct_mutex);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004201
Chris Wilson0be555b2010-08-04 15:36:30 +01004202 /* Count all active objects as busy, even if they are currently not used
4203 * by the gpu. Users of this interface expect objects to eventually
4204 * become non-busy without any further actions, therefore emit any
4205 * necessary flushes here.
Eric Anholtc4de0a52008-12-14 19:05:04 -08004206 */
Chris Wilson0be555b2010-08-04 15:36:30 +01004207 obj_priv = to_intel_bo(obj);
4208 args->busy = obj_priv->active;
4209 if (args->busy) {
4210 /* Unconditionally flush objects, even when the gpu still uses this
4211 * object. Userspace calling this function indicates that it wants to
4212 * use this buffer rather sooner than later, so issuing the required
4213 * flush earlier is beneficial.
4214 */
Chris Wilson92204342010-09-18 11:02:01 +01004215 if (obj->write_domain & I915_GEM_GPU_DOMAINS) {
4216 i915_gem_flush_ring(dev,
4217 obj_priv->ring,
4218 0, obj->write_domain);
Chris Wilson8dc5d142010-08-12 12:36:12 +01004219 (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring);
Chris Wilson0be555b2010-08-04 15:36:30 +01004220 }
4221
4222 /* Update the active list for the hardware's current position.
4223 * Otherwise this only updates on a delayed timer or when irqs
4224 * are actually unmasked, and our working set ends up being
4225 * larger than required.
4226 */
4227 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4228
4229 args->busy = obj_priv->active;
4230 }
Eric Anholt673a3942008-07-30 12:06:12 -07004231
4232 drm_gem_object_unreference(obj);
4233 mutex_unlock(&dev->struct_mutex);
4234 return 0;
4235}
4236
4237int
4238i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4239 struct drm_file *file_priv)
4240{
4241 return i915_gem_ring_throttle(dev, file_priv);
4242}
4243
Chris Wilson3ef94da2009-09-14 16:50:29 +01004244int
4245i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4246 struct drm_file *file_priv)
4247{
4248 struct drm_i915_gem_madvise *args = data;
4249 struct drm_gem_object *obj;
4250 struct drm_i915_gem_object *obj_priv;
4251
4252 switch (args->madv) {
4253 case I915_MADV_DONTNEED:
4254 case I915_MADV_WILLNEED:
4255 break;
4256 default:
4257 return -EINVAL;
4258 }
4259
4260 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4261 if (obj == NULL) {
4262 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4263 args->handle);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004264 return -ENOENT;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004265 }
4266
4267 mutex_lock(&dev->struct_mutex);
Daniel Vetter23010e42010-03-08 13:35:02 +01004268 obj_priv = to_intel_bo(obj);
Chris Wilson3ef94da2009-09-14 16:50:29 +01004269
4270 if (obj_priv->pin_count) {
4271 drm_gem_object_unreference(obj);
4272 mutex_unlock(&dev->struct_mutex);
4273
4274 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4275 return -EINVAL;
4276 }
4277
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004278 if (obj_priv->madv != __I915_MADV_PURGED)
4279 obj_priv->madv = args->madv;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004280
Chris Wilson2d7ef392009-09-20 23:13:10 +01004281 /* if the object is no longer bound, discard its backing storage */
4282 if (i915_gem_object_is_purgeable(obj_priv) &&
4283 obj_priv->gtt_space == NULL)
4284 i915_gem_object_truncate(obj);
4285
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004286 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4287
Chris Wilson3ef94da2009-09-14 16:50:29 +01004288 drm_gem_object_unreference(obj);
4289 mutex_unlock(&dev->struct_mutex);
4290
4291 return 0;
4292}
4293
Daniel Vetterac52bc52010-04-09 19:05:06 +00004294struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4295 size_t size)
4296{
Daniel Vetterc397b902010-04-09 19:05:07 +00004297 struct drm_i915_gem_object *obj;
4298
4299 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4300 if (obj == NULL)
4301 return NULL;
4302
4303 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4304 kfree(obj);
4305 return NULL;
4306 }
4307
4308 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4309 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4310
4311 obj->agp_type = AGP_USER_MEMORY;
Daniel Vetter62b8b212010-04-09 19:05:08 +00004312 obj->base.driver_private = NULL;
Daniel Vetterc397b902010-04-09 19:05:07 +00004313 obj->fence_reg = I915_FENCE_REG_NONE;
4314 INIT_LIST_HEAD(&obj->list);
4315 INIT_LIST_HEAD(&obj->gpu_write_list);
Daniel Vetterc397b902010-04-09 19:05:07 +00004316 obj->madv = I915_MADV_WILLNEED;
4317
4318 trace_i915_gem_object_create(&obj->base);
4319
4320 return &obj->base;
Daniel Vetterac52bc52010-04-09 19:05:06 +00004321}
4322
Eric Anholt673a3942008-07-30 12:06:12 -07004323int i915_gem_init_object(struct drm_gem_object *obj)
4324{
Daniel Vetterc397b902010-04-09 19:05:07 +00004325 BUG();
Jesse Barnesde151cf2008-11-12 10:03:55 -08004326
Eric Anholt673a3942008-07-30 12:06:12 -07004327 return 0;
4328}
4329
Chris Wilsonbe726152010-07-23 23:18:50 +01004330static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4331{
4332 struct drm_device *dev = obj->dev;
4333 drm_i915_private_t *dev_priv = dev->dev_private;
4334 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4335 int ret;
4336
4337 ret = i915_gem_object_unbind(obj);
4338 if (ret == -ERESTARTSYS) {
4339 list_move(&obj_priv->list,
4340 &dev_priv->mm.deferred_free_list);
4341 return;
4342 }
4343
4344 if (obj_priv->mmap_offset)
4345 i915_gem_free_mmap_offset(obj);
4346
4347 drm_gem_object_release(obj);
4348
4349 kfree(obj_priv->page_cpu_valid);
4350 kfree(obj_priv->bit_17);
4351 kfree(obj_priv);
4352}
4353
Eric Anholt673a3942008-07-30 12:06:12 -07004354void i915_gem_free_object(struct drm_gem_object *obj)
4355{
Jesse Barnesde151cf2008-11-12 10:03:55 -08004356 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01004357 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004358
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004359 trace_i915_gem_object_destroy(obj);
4360
Eric Anholt673a3942008-07-30 12:06:12 -07004361 while (obj_priv->pin_count > 0)
4362 i915_gem_object_unpin(obj);
4363
Dave Airlie71acb5e2008-12-30 20:31:46 +10004364 if (obj_priv->phys_obj)
4365 i915_gem_detach_phys_object(dev, obj);
4366
Chris Wilsonbe726152010-07-23 23:18:50 +01004367 i915_gem_free_object_tail(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004368}
4369
Jesse Barnes5669fca2009-02-17 15:13:31 -08004370int
Eric Anholt673a3942008-07-30 12:06:12 -07004371i915_gem_idle(struct drm_device *dev)
4372{
4373 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson29105cc2010-01-07 10:39:13 +00004374 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004375
Keith Packard6dbe2772008-10-14 21:41:13 -07004376 mutex_lock(&dev->struct_mutex);
4377
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004378 if (dev_priv->mm.suspended ||
Zou Nan haid1b851f2010-05-21 09:08:57 +08004379 (dev_priv->render_ring.gem_object == NULL) ||
4380 (HAS_BSD(dev) &&
4381 dev_priv->bsd_ring.gem_object == NULL)) {
Keith Packard6dbe2772008-10-14 21:41:13 -07004382 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004383 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07004384 }
Eric Anholt673a3942008-07-30 12:06:12 -07004385
Chris Wilson29105cc2010-01-07 10:39:13 +00004386 ret = i915_gpu_idle(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004387 if (ret) {
4388 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004389 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07004390 }
Eric Anholt673a3942008-07-30 12:06:12 -07004391
Chris Wilson29105cc2010-01-07 10:39:13 +00004392 /* Under UMS, be paranoid and evict. */
4393 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01004394 ret = i915_gem_evict_inactive(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004395 if (ret) {
4396 mutex_unlock(&dev->struct_mutex);
4397 return ret;
4398 }
4399 }
4400
4401 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4402 * We need to replace this with a semaphore, or something.
4403 * And not confound mm.suspended!
4404 */
4405 dev_priv->mm.suspended = 1;
Daniel Vetterbc0c7f12010-08-20 18:18:48 +02004406 del_timer_sync(&dev_priv->hangcheck_timer);
Chris Wilson29105cc2010-01-07 10:39:13 +00004407
4408 i915_kernel_lost_context(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004409 i915_gem_cleanup_ringbuffer(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004410
Keith Packard6dbe2772008-10-14 21:41:13 -07004411 mutex_unlock(&dev->struct_mutex);
4412
Chris Wilson29105cc2010-01-07 10:39:13 +00004413 /* Cancel the retire work handler, which should be idle now. */
4414 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4415
Eric Anholt673a3942008-07-30 12:06:12 -07004416 return 0;
4417}
4418
Jesse Barnese552eb72010-04-21 11:39:23 -07004419/*
4420 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4421 * over cache flushing.
4422 */
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004423static int
Jesse Barnese552eb72010-04-21 11:39:23 -07004424i915_gem_init_pipe_control(struct drm_device *dev)
4425{
4426 drm_i915_private_t *dev_priv = dev->dev_private;
4427 struct drm_gem_object *obj;
4428 struct drm_i915_gem_object *obj_priv;
4429 int ret;
4430
Eric Anholt34dc4d42010-05-07 14:30:03 -07004431 obj = i915_gem_alloc_object(dev, 4096);
Jesse Barnese552eb72010-04-21 11:39:23 -07004432 if (obj == NULL) {
4433 DRM_ERROR("Failed to allocate seqno page\n");
4434 ret = -ENOMEM;
4435 goto err;
4436 }
4437 obj_priv = to_intel_bo(obj);
4438 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4439
4440 ret = i915_gem_object_pin(obj, 4096);
4441 if (ret)
4442 goto err_unref;
4443
4444 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4445 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4446 if (dev_priv->seqno_page == NULL)
4447 goto err_unpin;
4448
4449 dev_priv->seqno_obj = obj;
4450 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4451
4452 return 0;
4453
4454err_unpin:
4455 i915_gem_object_unpin(obj);
4456err_unref:
4457 drm_gem_object_unreference(obj);
4458err:
4459 return ret;
4460}
4461
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004462
4463static void
Jesse Barnese552eb72010-04-21 11:39:23 -07004464i915_gem_cleanup_pipe_control(struct drm_device *dev)
4465{
4466 drm_i915_private_t *dev_priv = dev->dev_private;
4467 struct drm_gem_object *obj;
4468 struct drm_i915_gem_object *obj_priv;
4469
4470 obj = dev_priv->seqno_obj;
4471 obj_priv = to_intel_bo(obj);
4472 kunmap(obj_priv->pages[0]);
4473 i915_gem_object_unpin(obj);
4474 drm_gem_object_unreference(obj);
4475 dev_priv->seqno_obj = NULL;
4476
4477 dev_priv->seqno_page = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07004478}
4479
Eric Anholt673a3942008-07-30 12:06:12 -07004480int
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004481i915_gem_init_ringbuffer(struct drm_device *dev)
4482{
4483 drm_i915_private_t *dev_priv = dev->dev_private;
4484 int ret;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004485
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004486 dev_priv->render_ring = render_ring;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004487
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004488 if (!I915_NEED_GFX_HWS(dev)) {
4489 dev_priv->render_ring.status_page.page_addr
4490 = dev_priv->status_page_dmah->vaddr;
4491 memset(dev_priv->render_ring.status_page.page_addr,
4492 0, PAGE_SIZE);
4493 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004494
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004495 if (HAS_PIPE_CONTROL(dev)) {
4496 ret = i915_gem_init_pipe_control(dev);
4497 if (ret)
4498 return ret;
4499 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004500
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004501 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004502 if (ret)
4503 goto cleanup_pipe_control;
4504
4505 if (HAS_BSD(dev)) {
Zou Nan haid1b851f2010-05-21 09:08:57 +08004506 dev_priv->bsd_ring = bsd_ring;
4507 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004508 if (ret)
4509 goto cleanup_render_ring;
Zou Nan haid1b851f2010-05-21 09:08:57 +08004510 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004511
Chris Wilson6f392d52010-08-07 11:01:22 +01004512 dev_priv->next_seqno = 1;
4513
Chris Wilson68f95ba2010-05-27 13:18:22 +01004514 return 0;
4515
4516cleanup_render_ring:
4517 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4518cleanup_pipe_control:
4519 if (HAS_PIPE_CONTROL(dev))
4520 i915_gem_cleanup_pipe_control(dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004521 return ret;
4522}
4523
4524void
4525i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4526{
4527 drm_i915_private_t *dev_priv = dev->dev_private;
4528
4529 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004530 if (HAS_BSD(dev))
4531 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004532 if (HAS_PIPE_CONTROL(dev))
4533 i915_gem_cleanup_pipe_control(dev);
4534}
4535
4536int
Eric Anholt673a3942008-07-30 12:06:12 -07004537i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4538 struct drm_file *file_priv)
4539{
4540 drm_i915_private_t *dev_priv = dev->dev_private;
4541 int ret;
4542
Jesse Barnes79e53942008-11-07 14:24:08 -08004543 if (drm_core_check_feature(dev, DRIVER_MODESET))
4544 return 0;
4545
Ben Gamariba1234d2009-09-14 17:48:47 -04004546 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07004547 DRM_ERROR("Reenabling wedged hardware, good luck\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04004548 atomic_set(&dev_priv->mm.wedged, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004549 }
4550
Eric Anholt673a3942008-07-30 12:06:12 -07004551 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004552 dev_priv->mm.suspended = 0;
4553
4554 ret = i915_gem_init_ringbuffer(dev);
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004555 if (ret != 0) {
4556 mutex_unlock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004557 return ret;
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004558 }
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004559
Zou Nan hai852835f2010-05-21 09:08:56 +08004560 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
Zou Nan haid1b851f2010-05-21 09:08:57 +08004561 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004562 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4563 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
Zou Nan hai852835f2010-05-21 09:08:56 +08004564 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
Zou Nan haid1b851f2010-05-21 09:08:57 +08004565 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004566 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004567
Chris Wilson5f353082010-06-07 14:03:03 +01004568 ret = drm_irq_install(dev);
4569 if (ret)
4570 goto cleanup_ringbuffer;
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004571
Eric Anholt673a3942008-07-30 12:06:12 -07004572 return 0;
Chris Wilson5f353082010-06-07 14:03:03 +01004573
4574cleanup_ringbuffer:
4575 mutex_lock(&dev->struct_mutex);
4576 i915_gem_cleanup_ringbuffer(dev);
4577 dev_priv->mm.suspended = 1;
4578 mutex_unlock(&dev->struct_mutex);
4579
4580 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004581}
4582
4583int
4584i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4585 struct drm_file *file_priv)
4586{
Jesse Barnes79e53942008-11-07 14:24:08 -08004587 if (drm_core_check_feature(dev, DRIVER_MODESET))
4588 return 0;
4589
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004590 drm_irq_uninstall(dev);
Linus Torvaldse6890f62009-09-08 17:09:24 -07004591 return i915_gem_idle(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004592}
4593
4594void
4595i915_gem_lastclose(struct drm_device *dev)
4596{
4597 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004598
Eric Anholte806b492009-01-22 09:56:58 -08004599 if (drm_core_check_feature(dev, DRIVER_MODESET))
4600 return;
4601
Keith Packard6dbe2772008-10-14 21:41:13 -07004602 ret = i915_gem_idle(dev);
4603 if (ret)
4604 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004605}
4606
4607void
4608i915_gem_load(struct drm_device *dev)
4609{
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004610 int i;
Eric Anholt673a3942008-07-30 12:06:12 -07004611 drm_i915_private_t *dev_priv = dev->dev_private;
4612
Eric Anholt673a3942008-07-30 12:06:12 -07004613 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
Daniel Vetter99fcb762010-02-07 16:20:18 +01004614 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004615 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004616 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
Chris Wilsonbe726152010-07-23 23:18:50 +01004617 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
Zou Nan hai852835f2010-05-21 09:08:56 +08004618 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4619 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004620 if (HAS_BSD(dev)) {
4621 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4622 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4623 }
Daniel Vetter007cc8a2010-04-28 11:02:31 +02004624 for (i = 0; i < 16; i++)
4625 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004626 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4627 i915_gem_retire_work_handler);
Chris Wilson31169712009-09-14 16:50:28 +01004628 spin_lock(&shrink_list_lock);
4629 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4630 spin_unlock(&shrink_list_lock);
4631
Dave Airlie94400122010-07-20 13:15:31 +10004632 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4633 if (IS_GEN3(dev)) {
4634 u32 tmp = I915_READ(MI_ARB_STATE);
4635 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4636 /* arb state is a masked write, so set bit + bit in mask */
4637 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4638 I915_WRITE(MI_ARB_STATE, tmp);
4639 }
4640 }
4641
Jesse Barnesde151cf2008-11-12 10:03:55 -08004642 /* Old X drivers will take 0-2 for front, back, depth buffers */
Eric Anholtb397c832010-01-26 09:43:10 -08004643 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4644 dev_priv->fence_reg_start = 3;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004645
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004646 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004647 dev_priv->num_fence_regs = 16;
4648 else
4649 dev_priv->num_fence_regs = 8;
4650
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004651 /* Initialize fence registers to zero */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004652 switch (INTEL_INFO(dev)->gen) {
4653 case 6:
4654 for (i = 0; i < 16; i++)
4655 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4656 break;
4657 case 5:
4658 case 4:
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004659 for (i = 0; i < 16; i++)
4660 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004661 break;
4662 case 3:
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004663 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4664 for (i = 0; i < 8; i++)
4665 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004666 case 2:
4667 for (i = 0; i < 8; i++)
4668 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4669 break;
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004670 }
Eric Anholt673a3942008-07-30 12:06:12 -07004671 i915_gem_detect_bit_6_swizzle(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004672 init_waitqueue_head(&dev_priv->pending_flip_queue);
Eric Anholt673a3942008-07-30 12:06:12 -07004673}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004674
4675/*
4676 * Create a physically contiguous memory object for this object
4677 * e.g. for cursor + overlay regs
4678 */
Chris Wilson995b6762010-08-20 13:23:26 +01004679static int i915_gem_init_phys_object(struct drm_device *dev,
4680 int id, int size, int align)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004681{
4682 drm_i915_private_t *dev_priv = dev->dev_private;
4683 struct drm_i915_gem_phys_object *phys_obj;
4684 int ret;
4685
4686 if (dev_priv->mm.phys_objs[id - 1] || !size)
4687 return 0;
4688
Eric Anholt9a298b22009-03-24 12:23:04 -07004689 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004690 if (!phys_obj)
4691 return -ENOMEM;
4692
4693 phys_obj->id = id;
4694
Chris Wilson6eeefaf2010-08-07 11:01:39 +01004695 phys_obj->handle = drm_pci_alloc(dev, size, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004696 if (!phys_obj->handle) {
4697 ret = -ENOMEM;
4698 goto kfree_obj;
4699 }
4700#ifdef CONFIG_X86
4701 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4702#endif
4703
4704 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4705
4706 return 0;
4707kfree_obj:
Eric Anholt9a298b22009-03-24 12:23:04 -07004708 kfree(phys_obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004709 return ret;
4710}
4711
Chris Wilson995b6762010-08-20 13:23:26 +01004712static void i915_gem_free_phys_object(struct drm_device *dev, int id)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004713{
4714 drm_i915_private_t *dev_priv = dev->dev_private;
4715 struct drm_i915_gem_phys_object *phys_obj;
4716
4717 if (!dev_priv->mm.phys_objs[id - 1])
4718 return;
4719
4720 phys_obj = dev_priv->mm.phys_objs[id - 1];
4721 if (phys_obj->cur_obj) {
4722 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4723 }
4724
4725#ifdef CONFIG_X86
4726 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4727#endif
4728 drm_pci_free(dev, phys_obj->handle);
4729 kfree(phys_obj);
4730 dev_priv->mm.phys_objs[id - 1] = NULL;
4731}
4732
4733void i915_gem_free_all_phys_object(struct drm_device *dev)
4734{
4735 int i;
4736
Dave Airlie260883c2009-01-22 17:58:49 +10004737 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004738 i915_gem_free_phys_object(dev, i);
4739}
4740
4741void i915_gem_detach_phys_object(struct drm_device *dev,
4742 struct drm_gem_object *obj)
4743{
4744 struct drm_i915_gem_object *obj_priv;
4745 int i;
4746 int ret;
4747 int page_count;
4748
Daniel Vetter23010e42010-03-08 13:35:02 +01004749 obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004750 if (!obj_priv->phys_obj)
4751 return;
4752
Chris Wilson4bdadb92010-01-27 13:36:32 +00004753 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004754 if (ret)
4755 goto out;
4756
4757 page_count = obj->size / PAGE_SIZE;
4758
4759 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004760 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004761 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4762
4763 memcpy(dst, src, PAGE_SIZE);
4764 kunmap_atomic(dst, KM_USER0);
4765 }
Eric Anholt856fa192009-03-19 14:10:50 -07004766 drm_clflush_pages(obj_priv->pages, page_count);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004767 drm_agp_chipset_flush(dev);
Chris Wilsond78b47b2009-06-17 21:52:49 +01004768
4769 i915_gem_object_put_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004770out:
4771 obj_priv->phys_obj->cur_obj = NULL;
4772 obj_priv->phys_obj = NULL;
4773}
4774
4775int
4776i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01004777 struct drm_gem_object *obj,
4778 int id,
4779 int align)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004780{
4781 drm_i915_private_t *dev_priv = dev->dev_private;
4782 struct drm_i915_gem_object *obj_priv;
4783 int ret = 0;
4784 int page_count;
4785 int i;
4786
4787 if (id > I915_MAX_PHYS_OBJECT)
4788 return -EINVAL;
4789
Daniel Vetter23010e42010-03-08 13:35:02 +01004790 obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004791
4792 if (obj_priv->phys_obj) {
4793 if (obj_priv->phys_obj->id == id)
4794 return 0;
4795 i915_gem_detach_phys_object(dev, obj);
4796 }
4797
Dave Airlie71acb5e2008-12-30 20:31:46 +10004798 /* create a new object */
4799 if (!dev_priv->mm.phys_objs[id - 1]) {
4800 ret = i915_gem_init_phys_object(dev, id,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01004801 obj->size, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004802 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08004803 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004804 goto out;
4805 }
4806 }
4807
4808 /* bind to the object */
4809 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4810 obj_priv->phys_obj->cur_obj = obj;
4811
Chris Wilson4bdadb92010-01-27 13:36:32 +00004812 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004813 if (ret) {
4814 DRM_ERROR("failed to get page list\n");
4815 goto out;
4816 }
4817
4818 page_count = obj->size / PAGE_SIZE;
4819
4820 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004821 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004822 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4823
4824 memcpy(dst, src, PAGE_SIZE);
4825 kunmap_atomic(src, KM_USER0);
4826 }
4827
Chris Wilsond78b47b2009-06-17 21:52:49 +01004828 i915_gem_object_put_pages(obj);
4829
Dave Airlie71acb5e2008-12-30 20:31:46 +10004830 return 0;
4831out:
4832 return ret;
4833}
4834
4835static int
4836i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4837 struct drm_i915_gem_pwrite *args,
4838 struct drm_file *file_priv)
4839{
Daniel Vetter23010e42010-03-08 13:35:02 +01004840 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004841 void *obj_addr;
4842 int ret;
4843 char __user *user_data;
4844
4845 user_data = (char __user *) (uintptr_t) args->data_ptr;
4846 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4847
Zhao Yakui44d98a62009-10-09 11:39:40 +08004848 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004849 ret = copy_from_user(obj_addr, user_data, args->size);
4850 if (ret)
4851 return -EFAULT;
4852
4853 drm_agp_chipset_flush(dev);
4854 return 0;
4855}
Eric Anholtb9624422009-06-03 07:27:35 +00004856
4857void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4858{
4859 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4860
4861 /* Clean up our request list when the client is going away, so that
4862 * later retire_requests won't dereference our soon-to-be-gone
4863 * file_priv.
4864 */
4865 mutex_lock(&dev->struct_mutex);
4866 while (!list_empty(&i915_file_priv->mm.request_list))
4867 list_del_init(i915_file_priv->mm.request_list.next);
4868 mutex_unlock(&dev->struct_mutex);
4869}
Chris Wilson31169712009-09-14 16:50:28 +01004870
Chris Wilson31169712009-09-14 16:50:28 +01004871static int
Chris Wilson1637ef42010-04-20 17:10:35 +01004872i915_gpu_is_active(struct drm_device *dev)
4873{
4874 drm_i915_private_t *dev_priv = dev->dev_private;
4875 int lists_empty;
4876
Chris Wilson1637ef42010-04-20 17:10:35 +01004877 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
Zou Nan hai852835f2010-05-21 09:08:56 +08004878 list_empty(&dev_priv->render_ring.active_list);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004879 if (HAS_BSD(dev))
4880 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
Chris Wilson1637ef42010-04-20 17:10:35 +01004881
4882 return !lists_empty;
4883}
4884
4885static int
Dave Chinner7f8275d2010-07-19 14:56:17 +10004886i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
Chris Wilson31169712009-09-14 16:50:28 +01004887{
4888 drm_i915_private_t *dev_priv, *next_dev;
4889 struct drm_i915_gem_object *obj_priv, *next_obj;
4890 int cnt = 0;
4891 int would_deadlock = 1;
4892
4893 /* "fast-path" to count number of available objects */
4894 if (nr_to_scan == 0) {
4895 spin_lock(&shrink_list_lock);
4896 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4897 struct drm_device *dev = dev_priv->dev;
4898
4899 if (mutex_trylock(&dev->struct_mutex)) {
4900 list_for_each_entry(obj_priv,
4901 &dev_priv->mm.inactive_list,
4902 list)
4903 cnt++;
4904 mutex_unlock(&dev->struct_mutex);
4905 }
4906 }
4907 spin_unlock(&shrink_list_lock);
4908
4909 return (cnt / 100) * sysctl_vfs_cache_pressure;
4910 }
4911
4912 spin_lock(&shrink_list_lock);
4913
Chris Wilson1637ef42010-04-20 17:10:35 +01004914rescan:
Chris Wilson31169712009-09-14 16:50:28 +01004915 /* first scan for clean buffers */
4916 list_for_each_entry_safe(dev_priv, next_dev,
4917 &shrink_list, mm.shrink_list) {
4918 struct drm_device *dev = dev_priv->dev;
4919
4920 if (! mutex_trylock(&dev->struct_mutex))
4921 continue;
4922
4923 spin_unlock(&shrink_list_lock);
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01004924 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004925
Chris Wilson31169712009-09-14 16:50:28 +01004926 list_for_each_entry_safe(obj_priv, next_obj,
4927 &dev_priv->mm.inactive_list,
4928 list) {
4929 if (i915_gem_object_is_purgeable(obj_priv)) {
Daniel Vettera8089e82010-04-09 19:05:09 +00004930 i915_gem_object_unbind(&obj_priv->base);
Chris Wilson31169712009-09-14 16:50:28 +01004931 if (--nr_to_scan <= 0)
4932 break;
4933 }
4934 }
4935
4936 spin_lock(&shrink_list_lock);
4937 mutex_unlock(&dev->struct_mutex);
4938
Chris Wilson963b4832009-09-20 23:03:54 +01004939 would_deadlock = 0;
4940
Chris Wilson31169712009-09-14 16:50:28 +01004941 if (nr_to_scan <= 0)
4942 break;
4943 }
4944
4945 /* second pass, evict/count anything still on the inactive list */
4946 list_for_each_entry_safe(dev_priv, next_dev,
4947 &shrink_list, mm.shrink_list) {
4948 struct drm_device *dev = dev_priv->dev;
4949
4950 if (! mutex_trylock(&dev->struct_mutex))
4951 continue;
4952
4953 spin_unlock(&shrink_list_lock);
4954
4955 list_for_each_entry_safe(obj_priv, next_obj,
4956 &dev_priv->mm.inactive_list,
4957 list) {
4958 if (nr_to_scan > 0) {
Daniel Vettera8089e82010-04-09 19:05:09 +00004959 i915_gem_object_unbind(&obj_priv->base);
Chris Wilson31169712009-09-14 16:50:28 +01004960 nr_to_scan--;
4961 } else
4962 cnt++;
4963 }
4964
4965 spin_lock(&shrink_list_lock);
4966 mutex_unlock(&dev->struct_mutex);
4967
4968 would_deadlock = 0;
4969 }
4970
Chris Wilson1637ef42010-04-20 17:10:35 +01004971 if (nr_to_scan) {
4972 int active = 0;
4973
4974 /*
4975 * We are desperate for pages, so as a last resort, wait
4976 * for the GPU to finish and discard whatever we can.
4977 * This has a dramatic impact to reduce the number of
4978 * OOM-killer events whilst running the GPU aggressively.
4979 */
4980 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4981 struct drm_device *dev = dev_priv->dev;
4982
4983 if (!mutex_trylock(&dev->struct_mutex))
4984 continue;
4985
4986 spin_unlock(&shrink_list_lock);
4987
4988 if (i915_gpu_is_active(dev)) {
4989 i915_gpu_idle(dev);
4990 active++;
4991 }
4992
4993 spin_lock(&shrink_list_lock);
4994 mutex_unlock(&dev->struct_mutex);
4995 }
4996
4997 if (active)
4998 goto rescan;
4999 }
5000
Chris Wilson31169712009-09-14 16:50:28 +01005001 spin_unlock(&shrink_list_lock);
5002
5003 if (would_deadlock)
5004 return -1;
5005 else if (cnt > 0)
5006 return (cnt / 100) * sysctl_vfs_cache_pressure;
5007 else
5008 return 0;
5009}
5010
5011static struct shrinker shrinker = {
5012 .shrink = i915_gem_shrink,
5013 .seeks = DEFAULT_SEEKS,
5014};
5015
5016__init void
5017i915_gem_shrinker_init(void)
5018{
5019 register_shrinker(&shrinker);
5020}
5021
5022__exit void
5023i915_gem_shrinker_exit(void)
5024{
5025 unregister_shrinker(&shrinker);
5026}