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Bob Wilsone60fee02009-06-22 23:27:02 +00001//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM NEON instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// NEON-specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19
20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
26
27// Types for vector shift by immediates. The "SHX" version is for long and
28// narrow operations where the source and destination vectors have different
29// types. The "SHINS" version is for shift and insert operations.
30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>]>;
32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
33 SDTCisVT<2, i32>]>;
34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
36
37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
44
45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
48
49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
55
56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
59
60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
62
63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
64 SDTCisVT<2, i32>]>;
65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
67
Bob Wilsonf4f1a272009-08-14 05:13:08 +000068def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
69
Bob Wilson206f6c42009-08-14 05:08:32 +000070// VDUPLANE can produce a quad-register result from a double-register source,
71// so the result is not constrained to match the source.
72def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
74 SDTCisVT<2, i32>]>>;
Bob Wilsone60fee02009-06-22 23:27:02 +000075
Bob Wilson3ac39132009-08-19 17:03:43 +000076def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
79
Bob Wilson08479272009-08-12 22:31:50 +000080def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
84
Anton Korobeynikovbe262ae2009-08-21 12:40:50 +000085def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
Bob Wilson1d2c4212010-02-17 00:31:29 +000086 SDTCisSameAs<0, 2>,
87 SDTCisSameAs<0, 3>]>;
Anton Korobeynikov394bbb82009-08-21 12:41:42 +000088def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
Anton Korobeynikovbe262ae2009-08-21 12:40:50 +000091
Bob Wilsonbc1d2dc2010-02-18 06:05:53 +000092def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
93 SDTCisSameAs<0, 2>]>;
94def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
96
Bob Wilsone60fee02009-06-22 23:27:02 +000097//===----------------------------------------------------------------------===//
98// NEON operand definitions
99//===----------------------------------------------------------------------===//
100
Bob Wilson6a14a002009-11-06 23:33:28 +0000101def h8imm : Operand<i8> {
102 let PrintMethod = "printHex8ImmOperand";
103}
104def h16imm : Operand<i16> {
105 let PrintMethod = "printHex16ImmOperand";
106}
107def h32imm : Operand<i32> {
108 let PrintMethod = "printHex32ImmOperand";
109}
110def h64imm : Operand<i64> {
111 let PrintMethod = "printHex64ImmOperand";
112}
113
Bob Wilsone60fee02009-06-22 23:27:02 +0000114//===----------------------------------------------------------------------===//
115// NEON load / store instructions
116//===----------------------------------------------------------------------===//
117
Bob Wilsone60fee02009-06-22 23:27:02 +0000118// Use vldmia to load a Q register as a D register pair.
Bob Wilson1d2c4212010-02-17 00:31:29 +0000119def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
120 "vldmia", "$addr, ${dst:dregpair}",
121 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
Evan Chengdabc6c02009-07-08 22:51:32 +0000122 let Inst{27-25} = 0b110;
123 let Inst{24} = 0; // P bit
124 let Inst{23} = 1; // U bit
125 let Inst{20} = 1;
Johnny Chen6e1b1ad2009-12-01 17:37:06 +0000126 let Inst{11-8} = 0b1011;
Evan Chengdabc6c02009-07-08 22:51:32 +0000127}
Bob Wilsone60fee02009-06-22 23:27:02 +0000128
Bob Wilson66b34002009-08-12 17:04:56 +0000129// Use vstmia to store a Q register as a D register pair.
Bob Wilson1d2c4212010-02-17 00:31:29 +0000130def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
131 "vstmia", "$addr, ${src:dregpair}",
132 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
Bob Wilson66b34002009-08-12 17:04:56 +0000133 let Inst{27-25} = 0b110;
134 let Inst{24} = 0; // P bit
135 let Inst{23} = 1; // U bit
136 let Inst{20} = 0;
Johnny Chen6e1b1ad2009-12-01 17:37:06 +0000137 let Inst{11-8} = 0b1011;
Bob Wilson66b34002009-08-12 17:04:56 +0000138}
139
Bob Wilsoned592c02009-07-08 18:11:30 +0000140// VLD1 : Vector Load (multiple single elements)
Bob Wilson70709822010-03-18 20:18:39 +0000141class VLD1D<bits<4> op7_4, string Dt, ValueType Ty>
Bob Wilsonb1721162009-10-07 21:53:04 +0000142 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
Bob Wilson70709822010-03-18 20:18:39 +0000143 "vld1", Dt, "\\{$dst\\}, $addr", "",
144 [(set DPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
145class VLD1Q<bits<4> op7_4, string Dt, ValueType Ty>
Bob Wilsonb1721162009-10-07 21:53:04 +0000146 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
Bob Wilson70709822010-03-18 20:18:39 +0000147 "vld1", Dt, "${dst:dregpair}, $addr", "",
148 [(set QPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000149
Bob Wilson70709822010-03-18 20:18:39 +0000150def VLD1d8 : VLD1D<0b0000, "8", v8i8>;
151def VLD1d16 : VLD1D<0b0100, "16", v4i16>;
152def VLD1d32 : VLD1D<0b1000, "32", v2i32>;
153def VLD1df : VLD1D<0b1000, "32", v2f32>;
154def VLD1d64 : VLD1D<0b1100, "64", v1i64>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000155
Bob Wilson70709822010-03-18 20:18:39 +0000156def VLD1q8 : VLD1Q<0b0000, "8", v16i8>;
157def VLD1q16 : VLD1Q<0b0100, "16", v8i16>;
158def VLD1q32 : VLD1Q<0b1000, "32", v4i32>;
159def VLD1qf : VLD1Q<0b1000, "32", v4f32>;
160def VLD1q64 : VLD1Q<0b1100, "64", v2i64>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000161
Bob Wilson06ce5bf2010-03-20 17:59:03 +0000162let mayLoad = 1 in {
163
164// ...with address register writeback:
165class VLD1DWB<bits<4> op7_4, string Dt>
166 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
167 (ins addrmode6:$addr), IIC_VLD1,
168 "vld1", Dt, "\\{$dst\\}, $addr",
169 "$addr.addr = $wb", []>;
170class VLD1QWB<bits<4> op7_4, string Dt>
171 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
172 (ins addrmode6:$addr), IIC_VLD1,
173 "vld1", Dt, "${dst:dregpair}, $addr",
174 "$addr.addr = $wb", []>;
175
176def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
177def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
178def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
179def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
180
181def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
182def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
183def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
184def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
185} // mayLoad = 1
186
187let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
188
Johnny Chen39fb1242010-02-23 20:51:23 +0000189// These (dreg triple/quadruple) are for disassembly only.
Bob Wilson70709822010-03-18 20:18:39 +0000190class VLD1D3<bits<4> op7_4, string Dt>
Johnny Chen39fb1242010-02-23 20:51:23 +0000191 : NLdSt<0, 0b10, 0b0110, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
Bob Wilson70709822010-03-18 20:18:39 +0000192 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
Johnny Chen39fb1242010-02-23 20:51:23 +0000193 "\\{$dst1, $dst2, $dst3\\}, $addr", "",
194 [/* For disassembly only; pattern left blank */]>;
Bob Wilson70709822010-03-18 20:18:39 +0000195class VLD1D4<bits<4> op7_4, string Dt>
Johnny Chen39fb1242010-02-23 20:51:23 +0000196 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
Bob Wilson70709822010-03-18 20:18:39 +0000197 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
Johnny Chen39fb1242010-02-23 20:51:23 +0000198 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
199 [/* For disassembly only; pattern left blank */]>;
200
Bob Wilson70709822010-03-18 20:18:39 +0000201def VLD1d8T : VLD1D3<0b0000, "8">;
202def VLD1d16T : VLD1D3<0b0100, "16">;
203def VLD1d32T : VLD1D3<0b1000, "32">;
204//def VLD1d64T : VLD1D3<0b1100, "64">;
Johnny Chen39fb1242010-02-23 20:51:23 +0000205
Bob Wilson70709822010-03-18 20:18:39 +0000206def VLD1d8Q : VLD1D4<0b0000, "8">;
207def VLD1d16Q : VLD1D4<0b0100, "16">;
208def VLD1d32Q : VLD1D4<0b1000, "32">;
209//def VLD1d64Q : VLD1D4<0b1100, "64">;
Johnny Chen39fb1242010-02-23 20:51:23 +0000210
Bob Wilson06ce5bf2010-03-20 17:59:03 +0000211// ...with address register writeback:
212class VLD1D3WB<bits<4> op7_4, string Dt>
213 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
214 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
215 "\\{$dst1, $dst2, $dst3\\}, $addr", "$addr.addr = $wb",
216 [/* For disassembly only; pattern left blank */]>;
217class VLD1D4WB<bits<4> op7_4, string Dt>
218 : NLdSt<0,0b10,0b0010,op7_4,
219 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
220 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
221 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "$addr.addr = $wb",
222 [/* For disassembly only; pattern left blank */]>;
Johnny Chen39fb1242010-02-23 20:51:23 +0000223
Bob Wilson06ce5bf2010-03-20 17:59:03 +0000224def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
225def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
226def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
227// VLD1d64T_UPD : implemented as VLD3d64_UPD
228
229def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
230def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
231def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
232// VLD1d64Q_UPD : implemented as VLD4d64_UPD
Bob Wilson66b34002009-08-12 17:04:56 +0000233
Bob Wilson055a90d2009-08-05 00:49:09 +0000234// VLD2 : Vector Load (multiple 2-element structures)
Bob Wilson70709822010-03-18 20:18:39 +0000235class VLD2D<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000236 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
237 (ins addrmode6:$addr), IIC_VLD2,
Bob Wilson70709822010-03-18 20:18:39 +0000238 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
239class VLD2Q<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000240 : NLdSt<0,0b10,0b0011,op7_4,
241 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
Bob Wilsone9829ca2009-10-06 22:01:59 +0000242 (ins addrmode6:$addr), IIC_VLD2,
Bob Wilson70709822010-03-18 20:18:39 +0000243 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
Bob Wilson055a90d2009-08-05 00:49:09 +0000244
Bob Wilson70709822010-03-18 20:18:39 +0000245def VLD2d8 : VLD2D<0b0000, "8">;
246def VLD2d16 : VLD2D<0b0100, "16">;
247def VLD2d32 : VLD2D<0b1000, "32">;
Bob Wilson8c3be582009-10-07 22:57:01 +0000248def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
249 (ins addrmode6:$addr), IIC_VLD1,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000250 "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
Bob Wilson055a90d2009-08-05 00:49:09 +0000251
Bob Wilson70709822010-03-18 20:18:39 +0000252def VLD2q8 : VLD2Q<0b0000, "8">;
253def VLD2q16 : VLD2Q<0b0100, "16">;
254def VLD2q32 : VLD2Q<0b1000, "32">;
Bob Wilsone9829ca2009-10-06 22:01:59 +0000255
Johnny Chen39fb1242010-02-23 20:51:23 +0000256// These (double-spaced dreg pair) are for disassembly only.
Bob Wilson70709822010-03-18 20:18:39 +0000257class VLD2Ddbl<bits<4> op7_4, string Dt>
Johnny Chen39fb1242010-02-23 20:51:23 +0000258 : NLdSt<0,0b10,0b1001,op7_4, (outs DPR:$dst1, DPR:$dst2),
259 (ins addrmode6:$addr), IIC_VLD2,
Bob Wilson70709822010-03-18 20:18:39 +0000260 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
Johnny Chen39fb1242010-02-23 20:51:23 +0000261
Bob Wilson70709822010-03-18 20:18:39 +0000262def VLD2d8D : VLD2Ddbl<0b0000, "8">;
263def VLD2d16D : VLD2Ddbl<0b0100, "16">;
264def VLD2d32D : VLD2Ddbl<0b1000, "32">;
Johnny Chen39fb1242010-02-23 20:51:23 +0000265
Bob Wilson055a90d2009-08-05 00:49:09 +0000266// VLD3 : Vector Load (multiple 3-element structures)
Bob Wilson70709822010-03-18 20:18:39 +0000267class VLD3D<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000268 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
269 (ins addrmode6:$addr), IIC_VLD3,
Bob Wilson70709822010-03-18 20:18:39 +0000270 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
271class VLD3WB<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000272 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
Bob Wilsona8b43622009-10-07 17:24:55 +0000273 (ins addrmode6:$addr), IIC_VLD3,
Bob Wilson70709822010-03-18 20:18:39 +0000274 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
Johnny Chen7c3f3862010-03-17 23:26:50 +0000275 "$addr.addr = $wb", []>;
Bob Wilson055a90d2009-08-05 00:49:09 +0000276
Bob Wilson70709822010-03-18 20:18:39 +0000277def VLD3d8 : VLD3D<0b0000, "8">;
278def VLD3d16 : VLD3D<0b0100, "16">;
279def VLD3d32 : VLD3D<0b1000, "32">;
Bob Wilsonda8cacc2009-10-07 23:39:57 +0000280def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
281 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
282 (ins addrmode6:$addr), IIC_VLD1,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000283 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
Bob Wilson055a90d2009-08-05 00:49:09 +0000284
Bob Wilsona8b43622009-10-07 17:24:55 +0000285// vld3 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000286def VLD3q8a : VLD3WB<0b0000, "8">;
287def VLD3q16a : VLD3WB<0b0100, "16">;
288def VLD3q32a : VLD3WB<0b1000, "32">;
Bob Wilsona8b43622009-10-07 17:24:55 +0000289
290// vld3 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000291def VLD3q8b : VLD3WB<0b0000, "8">;
292def VLD3q16b : VLD3WB<0b0100, "16">;
293def VLD3q32b : VLD3WB<0b1000, "32">;
Bob Wilsona8b43622009-10-07 17:24:55 +0000294
Bob Wilson055a90d2009-08-05 00:49:09 +0000295// VLD4 : Vector Load (multiple 4-element structures)
Bob Wilson70709822010-03-18 20:18:39 +0000296class VLD4D<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000297 : NLdSt<0,0b10,0b0000,op7_4,
298 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
David Goodwin78caa122009-09-23 21:38:08 +0000299 (ins addrmode6:$addr), IIC_VLD4,
Bob Wilson70709822010-03-18 20:18:39 +0000300 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
301class VLD4WB<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000302 : NLdSt<0,0b10,0b0001,op7_4,
303 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
Bob Wilson004a2e12009-10-07 18:09:32 +0000304 (ins addrmode6:$addr), IIC_VLD4,
Bob Wilson70709822010-03-18 20:18:39 +0000305 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
Johnny Chen7c3f3862010-03-17 23:26:50 +0000306 "$addr.addr = $wb", []>;
Bob Wilson055a90d2009-08-05 00:49:09 +0000307
Bob Wilson70709822010-03-18 20:18:39 +0000308def VLD4d8 : VLD4D<0b0000, "8">;
309def VLD4d16 : VLD4D<0b0100, "16">;
310def VLD4d32 : VLD4D<0b1000, "32">;
Bob Wilson7ce47502009-10-07 23:54:04 +0000311def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
312 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
313 (ins addrmode6:$addr), IIC_VLD1,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000314 "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
315 "", []>;
Bob Wilsond14b8b62009-09-01 04:26:28 +0000316
Bob Wilson004a2e12009-10-07 18:09:32 +0000317// vld4 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000318def VLD4q8a : VLD4WB<0b0000, "8">;
319def VLD4q16a : VLD4WB<0b0100, "16">;
320def VLD4q32a : VLD4WB<0b1000, "32">;
Bob Wilson004a2e12009-10-07 18:09:32 +0000321
322// vld4 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000323def VLD4q8b : VLD4WB<0b0000, "8">;
324def VLD4q16b : VLD4WB<0b0100, "16">;
325def VLD4q32b : VLD4WB<0b1000, "32">;
Bob Wilsonb1721162009-10-07 21:53:04 +0000326
327// VLD1LN : Vector Load (single element to one lane)
328// FIXME: Not yet implemented.
Bob Wilson004a2e12009-10-07 18:09:32 +0000329
Bob Wilsond14b8b62009-09-01 04:26:28 +0000330// VLD2LN : Vector Load (single 2-element structure to one lane)
Bob Wilson70709822010-03-18 20:18:39 +0000331class VLD2LN<bits<4> op11_8, string Dt>
Johnny Chen46f784e2009-11-23 18:16:16 +0000332 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
Evan Cheng09c61b32009-11-23 21:57:23 +0000333 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
Bob Wilson70709822010-03-18 20:18:39 +0000334 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
Evan Cheng09c61b32009-11-23 21:57:23 +0000335 "$src1 = $dst1, $src2 = $dst2", []>;
Bob Wilsond14b8b62009-09-01 04:26:28 +0000336
Johnny Chen9a5dc8b2009-11-19 19:20:17 +0000337// vld2 to single-spaced registers.
Bob Wilson70709822010-03-18 20:18:39 +0000338def VLD2LNd8 : VLD2LN<0b0001, "8">;
339def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
340def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
Bob Wilson5687d8a2009-10-08 18:56:10 +0000341
342// vld2 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000343def VLD2LNq16a: VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
344def VLD2LNq32a: VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
Bob Wilson5687d8a2009-10-08 18:56:10 +0000345
346// vld2 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000347def VLD2LNq16b: VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
348def VLD2LNq32b: VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
Bob Wilsond14b8b62009-09-01 04:26:28 +0000349
350// VLD3LN : Vector Load (single 3-element structure to one lane)
Bob Wilson70709822010-03-18 20:18:39 +0000351class VLD3LN<bits<4> op11_8, string Dt>
Johnny Chen46f784e2009-11-23 18:16:16 +0000352 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
Evan Cheng09c61b32009-11-23 21:57:23 +0000353 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
Bob Wilson70709822010-03-18 20:18:39 +0000354 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000355 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
Evan Cheng09c61b32009-11-23 21:57:23 +0000356 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
Bob Wilsond14b8b62009-09-01 04:26:28 +0000357
Johnny Chen9a5dc8b2009-11-19 19:20:17 +0000358// vld3 to single-spaced registers.
Bob Wilson70709822010-03-18 20:18:39 +0000359def VLD3LNd8 : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
360def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
361def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
Bob Wilson47a1ff62009-10-08 22:27:33 +0000362
363// vld3 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000364def VLD3LNq16a: VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
365def VLD3LNq32a: VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
Bob Wilson47a1ff62009-10-08 22:27:33 +0000366
367// vld3 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000368def VLD3LNq16b: VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
369def VLD3LNq32b: VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
Bob Wilsond14b8b62009-09-01 04:26:28 +0000370
371// VLD4LN : Vector Load (single 4-element structure to one lane)
Bob Wilson70709822010-03-18 20:18:39 +0000372class VLD4LN<bits<4> op11_8, string Dt>
Johnny Chen46f784e2009-11-23 18:16:16 +0000373 : NLdSt<1,0b10,op11_8,{?,?,?,?},
Evan Cheng09c61b32009-11-23 21:57:23 +0000374 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
375 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
Bob Wilson70709822010-03-18 20:18:39 +0000376 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000377 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
Evan Cheng09c61b32009-11-23 21:57:23 +0000378 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
Bob Wilsond14b8b62009-09-01 04:26:28 +0000379
Johnny Chen9a5dc8b2009-11-19 19:20:17 +0000380// vld4 to single-spaced registers.
Bob Wilson70709822010-03-18 20:18:39 +0000381def VLD4LNd8 : VLD4LN<0b0011, "8">;
382def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
383def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
Bob Wilson7a8c6df2009-10-08 22:53:57 +0000384
385// vld4 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000386def VLD4LNq16a: VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
387def VLD4LNq32a: VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
Bob Wilson7a8c6df2009-10-08 22:53:57 +0000388
389// vld4 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000390def VLD4LNq16b: VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
391def VLD4LNq32b: VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
Bob Wilsonb1721162009-10-07 21:53:04 +0000392
393// VLD1DUP : Vector Load (single element to all lanes)
394// VLD2DUP : Vector Load (single 2-element structure to all lanes)
395// VLD3DUP : Vector Load (single 3-element structure to all lanes)
396// VLD4DUP : Vector Load (single 4-element structure to all lanes)
397// FIXME: Not yet implemented.
Evan Cheng7c8d5ea2009-10-01 08:22:27 +0000398} // mayLoad = 1, hasExtraDefRegAllocReq = 1
Bob Wilsonee27bec2009-08-12 00:49:01 +0000399
Bob Wilson6a209cd2009-08-06 18:47:44 +0000400// VST1 : Vector Store (multiple single elements)
Bob Wilson70709822010-03-18 20:18:39 +0000401class VST1D<bits<4> op7_4, string Dt, ValueType Ty>
Bob Wilsonb1721162009-10-07 21:53:04 +0000402 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000403 "vst1", Dt, "\\{$src\\}, $addr", "",
404 [(int_arm_neon_vst1 addrmode6:$addr, (Ty DPR:$src))]>;
405class VST1Q<bits<4> op7_4, string Dt, ValueType Ty>
Bob Wilsonb1721162009-10-07 21:53:04 +0000406 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000407 "vst1", Dt, "${src:dregpair}, $addr", "",
408 [(int_arm_neon_vst1 addrmode6:$addr, (Ty QPR:$src))]>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000409
Evan Cheng7c8d5ea2009-10-01 08:22:27 +0000410let hasExtraSrcRegAllocReq = 1 in {
Bob Wilson70709822010-03-18 20:18:39 +0000411def VST1d8 : VST1D<0b0000, "8", v8i8>;
412def VST1d16 : VST1D<0b0100, "16", v4i16>;
413def VST1d32 : VST1D<0b1000, "32", v2i32>;
414def VST1df : VST1D<0b1000, "32", v2f32>;
415def VST1d64 : VST1D<0b1100, "64", v1i64>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000416
Bob Wilson70709822010-03-18 20:18:39 +0000417def VST1q8 : VST1Q<0b0000, "8", v16i8>;
418def VST1q16 : VST1Q<0b0100, "16", v8i16>;
419def VST1q32 : VST1Q<0b1000, "32", v4i32>;
420def VST1qf : VST1Q<0b1000, "32", v4f32>;
421def VST1q64 : VST1Q<0b1100, "64", v2i64>;
Evan Cheng7c8d5ea2009-10-01 08:22:27 +0000422} // hasExtraSrcRegAllocReq
Bob Wilson6a209cd2009-08-06 18:47:44 +0000423
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000424// These (dreg triple/quadruple) are for disassembly only.
Bob Wilson70709822010-03-18 20:18:39 +0000425class VST1D3<bits<4> op7_4, string Dt>
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000426 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
427 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000428 "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "",
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000429 [/* For disassembly only; pattern left blank */]>;
Bob Wilson70709822010-03-18 20:18:39 +0000430class VST1D4<bits<4> op7_4, string Dt>
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000431 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
432 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
Bob Wilson70709822010-03-18 20:18:39 +0000433 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000434 [/* For disassembly only; pattern left blank */]>;
435
Bob Wilson70709822010-03-18 20:18:39 +0000436def VST1d8T : VST1D3<0b0000, "8">;
437def VST1d16T : VST1D3<0b0100, "16">;
438def VST1d32T : VST1D3<0b1000, "32">;
439//def VST1d64T : VST1D3<0b1100, "64">;
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000440
Bob Wilson70709822010-03-18 20:18:39 +0000441def VST1d8Q : VST1D4<0b0000, "8">;
442def VST1d16Q : VST1D4<0b0100, "16">;
443def VST1d32Q : VST1D4<0b1000, "32">;
444//def VST1d64Q : VST1D4<0b1100, "64">;
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000445
446
Evan Cheng7c8d5ea2009-10-01 08:22:27 +0000447let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
Bob Wilson66b34002009-08-12 17:04:56 +0000448
Bob Wilson6a209cd2009-08-06 18:47:44 +0000449// VST2 : Vector Store (multiple 2-element structures)
Bob Wilson70709822010-03-18 20:18:39 +0000450class VST2D<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000451 : NLdSt<0,0b00,0b1000,op7_4, (outs),
452 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000453 "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
454class VST2Q<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000455 : NLdSt<0,0b00,0b0011,op7_4, (outs),
456 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
Bob Wilson70709822010-03-18 20:18:39 +0000457 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
Bob Wilson5fa67d352009-10-07 18:47:39 +0000458 "", []>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000459
Bob Wilson70709822010-03-18 20:18:39 +0000460def VST2d8 : VST2D<0b0000, "8">;
461def VST2d16 : VST2D<0b0100, "16">;
462def VST2d32 : VST2D<0b1000, "32">;
Bob Wilsondd43d1e2009-10-08 00:21:01 +0000463def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
464 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000465 "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000466
Bob Wilson70709822010-03-18 20:18:39 +0000467def VST2q8 : VST2Q<0b0000, "8">;
468def VST2q16 : VST2Q<0b0100, "16">;
469def VST2q32 : VST2Q<0b1000, "32">;
Bob Wilson5fa67d352009-10-07 18:47:39 +0000470
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000471// These (double-spaced dreg pair) are for disassembly only.
Bob Wilson70709822010-03-18 20:18:39 +0000472class VST2Ddbl<bits<4> op7_4, string Dt>
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000473 : NLdSt<0, 0b00, 0b1001, op7_4, (outs),
474 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000475 "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000476
Bob Wilson70709822010-03-18 20:18:39 +0000477def VST2d8D : VST2Ddbl<0b0000, "8">;
478def VST2d16D : VST2Ddbl<0b0100, "16">;
479def VST2d32D : VST2Ddbl<0b1000, "32">;
Johnny Chen30c6aeb2010-02-24 02:57:20 +0000480
Bob Wilson6a209cd2009-08-06 18:47:44 +0000481// VST3 : Vector Store (multiple 3-element structures)
Bob Wilson70709822010-03-18 20:18:39 +0000482class VST3D<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000483 : NLdSt<0,0b00,0b0100,op7_4, (outs),
484 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000485 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
486class VST3WB<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000487 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
488 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
Bob Wilson70709822010-03-18 20:18:39 +0000489 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr",
Johnny Chen7c3f3862010-03-17 23:26:50 +0000490 "$addr.addr = $wb", []>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000491
Bob Wilson70709822010-03-18 20:18:39 +0000492def VST3d8 : VST3D<0b0000, "8">;
493def VST3d16 : VST3D<0b0100, "16">;
494def VST3d32 : VST3D<0b1000, "32">;
Bob Wilson7200e5d2009-10-08 00:28:28 +0000495def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
496 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
497 IIC_VST,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000498 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000499
Bob Wilson2a85bd12009-10-07 20:30:08 +0000500// vst3 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000501def VST3q8a : VST3WB<0b0000, "8">;
502def VST3q16a : VST3WB<0b0100, "16">;
503def VST3q32a : VST3WB<0b1000, "32">;
Bob Wilson2a85bd12009-10-07 20:30:08 +0000504
505// vst3 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000506def VST3q8b : VST3WB<0b0000, "8">;
507def VST3q16b : VST3WB<0b0100, "16">;
508def VST3q32b : VST3WB<0b1000, "32">;
Bob Wilson2a85bd12009-10-07 20:30:08 +0000509
Bob Wilson6a209cd2009-08-06 18:47:44 +0000510// VST4 : Vector Store (multiple 4-element structures)
Bob Wilson70709822010-03-18 20:18:39 +0000511class VST4D<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000512 : NLdSt<0,0b00,0b0000,op7_4, (outs),
513 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
Bob Wilson70709822010-03-18 20:18:39 +0000514 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
Bob Wilson316062a2009-08-25 17:46:06 +0000515 "", []>;
Bob Wilson70709822010-03-18 20:18:39 +0000516class VST4WB<bits<4> op7_4, string Dt>
Bob Wilsonb1721162009-10-07 21:53:04 +0000517 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
518 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
Bob Wilson70709822010-03-18 20:18:39 +0000519 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
Johnny Chen7c3f3862010-03-17 23:26:50 +0000520 "$addr.addr = $wb", []>;
Bob Wilson6a209cd2009-08-06 18:47:44 +0000521
Bob Wilson70709822010-03-18 20:18:39 +0000522def VST4d8 : VST4D<0b0000, "8">;
523def VST4d16 : VST4D<0b0100, "16">;
524def VST4d32 : VST4D<0b1000, "32">;
Bob Wilson94b5d432009-10-08 05:18:18 +0000525def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
526 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
527 DPR:$src4), IIC_VST,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000528 "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
529 "", []>;
Bob Wilsonc2d65852009-09-01 18:51:56 +0000530
Bob Wilson931c76b2009-10-07 20:49:18 +0000531// vst4 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000532def VST4q8a : VST4WB<0b0000, "8">;
533def VST4q16a : VST4WB<0b0100, "16">;
534def VST4q32a : VST4WB<0b1000, "32">;
Bob Wilson931c76b2009-10-07 20:49:18 +0000535
536// vst4 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000537def VST4q8b : VST4WB<0b0000, "8">;
538def VST4q16b : VST4WB<0b0100, "16">;
539def VST4q32b : VST4WB<0b1000, "32">;
Bob Wilsonb1721162009-10-07 21:53:04 +0000540
541// VST1LN : Vector Store (single element from one lane)
542// FIXME: Not yet implemented.
Bob Wilson931c76b2009-10-07 20:49:18 +0000543
Bob Wilsonc2d65852009-09-01 18:51:56 +0000544// VST2LN : Vector Store (single 2-element structure from one lane)
Bob Wilson70709822010-03-18 20:18:39 +0000545class VST2LN<bits<4> op11_8, string Dt>
Johnny Chen46f784e2009-11-23 18:16:16 +0000546 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000547 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
Bob Wilson70709822010-03-18 20:18:39 +0000548 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
Bob Wilson1d2c4212010-02-17 00:31:29 +0000549 "", []>;
Bob Wilsonc2d65852009-09-01 18:51:56 +0000550
Johnny Chen9a5dc8b2009-11-19 19:20:17 +0000551// vst2 to single-spaced registers.
Bob Wilson70709822010-03-18 20:18:39 +0000552def VST2LNd8 : VST2LN<0b0001, "8">;
553def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
554def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
Bob Wilson18e94a72009-10-08 23:38:24 +0000555
556// vst2 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000557def VST2LNq16a: VST2LN<0b0101, "16"> { let Inst{5} = 1; }
558def VST2LNq32a: VST2LN<0b1001, "32"> { let Inst{6} = 1; }
Bob Wilson18e94a72009-10-08 23:38:24 +0000559
560// vst2 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000561def VST2LNq16b: VST2LN<0b0101, "16"> { let Inst{5} = 1; }
562def VST2LNq32b: VST2LN<0b1001, "32"> { let Inst{6} = 1; }
Bob Wilsonc2d65852009-09-01 18:51:56 +0000563
564// VST3LN : Vector Store (single 3-element structure from one lane)
Bob Wilson70709822010-03-18 20:18:39 +0000565class VST3LN<bits<4> op11_8, string Dt>
Johnny Chen46f784e2009-11-23 18:16:16 +0000566 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000567 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
Bob Wilson70709822010-03-18 20:18:39 +0000568 nohash_imm:$lane), IIC_VST, "vst3", Dt,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000569 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
Bob Wilsonc2d65852009-09-01 18:51:56 +0000570
Johnny Chen9a5dc8b2009-11-19 19:20:17 +0000571// vst3 to single-spaced registers.
Bob Wilson70709822010-03-18 20:18:39 +0000572def VST3LNd8 : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
573def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
574def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
Bob Wilsondbffb212009-10-08 23:51:31 +0000575
576// vst3 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000577def VST3LNq16a: VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
578def VST3LNq32a: VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
Bob Wilsondbffb212009-10-08 23:51:31 +0000579
580// vst3 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000581def VST3LNq16b: VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
582def VST3LNq32b: VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
Bob Wilsonc2d65852009-09-01 18:51:56 +0000583
584// VST4LN : Vector Store (single 4-element structure from one lane)
Bob Wilson70709822010-03-18 20:18:39 +0000585class VST4LN<bits<4> op11_8, string Dt>
Johnny Chen46f784e2009-11-23 18:16:16 +0000586 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000587 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
Bob Wilson70709822010-03-18 20:18:39 +0000588 nohash_imm:$lane), IIC_VST, "vst4", Dt,
Bob Wilson82dcfa32010-01-18 01:24:43 +0000589 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
Bob Wilson1d2c4212010-02-17 00:31:29 +0000590 "", []>;
Bob Wilsonc2d65852009-09-01 18:51:56 +0000591
Johnny Chen9a5dc8b2009-11-19 19:20:17 +0000592// vst4 to single-spaced registers.
Bob Wilson70709822010-03-18 20:18:39 +0000593def VST4LNd8 : VST4LN<0b0011, "8">;
594def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
595def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
Bob Wilsonc7692e02009-10-09 00:01:36 +0000596
597// vst4 to double-spaced even registers.
Bob Wilson70709822010-03-18 20:18:39 +0000598def VST4LNq16a: VST4LN<0b0111, "16"> { let Inst{5} = 1; }
599def VST4LNq32a: VST4LN<0b1011, "32"> { let Inst{6} = 1; }
Bob Wilsonc7692e02009-10-09 00:01:36 +0000600
601// vst4 to double-spaced odd registers.
Bob Wilson70709822010-03-18 20:18:39 +0000602def VST4LNq16b: VST4LN<0b0111, "16"> { let Inst{5} = 1; }
603def VST4LNq32b: VST4LN<0b1011, "32"> { let Inst{6} = 1; }
Bob Wilsonc7692e02009-10-09 00:01:36 +0000604
Evan Cheng7c8d5ea2009-10-01 08:22:27 +0000605} // mayStore = 1, hasExtraSrcRegAllocReq = 1
Bob Wilson6a209cd2009-08-06 18:47:44 +0000606
Bob Wilsoned592c02009-07-08 18:11:30 +0000607
Bob Wilsone60fee02009-06-22 23:27:02 +0000608//===----------------------------------------------------------------------===//
609// NEON pattern fragments
610//===----------------------------------------------------------------------===//
611
612// Extract D sub-registers of Q registers.
613// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
Anton Korobeynikov49284e72009-08-08 14:06:07 +0000614def DSubReg_i8_reg : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000615 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000616}]>;
Anton Korobeynikov49284e72009-08-08 14:06:07 +0000617def DSubReg_i16_reg : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000618 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000619}]>;
Anton Korobeynikov49284e72009-08-08 14:06:07 +0000620def DSubReg_i32_reg : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000621 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000622}]>;
Anton Korobeynikov49284e72009-08-08 14:06:07 +0000623def DSubReg_f64_reg : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000624 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000625}]>;
Anton Korobeynikovb261a192009-09-02 21:21:28 +0000626def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
627 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
628}]>;
Bob Wilsone60fee02009-06-22 23:27:02 +0000629
Anton Korobeynikov44e0a6c2009-08-28 23:41:26 +0000630// Extract S sub-registers of Q/D registers.
Anton Korobeynikov49284e72009-08-08 14:06:07 +0000631// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
632def SSubReg_f32_reg : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000633 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
Anton Korobeynikov49284e72009-08-08 14:06:07 +0000634}]>;
635
Bob Wilsone60fee02009-06-22 23:27:02 +0000636// Translate lane numbers from Q registers to D subregs.
637def SubReg_i8_lane : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000638 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000639}]>;
640def SubReg_i16_lane : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000641 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000642}]>;
643def SubReg_i32_lane : SDNodeXForm<imm, [{
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000644 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
Bob Wilsone60fee02009-06-22 23:27:02 +0000645}]>;
646
647//===----------------------------------------------------------------------===//
648// Instruction Classes
649//===----------------------------------------------------------------------===//
650
Bob Wilson154999f2010-02-17 22:23:11 +0000651// Basic 2-register operations: single-, double- and quad-register.
652class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
653 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
654 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
655 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
656 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
657 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
Bob Wilsone60fee02009-06-22 23:27:02 +0000658class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Bob Wilson154999f2010-02-17 22:23:11 +0000659 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
660 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
Bob Wilsone60fee02009-06-22 23:27:02 +0000661 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +0000662 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000663 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
664class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Bob Wilson154999f2010-02-17 22:23:11 +0000665 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
666 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
Bob Wilsone60fee02009-06-22 23:27:02 +0000667 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +0000668 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000669 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
670
Bob Wilson7c7fe6e2010-02-17 22:42:54 +0000671// Basic 2-register intrinsics, both double- and quad-register.
Bob Wilsone60fee02009-06-22 23:27:02 +0000672class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
David Goodwin78caa122009-09-23 21:38:08 +0000673 bits<2> op17_16, bits<5> op11_7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000674 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +0000675 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
676 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +0000677 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000678 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
679class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
David Goodwin78caa122009-09-23 21:38:08 +0000680 bits<2> op17_16, bits<5> op11_7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000681 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +0000682 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
683 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +0000684 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000685 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
686
687// Narrow 2-register intrinsics.
688class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
689 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000690 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin78caa122009-09-23 21:38:08 +0000691 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
Bob Wilsone60fee02009-06-22 23:27:02 +0000692 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +0000693 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000694 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
695
Bob Wilson52e0d9d2009-10-21 02:15:46 +0000696// Long 2-register intrinsics (currently only used for VMOVL).
697class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
698 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000699 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin78caa122009-09-23 21:38:08 +0000700 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +0000701 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +0000702 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000703 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
704
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +0000705// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
Evan Cheng09c61b32009-11-23 21:57:23 +0000706class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +0000707 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
David Goodwin78caa122009-09-23 21:38:08 +0000708 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
Evan Cheng09c61b32009-11-23 21:57:23 +0000709 OpcodeStr, Dt, "$dst1, $dst2",
Johnny Chen7c3f3862010-03-17 23:26:50 +0000710 "$src1 = $dst1, $src2 = $dst2", []>;
David Goodwin78caa122009-09-23 21:38:08 +0000711class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
Evan Cheng09c61b32009-11-23 21:57:23 +0000712 InstrItinClass itin, string OpcodeStr, string Dt>
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +0000713 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000714 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
Johnny Chen7c3f3862010-03-17 23:26:50 +0000715 "$src1 = $dst1, $src2 = $dst2", []>;
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +0000716
Bob Wilson154999f2010-02-17 22:23:11 +0000717// Basic 3-register operations: single-, double- and quad-register.
718class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
719 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
720 SDNode OpNode, bit Commutable>
721 : N3V<op24, op23, op21_20, op11_8, 0, op4,
722 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
723 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
724 let isCommutable = Commutable;
725}
726
Bob Wilsone60fee02009-06-22 23:27:02 +0000727class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000728 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000729 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
Bob Wilsone60fee02009-06-22 23:27:02 +0000730 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin78caa122009-09-23 21:38:08 +0000731 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000732 OpcodeStr, Dt, "$dst, $src1, $src2", "",
733 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
734 let isCommutable = Commutable;
735}
736// Same as N3VD but no data type.
737class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
738 InstrItinClass itin, string OpcodeStr,
739 ValueType ResTy, ValueType OpTy,
740 SDNode OpNode, bit Commutable>
741 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000742 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
743 OpcodeStr, "$dst, $src1, $src2", "",
744 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
Bob Wilsone60fee02009-06-22 23:27:02 +0000745 let isCommutable = Commutable;
746}
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000747class N3VDSL<bits<2> op21_20, bits<4> op11_8,
Evan Cheng09c61b32009-11-23 21:57:23 +0000748 InstrItinClass itin, string OpcodeStr, string Dt,
749 ValueType Ty, SDNode ShOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000750 : N3V<0, 1, op21_20, op11_8, 1, 0,
751 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +0000752 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000753 [(set (Ty DPR:$dst),
754 (Ty (ShOp (Ty DPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000755 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000756 let isCommutable = 0;
757}
758class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
Evan Cheng09c61b32009-11-23 21:57:23 +0000759 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000760 : N3V<0, 1, op21_20, op11_8, 1, 0,
761 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000762 IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000763 [(set (Ty DPR:$dst),
764 (Ty (ShOp (Ty DPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000765 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000766 let isCommutable = 0;
767}
768
Bob Wilsone60fee02009-06-22 23:27:02 +0000769class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000770 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000771 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
Bob Wilsone60fee02009-06-22 23:27:02 +0000772 : N3V<op24, op23, op21_20, op11_8, 1, op4,
David Goodwin78caa122009-09-23 21:38:08 +0000773 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000774 OpcodeStr, Dt, "$dst, $src1, $src2", "",
775 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
776 let isCommutable = Commutable;
777}
778class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
779 InstrItinClass itin, string OpcodeStr,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000780 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
Evan Cheng09c61b32009-11-23 21:57:23 +0000781 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000782 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
783 OpcodeStr, "$dst, $src1, $src2", "",
784 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
Bob Wilsone60fee02009-06-22 23:27:02 +0000785 let isCommutable = Commutable;
786}
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000787class N3VQSL<bits<2> op21_20, bits<4> op11_8,
Evan Cheng09c61b32009-11-23 21:57:23 +0000788 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +0000789 ValueType ResTy, ValueType OpTy, SDNode ShOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000790 : N3V<1, 1, op21_20, op11_8, 1, 0,
791 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +0000792 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000793 [(set (ResTy QPR:$dst),
794 (ResTy (ShOp (ResTy QPR:$src1),
795 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
796 imm:$lane)))))]> {
797 let isCommutable = 0;
798}
Bob Wilson1d2c4212010-02-17 00:31:29 +0000799class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
Evan Cheng09c61b32009-11-23 21:57:23 +0000800 ValueType ResTy, ValueType OpTy, SDNode ShOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000801 : N3V<1, 1, op21_20, op11_8, 1, 0,
802 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
Bob Wilson1d2c4212010-02-17 00:31:29 +0000803 IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000804 [(set (ResTy QPR:$dst),
805 (ResTy (ShOp (ResTy QPR:$src1),
806 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
807 imm:$lane)))))]> {
808 let isCommutable = 0;
809}
Bob Wilsone60fee02009-06-22 23:27:02 +0000810
811// Basic 3-register intrinsics, both double- and quad-register.
812class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000813 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000814 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
Bob Wilsone60fee02009-06-22 23:27:02 +0000815 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000816 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000817 OpcodeStr, Dt, "$dst, $src1, $src2", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000818 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
819 let isCommutable = Commutable;
820}
David Goodwin36bff0c2009-09-25 18:38:29 +0000821class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000822 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000823 : N3V<0, 1, op21_20, op11_8, 1, 0,
824 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +0000825 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000826 [(set (Ty DPR:$dst),
827 (Ty (IntOp (Ty DPR:$src1),
828 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
829 imm:$lane)))))]> {
830 let isCommutable = 0;
831}
David Goodwin36bff0c2009-09-25 18:38:29 +0000832class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000833 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000834 : N3V<0, 1, op21_20, op11_8, 1, 0,
835 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +0000836 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000837 [(set (Ty DPR:$dst),
838 (Ty (IntOp (Ty DPR:$src1),
839 (Ty (NEONvduplane (Ty DPR_8:$src2),
840 imm:$lane)))))]> {
841 let isCommutable = 0;
842}
843
Bob Wilsone60fee02009-06-22 23:27:02 +0000844class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000845 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000846 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
Bob Wilsone60fee02009-06-22 23:27:02 +0000847 : N3V<op24, op23, op21_20, op11_8, 1, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000848 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000849 OpcodeStr, Dt, "$dst, $src1, $src2", "",
Bob Wilsone60fee02009-06-22 23:27:02 +0000850 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
851 let isCommutable = Commutable;
852}
David Goodwin36bff0c2009-09-25 18:38:29 +0000853class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000854 string OpcodeStr, string Dt,
855 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000856 : N3V<1, 1, op21_20, op11_8, 1, 0,
857 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +0000858 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000859 [(set (ResTy QPR:$dst),
860 (ResTy (IntOp (ResTy QPR:$src1),
861 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
862 imm:$lane)))))]> {
863 let isCommutable = 0;
864}
David Goodwin36bff0c2009-09-25 18:38:29 +0000865class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000866 string OpcodeStr, string Dt,
867 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000868 : N3V<1, 1, op21_20, op11_8, 1, 0,
869 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +0000870 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000871 [(set (ResTy QPR:$dst),
872 (ResTy (IntOp (ResTy QPR:$src1),
873 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
874 imm:$lane)))))]> {
875 let isCommutable = 0;
876}
Bob Wilsone60fee02009-06-22 23:27:02 +0000877
Bob Wilson154999f2010-02-17 22:23:11 +0000878// Multiply-Add/Sub operations: single-, double- and quad-register.
879class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
880 InstrItinClass itin, string OpcodeStr, string Dt,
881 ValueType Ty, SDNode MulOp, SDNode OpNode>
882 : N3V<op24, op23, op21_20, op11_8, 0, op4,
883 (outs DPR_VFP2:$dst),
884 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
885 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
886
Bob Wilsone60fee02009-06-22 23:27:02 +0000887class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000888 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +0000889 ValueType Ty, SDNode MulOp, SDNode OpNode>
Bob Wilsone60fee02009-06-22 23:27:02 +0000890 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000891 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000892 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +0000893 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
894 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
David Goodwin36bff0c2009-09-25 18:38:29 +0000895class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000896 string OpcodeStr, string Dt,
897 ValueType Ty, SDNode MulOp, SDNode ShOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000898 : N3V<0, 1, op21_20, op11_8, 1, 0,
899 (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +0000900 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000901 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000902 [(set (Ty DPR:$dst),
903 (Ty (ShOp (Ty DPR:$src1),
904 (Ty (MulOp DPR:$src2,
905 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
Johnny Chen7c3f3862010-03-17 23:26:50 +0000906 imm:$lane)))))))]>;
David Goodwin36bff0c2009-09-25 18:38:29 +0000907class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000908 string OpcodeStr, string Dt,
909 ValueType Ty, SDNode MulOp, SDNode ShOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000910 : N3V<0, 1, op21_20, op11_8, 1, 0,
911 (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +0000912 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000913 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000914 [(set (Ty DPR:$dst),
915 (Ty (ShOp (Ty DPR:$src1),
916 (Ty (MulOp DPR:$src2,
917 (Ty (NEONvduplane (Ty DPR_8:$src3),
Johnny Chen7c3f3862010-03-17 23:26:50 +0000918 imm:$lane)))))))]>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000919
Bob Wilsone60fee02009-06-22 23:27:02 +0000920class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000921 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
David Goodwin36bff0c2009-09-25 18:38:29 +0000922 SDNode MulOp, SDNode OpNode>
Bob Wilsone60fee02009-06-22 23:27:02 +0000923 : N3V<op24, op23, op21_20, op11_8, 1, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000924 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000925 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +0000926 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
927 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
David Goodwin36bff0c2009-09-25 18:38:29 +0000928class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000929 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000930 SDNode MulOp, SDNode ShOp>
931 : N3V<1, 1, op21_20, op11_8, 1, 0,
932 (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +0000933 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000934 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000935 [(set (ResTy QPR:$dst),
936 (ResTy (ShOp (ResTy QPR:$src1),
937 (ResTy (MulOp QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000938 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
Johnny Chen7c3f3862010-03-17 23:26:50 +0000939 imm:$lane)))))))]>;
David Goodwin36bff0c2009-09-25 18:38:29 +0000940class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000941 string OpcodeStr, string Dt,
942 ValueType ResTy, ValueType OpTy,
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000943 SDNode MulOp, SDNode ShOp>
944 : N3V<1, 1, op21_20, op11_8, 1, 0,
945 (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +0000946 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000947 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000948 [(set (ResTy QPR:$dst),
949 (ResTy (ShOp (ResTy QPR:$src1),
950 (ResTy (MulOp QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +0000951 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
Johnny Chen7c3f3862010-03-17 23:26:50 +0000952 imm:$lane)))))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +0000953
954// Neon 3-argument intrinsics, both double- and quad-register.
955// The destination register is also used as the first source operand register.
956class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000957 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +0000958 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Bob Wilsone60fee02009-06-22 23:27:02 +0000959 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000960 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000961 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +0000962 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
963 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
964class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000965 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +0000966 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Bob Wilsone60fee02009-06-22 23:27:02 +0000967 : N3V<op24, op23, op21_20, op11_8, 1, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000968 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000969 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +0000970 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
971 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
972
973// Neon Long 3-argument intrinsic. The destination register is
974// a quad-register and is also used as the first source operand register.
975class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +0000976 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +0000977 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
Bob Wilsone60fee02009-06-22 23:27:02 +0000978 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +0000979 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000980 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +0000981 [(set QPR:$dst,
982 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
David Goodwin36bff0c2009-09-25 18:38:29 +0000983class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000984 string OpcodeStr, string Dt,
985 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000986 : N3V<op24, 1, op21_20, op11_8, 1, 0,
987 (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +0000988 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +0000989 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000990 [(set (ResTy QPR:$dst),
991 (ResTy (IntOp (ResTy QPR:$src1),
992 (OpTy DPR:$src2),
993 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
994 imm:$lane)))))]>;
Bob Wilson1d2c4212010-02-17 00:31:29 +0000995class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
996 InstrItinClass itin, string OpcodeStr, string Dt,
997 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +0000998 : N3V<op24, 1, op21_20, op11_8, 1, 0,
999 (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00001000 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001001 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001002 [(set (ResTy QPR:$dst),
1003 (ResTy (IntOp (ResTy QPR:$src1),
1004 (OpTy DPR:$src2),
1005 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1006 imm:$lane)))))]>;
1007
Bob Wilsone60fee02009-06-22 23:27:02 +00001008// Narrowing 3-register intrinsics.
1009class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001010 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
Bob Wilsone60fee02009-06-22 23:27:02 +00001011 Intrinsic IntOp, bit Commutable>
1012 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001013 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001014 OpcodeStr, Dt, "$dst, $src1, $src2", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001015 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1016 let isCommutable = Commutable;
1017}
1018
1019// Long 3-register intrinsics.
1020class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001021 InstrItinClass itin, string OpcodeStr, string Dt,
1022 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
Bob Wilsone60fee02009-06-22 23:27:02 +00001023 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001024 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001025 OpcodeStr, Dt, "$dst, $src1, $src2", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001026 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1027 let isCommutable = Commutable;
1028}
David Goodwin36bff0c2009-09-25 18:38:29 +00001029class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001030 string OpcodeStr, string Dt,
1031 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001032 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1033 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00001034 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001035 [(set (ResTy QPR:$dst),
1036 (ResTy (IntOp (OpTy DPR:$src1),
1037 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
Johnny Chen7c3f3862010-03-17 23:26:50 +00001038 imm:$lane)))))]>;
Bob Wilson1d2c4212010-02-17 00:31:29 +00001039class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1040 InstrItinClass itin, string OpcodeStr, string Dt,
1041 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001042 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1043 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00001044 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001045 [(set (ResTy QPR:$dst),
1046 (ResTy (IntOp (OpTy DPR:$src1),
1047 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
Johnny Chen7c3f3862010-03-17 23:26:50 +00001048 imm:$lane)))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001049
1050// Wide 3-register intrinsics.
1051class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001052 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
Bob Wilsone60fee02009-06-22 23:27:02 +00001053 Intrinsic IntOp, bit Commutable>
1054 : N3V<op24, op23, op21_20, op11_8, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001055 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001056 OpcodeStr, Dt, "$dst, $src1, $src2", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001057 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1058 let isCommutable = Commutable;
1059}
1060
1061// Pairwise long 2-register intrinsics, both double- and quad-register.
1062class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Cheng09c61b32009-11-23 21:57:23 +00001063 bits<2> op17_16, bits<5> op11_7, bit op4,
1064 string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +00001065 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1066 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +00001067 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001068 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1069class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Cheng09c61b32009-11-23 21:57:23 +00001070 bits<2> op17_16, bits<5> op11_7, bit op4,
1071 string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +00001072 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1073 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
Evan Cheng09c61b32009-11-23 21:57:23 +00001074 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001075 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1076
1077// Pairwise long 2-register accumulate intrinsics,
1078// both double- and quad-register.
1079// The destination register is also used as the first source operand register.
1080class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Cheng09c61b32009-11-23 21:57:23 +00001081 bits<2> op17_16, bits<5> op11_7, bit op4,
1082 string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +00001083 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1084 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001085 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001086 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00001087 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1088class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Cheng09c61b32009-11-23 21:57:23 +00001089 bits<2> op17_16, bits<5> op11_7, bit op4,
1090 string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +00001091 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1092 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001093 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001094 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00001095 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1096
1097// Shift by immediate,
1098// both double- and quad-register.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001099class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001100 InstrItinClass itin, string OpcodeStr, string Dt,
1101 ValueType Ty, SDNode OpNode>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001102 : N2VImm<op24, op23, op11_8, op7, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001103 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001104 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001105 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001106class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001107 InstrItinClass itin, string OpcodeStr, string Dt,
1108 ValueType Ty, SDNode OpNode>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001109 : N2VImm<op24, op23, op11_8, op7, 1, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001110 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001111 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001112 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1113
Johnny Chen7c3f3862010-03-17 23:26:50 +00001114// Long shift by immediate.
1115class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1116 string OpcodeStr, string Dt,
1117 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1118 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1119 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1120 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1121 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1122 (i32 imm:$SIMM))))]>;
1123
Bob Wilsone60fee02009-06-22 23:27:02 +00001124// Narrow shift by immediate.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001125class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001126 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +00001127 ValueType ResTy, ValueType OpTy, SDNode OpNode>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001128 : N2VImm<op24, op23, op11_8, op7, op6, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001129 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001130 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001131 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1132 (i32 imm:$SIMM))))]>;
1133
1134// Shift right by immediate and accumulate,
1135// both double- and quad-register.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001136class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001137 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001138 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1139 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001140 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00001141 [(set DPR:$dst, (Ty (add DPR:$src1,
1142 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001143class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001144 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001145 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1146 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001147 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00001148 [(set QPR:$dst, (Ty (add QPR:$src1,
1149 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1150
1151// Shift by immediate and insert,
1152// both double- and quad-register.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001153class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001154 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001155 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1156 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001157 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00001158 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001159class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001160 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001161 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1162 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001163 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00001164 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1165
1166// Convert, with fractional bits immediate,
1167// both double- and quad-register.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001168class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001169 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Bob Wilsone60fee02009-06-22 23:27:02 +00001170 Intrinsic IntOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001171 : N2VImm<op24, op23, op11_8, op7, 0, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001172 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001173 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001174 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001175class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001176 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Bob Wilsone60fee02009-06-22 23:27:02 +00001177 Intrinsic IntOp>
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001178 : N2VImm<op24, op23, op11_8, op7, 1, op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001179 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001180 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00001181 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1182
1183//===----------------------------------------------------------------------===//
1184// Multiclasses
1185//===----------------------------------------------------------------------===//
1186
Bob Wilson8af7b532009-10-03 04:44:16 +00001187// Abbreviations used in multiclass suffixes:
1188// Q = quarter int (8 bit) elements
1189// H = half int (16 bit) elements
1190// S = single int (32 bit) elements
1191// D = double int (64 bit) elements
1192
Johnny Chenfc9ef992010-02-23 00:33:12 +00001193// Neon 2-register vector operations -- for disassembly only.
1194
1195// First with only element sizes of 8, 16 and 32 bits:
Johnny Chenc2b70b52010-02-23 01:42:58 +00001196multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1197 bits<5> op11_7, bit op4, string opc, string Dt,
1198 string asm> {
Johnny Chenfc9ef992010-02-23 00:33:12 +00001199 // 64-bit vector types.
1200 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1201 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
Johnny Chenc2b70b52010-02-23 01:42:58 +00001202 opc, !strconcat(Dt, "8"), asm, "", []>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00001203 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1204 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
Johnny Chenc2b70b52010-02-23 01:42:58 +00001205 opc, !strconcat(Dt, "16"), asm, "", []>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00001206 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1207 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
Johnny Chenc2b70b52010-02-23 01:42:58 +00001208 opc, !strconcat(Dt, "32"), asm, "", []>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00001209 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1210 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1211 opc, "f32", asm, "", []> {
1212 let Inst{10} = 1; // overwrite F = 1
1213 }
1214
1215 // 128-bit vector types.
1216 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1217 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
Johnny Chenc2b70b52010-02-23 01:42:58 +00001218 opc, !strconcat(Dt, "8"), asm, "", []>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00001219 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1220 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
Johnny Chenc2b70b52010-02-23 01:42:58 +00001221 opc, !strconcat(Dt, "16"), asm, "", []>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00001222 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1223 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
Johnny Chenc2b70b52010-02-23 01:42:58 +00001224 opc, !strconcat(Dt, "32"), asm, "", []>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00001225 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1226 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1227 opc, "f32", asm, "", []> {
1228 let Inst{10} = 1; // overwrite F = 1
1229 }
1230}
1231
Bob Wilsone60fee02009-06-22 23:27:02 +00001232// Neon 3-register vector operations.
1233
1234// First with only element sizes of 8, 16 and 32 bits:
1235multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin78caa122009-09-23 21:38:08 +00001236 InstrItinClass itinD16, InstrItinClass itinD32,
1237 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001238 string OpcodeStr, string Dt,
1239 SDNode OpNode, bit Commutable = 0> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001240 // 64-bit vector types.
David Goodwin78caa122009-09-23 21:38:08 +00001241 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001242 OpcodeStr, !strconcat(Dt, "8"),
1243 v8i8, v8i8, OpNode, Commutable>;
David Goodwin78caa122009-09-23 21:38:08 +00001244 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001245 OpcodeStr, !strconcat(Dt, "16"),
1246 v4i16, v4i16, OpNode, Commutable>;
David Goodwin78caa122009-09-23 21:38:08 +00001247 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001248 OpcodeStr, !strconcat(Dt, "32"),
1249 v2i32, v2i32, OpNode, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001250
1251 // 128-bit vector types.
David Goodwin78caa122009-09-23 21:38:08 +00001252 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001253 OpcodeStr, !strconcat(Dt, "8"),
1254 v16i8, v16i8, OpNode, Commutable>;
David Goodwin78caa122009-09-23 21:38:08 +00001255 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001256 OpcodeStr, !strconcat(Dt, "16"),
1257 v8i16, v8i16, OpNode, Commutable>;
David Goodwin78caa122009-09-23 21:38:08 +00001258 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001259 OpcodeStr, !strconcat(Dt, "32"),
1260 v4i32, v4i32, OpNode, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001261}
1262
Evan Cheng09c61b32009-11-23 21:57:23 +00001263multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1264 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1265 v4i16, ShOp>;
1266 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
Evan Cheng67abcec2009-11-21 06:21:52 +00001267 v2i32, ShOp>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001268 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
Evan Cheng67abcec2009-11-21 06:21:52 +00001269 v8i16, v4i16, ShOp>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001270 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
Evan Cheng67abcec2009-11-21 06:21:52 +00001271 v4i32, v2i32, ShOp>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001272}
1273
Bob Wilsone60fee02009-06-22 23:27:02 +00001274// ....then also with element size 64 bits:
1275multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin78caa122009-09-23 21:38:08 +00001276 InstrItinClass itinD, InstrItinClass itinQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001277 string OpcodeStr, string Dt,
1278 SDNode OpNode, bit Commutable = 0>
David Goodwin78caa122009-09-23 21:38:08 +00001279 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001280 OpcodeStr, Dt, OpNode, Commutable> {
David Goodwin78caa122009-09-23 21:38:08 +00001281 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001282 OpcodeStr, !strconcat(Dt, "64"),
1283 v1i64, v1i64, OpNode, Commutable>;
David Goodwin78caa122009-09-23 21:38:08 +00001284 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001285 OpcodeStr, !strconcat(Dt, "64"),
1286 v2i64, v2i64, OpNode, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001287}
1288
1289
1290// Neon Narrowing 2-register vector intrinsics,
1291// source operand element sizes of 16, 32 and 64 bits:
1292multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
David Goodwin78caa122009-09-23 21:38:08 +00001293 bits<5> op11_7, bit op6, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001294 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilsone60fee02009-06-22 23:27:02 +00001295 Intrinsic IntOp> {
1296 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001297 itin, OpcodeStr, !strconcat(Dt, "16"),
1298 v8i8, v8i16, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001299 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001300 itin, OpcodeStr, !strconcat(Dt, "32"),
1301 v4i16, v4i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001302 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001303 itin, OpcodeStr, !strconcat(Dt, "64"),
1304 v2i32, v2i64, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001305}
1306
1307
1308// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1309// source operand element sizes of 16, 32 and 64 bits:
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001310multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001311 string OpcodeStr, string Dt, Intrinsic IntOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001312 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001313 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001314 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001315 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001316 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00001317 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001318}
1319
1320
1321// Neon 3-register vector intrinsics.
1322
1323// First with only element sizes of 16 and 32 bits:
1324multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001325 InstrItinClass itinD16, InstrItinClass itinD32,
1326 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001327 string OpcodeStr, string Dt,
1328 Intrinsic IntOp, bit Commutable = 0> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001329 // 64-bit vector types.
Evan Cheng67abcec2009-11-21 06:21:52 +00001330 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001331 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001332 v4i16, v4i16, IntOp, Commutable>;
Evan Cheng67abcec2009-11-21 06:21:52 +00001333 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001334 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001335 v2i32, v2i32, IntOp, Commutable>;
1336
1337 // 128-bit vector types.
Evan Cheng67abcec2009-11-21 06:21:52 +00001338 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001339 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001340 v8i16, v8i16, IntOp, Commutable>;
Evan Cheng67abcec2009-11-21 06:21:52 +00001341 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001342 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001343 v4i32, v4i32, IntOp, Commutable>;
1344}
1345
David Goodwin36bff0c2009-09-25 18:38:29 +00001346multiclass N3VIntSL_HS<bits<4> op11_8,
1347 InstrItinClass itinD16, InstrItinClass itinD32,
1348 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001349 string OpcodeStr, string Dt, Intrinsic IntOp> {
Evan Cheng67abcec2009-11-21 06:21:52 +00001350 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001351 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
Evan Cheng67abcec2009-11-21 06:21:52 +00001352 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001353 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
Evan Cheng67abcec2009-11-21 06:21:52 +00001354 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001355 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
Evan Cheng67abcec2009-11-21 06:21:52 +00001356 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001357 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001358}
1359
Bob Wilsone60fee02009-06-22 23:27:02 +00001360// ....then also with element size of 8 bits:
1361multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001362 InstrItinClass itinD16, InstrItinClass itinD32,
1363 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001364 string OpcodeStr, string Dt,
1365 Intrinsic IntOp, bit Commutable = 0>
David Goodwin36bff0c2009-09-25 18:38:29 +00001366 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001367 OpcodeStr, Dt, IntOp, Commutable> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001368 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001369 OpcodeStr, !strconcat(Dt, "8"),
1370 v8i8, v8i8, IntOp, Commutable>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001371 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001372 OpcodeStr, !strconcat(Dt, "8"),
1373 v16i8, v16i8, IntOp, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001374}
1375
1376// ....then also with element size of 64 bits:
1377multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001378 InstrItinClass itinD16, InstrItinClass itinD32,
1379 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001380 string OpcodeStr, string Dt,
1381 Intrinsic IntOp, bit Commutable = 0>
David Goodwin36bff0c2009-09-25 18:38:29 +00001382 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001383 OpcodeStr, Dt, IntOp, Commutable> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001384 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001385 OpcodeStr, !strconcat(Dt, "64"),
1386 v1i64, v1i64, IntOp, Commutable>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001387 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001388 OpcodeStr, !strconcat(Dt, "64"),
1389 v2i64, v2i64, IntOp, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001390}
1391
1392
1393// Neon Narrowing 3-register vector intrinsics,
1394// source operand element sizes of 16, 32 and 64 bits:
1395multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001396 string OpcodeStr, string Dt,
1397 Intrinsic IntOp, bit Commutable = 0> {
1398 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1399 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001400 v8i8, v8i16, IntOp, Commutable>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001401 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1402 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001403 v4i16, v4i32, IntOp, Commutable>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001404 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1405 OpcodeStr, !strconcat(Dt, "64"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001406 v2i32, v2i64, IntOp, Commutable>;
1407}
1408
1409
1410// Neon Long 3-register vector intrinsics.
1411
1412// First with only element sizes of 16 and 32 bits:
1413multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001414 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +00001415 Intrinsic IntOp, bit Commutable = 0> {
1416 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001417 OpcodeStr, !strconcat(Dt, "16"),
1418 v4i32, v4i16, IntOp, Commutable>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001419 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001420 OpcodeStr, !strconcat(Dt, "32"),
1421 v2i64, v2i32, IntOp, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001422}
1423
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001424multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
Evan Cheng09c61b32009-11-23 21:57:23 +00001425 InstrItinClass itin, string OpcodeStr, string Dt,
1426 Intrinsic IntOp> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001427 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001428 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001429 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001430 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001431}
1432
Bob Wilsone60fee02009-06-22 23:27:02 +00001433// ....then also with element size of 8 bits:
1434multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001435 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin36bff0c2009-09-25 18:38:29 +00001436 Intrinsic IntOp, bit Commutable = 0>
Evan Cheng09c61b32009-11-23 21:57:23 +00001437 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1438 IntOp, Commutable> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001439 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001440 OpcodeStr, !strconcat(Dt, "8"),
1441 v8i16, v8i8, IntOp, Commutable>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001442}
1443
1444
1445// Neon Wide 3-register vector intrinsics,
1446// source operand element sizes of 8, 16 and 32 bits:
1447multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001448 string OpcodeStr, string Dt,
1449 Intrinsic IntOp, bit Commutable = 0> {
1450 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1451 OpcodeStr, !strconcat(Dt, "8"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001452 v8i16, v8i8, IntOp, Commutable>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001453 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1454 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001455 v4i32, v4i16, IntOp, Commutable>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001456 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1457 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilsone60fee02009-06-22 23:27:02 +00001458 v2i64, v2i32, IntOp, Commutable>;
1459}
1460
1461
1462// Neon Multiply-Op vector operations,
1463// element sizes of 8, 16 and 32 bits:
1464multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin36bff0c2009-09-25 18:38:29 +00001465 InstrItinClass itinD16, InstrItinClass itinD32,
1466 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001467 string OpcodeStr, string Dt, SDNode OpNode> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001468 // 64-bit vector types.
David Goodwin36bff0c2009-09-25 18:38:29 +00001469 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001470 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001471 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001472 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001473 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001474 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001475
1476 // 128-bit vector types.
David Goodwin36bff0c2009-09-25 18:38:29 +00001477 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001478 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001479 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001480 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001481 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001482 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001483}
1484
David Goodwin36bff0c2009-09-25 18:38:29 +00001485multiclass N3VMulOpSL_HS<bits<4> op11_8,
1486 InstrItinClass itinD16, InstrItinClass itinD32,
1487 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001488 string OpcodeStr, string Dt, SDNode ShOp> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001489 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
Evan Cheng09c61b32009-11-23 21:57:23 +00001490 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001491 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
Evan Cheng09c61b32009-11-23 21:57:23 +00001492 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001493 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001494 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1495 mul, ShOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001496 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001497 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1498 mul, ShOp>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001499}
Bob Wilsone60fee02009-06-22 23:27:02 +00001500
1501// Neon 3-argument intrinsics,
1502// element sizes of 8, 16 and 32 bits:
1503multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001504 string OpcodeStr, string Dt, Intrinsic IntOp> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001505 // 64-bit vector types.
David Goodwin36bff0c2009-09-25 18:38:29 +00001506 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001507 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001508 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001509 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001510 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001511 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001512
1513 // 128-bit vector types.
David Goodwin36bff0c2009-09-25 18:38:29 +00001514 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001515 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001516 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001517 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001518 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001519 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001520}
1521
1522
1523// Neon Long 3-argument intrinsics.
1524
1525// First with only element sizes of 16 and 32 bits:
1526multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001527 string OpcodeStr, string Dt, Intrinsic IntOp> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001528 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001529 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001530 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001531 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001532}
1533
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001534multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
Evan Cheng09c61b32009-11-23 21:57:23 +00001535 string OpcodeStr, string Dt, Intrinsic IntOp> {
David Goodwin36bff0c2009-09-25 18:38:29 +00001536 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001537 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001538 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001539 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001540}
1541
Bob Wilsone60fee02009-06-22 23:27:02 +00001542// ....then also with element size of 8 bits:
1543multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001544 string OpcodeStr, string Dt, Intrinsic IntOp>
1545 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
Bob Wilson85f30d72009-10-15 21:57:47 +00001546 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001547 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001548}
1549
1550
1551// Neon 2-register vector intrinsics,
1552// element sizes of 8, 16 and 32 bits:
1553multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
David Goodwin78caa122009-09-23 21:38:08 +00001554 bits<5> op11_7, bit op4,
1555 InstrItinClass itinD, InstrItinClass itinQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00001556 string OpcodeStr, string Dt, Intrinsic IntOp> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001557 // 64-bit vector types.
1558 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001559 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001560 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001561 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001562 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001563 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001564
1565 // 128-bit vector types.
1566 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001567 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001568 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001569 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001570 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001571 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001572}
1573
1574
1575// Neon Pairwise long 2-register intrinsics,
1576// element sizes of 8, 16 and 32 bits:
1577multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1578 bits<5> op11_7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001579 string OpcodeStr, string Dt, Intrinsic IntOp> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001580 // 64-bit vector types.
1581 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001582 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001583 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001584 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001585 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001586 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001587
1588 // 128-bit vector types.
1589 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001590 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001591 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001592 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001593 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001594 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001595}
1596
1597
1598// Neon Pairwise long 2-register accumulate intrinsics,
1599// element sizes of 8, 16 and 32 bits:
1600multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1601 bits<5> op11_7, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001602 string OpcodeStr, string Dt, Intrinsic IntOp> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001603 // 64-bit vector types.
1604 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001605 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001606 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001607 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001608 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001609 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001610
1611 // 128-bit vector types.
1612 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001613 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001614 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001615 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001616 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001617 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001618}
1619
1620
1621// Neon 2-register vector shift by immediate,
1622// element sizes of 8, 16, 32 and 64 bits:
1623multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001624 InstrItinClass itin, string OpcodeStr, string Dt,
1625 SDNode OpNode> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001626 // 64-bit vector types.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001627 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001628 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001629 let Inst{21-19} = 0b001; // imm6 = 001xxx
1630 }
1631 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001632 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001633 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1634 }
1635 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001636 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001637 let Inst{21} = 0b1; // imm6 = 1xxxxx
1638 }
1639 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001640 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001641 // imm6 = xxxxxx
Bob Wilsone60fee02009-06-22 23:27:02 +00001642
1643 // 128-bit vector types.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001644 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001645 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001646 let Inst{21-19} = 0b001; // imm6 = 001xxx
1647 }
1648 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001649 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001650 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1651 }
1652 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001653 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001654 let Inst{21} = 0b1; // imm6 = 1xxxxx
1655 }
1656 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001657 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001658 // imm6 = xxxxxx
Bob Wilsone60fee02009-06-22 23:27:02 +00001659}
1660
1661
1662// Neon Shift-Accumulate vector operations,
1663// element sizes of 8, 16, 32 and 64 bits:
1664multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001665 string OpcodeStr, string Dt, SDNode ShOp> {
Bob Wilsone60fee02009-06-22 23:27:02 +00001666 // 64-bit vector types.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001667 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001668 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001669 let Inst{21-19} = 0b001; // imm6 = 001xxx
1670 }
1671 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001672 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001673 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1674 }
1675 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001676 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001677 let Inst{21} = 0b1; // imm6 = 1xxxxx
1678 }
1679 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001680 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001681 // imm6 = xxxxxx
Bob Wilsone60fee02009-06-22 23:27:02 +00001682
1683 // 128-bit vector types.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001684 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001685 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001686 let Inst{21-19} = 0b001; // imm6 = 001xxx
1687 }
1688 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001689 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001690 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1691 }
1692 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001693 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001694 let Inst{21} = 0b1; // imm6 = 1xxxxx
1695 }
1696 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001697 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001698 // imm6 = xxxxxx
Bob Wilsone60fee02009-06-22 23:27:02 +00001699}
1700
1701
1702// Neon Shift-Insert vector operations,
1703// element sizes of 8, 16, 32 and 64 bits:
1704multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1705 string OpcodeStr, SDNode ShOp> {
1706 // 64-bit vector types.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001707 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001708 OpcodeStr, "8", v8i8, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001709 let Inst{21-19} = 0b001; // imm6 = 001xxx
1710 }
1711 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001712 OpcodeStr, "16", v4i16, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001713 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1714 }
1715 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001716 OpcodeStr, "32", v2i32, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001717 let Inst{21} = 0b1; // imm6 = 1xxxxx
1718 }
1719 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001720 OpcodeStr, "64", v1i64, ShOp>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001721 // imm6 = xxxxxx
Bob Wilsone60fee02009-06-22 23:27:02 +00001722
1723 // 128-bit vector types.
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001724 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001725 OpcodeStr, "8", v16i8, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001726 let Inst{21-19} = 0b001; // imm6 = 001xxx
1727 }
1728 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001729 OpcodeStr, "16", v8i16, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001730 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1731 }
1732 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001733 OpcodeStr, "32", v4i32, ShOp> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001734 let Inst{21} = 0b1; // imm6 = 1xxxxx
1735 }
1736 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001737 OpcodeStr, "64", v2i64, ShOp>;
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001738 // imm6 = xxxxxx
1739}
1740
1741// Neon Shift Long operations,
1742// element sizes of 8, 16, 32 bits:
1743multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
Evan Cheng09c61b32009-11-23 21:57:23 +00001744 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001745 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001746 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001747 let Inst{21-19} = 0b001; // imm6 = 001xxx
1748 }
1749 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001750 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001751 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1752 }
1753 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
Evan Cheng09c61b32009-11-23 21:57:23 +00001754 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001755 let Inst{21} = 0b1; // imm6 = 1xxxxx
1756 }
1757}
1758
1759// Neon Shift Narrow operations,
1760// element sizes of 16, 32, 64 bits:
1761multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
Evan Cheng09c61b32009-11-23 21:57:23 +00001762 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001763 SDNode OpNode> {
1764 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001765 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001766 let Inst{21-19} = 0b001; // imm6 = 001xxx
1767 }
1768 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001769 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001770 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1771 }
1772 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
Evan Cheng09c61b32009-11-23 21:57:23 +00001773 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00001774 let Inst{21} = 0b1; // imm6 = 1xxxxx
1775 }
Bob Wilsone60fee02009-06-22 23:27:02 +00001776}
1777
1778//===----------------------------------------------------------------------===//
1779// Instruction Definitions.
1780//===----------------------------------------------------------------------===//
1781
1782// Vector Add Operations.
1783
1784// VADD : Vector Add (integer and floating-point)
Evan Cheng09c61b32009-11-23 21:57:23 +00001785defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
Evan Cheng67abcec2009-11-21 06:21:52 +00001786 add, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001787def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001788 v2f32, v2f32, fadd, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001789def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001790 v4f32, v4f32, fadd, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001791// VADDL : Vector Add Long (Q = D + D)
Evan Cheng09c61b32009-11-23 21:57:23 +00001792defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
Evan Cheng67abcec2009-11-21 06:21:52 +00001793 int_arm_neon_vaddls, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001794defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
Evan Cheng67abcec2009-11-21 06:21:52 +00001795 int_arm_neon_vaddlu, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001796// VADDW : Vector Add Wide (Q = Q + D)
Evan Cheng09c61b32009-11-23 21:57:23 +00001797defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1798defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001799// VHADD : Vector Halving Add
David Goodwin36bff0c2009-09-25 18:38:29 +00001800defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001801 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001802defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001803 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001804// VRHADD : Vector Rounding Halving Add
David Goodwin36bff0c2009-09-25 18:38:29 +00001805defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001806 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001807defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001808 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001809// VQADD : Vector Saturating Add
David Goodwin36bff0c2009-09-25 18:38:29 +00001810defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001811 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001812defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001813 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001814// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
Evan Cheng09c61b32009-11-23 21:57:23 +00001815defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
1816 int_arm_neon_vaddhn, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001817// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
Evan Cheng09c61b32009-11-23 21:57:23 +00001818defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
1819 int_arm_neon_vraddhn, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001820
1821// Vector Multiply Operations.
1822
1823// VMUL : Vector Multiply (integer, polynomial and floating-point)
Evan Cheng67abcec2009-11-21 06:21:52 +00001824defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001825 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
1826def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
Evan Cheng67abcec2009-11-21 06:21:52 +00001827 v8i8, v8i8, int_arm_neon_vmulp, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001828def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
Evan Cheng67abcec2009-11-21 06:21:52 +00001829 v16i8, v16i8, int_arm_neon_vmulp, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001830def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
Bob Wilson1d2c4212010-02-17 00:31:29 +00001831 v2f32, v2f32, fmul, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001832def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
Bob Wilson1d2c4212010-02-17 00:31:29 +00001833 v4f32, v4f32, fmul, 1>;
1834defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
1835def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
1836def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
1837 v2f32, fmul>;
1838
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001839def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1840 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1841 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1842 (v4i16 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001843 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001844 (SubReg_i16_lane imm:$lane)))>;
1845def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1846 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1847 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1848 (v2i32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001849 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001850 (SubReg_i32_lane imm:$lane)))>;
1851def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1852 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1853 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1854 (v2f32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001855 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001856 (SubReg_i32_lane imm:$lane)))>;
1857
Bob Wilsone60fee02009-06-22 23:27:02 +00001858// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
David Goodwin36bff0c2009-09-25 18:38:29 +00001859defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1860 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001861 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001862defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1863 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001864 "vqdmulh", "s", int_arm_neon_vqdmulh>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001865def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
Evan Cheng67abcec2009-11-21 06:21:52 +00001866 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1867 imm:$lane)))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001868 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1869 (v4i16 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001870 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001871 (SubReg_i16_lane imm:$lane)))>;
1872def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
Evan Cheng67abcec2009-11-21 06:21:52 +00001873 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1874 imm:$lane)))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001875 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1876 (v2i32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001877 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001878 (SubReg_i32_lane imm:$lane)))>;
1879
Bob Wilsone60fee02009-06-22 23:27:02 +00001880// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
David Goodwin36bff0c2009-09-25 18:38:29 +00001881defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1882 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001883 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001884defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1885 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00001886 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001887def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
Evan Cheng67abcec2009-11-21 06:21:52 +00001888 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1889 imm:$lane)))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001890 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1891 (v4i16 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001892 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001893 (SubReg_i16_lane imm:$lane)))>;
1894def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
Evan Cheng67abcec2009-11-21 06:21:52 +00001895 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1896 imm:$lane)))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001897 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1898 (v2i32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001899 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001900 (SubReg_i32_lane imm:$lane)))>;
1901
Bob Wilsone60fee02009-06-22 23:27:02 +00001902// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
Evan Cheng09c61b32009-11-23 21:57:23 +00001903defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
Evan Cheng67abcec2009-11-21 06:21:52 +00001904 int_arm_neon_vmulls, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001905defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
Evan Cheng67abcec2009-11-21 06:21:52 +00001906 int_arm_neon_vmullu, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001907def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
Evan Cheng67abcec2009-11-21 06:21:52 +00001908 v8i16, v8i8, int_arm_neon_vmullp, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001909defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
Evan Cheng67abcec2009-11-21 06:21:52 +00001910 int_arm_neon_vmulls>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001911defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
Evan Cheng67abcec2009-11-21 06:21:52 +00001912 int_arm_neon_vmullu>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001913
Bob Wilsone60fee02009-06-22 23:27:02 +00001914// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
Evan Cheng09c61b32009-11-23 21:57:23 +00001915defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
Evan Cheng67abcec2009-11-21 06:21:52 +00001916 int_arm_neon_vqdmull, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001917defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
Evan Cheng67abcec2009-11-21 06:21:52 +00001918 int_arm_neon_vqdmull>;
Bob Wilsone60fee02009-06-22 23:27:02 +00001919
1920// Vector Multiply-Accumulate and Multiply-Subtract Operations.
1921
1922// VMLA : Vector Multiply Accumulate (integer and floating-point)
David Goodwin36bff0c2009-09-25 18:38:29 +00001923defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001924 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1925def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001926 v2f32, fmul, fadd>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001927def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001928 v4f32, fmul, fadd>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001929defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001930 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1931def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001932 v2f32, fmul, fadd>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001933def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001934 v4f32, v2f32, fmul, fadd>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001935
1936def : Pat<(v8i16 (add (v8i16 QPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +00001937 (mul (v8i16 QPR:$src2),
1938 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1939 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001940 (v4i16 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001941 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001942 (SubReg_i16_lane imm:$lane)))>;
1943
1944def : Pat<(v4i32 (add (v4i32 QPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +00001945 (mul (v4i32 QPR:$src2),
1946 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1947 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001948 (v2i32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001949 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001950 (SubReg_i32_lane imm:$lane)))>;
1951
1952def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +00001953 (fmul (v4f32 QPR:$src2),
1954 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001955 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1956 (v4f32 QPR:$src2),
1957 (v2f32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001958 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001959 (SubReg_i32_lane imm:$lane)))>;
1960
Bob Wilsone60fee02009-06-22 23:27:02 +00001961// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
Evan Cheng09c61b32009-11-23 21:57:23 +00001962defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
1963defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001964
Evan Cheng09c61b32009-11-23 21:57:23 +00001965defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
1966defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001967
Bob Wilsone60fee02009-06-22 23:27:02 +00001968// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
Evan Cheng09c61b32009-11-23 21:57:23 +00001969defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
1970 int_arm_neon_vqdmlal>;
1971defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001972
Bob Wilsone60fee02009-06-22 23:27:02 +00001973// VMLS : Vector Multiply Subtract (integer and floating-point)
Bob Wilson64c60912009-10-03 04:41:21 +00001974defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001975 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1976def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001977 v2f32, fmul, fsub>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001978def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001979 v4f32, fmul, fsub>;
David Goodwin36bff0c2009-09-25 18:38:29 +00001980defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
Evan Cheng09c61b32009-11-23 21:57:23 +00001981 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1982def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001983 v2f32, fmul, fsub>;
Evan Cheng09c61b32009-11-23 21:57:23 +00001984def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00001985 v4f32, v2f32, fmul, fsub>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001986
1987def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +00001988 (mul (v8i16 QPR:$src2),
1989 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1990 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001991 (v4i16 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson1d2c4212010-02-17 00:31:29 +00001992 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001993 (SubReg_i16_lane imm:$lane)))>;
1994
1995def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +00001996 (mul (v4i32 QPR:$src2),
1997 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1998 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00001999 (v2i32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson1d2c4212010-02-17 00:31:29 +00002000 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00002001 (SubReg_i32_lane imm:$lane)))>;
2002
2003def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
Bob Wilson1d2c4212010-02-17 00:31:29 +00002004 (fmul (v4f32 QPR:$src2),
2005 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2006 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00002007 (v2f32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson1d2c4212010-02-17 00:31:29 +00002008 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikovdd528192009-09-08 15:22:32 +00002009 (SubReg_i32_lane imm:$lane)))>;
2010
Bob Wilsone60fee02009-06-22 23:27:02 +00002011// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
Evan Cheng09c61b32009-11-23 21:57:23 +00002012defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2013defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00002014
Evan Cheng09c61b32009-11-23 21:57:23 +00002015defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2016defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
Anton Korobeynikovdd528192009-09-08 15:22:32 +00002017
Bob Wilsone60fee02009-06-22 23:27:02 +00002018// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
Evan Cheng09c61b32009-11-23 21:57:23 +00002019defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2020 int_arm_neon_vqdmlsl>;
2021defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002022
2023// Vector Subtract Operations.
2024
2025// VSUB : Vector Subtract (integer and floating-point)
Evan Cheng67abcec2009-11-21 06:21:52 +00002026defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002027 "vsub", "i", sub, 0>;
2028def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002029 v2f32, v2f32, fsub, 0>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002030def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002031 v4f32, v4f32, fsub, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002032// VSUBL : Vector Subtract Long (Q = D - D)
Evan Cheng09c61b32009-11-23 21:57:23 +00002033defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
Evan Cheng67abcec2009-11-21 06:21:52 +00002034 int_arm_neon_vsubls, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002035defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
Evan Cheng67abcec2009-11-21 06:21:52 +00002036 int_arm_neon_vsublu, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002037// VSUBW : Vector Subtract Wide (Q = Q - D)
Evan Cheng09c61b32009-11-23 21:57:23 +00002038defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2039defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002040// VHSUB : Vector Halving Subtract
Evan Cheng67abcec2009-11-21 06:21:52 +00002041defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2042 IIC_VBINi4Q, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002043 "vhsub", "s", int_arm_neon_vhsubs, 0>;
Evan Cheng67abcec2009-11-21 06:21:52 +00002044defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2045 IIC_VBINi4Q, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002046 "vhsub", "u", int_arm_neon_vhsubu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002047// VQSUB : Vector Saturing Subtract
Evan Cheng67abcec2009-11-21 06:21:52 +00002048defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2049 IIC_VBINi4Q, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002050 "vqsub", "s", int_arm_neon_vqsubs, 0>;
Evan Cheng67abcec2009-11-21 06:21:52 +00002051defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2052 IIC_VBINi4Q, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002053 "vqsub", "u", int_arm_neon_vqsubu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002054// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
Evan Cheng09c61b32009-11-23 21:57:23 +00002055defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2056 int_arm_neon_vsubhn, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002057// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
Evan Cheng09c61b32009-11-23 21:57:23 +00002058defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2059 int_arm_neon_vrsubhn, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002060
2061// Vector Comparisons.
2062
2063// VCEQ : Vector Compare Equal
David Goodwin78caa122009-09-23 21:38:08 +00002064defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002065 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2066def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
Evan Cheng67abcec2009-11-21 06:21:52 +00002067 NEONvceq, 1>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002068def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
Evan Cheng67abcec2009-11-21 06:21:52 +00002069 NEONvceq, 1>;
Johnny Chenfc9ef992010-02-23 00:33:12 +00002070// For disassembly only.
Johnny Chenc2b70b52010-02-23 01:42:58 +00002071defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2072 "$dst, $src, #0">;
Johnny Chenfc9ef992010-02-23 00:33:12 +00002073
Bob Wilsone60fee02009-06-22 23:27:02 +00002074// VCGE : Vector Compare Greater Than or Equal
David Goodwin78caa122009-09-23 21:38:08 +00002075defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002076 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
David Goodwin78caa122009-09-23 21:38:08 +00002077defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002078 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2079def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002080 v2i32, v2f32, NEONvcge, 0>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002081def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
Evan Cheng67abcec2009-11-21 06:21:52 +00002082 NEONvcge, 0>;
Johnny Chenc2b70b52010-02-23 01:42:58 +00002083// For disassembly only.
2084defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2085 "$dst, $src, #0">;
2086// For disassembly only.
2087defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2088 "$dst, $src, #0">;
2089
Bob Wilsone60fee02009-06-22 23:27:02 +00002090// VCGT : Vector Compare Greater Than
David Goodwin78caa122009-09-23 21:38:08 +00002091defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002092 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
David Goodwin78caa122009-09-23 21:38:08 +00002093defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002094 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2095def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
Evan Cheng67abcec2009-11-21 06:21:52 +00002096 NEONvcgt, 0>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002097def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
Evan Cheng67abcec2009-11-21 06:21:52 +00002098 NEONvcgt, 0>;
Johnny Chenc2b70b52010-02-23 01:42:58 +00002099// For disassembly only.
2100defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2101 "$dst, $src, #0">;
2102// For disassembly only.
2103defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2104 "$dst, $src, #0">;
2105
Bob Wilsone60fee02009-06-22 23:27:02 +00002106// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
Evan Cheng09c61b32009-11-23 21:57:23 +00002107def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002108 v2i32, v2f32, int_arm_neon_vacged, 0>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002109def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002110 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002111// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
Evan Cheng09c61b32009-11-23 21:57:23 +00002112def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002113 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002114def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
Evan Cheng67abcec2009-11-21 06:21:52 +00002115 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002116// VTST : Vector Test Bits
David Goodwin78caa122009-09-23 21:38:08 +00002117defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Bob Wilsona21a9cc2010-01-17 06:35:17 +00002118 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002119
2120// Vector Bitwise Operations.
2121
2122// VAND : Vector Bitwise AND
Evan Cheng09c61b32009-11-23 21:57:23 +00002123def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2124 v2i32, v2i32, and, 1>;
2125def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2126 v4i32, v4i32, and, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002127
2128// VEOR : Vector Bitwise Exclusive OR
Evan Cheng09c61b32009-11-23 21:57:23 +00002129def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2130 v2i32, v2i32, xor, 1>;
2131def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2132 v4i32, v4i32, xor, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002133
2134// VORR : Vector Bitwise OR
Evan Cheng09c61b32009-11-23 21:57:23 +00002135def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2136 v2i32, v2i32, or, 1>;
2137def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2138 v4i32, v4i32, or, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002139
2140// VBIC : Vector Bitwise Bit Clear (AND NOT)
Evan Cheng09c61b32009-11-23 21:57:23 +00002141def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
David Goodwin78caa122009-09-23 21:38:08 +00002142 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002143 "vbic", "$dst, $src1, $src2", "",
Anton Korobeynikov14636a52009-09-08 22:51:43 +00002144 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2145 (vnot_conv DPR:$src2))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002146def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002147 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002148 "vbic", "$dst, $src1, $src2", "",
Anton Korobeynikov14636a52009-09-08 22:51:43 +00002149 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2150 (vnot_conv QPR:$src2))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002151
2152// VORN : Vector Bitwise OR NOT
Evan Cheng09c61b32009-11-23 21:57:23 +00002153def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
David Goodwin78caa122009-09-23 21:38:08 +00002154 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002155 "vorn", "$dst, $src1, $src2", "",
Anton Korobeynikov14636a52009-09-08 22:51:43 +00002156 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2157 (vnot_conv DPR:$src2))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002158def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002159 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002160 "vorn", "$dst, $src1, $src2", "",
Anton Korobeynikov14636a52009-09-08 22:51:43 +00002161 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2162 (vnot_conv QPR:$src2))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002163
2164// VMVN : Vector Bitwise NOT
Evan Cheng09c61b32009-11-23 21:57:23 +00002165def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
David Goodwin36bff0c2009-09-25 18:38:29 +00002166 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002167 "vmvn", "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002168 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002169def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
David Goodwin36bff0c2009-09-25 18:38:29 +00002170 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002171 "vmvn", "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002172 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2173def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2174def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2175
2176// VBSL : Vector Bitwise Select
Evan Cheng09c61b32009-11-23 21:57:23 +00002177def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002178 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002179 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00002180 [(set DPR:$dst,
2181 (v2i32 (or (and DPR:$src2, DPR:$src1),
Anton Korobeynikov14636a52009-09-08 22:51:43 +00002182 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002183def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002184 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002185 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
Bob Wilsone60fee02009-06-22 23:27:02 +00002186 [(set QPR:$dst,
2187 (v4i32 (or (and QPR:$src2, QPR:$src1),
Anton Korobeynikov14636a52009-09-08 22:51:43 +00002188 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002189
2190// VBIF : Vector Bitwise Insert if False
Evan Cheng09c61b32009-11-23 21:57:23 +00002191// like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
Johnny Chen7c313be2010-02-09 23:05:23 +00002192def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2193 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2194 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2195 [/* For disassembly only; pattern left blank */]>;
2196def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2197 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2198 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2199 [/* For disassembly only; pattern left blank */]>;
2200
Bob Wilsone60fee02009-06-22 23:27:02 +00002201// VBIT : Vector Bitwise Insert if True
Evan Cheng09c61b32009-11-23 21:57:23 +00002202// like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
Johnny Chen7c313be2010-02-09 23:05:23 +00002203def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2204 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2205 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2206 [/* For disassembly only; pattern left blank */]>;
2207def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2208 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2209 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2210 [/* For disassembly only; pattern left blank */]>;
2211
2212// VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
Bob Wilsone60fee02009-06-22 23:27:02 +00002213// for equivalent operations with different register constraints; it just
2214// inserts copies.
2215
2216// Vector Absolute Differences.
2217
2218// VABD : Vector Absolute Difference
Evan Cheng67abcec2009-11-21 06:21:52 +00002219defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2220 IIC_VBINi4Q, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002221 "vabd", "s", int_arm_neon_vabds, 0>;
Evan Cheng67abcec2009-11-21 06:21:52 +00002222defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2223 IIC_VBINi4Q, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002224 "vabd", "u", int_arm_neon_vabdu, 0>;
Evan Cheng67abcec2009-11-21 06:21:52 +00002225def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
Evan Cheng09c61b32009-11-23 21:57:23 +00002226 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
Evan Cheng67abcec2009-11-21 06:21:52 +00002227def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002228 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002229
2230// VABDL : Vector Absolute Difference Long (Q = | D - D |)
Evan Cheng67abcec2009-11-21 06:21:52 +00002231defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002232 "vabdl", "s", int_arm_neon_vabdls, 0>;
Evan Cheng67abcec2009-11-21 06:21:52 +00002233defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002234 "vabdl", "u", int_arm_neon_vabdlu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002235
2236// VABA : Vector Absolute Difference and Accumulate
Evan Cheng09c61b32009-11-23 21:57:23 +00002237defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2238defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002239
2240// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
Evan Cheng09c61b32009-11-23 21:57:23 +00002241defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2242defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002243
2244// Vector Maximum and Minimum.
2245
2246// VMAX : Vector Maximum
Bob Wilson1d2c4212010-02-17 00:31:29 +00002247defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002248 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
Bob Wilson1d2c4212010-02-17 00:31:29 +00002249defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002250 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2251def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2252 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2253def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2254 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002255
2256// VMIN : Vector Minimum
Bob Wilson1d2c4212010-02-17 00:31:29 +00002257defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002258 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
Bob Wilson1d2c4212010-02-17 00:31:29 +00002259defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Evan Cheng09c61b32009-11-23 21:57:23 +00002260 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2261def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2262 v2f32, v2f32, int_arm_neon_vmins, 1>;
2263def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2264 v4f32, v4f32, int_arm_neon_vmins, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002265
2266// Vector Pairwise Operations.
2267
2268// VPADD : Vector Pairwise Add
Evan Cheng09c61b32009-11-23 21:57:23 +00002269def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2270 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2271def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2272 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2273def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2274 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2275def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2276 v2f32, v2f32, int_arm_neon_vpadd, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002277
2278// VPADDL : Vector Pairwise Add Long
Evan Cheng09c61b32009-11-23 21:57:23 +00002279defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
Bob Wilsone60fee02009-06-22 23:27:02 +00002280 int_arm_neon_vpaddls>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002281defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
Bob Wilsone60fee02009-06-22 23:27:02 +00002282 int_arm_neon_vpaddlu>;
2283
2284// VPADAL : Vector Pairwise Add and Accumulate Long
Evan Cheng09c61b32009-11-23 21:57:23 +00002285defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
Bob Wilsone60fee02009-06-22 23:27:02 +00002286 int_arm_neon_vpadals>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002287defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
Bob Wilsone60fee02009-06-22 23:27:02 +00002288 int_arm_neon_vpadalu>;
2289
2290// VPMAX : Vector Pairwise Maximum
Evan Cheng09c61b32009-11-23 21:57:23 +00002291def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2292 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2293def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2294 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2295def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2296 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2297def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2298 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2299def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2300 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2301def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2302 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2303def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2304 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002305
2306// VPMIN : Vector Pairwise Minimum
Evan Cheng09c61b32009-11-23 21:57:23 +00002307def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2308 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2309def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2310 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2311def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2312 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2313def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2314 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2315def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2316 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2317def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2318 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2319def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2320 v2f32, v2f32, int_arm_neon_vpmins, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002321
2322// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2323
2324// VRECPE : Vector Reciprocal Estimate
David Goodwin78caa122009-09-23 21:38:08 +00002325def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002326 IIC_VUNAD, "vrecpe", "u32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002327 v2i32, v2i32, int_arm_neon_vrecpe>;
David Goodwin78caa122009-09-23 21:38:08 +00002328def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002329 IIC_VUNAQ, "vrecpe", "u32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002330 v4i32, v4i32, int_arm_neon_vrecpe>;
David Goodwin78caa122009-09-23 21:38:08 +00002331def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002332 IIC_VUNAD, "vrecpe", "f32",
Bob Wilson8f10b3f2009-08-11 05:39:44 +00002333 v2f32, v2f32, int_arm_neon_vrecpe>;
David Goodwin78caa122009-09-23 21:38:08 +00002334def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002335 IIC_VUNAQ, "vrecpe", "f32",
Bob Wilson8f10b3f2009-08-11 05:39:44 +00002336 v4f32, v4f32, int_arm_neon_vrecpe>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002337
2338// VRECPS : Vector Reciprocal Step
Evan Cheng09c61b32009-11-23 21:57:23 +00002339def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2340 IIC_VRECSD, "vrecps", "f32",
2341 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2342def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2343 IIC_VRECSQ, "vrecps", "f32",
2344 v4f32, v4f32, int_arm_neon_vrecps, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002345
2346// VRSQRTE : Vector Reciprocal Square Root Estimate
David Goodwin78caa122009-09-23 21:38:08 +00002347def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002348 IIC_VUNAD, "vrsqrte", "u32",
David Goodwin78caa122009-09-23 21:38:08 +00002349 v2i32, v2i32, int_arm_neon_vrsqrte>;
2350def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002351 IIC_VUNAQ, "vrsqrte", "u32",
David Goodwin78caa122009-09-23 21:38:08 +00002352 v4i32, v4i32, int_arm_neon_vrsqrte>;
2353def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002354 IIC_VUNAD, "vrsqrte", "f32",
David Goodwin78caa122009-09-23 21:38:08 +00002355 v2f32, v2f32, int_arm_neon_vrsqrte>;
2356def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002357 IIC_VUNAQ, "vrsqrte", "f32",
David Goodwin78caa122009-09-23 21:38:08 +00002358 v4f32, v4f32, int_arm_neon_vrsqrte>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002359
2360// VRSQRTS : Vector Reciprocal Square Root Step
Evan Cheng09c61b32009-11-23 21:57:23 +00002361def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2362 IIC_VRECSD, "vrsqrts", "f32",
2363 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2364def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2365 IIC_VRECSQ, "vrsqrts", "f32",
2366 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002367
2368// Vector Shifts.
2369
2370// VSHL : Vector Shift
Johnny Chen7c3f3862010-03-17 23:26:50 +00002371defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2372 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2373defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2374 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002375// VSHL : Vector Shift Left (Immediate)
Johnny Chen7c3f3862010-03-17 23:26:50 +00002376defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002377// VSHR : Vector Shift Right (Immediate)
Evan Cheng09c61b32009-11-23 21:57:23 +00002378defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2379defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002380
2381// VSHLL : Vector Shift Left Long
Evan Cheng09c61b32009-11-23 21:57:23 +00002382defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2383defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002384
2385// VSHLL : Vector Shift Left Long (with maximum shift count)
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002386class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
Evan Cheng09c61b32009-11-23 21:57:23 +00002387 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002388 ValueType OpTy, SDNode OpNode>
Evan Cheng09c61b32009-11-23 21:57:23 +00002389 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2390 ResTy, OpTy, OpNode> {
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002391 let Inst{21-16} = op21_16;
2392}
Evan Cheng09c61b32009-11-23 21:57:23 +00002393def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002394 v8i16, v8i8, NEONvshlli>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002395def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002396 v4i32, v4i16, NEONvshlli>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002397def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002398 v2i64, v2i32, NEONvshlli>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002399
2400// VSHRN : Vector Shift Right and Narrow
Bob Wilson1d2c4212010-02-17 00:31:29 +00002401defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2402 NEONvshrn>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002403
2404// VRSHL : Vector Rounding Shift
Johnny Chen7c3f3862010-03-17 23:26:50 +00002405defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2406 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2407defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2408 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002409// VRSHR : Vector Rounding Shift Right
Bob Wilson1d2c4212010-02-17 00:31:29 +00002410defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2411defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002412
2413// VRSHRN : Vector Rounding Shift Right and Narrow
Evan Cheng09c61b32009-11-23 21:57:23 +00002414defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002415 NEONvrshrn>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002416
2417// VQSHL : Vector Saturating Shift
Johnny Chen7c3f3862010-03-17 23:26:50 +00002418defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2419 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2420defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2421 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002422// VQSHL : Vector Saturating Shift Left (Immediate)
Johnny Chen7c3f3862010-03-17 23:26:50 +00002423defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2424defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002425// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
Johnny Chen7c3f3862010-03-17 23:26:50 +00002426defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002427
2428// VQSHRN : Vector Saturating Shift Right and Narrow
Evan Cheng09c61b32009-11-23 21:57:23 +00002429defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002430 NEONvqshrns>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002431defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002432 NEONvqshrnu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002433
2434// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
Evan Cheng09c61b32009-11-23 21:57:23 +00002435defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002436 NEONvqshrnsu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002437
2438// VQRSHL : Vector Saturating Rounding Shift
Johnny Chen7c3f3862010-03-17 23:26:50 +00002439defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2440 IIC_VSHLi4Q, "vqrshl", "s",
2441 int_arm_neon_vqrshifts, 0>;
2442defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2443 IIC_VSHLi4Q, "vqrshl", "u",
2444 int_arm_neon_vqrshiftu, 0>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002445
2446// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
Evan Cheng09c61b32009-11-23 21:57:23 +00002447defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002448 NEONvqrshrns>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002449defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002450 NEONvqrshrnu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002451
2452// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
Evan Cheng09c61b32009-11-23 21:57:23 +00002453defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002454 NEONvqrshrnsu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002455
2456// VSRA : Vector Shift Right and Accumulate
Evan Cheng09c61b32009-11-23 21:57:23 +00002457defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2458defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002459// VRSRA : Vector Rounding Shift Right and Accumulate
Evan Cheng09c61b32009-11-23 21:57:23 +00002460defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2461defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002462
2463// VSLI : Vector Shift Left and Insert
Johnny Chen7c3f3862010-03-17 23:26:50 +00002464defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002465// VSRI : Vector Shift Right and Insert
Evan Cheng09c61b32009-11-23 21:57:23 +00002466defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002467
2468// Vector Absolute and Saturating Absolute.
2469
2470// VABS : Vector Absolute Value
David Goodwin78caa122009-09-23 21:38:08 +00002471defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002472 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
Bob Wilsone60fee02009-06-22 23:27:02 +00002473 int_arm_neon_vabs>;
David Goodwin78caa122009-09-23 21:38:08 +00002474def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002475 IIC_VUNAD, "vabs", "f32",
Bob Wilson8f10b3f2009-08-11 05:39:44 +00002476 v2f32, v2f32, int_arm_neon_vabs>;
David Goodwin78caa122009-09-23 21:38:08 +00002477def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002478 IIC_VUNAQ, "vabs", "f32",
Bob Wilson8f10b3f2009-08-11 05:39:44 +00002479 v4f32, v4f32, int_arm_neon_vabs>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002480
2481// VQABS : Vector Saturating Absolute Value
David Goodwin78caa122009-09-23 21:38:08 +00002482defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002483 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
Bob Wilsone60fee02009-06-22 23:27:02 +00002484 int_arm_neon_vqabs>;
2485
2486// Vector Negate.
2487
2488def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2489def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2490
Evan Cheng09c61b32009-11-23 21:57:23 +00002491class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsone60fee02009-06-22 23:27:02 +00002492 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002493 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002494 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002495class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsone60fee02009-06-22 23:27:02 +00002496 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002497 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002498 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2499
2500// VNEG : Vector Negate
Evan Cheng09c61b32009-11-23 21:57:23 +00002501def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2502def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2503def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2504def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2505def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2506def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002507
2508// VNEG : Vector Negate (floating-point)
Bob Wilson154999f2010-02-17 22:23:11 +00002509def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
David Goodwin36bff0c2009-09-25 18:38:29 +00002510 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002511 "vneg", "f32", "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002512 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2513def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
David Goodwin36bff0c2009-09-25 18:38:29 +00002514 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002515 "vneg", "f32", "$dst, $src", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002516 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2517
2518def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2519def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2520def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2521def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2522def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2523def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2524
2525// VQNEG : Vector Saturating Negate
David Goodwin78caa122009-09-23 21:38:08 +00002526defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002527 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
Bob Wilsone60fee02009-06-22 23:27:02 +00002528 int_arm_neon_vqneg>;
2529
2530// Vector Bit Counting Operations.
2531
2532// VCLS : Vector Count Leading Sign Bits
David Goodwin78caa122009-09-23 21:38:08 +00002533defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002534 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
Bob Wilsone60fee02009-06-22 23:27:02 +00002535 int_arm_neon_vcls>;
2536// VCLZ : Vector Count Leading Zeros
David Goodwin78caa122009-09-23 21:38:08 +00002537defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002538 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
Bob Wilsone60fee02009-06-22 23:27:02 +00002539 int_arm_neon_vclz>;
2540// VCNT : Vector Count One Bits
David Goodwin78caa122009-09-23 21:38:08 +00002541def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002542 IIC_VCNTiD, "vcnt", "8",
Bob Wilsone60fee02009-06-22 23:27:02 +00002543 v8i8, v8i8, int_arm_neon_vcnt>;
David Goodwin78caa122009-09-23 21:38:08 +00002544def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
Evan Cheng09c61b32009-11-23 21:57:23 +00002545 IIC_VCNTiQ, "vcnt", "8",
Bob Wilsone60fee02009-06-22 23:27:02 +00002546 v16i8, v16i8, int_arm_neon_vcnt>;
2547
Johnny Chened5852c2010-02-24 20:06:07 +00002548// Vector Swap -- for disassembly only.
2549def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2550 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2551 "vswp", "$dst, $src", "", []>;
2552def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2553 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2554 "vswp", "$dst, $src", "", []>;
2555
Bob Wilsone60fee02009-06-22 23:27:02 +00002556// Vector Move Operations.
2557
2558// VMOV : Vector Move (Register)
2559
Evan Cheng09c61b32009-11-23 21:57:23 +00002560def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2561 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2562def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2563 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002564
2565// VMOV : Vector Move (Immediate)
2566
2567// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2568def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2569 return ARM::getVMOVImm(N, 1, *CurDAG);
2570}]>;
2571def vmovImm8 : PatLeaf<(build_vector), [{
2572 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2573}], VMOV_get_imm8>;
2574
2575// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2576def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2577 return ARM::getVMOVImm(N, 2, *CurDAG);
2578}]>;
2579def vmovImm16 : PatLeaf<(build_vector), [{
2580 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2581}], VMOV_get_imm16>;
2582
2583// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2584def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2585 return ARM::getVMOVImm(N, 4, *CurDAG);
2586}]>;
2587def vmovImm32 : PatLeaf<(build_vector), [{
2588 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2589}], VMOV_get_imm32>;
2590
2591// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2592def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2593 return ARM::getVMOVImm(N, 8, *CurDAG);
2594}]>;
2595def vmovImm64 : PatLeaf<(build_vector), [{
2596 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2597}], VMOV_get_imm64>;
2598
2599// Note: Some of the cmode bits in the following VMOV instructions need to
2600// be encoded based on the immed values.
2601
2602def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002603 (ins h8imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002604 "vmov", "i8", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002605 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2606def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002607 (ins h8imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002608 "vmov", "i8", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002609 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2610
Johnny Chencf4fad22009-12-01 00:02:02 +00002611def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002612 (ins h16imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002613 "vmov", "i16", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002614 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
Johnny Chencf4fad22009-12-01 00:02:02 +00002615def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002616 (ins h16imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002617 "vmov", "i16", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002618 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2619
Johnny Chencf4fad22009-12-01 00:02:02 +00002620def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002621 (ins h32imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002622 "vmov", "i32", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002623 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
Johnny Chencf4fad22009-12-01 00:02:02 +00002624def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002625 (ins h32imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002626 "vmov", "i32", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002627 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2628
2629def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002630 (ins h64imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002631 "vmov", "i64", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002632 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2633def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
Bob Wilson6a14a002009-11-06 23:33:28 +00002634 (ins h64imm:$SIMM), IIC_VMOVImm,
Evan Cheng09c61b32009-11-23 21:57:23 +00002635 "vmov", "i64", "$dst, $SIMM", "",
Bob Wilsone60fee02009-06-22 23:27:02 +00002636 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2637
2638// VMOV : Vector Get Lane (move scalar to ARM core register)
2639
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002640def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
Bob Wilson30ff4492009-08-21 21:58:55 +00002641 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002642 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
Bob Wilsone60fee02009-06-22 23:27:02 +00002643 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2644 imm:$lane))]>;
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002645def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
Bob Wilson30ff4492009-08-21 21:58:55 +00002646 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002647 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
Bob Wilsone60fee02009-06-22 23:27:02 +00002648 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2649 imm:$lane))]>;
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002650def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
Bob Wilson30ff4492009-08-21 21:58:55 +00002651 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002652 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
Bob Wilsone60fee02009-06-22 23:27:02 +00002653 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2654 imm:$lane))]>;
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002655def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
Bob Wilson30ff4492009-08-21 21:58:55 +00002656 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002657 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
Bob Wilsone60fee02009-06-22 23:27:02 +00002658 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2659 imm:$lane))]>;
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002660def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
Bob Wilson30ff4492009-08-21 21:58:55 +00002661 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002662 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
Bob Wilsone60fee02009-06-22 23:27:02 +00002663 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2664 imm:$lane))]>;
2665// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2666def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2667 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002668 (DSubReg_i8_reg imm:$lane))),
Bob Wilsone60fee02009-06-22 23:27:02 +00002669 (SubReg_i8_lane imm:$lane))>;
2670def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2671 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002672 (DSubReg_i16_reg imm:$lane))),
Bob Wilsone60fee02009-06-22 23:27:02 +00002673 (SubReg_i16_lane imm:$lane))>;
2674def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2675 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002676 (DSubReg_i8_reg imm:$lane))),
Bob Wilsone60fee02009-06-22 23:27:02 +00002677 (SubReg_i8_lane imm:$lane))>;
2678def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2679 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002680 (DSubReg_i16_reg imm:$lane))),
Bob Wilsone60fee02009-06-22 23:27:02 +00002681 (SubReg_i16_lane imm:$lane))>;
2682def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2683 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002684 (DSubReg_i32_reg imm:$lane))),
Bob Wilsone60fee02009-06-22 23:27:02 +00002685 (SubReg_i32_lane imm:$lane))>;
Anton Korobeynikov44e0a6c2009-08-28 23:41:26 +00002686def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
Bob Wilson1d2c4212010-02-17 00:31:29 +00002687 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
Anton Korobeynikov3600d162009-09-12 22:21:08 +00002688 (SSubReg_f32_reg imm:$src2))>;
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002689def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
Bob Wilson1d2c4212010-02-17 00:31:29 +00002690 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
Anton Korobeynikov3600d162009-09-12 22:21:08 +00002691 (SSubReg_f32_reg imm:$src2))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002692//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002693// (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002694def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002695 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002696
2697
2698// VMOV : Vector Set Lane (move ARM core register to scalar)
2699
2700let Constraints = "$src1 = $dst" in {
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002701def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
Bob Wilson30ff4492009-08-21 21:58:55 +00002702 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002703 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
Bob Wilsone60fee02009-06-22 23:27:02 +00002704 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2705 GPR:$src2, imm:$lane))]>;
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002706def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
Bob Wilson30ff4492009-08-21 21:58:55 +00002707 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002708 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
Bob Wilsone60fee02009-06-22 23:27:02 +00002709 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2710 GPR:$src2, imm:$lane))]>;
Johnny Chen0c1d2c12009-11-23 17:48:17 +00002711def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
Bob Wilson30ff4492009-08-21 21:58:55 +00002712 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
Evan Cheng09c61b32009-11-23 21:57:23 +00002713 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
Bob Wilsone60fee02009-06-22 23:27:02 +00002714 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2715 GPR:$src2, imm:$lane))]>;
2716}
2717def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2718 (v16i8 (INSERT_SUBREG QPR:$src1,
Chris Lattner4e624722010-03-08 18:51:21 +00002719 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002720 (DSubReg_i8_reg imm:$lane))),
Chris Lattner4e624722010-03-08 18:51:21 +00002721 GPR:$src2, (SubReg_i8_lane imm:$lane))),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002722 (DSubReg_i8_reg imm:$lane)))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002723def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2724 (v8i16 (INSERT_SUBREG QPR:$src1,
Chris Lattner4e624722010-03-08 18:51:21 +00002725 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002726 (DSubReg_i16_reg imm:$lane))),
Chris Lattner4e624722010-03-08 18:51:21 +00002727 GPR:$src2, (SubReg_i16_lane imm:$lane))),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002728 (DSubReg_i16_reg imm:$lane)))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002729def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2730 (v4i32 (INSERT_SUBREG QPR:$src1,
Chris Lattner4e624722010-03-08 18:51:21 +00002731 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002732 (DSubReg_i32_reg imm:$lane))),
Chris Lattner4e624722010-03-08 18:51:21 +00002733 GPR:$src2, (SubReg_i32_lane imm:$lane))),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002734 (DSubReg_i32_reg imm:$lane)))>;
2735
Anton Korobeynikovd3352772009-08-30 19:06:39 +00002736def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
Anton Korobeynikovd9331212009-11-02 00:11:39 +00002737 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2738 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002739def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
Anton Korobeynikovd9331212009-11-02 00:11:39 +00002740 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2741 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002742
2743//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002744// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002745def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
Anton Korobeynikov49284e72009-08-08 14:06:07 +00002746 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002747
Anton Korobeynikovbaee7b22009-08-27 14:38:44 +00002748def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2749 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
Chris Lattnerc002b572010-03-15 00:52:43 +00002750def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
Anton Korobeynikovbaee7b22009-08-27 14:38:44 +00002751 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2752def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2753 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2754
Anton Korobeynikov872393c2009-08-27 16:10:17 +00002755def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2756 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2757def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2758 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2759def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2760 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2761
2762def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2763 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2764 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2765 arm_dsubreg_0)>;
2766def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2767 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2768 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2769 arm_dsubreg_0)>;
2770def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2771 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2772 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2773 arm_dsubreg_0)>;
2774
Bob Wilsone60fee02009-06-22 23:27:02 +00002775// VDUP : Vector Duplicate (from ARM core register to all elements)
2776
Evan Cheng09c61b32009-11-23 21:57:23 +00002777class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
Bob Wilsone60fee02009-06-22 23:27:02 +00002778 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002779 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
Bob Wilsonf4f1a272009-08-14 05:13:08 +00002780 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002781class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
Bob Wilsone60fee02009-06-22 23:27:02 +00002782 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002783 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
Bob Wilsonf4f1a272009-08-14 05:13:08 +00002784 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002785
Evan Cheng09c61b32009-11-23 21:57:23 +00002786def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
2787def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
2788def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
2789def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
2790def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
2791def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002792
2793def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002794 IIC_VMOVIS, "vdup", "32", "$dst, $src",
Bob Wilsonf4f1a272009-08-14 05:13:08 +00002795 [(set DPR:$dst, (v2f32 (NEONvdup
2796 (f32 (bitconvert GPR:$src)))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002797def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002798 IIC_VMOVIS, "vdup", "32", "$dst, $src",
Bob Wilsonf4f1a272009-08-14 05:13:08 +00002799 [(set QPR:$dst, (v4f32 (NEONvdup
2800 (f32 (bitconvert GPR:$src)))))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002801
2802// VDUP : Vector Duplicate Lane (from scalar to all elements)
2803
Evan Cheng09c61b32009-11-23 21:57:23 +00002804class VDUPLND<bits<2> op19_18, bits<2> op17_16,
2805 string OpcodeStr, string Dt, ValueType Ty>
Johnny Chen9ee642f2009-11-23 21:00:43 +00002806 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
David Goodwin36bff0c2009-09-25 18:38:29 +00002807 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002808 OpcodeStr, Dt, "$dst, $src[$lane]", "",
Bob Wilson206f6c42009-08-14 05:08:32 +00002809 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002810
Evan Cheng09c61b32009-11-23 21:57:23 +00002811class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
Johnny Chen9ee642f2009-11-23 21:00:43 +00002812 ValueType ResTy, ValueType OpTy>
2813 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
David Goodwin36bff0c2009-09-25 18:38:29 +00002814 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002815 OpcodeStr, Dt, "$dst, $src[$lane]", "",
Bob Wilson206f6c42009-08-14 05:08:32 +00002816 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002817
Bob Wilson52e0d9d2009-10-21 02:15:46 +00002818// Inst{19-16} is partially specified depending on the element size.
2819
Evan Cheng09c61b32009-11-23 21:57:23 +00002820def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
2821def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
2822def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
2823def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
2824def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
2825def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
2826def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
2827def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002828
Bob Wilson206f6c42009-08-14 05:08:32 +00002829def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2830 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2831 (DSubReg_i8_reg imm:$lane))),
2832 (SubReg_i8_lane imm:$lane)))>;
2833def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2834 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2835 (DSubReg_i16_reg imm:$lane))),
2836 (SubReg_i16_lane imm:$lane)))>;
2837def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2838 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2839 (DSubReg_i32_reg imm:$lane))),
2840 (SubReg_i32_lane imm:$lane)))>;
2841def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2842 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2843 (DSubReg_i32_reg imm:$lane))),
2844 (SubReg_i32_lane imm:$lane)))>;
2845
Johnny Chen9ee642f2009-11-23 21:00:43 +00002846def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2847 (outs DPR:$dst), (ins SPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002848 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
Johnny Chen9ee642f2009-11-23 21:00:43 +00002849 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
Anton Korobeynikov9c913fb2009-08-07 22:36:50 +00002850
Johnny Chen9ee642f2009-11-23 21:00:43 +00002851def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2852 (outs QPR:$dst), (ins SPR:$src),
Evan Cheng09c61b32009-11-23 21:57:23 +00002853 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
Johnny Chen9ee642f2009-11-23 21:00:43 +00002854 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
Anton Korobeynikov9c913fb2009-08-07 22:36:50 +00002855
Anton Korobeynikovb261a192009-09-02 21:21:28 +00002856def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2857 (INSERT_SUBREG QPR:$src,
Bob Wilson1d2c4212010-02-17 00:31:29 +00002858 (i64 (EXTRACT_SUBREG QPR:$src,
2859 (DSubReg_f64_reg imm:$lane))),
Anton Korobeynikovb261a192009-09-02 21:21:28 +00002860 (DSubReg_f64_other_reg imm:$lane))>;
2861def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2862 (INSERT_SUBREG QPR:$src,
Bob Wilson1d2c4212010-02-17 00:31:29 +00002863 (f64 (EXTRACT_SUBREG QPR:$src,
2864 (DSubReg_f64_reg imm:$lane))),
Anton Korobeynikovb261a192009-09-02 21:21:28 +00002865 (DSubReg_f64_other_reg imm:$lane))>;
2866
Bob Wilsone60fee02009-06-22 23:27:02 +00002867// VMOVN : Vector Narrowing Move
Evan Cheng09c61b32009-11-23 21:57:23 +00002868defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
2869 "vmovn", "i", int_arm_neon_vmovn>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002870// VQMOVN : Vector Saturating Narrowing Move
Evan Cheng09c61b32009-11-23 21:57:23 +00002871defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
2872 "vqmovn", "s", int_arm_neon_vqmovns>;
2873defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
2874 "vqmovn", "u", int_arm_neon_vqmovnu>;
2875defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
2876 "vqmovun", "s", int_arm_neon_vqmovnsu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002877// VMOVL : Vector Lengthening Move
Evan Cheng09c61b32009-11-23 21:57:23 +00002878defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
2879 int_arm_neon_vmovls>;
2880defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
2881 int_arm_neon_vmovlu>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002882
2883// Vector Conversions.
2884
Johnny Chen09a43762010-03-17 17:52:21 +00002885// VCVT : Vector Convert Between Floating-Point and Integers
Johnny Chen7c3f3862010-03-17 23:26:50 +00002886def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2887 v2i32, v2f32, fp_to_sint>;
2888def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2889 v2i32, v2f32, fp_to_uint>;
2890def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2891 v2f32, v2i32, sint_to_fp>;
2892def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2893 v2f32, v2i32, uint_to_fp>;
Johnny Chen09a43762010-03-17 17:52:21 +00002894
Johnny Chen7c3f3862010-03-17 23:26:50 +00002895def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2896 v4i32, v4f32, fp_to_sint>;
2897def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2898 v4i32, v4f32, fp_to_uint>;
2899def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2900 v4f32, v4i32, sint_to_fp>;
2901def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2902 v4f32, v4i32, uint_to_fp>;
Bob Wilsone60fee02009-06-22 23:27:02 +00002903
2904// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
Evan Cheng09c61b32009-11-23 21:57:23 +00002905def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002906 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002907def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002908 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002909def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002910 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002911def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002912 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2913
Evan Cheng09c61b32009-11-23 21:57:23 +00002914def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002915 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002916def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002917 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002918def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002919 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002920def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
Bob Wilsone60fee02009-06-22 23:27:02 +00002921 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2922
Bob Wilson08479272009-08-12 22:31:50 +00002923// Vector Reverse.
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002924
2925// VREV64 : Vector Reverse elements within 64-bit doublewords
2926
Evan Cheng09c61b32009-11-23 21:57:23 +00002927class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002928 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002929 (ins DPR:$src), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002930 OpcodeStr, Dt, "$dst, $src", "",
Bob Wilson08479272009-08-12 22:31:50 +00002931 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002932class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002933 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002934 (ins QPR:$src), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002935 OpcodeStr, Dt, "$dst, $src", "",
Bob Wilson08479272009-08-12 22:31:50 +00002936 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002937
Evan Cheng09c61b32009-11-23 21:57:23 +00002938def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
2939def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
2940def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
2941def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002942
Evan Cheng09c61b32009-11-23 21:57:23 +00002943def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
2944def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
2945def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
2946def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002947
2948// VREV32 : Vector Reverse elements within 32-bit words
2949
Evan Cheng09c61b32009-11-23 21:57:23 +00002950class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002951 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002952 (ins DPR:$src), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002953 OpcodeStr, Dt, "$dst, $src", "",
Bob Wilson08479272009-08-12 22:31:50 +00002954 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002955class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002956 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002957 (ins QPR:$src), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002958 OpcodeStr, Dt, "$dst, $src", "",
Bob Wilson08479272009-08-12 22:31:50 +00002959 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002960
Evan Cheng09c61b32009-11-23 21:57:23 +00002961def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
2962def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002963
Evan Cheng09c61b32009-11-23 21:57:23 +00002964def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
2965def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002966
2967// VREV16 : Vector Reverse elements within 16-bit halfwords
2968
Evan Cheng09c61b32009-11-23 21:57:23 +00002969class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002970 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002971 (ins DPR:$src), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002972 OpcodeStr, Dt, "$dst, $src", "",
Bob Wilson08479272009-08-12 22:31:50 +00002973 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
Evan Cheng09c61b32009-11-23 21:57:23 +00002974class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002975 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00002976 (ins QPR:$src), IIC_VMOVD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002977 OpcodeStr, Dt, "$dst, $src", "",
Bob Wilson08479272009-08-12 22:31:50 +00002978 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002979
Evan Cheng09c61b32009-11-23 21:57:23 +00002980def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
2981def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
Bob Wilsonc1cd72e2009-07-26 00:39:34 +00002982
Bob Wilson3ac39132009-08-19 17:03:43 +00002983// Other Vector Shuffles.
2984
2985// VEXT : Vector Extract
2986
Evan Cheng09c61b32009-11-23 21:57:23 +00002987class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
Johnny Chen6c6fa9a2009-11-23 20:09:13 +00002988 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
2989 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
Evan Cheng09c61b32009-11-23 21:57:23 +00002990 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
Johnny Chen6c6fa9a2009-11-23 20:09:13 +00002991 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2992 (Ty DPR:$rhs), imm:$index)))]>;
Anton Korobeynikov6c28c002009-08-21 12:40:21 +00002993
Evan Cheng09c61b32009-11-23 21:57:23 +00002994class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
Johnny Chen6c6fa9a2009-11-23 20:09:13 +00002995 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
2996 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
Evan Cheng09c61b32009-11-23 21:57:23 +00002997 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
Johnny Chen6c6fa9a2009-11-23 20:09:13 +00002998 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2999 (Ty QPR:$rhs), imm:$index)))]>;
Anton Korobeynikov6c28c002009-08-21 12:40:21 +00003000
Evan Cheng09c61b32009-11-23 21:57:23 +00003001def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3002def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3003def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3004def VEXTdf : VEXTd<"vext", "32", v2f32>;
Anton Korobeynikov6c28c002009-08-21 12:40:21 +00003005
Evan Cheng09c61b32009-11-23 21:57:23 +00003006def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3007def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3008def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3009def VEXTqf : VEXTq<"vext", "32", v4f32>;
Bob Wilson3ac39132009-08-19 17:03:43 +00003010
Bob Wilson3b169332009-08-08 05:53:00 +00003011// VTRN : Vector Transpose
3012
Evan Cheng09c61b32009-11-23 21:57:23 +00003013def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3014def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3015def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
Bob Wilson3b169332009-08-08 05:53:00 +00003016
Evan Cheng09c61b32009-11-23 21:57:23 +00003017def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3018def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3019def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
Bob Wilson3b169332009-08-08 05:53:00 +00003020
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +00003021// VUZP : Vector Unzip (Deinterleave)
3022
Evan Cheng09c61b32009-11-23 21:57:23 +00003023def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3024def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3025def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +00003026
Evan Cheng09c61b32009-11-23 21:57:23 +00003027def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3028def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3029def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +00003030
3031// VZIP : Vector Zip (Interleave)
3032
Evan Cheng09c61b32009-11-23 21:57:23 +00003033def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3034def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3035def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
Bob Wilsonc1eaa4d2009-08-08 06:13:25 +00003036
Evan Cheng09c61b32009-11-23 21:57:23 +00003037def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3038def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3039def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
Bob Wilson3b169332009-08-08 05:53:00 +00003040
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003041// Vector Table Lookup and Table Extension.
3042
3043// VTBL : Vector Table Lookup
3044def VTBL1
3045 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003046 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
Evan Cheng09c61b32009-11-23 21:57:23 +00003047 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003048 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
Evan Cheng7c8d5ea2009-10-01 08:22:27 +00003049let hasExtraSrcRegAllocReq = 1 in {
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003050def VTBL2
3051 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003052 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
Bob Wilson82dcfa32010-01-18 01:24:43 +00003053 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003054 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3055 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3056def VTBL3
3057 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003058 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
Bob Wilson82dcfa32010-01-18 01:24:43 +00003059 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003060 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3061 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3062def VTBL4
3063 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003064 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
Bob Wilson82dcfa32010-01-18 01:24:43 +00003065 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003066 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3067 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
Evan Cheng7c8d5ea2009-10-01 08:22:27 +00003068} // hasExtraSrcRegAllocReq = 1
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003069
3070// VTBX : Vector Table Extension
3071def VTBX1
3072 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003073 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
Evan Cheng09c61b32009-11-23 21:57:23 +00003074 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003075 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3076 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
Evan Cheng7c8d5ea2009-10-01 08:22:27 +00003077let hasExtraSrcRegAllocReq = 1 in {
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003078def VTBX2
3079 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003080 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
Bob Wilson82dcfa32010-01-18 01:24:43 +00003081 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003082 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3083 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3084def VTBX3
3085 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
David Goodwin36bff0c2009-09-25 18:38:29 +00003086 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
Bob Wilson82dcfa32010-01-18 01:24:43 +00003087 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003088 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3089 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3090def VTBX4
3091 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
David Goodwin36bff0c2009-09-25 18:38:29 +00003092 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
Bob Wilson82dcfa32010-01-18 01:24:43 +00003093 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3094 "$orig = $dst",
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003095 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3096 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
Evan Cheng7c8d5ea2009-10-01 08:22:27 +00003097} // hasExtraSrcRegAllocReq = 1
Bob Wilson5ef42ed2009-08-12 20:51:55 +00003098
Bob Wilsone60fee02009-06-22 23:27:02 +00003099//===----------------------------------------------------------------------===//
Evan Cheng46961d82009-08-07 19:30:41 +00003100// NEON instructions for single-precision FP math
3101//===----------------------------------------------------------------------===//
3102
Bob Wilson154999f2010-02-17 22:23:11 +00003103class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3104 : NEONFPPat<(ResTy (OpNode SPR:$a)),
Chris Lattner4e624722010-03-08 18:51:21 +00003105 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3106 SPR:$a, arm_ssubreg_0))),
Bob Wilson154999f2010-02-17 22:23:11 +00003107 arm_ssubreg_0)>;
3108
3109class N3VSPat<SDNode OpNode, NeonI Inst>
3110 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
Chris Lattner4e624722010-03-08 18:51:21 +00003111 (EXTRACT_SUBREG (v2f32
3112 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3113 SPR:$a, arm_ssubreg_0),
3114 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3115 SPR:$b, arm_ssubreg_0))),
Bob Wilson154999f2010-02-17 22:23:11 +00003116 arm_ssubreg_0)>;
3117
3118class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3119 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3120 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3121 SPR:$acc, arm_ssubreg_0),
3122 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3123 SPR:$a, arm_ssubreg_0),
3124 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3125 SPR:$b, arm_ssubreg_0)),
3126 arm_ssubreg_0)>;
3127
Evan Cheng46961d82009-08-07 19:30:41 +00003128// These need separate instructions because they must use DPR_VFP2 register
3129// class which have SPR sub-registers.
3130
3131// Vector Add Operations used for single-precision FP
3132let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003133def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3134def : N3VSPat<fadd, VADDfd_sfp>;
Evan Cheng46961d82009-08-07 19:30:41 +00003135
David Goodwin4b358db2009-08-10 22:17:39 +00003136// Vector Sub Operations used for single-precision FP
3137let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003138def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3139def : N3VSPat<fsub, VSUBfd_sfp>;
David Goodwin4b358db2009-08-10 22:17:39 +00003140
Evan Cheng46961d82009-08-07 19:30:41 +00003141// Vector Multiply Operations used for single-precision FP
3142let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003143def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3144def : N3VSPat<fmul, VMULfd_sfp>;
Evan Cheng46961d82009-08-07 19:30:41 +00003145
3146// Vector Multiply-Accumulate/Subtract used for single-precision FP
Jim Grosbach67420bf2009-10-31 22:57:36 +00003147// vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3148// we want to avoid them for now. e.g., alternating vmla/vadd instructions.
Evan Cheng46961d82009-08-07 19:30:41 +00003149
Jim Grosbach67420bf2009-10-31 22:57:36 +00003150//let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003151//def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
Bob Wilson1d2c4212010-02-17 00:31:29 +00003152// v2f32, fmul, fadd>;
Bob Wilson154999f2010-02-17 22:23:11 +00003153//def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
Jim Grosbach67420bf2009-10-31 22:57:36 +00003154
3155//let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003156//def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
Bob Wilson1d2c4212010-02-17 00:31:29 +00003157// v2f32, fmul, fsub>;
Bob Wilson154999f2010-02-17 22:23:11 +00003158//def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
Evan Cheng46961d82009-08-07 19:30:41 +00003159
David Goodwin4b358db2009-08-10 22:17:39 +00003160// Vector Absolute used for single-precision FP
Evan Cheng46961d82009-08-07 19:30:41 +00003161let neverHasSideEffects = 1 in
Bob Wilson7c7fe6e2010-02-17 22:42:54 +00003162def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3163 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3164 "vabs", "f32", "$dst, $src", "", []>;
Bob Wilson154999f2010-02-17 22:23:11 +00003165def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
Evan Cheng46961d82009-08-07 19:30:41 +00003166
David Goodwin4b358db2009-08-10 22:17:39 +00003167// Vector Negate used for single-precision FP
Evan Cheng46961d82009-08-07 19:30:41 +00003168let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003169def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3170 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3171 "vneg", "f32", "$dst, $src", "", []>;
3172def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
Evan Cheng46961d82009-08-07 19:30:41 +00003173
Bob Wilsonbc1d2dc2010-02-18 06:05:53 +00003174// Vector Maximum used for single-precision FP
3175let neverHasSideEffects = 1 in
3176def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3177 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3178 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3179def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3180
3181// Vector Minimum used for single-precision FP
3182let neverHasSideEffects = 1 in
3183def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3184 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3185 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3186def : N3VSPat<NEONfmin, VMINfd_sfp>;
3187
David Goodwin4b358db2009-08-10 22:17:39 +00003188// Vector Convert between single-precision FP and integer
3189let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003190def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3191 v2i32, v2f32, fp_to_sint>;
Bob Wilson899588e2010-03-19 22:51:32 +00003192def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
David Goodwin4b358db2009-08-10 22:17:39 +00003193
3194let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003195def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3196 v2i32, v2f32, fp_to_uint>;
Bob Wilson899588e2010-03-19 22:51:32 +00003197def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
David Goodwin4b358db2009-08-10 22:17:39 +00003198
3199let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003200def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3201 v2f32, v2i32, sint_to_fp>;
Bob Wilson899588e2010-03-19 22:51:32 +00003202def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
David Goodwin4b358db2009-08-10 22:17:39 +00003203
3204let neverHasSideEffects = 1 in
Bob Wilson154999f2010-02-17 22:23:11 +00003205def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3206 v2f32, v2i32, uint_to_fp>;
Bob Wilson899588e2010-03-19 22:51:32 +00003207def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
David Goodwin4b358db2009-08-10 22:17:39 +00003208
Evan Cheng46961d82009-08-07 19:30:41 +00003209//===----------------------------------------------------------------------===//
Bob Wilsone60fee02009-06-22 23:27:02 +00003210// Non-Instruction Patterns
3211//===----------------------------------------------------------------------===//
3212
3213// bit_convert
3214def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3215def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3216def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3217def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3218def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3219def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3220def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3221def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3222def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3223def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3224def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3225def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3226def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3227def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3228def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3229def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3230def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3231def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3232def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3233def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3234def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3235def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3236def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3237def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3238def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3239def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3240def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3241def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3242def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3243def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3244
3245def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3246def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3247def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3248def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3249def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3250def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3251def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3252def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3253def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3254def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3255def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3256def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3257def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3258def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3259def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3260def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3261def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3262def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3263def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3264def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3265def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3266def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3267def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3268def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3269def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3270def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3271def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3272def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3273def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3274def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;