Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 1 | //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the base ARM implementation of TargetRegisterInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARM.h" |
| 15 | #include "ARMAddressingModes.h" |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 16 | #include "ARMBaseInstrInfo.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 17 | #include "ARMBaseRegisterInfo.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 18 | #include "ARMFrameLowering.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 19 | #include "ARMInstrInfo.h" |
| 20 | #include "ARMMachineFunctionInfo.h" |
| 21 | #include "ARMSubtarget.h" |
| 22 | #include "llvm/Constants.h" |
| 23 | #include "llvm/DerivedTypes.h" |
Owen Anderson | 9adc0ab | 2009-07-14 23:09:55 +0000 | [diff] [blame] | 24 | #include "llvm/Function.h" |
| 25 | #include "llvm/LLVMContext.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineConstantPool.h" |
| 27 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 28 | #include "llvm/CodeGen/MachineFunction.h" |
| 29 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 30 | #include "llvm/CodeGen/MachineLocation.h" |
| 31 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 32 | #include "llvm/CodeGen/RegisterScavenging.h" |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 33 | #include "llvm/Support/Debug.h" |
Torok Edwin | ab7c09b | 2009-07-08 18:01:40 +0000 | [diff] [blame] | 34 | #include "llvm/Support/ErrorHandling.h" |
Torok Edwin | dac237e | 2009-07-08 20:53:28 +0000 | [diff] [blame] | 35 | #include "llvm/Support/raw_ostream.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 36 | #include "llvm/Target/TargetFrameLowering.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 37 | #include "llvm/Target/TargetMachine.h" |
| 38 | #include "llvm/Target/TargetOptions.h" |
| 39 | #include "llvm/ADT/BitVector.h" |
| 40 | #include "llvm/ADT/SmallVector.h" |
Jim Grosbach | 18ed9c9 | 2009-10-20 20:19:50 +0000 | [diff] [blame] | 41 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 42 | |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 43 | #define GET_REGINFO_TARGET_DESC |
Evan Cheng | a347f85 | 2011-06-24 01:44:41 +0000 | [diff] [blame] | 44 | #include "ARMGenRegisterInfo.inc" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 45 | |
Evan Cheng | 1b4886d | 2010-11-18 01:28:51 +0000 | [diff] [blame] | 46 | using namespace llvm; |
| 47 | |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 48 | static cl::opt<bool> |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 49 | ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 50 | cl::desc("Force use of virtual base registers for stack load/store")); |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 51 | static cl::opt<bool> |
Jim Grosbach | ae47c6d | 2010-08-26 00:58:06 +0000 | [diff] [blame] | 52 | EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 53 | cl::desc("Enable pre-regalloc stack frame index allocation")); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 54 | static cl::opt<bool> |
Jim Grosbach | d0bd76b | 2010-09-08 20:12:02 +0000 | [diff] [blame] | 55 | EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 56 | cl::desc("Enable use of a base pointer for complex stack frames")); |
| 57 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 58 | ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 59 | const ARMSubtarget &sti) |
Evan Cheng | 0e6a052 | 2011-07-18 20:57:22 +0000 | [diff] [blame^] | 60 | : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 61 | FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), |
| 62 | BasePtr(ARM::R6) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | const unsigned* |
| 66 | ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
| 67 | static const unsigned CalleeSavedRegs[] = { |
| 68 | ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, |
| 69 | ARM::R7, ARM::R6, ARM::R5, ARM::R4, |
| 70 | |
| 71 | ARM::D15, ARM::D14, ARM::D13, ARM::D12, |
| 72 | ARM::D11, ARM::D10, ARM::D9, ARM::D8, |
| 73 | 0 |
| 74 | }; |
| 75 | |
| 76 | static const unsigned DarwinCalleeSavedRegs[] = { |
| 77 | // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved |
| 78 | // register. |
Jim Grosbach | ab3d00e | 2010-11-02 17:35:25 +0000 | [diff] [blame] | 79 | ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, |
| 80 | ARM::R11, ARM::R10, ARM::R8, |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 81 | |
| 82 | ARM::D15, ARM::D14, ARM::D13, ARM::D12, |
| 83 | ARM::D11, ARM::D10, ARM::D9, ARM::D8, |
| 84 | 0 |
| 85 | }; |
| 86 | return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; |
| 87 | } |
| 88 | |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 89 | BitVector ARMBaseRegisterInfo:: |
| 90 | getReservedRegs(const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 91 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 92 | |
Chris Lattner | 7a2bdde | 2011-04-15 05:18:47 +0000 | [diff] [blame] | 93 | // FIXME: avoid re-calculating this every time. |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 94 | BitVector Reserved(getNumRegs()); |
| 95 | Reserved.set(ARM::SP); |
| 96 | Reserved.set(ARM::PC); |
Nate Begeman | d1fb583 | 2010-08-03 21:31:55 +0000 | [diff] [blame] | 97 | Reserved.set(ARM::FPSCR); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 98 | if (TFI->hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 99 | Reserved.set(FramePtr); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 100 | if (hasBasePointer(MF)) |
| 101 | Reserved.set(BasePtr); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 102 | // Some targets reserve R9. |
| 103 | if (STI.isR9Reserved()) |
| 104 | Reserved.set(ARM::R9); |
Jakob Stoklund Olesen | 3b6434e | 2011-06-18 00:53:27 +0000 | [diff] [blame] | 105 | // Reserve D16-D31 if the subtarget doesn't support them. |
| 106 | if (!STI.hasVFP3() || STI.hasD16()) { |
| 107 | assert(ARM::D31 == ARM::D16 + 15); |
| 108 | for (unsigned i = 0; i != 16; ++i) |
| 109 | Reserved.set(ARM::D16 + i); |
| 110 | } |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 111 | return Reserved; |
| 112 | } |
| 113 | |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 114 | bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, |
| 115 | unsigned Reg) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 116 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 117 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 118 | switch (Reg) { |
| 119 | default: break; |
| 120 | case ARM::SP: |
| 121 | case ARM::PC: |
| 122 | return true; |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 123 | case ARM::R6: |
| 124 | if (hasBasePointer(MF)) |
| 125 | return true; |
| 126 | break; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 127 | case ARM::R7: |
| 128 | case ARM::R11: |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 129 | if (FramePtr == Reg && TFI->hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 130 | return true; |
| 131 | break; |
| 132 | case ARM::R9: |
| 133 | return STI.isR9Reserved(); |
| 134 | } |
| 135 | |
| 136 | return false; |
| 137 | } |
| 138 | |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 139 | const TargetRegisterClass * |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 140 | ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, |
| 141 | const TargetRegisterClass *B, |
| 142 | unsigned SubIdx) const { |
| 143 | switch (SubIdx) { |
| 144 | default: return 0; |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 145 | case ARM::ssub_0: |
| 146 | case ARM::ssub_1: |
| 147 | case ARM::ssub_2: |
| 148 | case ARM::ssub_3: { |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 149 | // S sub-registers. |
| 150 | if (A->getSize() == 8) { |
Evan Cheng | ba90864 | 2009-11-03 05:52:54 +0000 | [diff] [blame] | 151 | if (B == &ARM::SPR_8RegClass) |
| 152 | return &ARM::DPR_8RegClass; |
| 153 | assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 154 | if (A == &ARM::DPR_8RegClass) |
| 155 | return A; |
| 156 | return &ARM::DPR_VFP2RegClass; |
| 157 | } |
| 158 | |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 159 | if (A->getSize() == 16) { |
| 160 | if (B == &ARM::SPR_8RegClass) |
| 161 | return &ARM::QPR_8RegClass; |
| 162 | return &ARM::QPR_VFP2RegClass; |
| 163 | } |
| 164 | |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 165 | if (A->getSize() == 32) { |
| 166 | if (B == &ARM::SPR_8RegClass) |
| 167 | return 0; // Do not allow coalescing! |
| 168 | return &ARM::QQPR_VFP2RegClass; |
| 169 | } |
| 170 | |
| 171 | assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); |
| 172 | return 0; // Do not allow coalescing! |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 173 | } |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 174 | case ARM::dsub_0: |
| 175 | case ARM::dsub_1: |
| 176 | case ARM::dsub_2: |
| 177 | case ARM::dsub_3: { |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 178 | // D sub-registers. |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 179 | if (A->getSize() == 16) { |
| 180 | if (B == &ARM::DPR_VFP2RegClass) |
| 181 | return &ARM::QPR_VFP2RegClass; |
| 182 | if (B == &ARM::DPR_8RegClass) |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 183 | return 0; // Do not allow coalescing! |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 184 | return A; |
| 185 | } |
| 186 | |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 187 | if (A->getSize() == 32) { |
| 188 | if (B == &ARM::DPR_VFP2RegClass) |
| 189 | return &ARM::QQPR_VFP2RegClass; |
| 190 | if (B == &ARM::DPR_8RegClass) |
| 191 | return 0; // Do not allow coalescing! |
| 192 | return A; |
| 193 | } |
| 194 | |
| 195 | assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); |
| 196 | if (B != &ARM::DPRRegClass) |
| 197 | return 0; // Do not allow coalescing! |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 198 | return A; |
| 199 | } |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 200 | case ARM::dsub_4: |
| 201 | case ARM::dsub_5: |
| 202 | case ARM::dsub_6: |
| 203 | case ARM::dsub_7: { |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 204 | // D sub-registers of QQQQ registers. |
| 205 | if (A->getSize() == 64 && B == &ARM::DPRRegClass) |
| 206 | return A; |
| 207 | return 0; // Do not allow coalescing! |
| 208 | } |
| 209 | |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 210 | case ARM::qsub_0: |
| 211 | case ARM::qsub_1: { |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 212 | // Q sub-registers. |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 213 | if (A->getSize() == 32) { |
| 214 | if (B == &ARM::QPR_VFP2RegClass) |
| 215 | return &ARM::QQPR_VFP2RegClass; |
| 216 | if (B == &ARM::QPR_8RegClass) |
| 217 | return 0; // Do not allow coalescing! |
| 218 | return A; |
| 219 | } |
| 220 | |
| 221 | assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); |
| 222 | if (B == &ARM::QPRRegClass) |
| 223 | return A; |
| 224 | return 0; // Do not allow coalescing! |
| 225 | } |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 226 | case ARM::qsub_2: |
| 227 | case ARM::qsub_3: { |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 228 | // Q sub-registers of QQQQ registers. |
| 229 | if (A->getSize() == 64 && B == &ARM::QPRRegClass) |
| 230 | return A; |
| 231 | return 0; // Do not allow coalescing! |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 232 | } |
| 233 | } |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 234 | return 0; |
| 235 | } |
| 236 | |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 237 | bool |
Bob Wilson | 91a74da | 2010-06-02 18:54:47 +0000 | [diff] [blame] | 238 | ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 239 | SmallVectorImpl<unsigned> &SubIndices, |
| 240 | unsigned &NewSubIdx) const { |
| 241 | |
| 242 | unsigned Size = RC->getSize() * 8; |
| 243 | if (Size < 6) |
| 244 | return 0; |
| 245 | |
| 246 | NewSubIdx = 0; // Whole register. |
| 247 | unsigned NumRegs = SubIndices.size(); |
| 248 | if (NumRegs == 8) { |
| 249 | // 8 D registers -> 1 QQQQ register. |
| 250 | return (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 251 | SubIndices[0] == ARM::dsub_0 && |
| 252 | SubIndices[1] == ARM::dsub_1 && |
| 253 | SubIndices[2] == ARM::dsub_2 && |
| 254 | SubIndices[3] == ARM::dsub_3 && |
| 255 | SubIndices[4] == ARM::dsub_4 && |
| 256 | SubIndices[5] == ARM::dsub_5 && |
| 257 | SubIndices[6] == ARM::dsub_6 && |
| 258 | SubIndices[7] == ARM::dsub_7); |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 259 | } else if (NumRegs == 4) { |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 260 | if (SubIndices[0] == ARM::qsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 261 | // 4 Q registers -> 1 QQQQ register. |
| 262 | return (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 263 | SubIndices[1] == ARM::qsub_1 && |
| 264 | SubIndices[2] == ARM::qsub_2 && |
| 265 | SubIndices[3] == ARM::qsub_3); |
| 266 | } else if (SubIndices[0] == ARM::dsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 267 | // 4 D registers -> 1 QQ register. |
| 268 | if (Size >= 256 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 269 | SubIndices[1] == ARM::dsub_1 && |
| 270 | SubIndices[2] == ARM::dsub_2 && |
| 271 | SubIndices[3] == ARM::dsub_3) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 272 | if (Size == 512) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 273 | NewSubIdx = ARM::qqsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 274 | return true; |
| 275 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 276 | } else if (SubIndices[0] == ARM::dsub_4) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 277 | // 4 D registers -> 1 QQ register (2nd). |
| 278 | if (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 279 | SubIndices[1] == ARM::dsub_5 && |
| 280 | SubIndices[2] == ARM::dsub_6 && |
| 281 | SubIndices[3] == ARM::dsub_7) { |
| 282 | NewSubIdx = ARM::qqsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 283 | return true; |
| 284 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 285 | } else if (SubIndices[0] == ARM::ssub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 286 | // 4 S registers -> 1 Q register. |
| 287 | if (Size >= 128 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 288 | SubIndices[1] == ARM::ssub_1 && |
| 289 | SubIndices[2] == ARM::ssub_2 && |
| 290 | SubIndices[3] == ARM::ssub_3) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 291 | if (Size >= 256) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 292 | NewSubIdx = ARM::qsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 293 | return true; |
| 294 | } |
| 295 | } |
| 296 | } else if (NumRegs == 2) { |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 297 | if (SubIndices[0] == ARM::qsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 298 | // 2 Q registers -> 1 QQ register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 299 | if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 300 | if (Size == 512) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 301 | NewSubIdx = ARM::qqsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 302 | return true; |
| 303 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 304 | } else if (SubIndices[0] == ARM::qsub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 305 | // 2 Q registers -> 1 QQ register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 306 | if (Size == 512 && SubIndices[1] == ARM::qsub_3) { |
| 307 | NewSubIdx = ARM::qqsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 308 | return true; |
| 309 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 310 | } else if (SubIndices[0] == ARM::dsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 311 | // 2 D registers -> 1 Q register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 312 | if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 313 | if (Size >= 256) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 314 | NewSubIdx = ARM::qsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 315 | return true; |
| 316 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 317 | } else if (SubIndices[0] == ARM::dsub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 318 | // 2 D registers -> 1 Q register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 319 | if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { |
| 320 | NewSubIdx = ARM::qsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 321 | return true; |
| 322 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 323 | } else if (SubIndices[0] == ARM::dsub_4) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 324 | // 2 D registers -> 1 Q register (3rd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 325 | if (Size == 512 && SubIndices[1] == ARM::dsub_5) { |
| 326 | NewSubIdx = ARM::qsub_2; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 327 | return true; |
| 328 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 329 | } else if (SubIndices[0] == ARM::dsub_6) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 330 | // 2 D registers -> 1 Q register (3rd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 331 | if (Size == 512 && SubIndices[1] == ARM::dsub_7) { |
| 332 | NewSubIdx = ARM::qsub_3; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 333 | return true; |
| 334 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 335 | } else if (SubIndices[0] == ARM::ssub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 336 | // 2 S registers -> 1 D register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 337 | if (SubIndices[1] == ARM::ssub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 338 | if (Size >= 128) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 339 | NewSubIdx = ARM::dsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 340 | return true; |
| 341 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 342 | } else if (SubIndices[0] == ARM::ssub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 343 | // 2 S registers -> 1 D register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 344 | if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { |
| 345 | NewSubIdx = ARM::dsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 346 | return true; |
| 347 | } |
| 348 | } |
| 349 | } |
| 350 | return false; |
| 351 | } |
| 352 | |
Jakob Stoklund Olesen | c9e5015 | 2011-04-26 18:52:33 +0000 | [diff] [blame] | 353 | const TargetRegisterClass* |
| 354 | ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) |
| 355 | const { |
| 356 | const TargetRegisterClass *Super = RC; |
| 357 | TargetRegisterClass::sc_iterator I = RC->superclasses_begin(); |
| 358 | do { |
| 359 | switch (Super->getID()) { |
| 360 | case ARM::GPRRegClassID: |
| 361 | case ARM::SPRRegClassID: |
| 362 | case ARM::DPRRegClassID: |
| 363 | case ARM::QPRRegClassID: |
| 364 | case ARM::QQPRRegClassID: |
| 365 | case ARM::QQQQPRRegClassID: |
| 366 | return Super; |
| 367 | } |
| 368 | Super = *I++; |
| 369 | } while (Super); |
| 370 | return RC; |
| 371 | } |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 372 | |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 373 | const TargetRegisterClass * |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 374 | ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { |
Jim Grosbach | e11a8f5 | 2009-09-11 19:49:06 +0000 | [diff] [blame] | 375 | return ARM::GPRRegisterClass; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 376 | } |
| 377 | |
Cameron Zwarich | be2119e | 2011-03-07 21:56:36 +0000 | [diff] [blame] | 378 | unsigned |
| 379 | ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, |
| 380 | MachineFunction &MF) const { |
| 381 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
| 382 | |
| 383 | switch (RC->getID()) { |
| 384 | default: |
| 385 | return 0; |
| 386 | case ARM::tGPRRegClassID: |
| 387 | return TFI->hasFP(MF) ? 4 : 5; |
| 388 | case ARM::GPRRegClassID: { |
| 389 | unsigned FP = TFI->hasFP(MF) ? 1 : 0; |
| 390 | return 10 - FP - (STI.isR9Reserved() ? 1 : 0); |
| 391 | } |
| 392 | case ARM::SPRRegClassID: // Currently not used as 'rep' register class. |
| 393 | case ARM::DPRRegClassID: |
| 394 | return 32 - 10; |
| 395 | } |
| 396 | } |
| 397 | |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 398 | /// getRawAllocationOrder - Returns the register allocation order for a |
| 399 | /// specified register class with a target-dependent hint. |
| 400 | ArrayRef<unsigned> |
| 401 | ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, |
| 402 | unsigned HintType, unsigned HintReg, |
| 403 | const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 404 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 405 | // Alternative register allocation orders when favoring even / odd registers |
| 406 | // of register pairs. |
| 407 | |
| 408 | // No FP, R9 is available. |
| 409 | static const unsigned GPREven1[] = { |
| 410 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, |
| 411 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 412 | ARM::R9, ARM::R11 |
| 413 | }; |
| 414 | static const unsigned GPROdd1[] = { |
| 415 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, |
| 416 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 417 | ARM::R8, ARM::R10 |
| 418 | }; |
| 419 | |
| 420 | // FP is R7, R9 is available. |
| 421 | static const unsigned GPREven2[] = { |
| 422 | ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, |
| 423 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, |
| 424 | ARM::R9, ARM::R11 |
| 425 | }; |
| 426 | static const unsigned GPROdd2[] = { |
| 427 | ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, |
| 428 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 429 | ARM::R8, ARM::R10 |
| 430 | }; |
| 431 | |
| 432 | // FP is R11, R9 is available. |
| 433 | static const unsigned GPREven3[] = { |
| 434 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, |
| 435 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 436 | ARM::R9 |
| 437 | }; |
| 438 | static const unsigned GPROdd3[] = { |
| 439 | ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, |
| 440 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, |
| 441 | ARM::R8 |
| 442 | }; |
| 443 | |
| 444 | // No FP, R9 is not available. |
| 445 | static const unsigned GPREven4[] = { |
| 446 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, |
| 447 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, |
| 448 | ARM::R11 |
| 449 | }; |
| 450 | static const unsigned GPROdd4[] = { |
| 451 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, |
| 452 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 453 | ARM::R10 |
| 454 | }; |
| 455 | |
| 456 | // FP is R7, R9 is not available. |
| 457 | static const unsigned GPREven5[] = { |
| 458 | ARM::R0, ARM::R2, ARM::R4, ARM::R10, |
| 459 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, |
| 460 | ARM::R11 |
| 461 | }; |
| 462 | static const unsigned GPROdd5[] = { |
| 463 | ARM::R1, ARM::R3, ARM::R5, ARM::R11, |
| 464 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 465 | ARM::R10 |
| 466 | }; |
| 467 | |
| 468 | // FP is R11, R9 is not available. |
| 469 | static const unsigned GPREven6[] = { |
| 470 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, |
| 471 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 |
| 472 | }; |
| 473 | static const unsigned GPROdd6[] = { |
| 474 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, |
| 475 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 |
| 476 | }; |
| 477 | |
Jakob Stoklund Olesen | eb5067e | 2011-03-25 01:48:18 +0000 | [diff] [blame] | 478 | // We only support even/odd hints for GPR and rGPR. |
| 479 | if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass) |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 480 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 481 | |
| 482 | if (HintType == ARMRI::RegPairEven) { |
| 483 | if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) |
| 484 | // It's no longer possible to fulfill this hint. Return the default |
| 485 | // allocation order. |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 486 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 487 | |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 488 | if (!TFI->hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 489 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 490 | return makeArrayRef(GPREven1); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 491 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 492 | return makeArrayRef(GPREven4); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 493 | } else if (FramePtr == ARM::R7) { |
| 494 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 495 | return makeArrayRef(GPREven2); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 496 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 497 | return makeArrayRef(GPREven5); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 498 | } else { // FramePtr == ARM::R11 |
| 499 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 500 | return makeArrayRef(GPREven3); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 501 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 502 | return makeArrayRef(GPREven6); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 503 | } |
| 504 | } else if (HintType == ARMRI::RegPairOdd) { |
| 505 | if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) |
| 506 | // It's no longer possible to fulfill this hint. Return the default |
| 507 | // allocation order. |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 508 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 509 | |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 510 | if (!TFI->hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 511 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 512 | return makeArrayRef(GPROdd1); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 513 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 514 | return makeArrayRef(GPROdd4); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 515 | } else if (FramePtr == ARM::R7) { |
| 516 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 517 | return makeArrayRef(GPROdd2); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 518 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 519 | return makeArrayRef(GPROdd5); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 520 | } else { // FramePtr == ARM::R11 |
| 521 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 522 | return makeArrayRef(GPROdd3); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 523 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 524 | return makeArrayRef(GPROdd6); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 525 | } |
| 526 | } |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 527 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 528 | } |
| 529 | |
| 530 | /// ResolveRegAllocHint - Resolves the specified register allocation hint |
| 531 | /// to a physical register. Returns the physical register if it is successful. |
| 532 | unsigned |
| 533 | ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, |
| 534 | const MachineFunction &MF) const { |
| 535 | if (Reg == 0 || !isPhysicalRegister(Reg)) |
| 536 | return 0; |
| 537 | if (Type == 0) |
| 538 | return Reg; |
| 539 | else if (Type == (unsigned)ARMRI::RegPairOdd) |
| 540 | // Odd register. |
| 541 | return getRegisterPairOdd(Reg, MF); |
| 542 | else if (Type == (unsigned)ARMRI::RegPairEven) |
| 543 | // Even register. |
| 544 | return getRegisterPairEven(Reg, MF); |
| 545 | return 0; |
| 546 | } |
| 547 | |
| 548 | void |
| 549 | ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, |
| 550 | MachineFunction &MF) const { |
| 551 | MachineRegisterInfo *MRI = &MF.getRegInfo(); |
| 552 | std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); |
| 553 | if ((Hint.first == (unsigned)ARMRI::RegPairOdd || |
| 554 | Hint.first == (unsigned)ARMRI::RegPairEven) && |
Jakob Stoklund Olesen | c9df025 | 2011-01-10 02:58:51 +0000 | [diff] [blame] | 555 | TargetRegisterInfo::isVirtualRegister(Hint.second)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 556 | // If 'Reg' is one of the even / odd register pair and it's now changed |
| 557 | // (e.g. coalesced) into a different register. The other register of the |
| 558 | // pair allocation hint must be updated to reflect the relationship |
| 559 | // change. |
| 560 | unsigned OtherReg = Hint.second; |
| 561 | Hint = MRI->getRegAllocationHint(OtherReg); |
| 562 | if (Hint.second == Reg) |
| 563 | // Make sure the pair has not already divorced. |
| 564 | MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); |
| 565 | } |
| 566 | } |
| 567 | |
Bob Wilson | f6a4d3c | 2011-04-19 18:11:45 +0000 | [diff] [blame] | 568 | bool |
| 569 | ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { |
| 570 | // CortexA9 has a Write-after-write hazard for NEON registers. |
| 571 | if (!STI.isCortexA9()) |
| 572 | return false; |
| 573 | |
| 574 | switch (RC->getID()) { |
| 575 | case ARM::DPRRegClassID: |
| 576 | case ARM::DPR_8RegClassID: |
| 577 | case ARM::DPR_VFP2RegClassID: |
| 578 | case ARM::QPRRegClassID: |
| 579 | case ARM::QPR_8RegClassID: |
| 580 | case ARM::QPR_VFP2RegClassID: |
| 581 | case ARM::SPRRegClassID: |
| 582 | case ARM::SPR_8RegClassID: |
| 583 | // Avoid reusing S, D, and Q registers. |
| 584 | // Don't increase register pressure for QQ and QQQQ. |
| 585 | return true; |
| 586 | default: |
| 587 | return false; |
| 588 | } |
| 589 | } |
| 590 | |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 591 | bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 592 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 593 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 594 | |
| 595 | if (!EnableBasePointer) |
| 596 | return false; |
| 597 | |
| 598 | if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) |
| 599 | return true; |
| 600 | |
| 601 | // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited |
| 602 | // negative range for ldr/str (255), and thumb1 is positive offsets only. |
| 603 | // It's going to be better to use the SP or Base Pointer instead. When there |
| 604 | // are variable sized objects, we can't reference off of the SP, so we |
| 605 | // reserve a Base Pointer. |
| 606 | if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { |
| 607 | // Conservatively estimate whether the negative offset from the frame |
| 608 | // pointer will be sufficient to reach. If a function has a smallish |
| 609 | // frame, it's less likely to have lots of spills and callee saved |
| 610 | // space, so it's all more likely to be within range of the frame pointer. |
| 611 | // If it's wrong, the scavenger will still enable access to work, it just |
| 612 | // won't be optimal. |
| 613 | if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) |
| 614 | return false; |
| 615 | return true; |
| 616 | } |
| 617 | |
| 618 | return false; |
| 619 | } |
| 620 | |
| 621 | bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { |
Jim Grosbach | 30c93e1 | 2010-09-08 17:22:12 +0000 | [diff] [blame] | 622 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 623 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 30c93e1 | 2010-09-08 17:22:12 +0000 | [diff] [blame] | 624 | // We can't realign the stack if: |
| 625 | // 1. Dynamic stack realignment is explicitly disabled, |
| 626 | // 2. This is a Thumb1 function (it's not useful, so we don't bother), or |
| 627 | // 3. There are VLAs in the function and the base pointer is disabled. |
| 628 | return (RealignStack && !AFI->isThumb1OnlyFunction() && |
| 629 | (!MFI->hasVarSizedObjects() || EnableBasePointer)); |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 630 | } |
| 631 | |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 632 | bool ARMBaseRegisterInfo:: |
| 633 | needsStackRealignment(const MachineFunction &MF) const { |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 634 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Eric Christopher | d4c36ce | 2010-07-17 00:27:24 +0000 | [diff] [blame] | 635 | const Function *F = MF.getFunction(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 636 | unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); |
Jim Grosbach | fc63300 | 2010-09-03 18:28:19 +0000 | [diff] [blame] | 637 | bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || |
Eric Christopher | 697cba8 | 2010-07-17 00:33:04 +0000 | [diff] [blame] | 638 | F->hasFnAttr(Attribute::StackAlignment)); |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 639 | |
Eric Christopher | d4c36ce | 2010-07-17 00:27:24 +0000 | [diff] [blame] | 640 | return requiresRealignment && canRealignStack(MF); |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 641 | } |
| 642 | |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 643 | bool ARMBaseRegisterInfo:: |
| 644 | cannotEliminateFrame(const MachineFunction &MF) const { |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 645 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Bill Wendling | b92187a | 2010-05-14 21:14:32 +0000 | [diff] [blame] | 646 | if (DisableFramePointerElim(MF) && MFI->adjustsStack()) |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 647 | return true; |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 648 | return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() |
| 649 | || needsStackRealignment(MF); |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 650 | } |
| 651 | |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 652 | unsigned |
David Greene | 3f2bf85 | 2009-11-12 20:49:22 +0000 | [diff] [blame] | 653 | ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 654 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 655 | |
| 656 | if (TFI->hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 657 | return FramePtr; |
| 658 | return ARM::SP; |
| 659 | } |
| 660 | |
| 661 | unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 662 | llvm_unreachable("What is the exception register"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 667 | llvm_unreachable("What is the exception handler register"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 668 | return 0; |
| 669 | } |
| 670 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 671 | unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 672 | const MachineFunction &MF) const { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 673 | switch (Reg) { |
| 674 | default: break; |
| 675 | // Return 0 if either register of the pair is a special register. |
| 676 | // So no R12, etc. |
| 677 | case ARM::R1: |
| 678 | return ARM::R0; |
| 679 | case ARM::R3: |
Jim Grosbach | 6009751 | 2009-10-19 22:57:03 +0000 | [diff] [blame] | 680 | return ARM::R2; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 681 | case ARM::R5: |
| 682 | return ARM::R4; |
| 683 | case ARM::R7: |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 684 | return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) |
| 685 | ? 0 : ARM::R6; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 686 | case ARM::R9: |
| 687 | return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; |
| 688 | case ARM::R11: |
| 689 | return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; |
| 690 | |
| 691 | case ARM::S1: |
| 692 | return ARM::S0; |
| 693 | case ARM::S3: |
| 694 | return ARM::S2; |
| 695 | case ARM::S5: |
| 696 | return ARM::S4; |
| 697 | case ARM::S7: |
| 698 | return ARM::S6; |
| 699 | case ARM::S9: |
| 700 | return ARM::S8; |
| 701 | case ARM::S11: |
| 702 | return ARM::S10; |
| 703 | case ARM::S13: |
| 704 | return ARM::S12; |
| 705 | case ARM::S15: |
| 706 | return ARM::S14; |
| 707 | case ARM::S17: |
| 708 | return ARM::S16; |
| 709 | case ARM::S19: |
| 710 | return ARM::S18; |
| 711 | case ARM::S21: |
| 712 | return ARM::S20; |
| 713 | case ARM::S23: |
| 714 | return ARM::S22; |
| 715 | case ARM::S25: |
| 716 | return ARM::S24; |
| 717 | case ARM::S27: |
| 718 | return ARM::S26; |
| 719 | case ARM::S29: |
| 720 | return ARM::S28; |
| 721 | case ARM::S31: |
| 722 | return ARM::S30; |
| 723 | |
| 724 | case ARM::D1: |
| 725 | return ARM::D0; |
| 726 | case ARM::D3: |
| 727 | return ARM::D2; |
| 728 | case ARM::D5: |
| 729 | return ARM::D4; |
| 730 | case ARM::D7: |
| 731 | return ARM::D6; |
| 732 | case ARM::D9: |
| 733 | return ARM::D8; |
| 734 | case ARM::D11: |
| 735 | return ARM::D10; |
| 736 | case ARM::D13: |
| 737 | return ARM::D12; |
| 738 | case ARM::D15: |
| 739 | return ARM::D14; |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 740 | case ARM::D17: |
| 741 | return ARM::D16; |
| 742 | case ARM::D19: |
| 743 | return ARM::D18; |
| 744 | case ARM::D21: |
| 745 | return ARM::D20; |
| 746 | case ARM::D23: |
| 747 | return ARM::D22; |
| 748 | case ARM::D25: |
| 749 | return ARM::D24; |
| 750 | case ARM::D27: |
| 751 | return ARM::D26; |
| 752 | case ARM::D29: |
| 753 | return ARM::D28; |
| 754 | case ARM::D31: |
| 755 | return ARM::D30; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 756 | } |
| 757 | |
| 758 | return 0; |
| 759 | } |
| 760 | |
| 761 | unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, |
| 762 | const MachineFunction &MF) const { |
| 763 | switch (Reg) { |
| 764 | default: break; |
| 765 | // Return 0 if either register of the pair is a special register. |
| 766 | // So no R12, etc. |
| 767 | case ARM::R0: |
| 768 | return ARM::R1; |
| 769 | case ARM::R2: |
Jim Grosbach | 6009751 | 2009-10-19 22:57:03 +0000 | [diff] [blame] | 770 | return ARM::R3; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 771 | case ARM::R4: |
| 772 | return ARM::R5; |
| 773 | case ARM::R6: |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 774 | return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) |
| 775 | ? 0 : ARM::R7; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 776 | case ARM::R8: |
| 777 | return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; |
| 778 | case ARM::R10: |
| 779 | return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; |
| 780 | |
| 781 | case ARM::S0: |
| 782 | return ARM::S1; |
| 783 | case ARM::S2: |
| 784 | return ARM::S3; |
| 785 | case ARM::S4: |
| 786 | return ARM::S5; |
| 787 | case ARM::S6: |
| 788 | return ARM::S7; |
| 789 | case ARM::S8: |
| 790 | return ARM::S9; |
| 791 | case ARM::S10: |
| 792 | return ARM::S11; |
| 793 | case ARM::S12: |
| 794 | return ARM::S13; |
| 795 | case ARM::S14: |
| 796 | return ARM::S15; |
| 797 | case ARM::S16: |
| 798 | return ARM::S17; |
| 799 | case ARM::S18: |
| 800 | return ARM::S19; |
| 801 | case ARM::S20: |
| 802 | return ARM::S21; |
| 803 | case ARM::S22: |
| 804 | return ARM::S23; |
| 805 | case ARM::S24: |
| 806 | return ARM::S25; |
| 807 | case ARM::S26: |
| 808 | return ARM::S27; |
| 809 | case ARM::S28: |
| 810 | return ARM::S29; |
| 811 | case ARM::S30: |
| 812 | return ARM::S31; |
| 813 | |
| 814 | case ARM::D0: |
| 815 | return ARM::D1; |
| 816 | case ARM::D2: |
| 817 | return ARM::D3; |
| 818 | case ARM::D4: |
| 819 | return ARM::D5; |
| 820 | case ARM::D6: |
| 821 | return ARM::D7; |
| 822 | case ARM::D8: |
| 823 | return ARM::D9; |
| 824 | case ARM::D10: |
| 825 | return ARM::D11; |
| 826 | case ARM::D12: |
| 827 | return ARM::D13; |
| 828 | case ARM::D14: |
| 829 | return ARM::D15; |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 830 | case ARM::D16: |
| 831 | return ARM::D17; |
| 832 | case ARM::D18: |
| 833 | return ARM::D19; |
| 834 | case ARM::D20: |
| 835 | return ARM::D21; |
| 836 | case ARM::D22: |
| 837 | return ARM::D23; |
| 838 | case ARM::D24: |
| 839 | return ARM::D25; |
| 840 | case ARM::D26: |
| 841 | return ARM::D27; |
| 842 | case ARM::D28: |
| 843 | return ARM::D29; |
| 844 | case ARM::D30: |
| 845 | return ARM::D31; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | return 0; |
| 849 | } |
| 850 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 851 | /// emitLoadConstPool - Emits a load from constpool to materialize the |
| 852 | /// specified immediate. |
| 853 | void ARMBaseRegisterInfo:: |
| 854 | emitLoadConstPool(MachineBasicBlock &MBB, |
| 855 | MachineBasicBlock::iterator &MBBI, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 856 | DebugLoc dl, |
Evan Cheng | 3784453 | 2009-07-16 09:20:10 +0000 | [diff] [blame] | 857 | unsigned DestReg, unsigned SubIdx, int Val, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 858 | ARMCC::CondCodes Pred, |
Anton Korobeynikov | 3daccd8 | 2011-03-05 18:43:50 +0000 | [diff] [blame] | 859 | unsigned PredReg, unsigned MIFlags) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 860 | MachineFunction &MF = *MBB.getParent(); |
| 861 | MachineConstantPool *ConstantPool = MF.getConstantPool(); |
Dan Gohman | 46510a7 | 2010-04-15 01:51:59 +0000 | [diff] [blame] | 862 | const Constant *C = |
Owen Anderson | 1d0be15 | 2009-08-13 21:58:54 +0000 | [diff] [blame] | 863 | ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 864 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); |
| 865 | |
Evan Cheng | 3784453 | 2009-07-16 09:20:10 +0000 | [diff] [blame] | 866 | BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) |
| 867 | .addReg(DestReg, getDefRegState(true), SubIdx) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 868 | .addConstantPoolIndex(Idx) |
Anton Korobeynikov | 3daccd8 | 2011-03-05 18:43:50 +0000 | [diff] [blame] | 869 | .addImm(0).addImm(Pred).addReg(PredReg) |
| 870 | .setMIFlags(MIFlags); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 871 | } |
| 872 | |
| 873 | bool ARMBaseRegisterInfo:: |
| 874 | requiresRegisterScavenging(const MachineFunction &MF) const { |
| 875 | return true; |
| 876 | } |
Jim Grosbach | 41fff8c | 2009-10-21 23:40:56 +0000 | [diff] [blame] | 877 | |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 878 | bool ARMBaseRegisterInfo:: |
| 879 | requiresFrameIndexScavenging(const MachineFunction &MF) const { |
Jim Grosbach | ca5dfb7 | 2009-10-28 17:33:28 +0000 | [diff] [blame] | 880 | return true; |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 881 | } |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 882 | |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 883 | bool ARMBaseRegisterInfo:: |
| 884 | requiresVirtualBaseRegisters(const MachineFunction &MF) const { |
| 885 | return EnableLocalStackAlloc; |
| 886 | } |
| 887 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 888 | static void |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 889 | emitSPUpdate(bool isARM, |
| 890 | MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 891 | DebugLoc dl, const ARMBaseInstrInfo &TII, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 892 | int NumBytes, |
| 893 | ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 894 | if (isARM) |
| 895 | emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, |
| 896 | Pred, PredReg, TII); |
| 897 | else |
| 898 | emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, |
| 899 | Pred, PredReg, TII); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 900 | } |
| 901 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 902 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 903 | void ARMBaseRegisterInfo:: |
| 904 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 905 | MachineBasicBlock::iterator I) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 906 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 907 | if (!TFI->hasReservedCallFrame(MF)) { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 908 | // If we have alloca, convert as follows: |
| 909 | // ADJCALLSTACKDOWN -> sub, sp, sp, amount |
| 910 | // ADJCALLSTACKUP -> add, sp, sp, amount |
| 911 | MachineInstr *Old = I; |
| 912 | DebugLoc dl = Old->getDebugLoc(); |
| 913 | unsigned Amount = Old->getOperand(0).getImm(); |
| 914 | if (Amount != 0) { |
| 915 | // We need to keep the stack aligned properly. To do this, we round the |
| 916 | // amount of space needed for the outgoing arguments up to the next |
| 917 | // alignment boundary. |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 918 | unsigned Align = TFI->getStackAlignment(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 919 | Amount = (Amount+Align-1)/Align*Align; |
| 920 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 921 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 922 | assert(!AFI->isThumb1OnlyFunction() && |
Jim Grosbach | cf453ee | 2010-02-23 17:16:27 +0000 | [diff] [blame] | 923 | "This eliminateCallFramePseudoInstr does not support Thumb1!"); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 924 | bool isARM = !AFI->isThumbFunction(); |
| 925 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 926 | // Replace the pseudo instruction with a new instruction... |
| 927 | unsigned Opc = Old->getOpcode(); |
Jim Grosbach | 4c7628e | 2010-02-22 22:47:46 +0000 | [diff] [blame] | 928 | int PIdx = Old->findFirstPredOperandIdx(); |
| 929 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 930 | ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 931 | if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { |
| 932 | // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. |
| 933 | unsigned PredReg = Old->getOperand(2).getReg(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 934 | emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 935 | } else { |
| 936 | // Note: PredReg is operand 3 for ADJCALLSTACKUP. |
| 937 | unsigned PredReg = Old->getOperand(3).getReg(); |
| 938 | assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 939 | emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 940 | } |
| 941 | } |
| 942 | } |
| 943 | MBB.erase(I); |
| 944 | } |
| 945 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 946 | int64_t ARMBaseRegisterInfo:: |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 947 | getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 948 | const MCInstrDesc &Desc = MI->getDesc(); |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 949 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 950 | int64_t InstrOffs = 0;; |
| 951 | int Scale = 1; |
| 952 | unsigned ImmIdx = 0; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 953 | switch (AddrMode) { |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 954 | case ARMII::AddrModeT2_i8: |
| 955 | case ARMII::AddrModeT2_i12: |
Jim Grosbach | 3e55612 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 956 | case ARMII::AddrMode_i12: |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 957 | InstrOffs = MI->getOperand(Idx+1).getImm(); |
| 958 | Scale = 1; |
| 959 | break; |
| 960 | case ARMII::AddrMode5: { |
| 961 | // VFP address mode. |
| 962 | const MachineOperand &OffOp = MI->getOperand(Idx+1); |
Jim Grosbach | f78ee63 | 2010-08-25 19:11:34 +0000 | [diff] [blame] | 963 | InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 964 | if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) |
| 965 | InstrOffs = -InstrOffs; |
| 966 | Scale = 4; |
| 967 | break; |
| 968 | } |
| 969 | case ARMII::AddrMode2: { |
| 970 | ImmIdx = Idx+2; |
| 971 | InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); |
| 972 | if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 973 | InstrOffs = -InstrOffs; |
| 974 | break; |
| 975 | } |
| 976 | case ARMII::AddrMode3: { |
| 977 | ImmIdx = Idx+2; |
| 978 | InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); |
| 979 | if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 980 | InstrOffs = -InstrOffs; |
| 981 | break; |
| 982 | } |
| 983 | case ARMII::AddrModeT1_s: { |
| 984 | ImmIdx = Idx+1; |
| 985 | InstrOffs = MI->getOperand(ImmIdx).getImm(); |
| 986 | Scale = 4; |
| 987 | break; |
| 988 | } |
| 989 | default: |
| 990 | llvm_unreachable("Unsupported addressing mode!"); |
| 991 | break; |
| 992 | } |
| 993 | |
| 994 | return InstrOffs * Scale; |
| 995 | } |
| 996 | |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 997 | /// needsFrameBaseReg - Returns true if the instruction's frame index |
| 998 | /// reference would be better served by a base register other than FP |
| 999 | /// or SP. Used by LocalStackFrameAllocation to determine which frame index |
| 1000 | /// references it should create new base registers for. |
| 1001 | bool ARMBaseRegisterInfo:: |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1002 | needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { |
| 1003 | for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { |
| 1004 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); |
| 1005 | } |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1006 | |
| 1007 | // It's the load/store FI references that cause issues, as it can be difficult |
| 1008 | // to materialize the offset if it won't fit in the literal field. Estimate |
| 1009 | // based on the size of the local frame and some conservative assumptions |
| 1010 | // about the rest of the stack frame (note, this is pre-regalloc, so |
| 1011 | // we don't know everything for certain yet) whether this offset is likely |
| 1012 | // to be out of range of the immediate. Return true if so. |
| 1013 | |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1014 | // We only generate virtual base registers for loads and stores, so |
| 1015 | // return false for everything else. |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1016 | unsigned Opc = MI->getOpcode(); |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1017 | switch (Opc) { |
Jim Grosbach | c1d3021 | 2010-10-27 00:19:44 +0000 | [diff] [blame] | 1018 | case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: |
Jim Grosbach | 7e3383c | 2010-10-27 23:12:14 +0000 | [diff] [blame] | 1019 | case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1020 | case ARM::t2LDRi12: case ARM::t2LDRi8: |
| 1021 | case ARM::t2STRi12: case ARM::t2STRi8: |
| 1022 | case ARM::VLDRS: case ARM::VLDRD: |
| 1023 | case ARM::VSTRS: case ARM::VSTRD: |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1024 | case ARM::tSTRspi: case ARM::tLDRspi: |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1025 | if (ForceAllBaseRegAlloc) |
| 1026 | return true; |
| 1027 | break; |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1028 | default: |
| 1029 | return false; |
| 1030 | } |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1031 | |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1032 | // Without a virtual base register, if the function has variable sized |
| 1033 | // objects, all fixed-size local references will be via the frame pointer, |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1034 | // Approximate the offset and see if it's legal for the instruction. |
| 1035 | // Note that the incoming offset is based on the SP value at function entry, |
| 1036 | // so it'll be negative. |
| 1037 | MachineFunction &MF = *MI->getParent()->getParent(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 1038 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1039 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1040 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1041 | |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1042 | // Estimate an offset from the frame pointer. |
| 1043 | // Conservatively assume all callee-saved registers get pushed. R4-R6 |
| 1044 | // will be earlier than the FP, so we ignore those. |
| 1045 | // R7, LR |
| 1046 | int64_t FPOffset = Offset - 8; |
| 1047 | // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 |
| 1048 | if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) |
| 1049 | FPOffset -= 80; |
| 1050 | // Estimate an offset from the stack pointer. |
Jim Grosbach | c1dc78d | 2010-08-31 18:52:31 +0000 | [diff] [blame] | 1051 | // The incoming offset is relating to the SP at the start of the function, |
| 1052 | // but when we access the local it'll be relative to the SP after local |
| 1053 | // allocation, so adjust our SP-relative offset by that allocation size. |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1054 | Offset = -Offset; |
Jim Grosbach | c1dc78d | 2010-08-31 18:52:31 +0000 | [diff] [blame] | 1055 | Offset += MFI->getLocalFrameSize(); |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1056 | // Assume that we'll have at least some spill slots allocated. |
| 1057 | // FIXME: This is a total SWAG number. We should run some statistics |
| 1058 | // and pick a real one. |
| 1059 | Offset += 128; // 128 bytes of spill slots |
| 1060 | |
| 1061 | // If there is a frame pointer, try using it. |
| 1062 | // The FP is only available if there is no dynamic realignment. We |
| 1063 | // don't know for sure yet whether we'll need that, so we guess based |
| 1064 | // on whether there are any local variables that would trigger it. |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 1065 | unsigned StackAlign = TFI->getStackAlignment(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 1066 | if (TFI->hasFP(MF) && |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1067 | !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { |
| 1068 | if (isFrameOffsetLegal(MI, FPOffset)) |
| 1069 | return false; |
| 1070 | } |
| 1071 | // If we can reference via the stack pointer, try that. |
| 1072 | // FIXME: This (and the code that resolves the references) can be improved |
| 1073 | // to only disallow SP relative references in the live range of |
| 1074 | // the VLA(s). In practice, it's unclear how much difference that |
| 1075 | // would make, but it may be worth doing. |
| 1076 | if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) |
| 1077 | return false; |
| 1078 | |
| 1079 | // The offset likely isn't legal, we want to allocate a virtual base register. |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1080 | return true; |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1081 | } |
| 1082 | |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 1083 | /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to |
| 1084 | /// be a pointer to FrameIdx at the beginning of the basic block. |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1085 | void ARMBaseRegisterInfo:: |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 1086 | materializeFrameBaseRegister(MachineBasicBlock *MBB, |
| 1087 | unsigned BaseReg, int FrameIdx, |
| 1088 | int64_t Offset) const { |
| 1089 | ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1090 | unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : |
| 1091 | (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1092 | |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 1093 | MachineBasicBlock::iterator Ins = MBB->begin(); |
| 1094 | DebugLoc DL; // Defaults to "unknown" |
| 1095 | if (Ins != MBB->end()) |
| 1096 | DL = Ins->getDebugLoc(); |
| 1097 | |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 1098 | const MCInstrDesc &MCID = TII.get(ADDriOpc); |
Cameron Zwarich | 2180372 | 2011-05-19 02:18:27 +0000 | [diff] [blame] | 1099 | MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 1100 | MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this)); |
Cameron Zwarich | 2180372 | 2011-05-19 02:18:27 +0000 | [diff] [blame] | 1101 | |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 1102 | MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1103 | .addFrameIndex(FrameIdx).addImm(Offset); |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 1104 | |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1105 | if (!AFI->isThumb1OnlyFunction()) |
| 1106 | AddDefaultCC(AddDefaultPred(MIB)); |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1107 | } |
| 1108 | |
| 1109 | void |
| 1110 | ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, |
| 1111 | unsigned BaseReg, int64_t Offset) const { |
| 1112 | MachineInstr &MI = *I; |
| 1113 | MachineBasicBlock &MBB = *MI.getParent(); |
| 1114 | MachineFunction &MF = *MBB.getParent(); |
| 1115 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 1116 | int Off = Offset; // ARM doesn't need the general 64-bit offsets |
| 1117 | unsigned i = 0; |
| 1118 | |
| 1119 | assert(!AFI->isThumb1OnlyFunction() && |
| 1120 | "This resolveFrameIndex does not support Thumb1!"); |
| 1121 | |
| 1122 | while (!MI.getOperand(i).isFI()) { |
| 1123 | ++i; |
| 1124 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1125 | } |
| 1126 | bool Done = false; |
| 1127 | if (!AFI->isThumbFunction()) |
| 1128 | Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); |
| 1129 | else { |
| 1130 | assert(AFI->isThumb2Function()); |
| 1131 | Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); |
| 1132 | } |
| 1133 | assert (Done && "Unable to resolve frame index!"); |
| 1134 | } |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1135 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1136 | bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, |
| 1137 | int64_t Offset) const { |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 1138 | const MCInstrDesc &Desc = MI->getDesc(); |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1139 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 1140 | unsigned i = 0; |
| 1141 | |
| 1142 | while (!MI->getOperand(i).isFI()) { |
| 1143 | ++i; |
| 1144 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); |
| 1145 | } |
| 1146 | |
| 1147 | // AddrMode4 and AddrMode6 cannot handle any offset. |
| 1148 | if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) |
| 1149 | return Offset == 0; |
| 1150 | |
| 1151 | unsigned NumBits = 0; |
| 1152 | unsigned Scale = 1; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1153 | bool isSigned = true; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1154 | switch (AddrMode) { |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1155 | case ARMII::AddrModeT2_i8: |
| 1156 | case ARMII::AddrModeT2_i12: |
| 1157 | // i8 supports only negative, and i12 supports only positive, so |
| 1158 | // based on Offset sign, consider the appropriate instruction |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1159 | Scale = 1; |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1160 | if (Offset < 0) { |
| 1161 | NumBits = 8; |
| 1162 | Offset = -Offset; |
| 1163 | } else { |
| 1164 | NumBits = 12; |
| 1165 | } |
| 1166 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1167 | case ARMII::AddrMode5: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1168 | // VFP address mode. |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1169 | NumBits = 8; |
| 1170 | Scale = 4; |
| 1171 | break; |
Jim Grosbach | 3e55612 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 1172 | case ARMII::AddrMode_i12: |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1173 | case ARMII::AddrMode2: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1174 | NumBits = 12; |
| 1175 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1176 | case ARMII::AddrMode3: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1177 | NumBits = 8; |
| 1178 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1179 | case ARMII::AddrModeT1_s: |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1180 | NumBits = 5; |
| 1181 | Scale = 4; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1182 | isSigned = false; |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1183 | break; |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1184 | default: |
| 1185 | llvm_unreachable("Unsupported addressing mode!"); |
| 1186 | break; |
| 1187 | } |
| 1188 | |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1189 | Offset += getFrameIndexInstrOffset(MI, i); |
Jim Grosbach | d4511e9 | 2010-08-31 18:49:31 +0000 | [diff] [blame] | 1190 | // Make sure the offset is encodable for instructions that scale the |
| 1191 | // immediate. |
| 1192 | if ((Offset & (Scale-1)) != 0) |
| 1193 | return false; |
| 1194 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1195 | if (isSigned && Offset < 0) |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1196 | Offset = -Offset; |
| 1197 | |
| 1198 | unsigned Mask = (1 << NumBits) - 1; |
| 1199 | if ((unsigned)Offset <= Mask * Scale) |
| 1200 | return true; |
Jim Grosbach | 74d803a | 2010-08-18 17:57:37 +0000 | [diff] [blame] | 1201 | |
| 1202 | return false; |
| 1203 | } |
| 1204 | |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1205 | void |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1206 | ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1207 | int SPAdj, RegScavenger *RS) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1208 | unsigned i = 0; |
| 1209 | MachineInstr &MI = *II; |
| 1210 | MachineBasicBlock &MBB = *MI.getParent(); |
| 1211 | MachineFunction &MF = *MBB.getParent(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 1212 | const ARMFrameLowering *TFI = |
| 1213 | static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1214 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1215 | assert(!AFI->isThumb1OnlyFunction() && |
Bob Wilson | a15de00 | 2009-09-18 21:42:44 +0000 | [diff] [blame] | 1216 | "This eliminateFrameIndex does not support Thumb1!"); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1217 | |
| 1218 | while (!MI.getOperand(i).isFI()) { |
| 1219 | ++i; |
| 1220 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1221 | } |
| 1222 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1223 | int FrameIndex = MI.getOperand(i).getIndex(); |
Jim Grosbach | a37aa54 | 2009-11-22 20:05:32 +0000 | [diff] [blame] | 1224 | unsigned FrameReg; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1225 | |
Anton Korobeynikov | 82f5874 | 2010-11-20 15:59:32 +0000 | [diff] [blame] | 1226 | int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1227 | |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 1228 | // Special handling of dbg_value instructions. |
| 1229 | if (MI.isDebugValue()) { |
| 1230 | MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); |
| 1231 | MI.getOperand(i+1).ChangeToImmediate(Offset); |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1232 | return; |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 1233 | } |
| 1234 | |
Evan Cheng | 48d8afa | 2009-11-01 21:12:51 +0000 | [diff] [blame] | 1235 | // Modify MI as necessary to handle as much of 'Offset' as possible |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1236 | bool Done = false; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1237 | if (!AFI->isThumbFunction()) |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1238 | Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1239 | else { |
| 1240 | assert(AFI->isThumb2Function()); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1241 | Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1242 | } |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1243 | if (Done) |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1244 | return; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1245 | |
| 1246 | // If we get here, the immediate doesn't fit into the instruction. We folded |
| 1247 | // as much as possible above, handle the rest, providing a register that is |
| 1248 | // SP+LargeImm. |
Daniel Dunbar | 19bb87d | 2009-08-28 08:08:22 +0000 | [diff] [blame] | 1249 | assert((Offset || |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1250 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || |
| 1251 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1252 | "This code isn't needed if offset already handled!"); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1253 | |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 1254 | unsigned ScratchReg = 0; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1255 | int PIdx = MI.findFirstPredOperandIdx(); |
| 1256 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 1257 | ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); |
| 1258 | unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1259 | if (Offset == 0) |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1260 | // Must be addrmode4/6. |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1261 | MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1262 | else { |
Jim Grosbach | ca5dfb7 | 2009-10-28 17:33:28 +0000 | [diff] [blame] | 1263 | ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1264 | if (!AFI->isThumbFunction()) |
| 1265 | emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, |
| 1266 | Offset, Pred, PredReg, TII); |
| 1267 | else { |
| 1268 | assert(AFI->isThumb2Function()); |
| 1269 | emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, |
| 1270 | Offset, Pred, PredReg, TII); |
| 1271 | } |
Jim Grosbach | cde3129 | 2010-12-09 01:22:13 +0000 | [diff] [blame] | 1272 | // Update the original instruction to use the scratch register. |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1273 | MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1274 | } |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1275 | } |