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Nate Begeman21e463b2005-10-16 05:39:50 +00001//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
Misha Brukmanb5f662f2005-04-21 23:30:14 +00002//
Misha Brukmanf2ccb772004-08-17 04:55:41 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanb5f662f2005-04-21 23:30:14 +00007//
Misha Brukmanf2ccb772004-08-17 04:55:41 +00008//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner16e71f22005-10-14 23:59:06 +000014#include "PPCInstrInfo.h"
Owen Andersonf6372aa2008-01-01 21:11:32 +000015#include "PPCInstrBuilder.h"
Bill Wendling7194aaf2008-03-03 22:19:16 +000016#include "PPCMachineFunctionInfo.h"
Chris Lattnerdf4ed632006-11-17 22:10:59 +000017#include "PPCPredicates.h"
Chris Lattner4c7b43b2005-10-14 23:37:35 +000018#include "PPCGenInstrInfo.inc"
Chris Lattnerb1d26f62006-06-17 00:01:04 +000019#include "PPCTargetMachine.h"
Owen Anderson718cb662007-09-07 04:06:50 +000020#include "llvm/ADT/STLExtras.h"
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +000021#include "llvm/CodeGen/MachineFrameInfo.h"
Misha Brukmanf2ccb772004-08-17 04:55:41 +000022#include "llvm/CodeGen/MachineInstrBuilder.h"
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +000023#include "llvm/CodeGen/MachineMemOperand.h"
Jakob Stoklund Olesen24329662010-02-26 21:09:24 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +000025#include "llvm/CodeGen/PseudoSourceValue.h"
Bill Wendling880d0f62008-03-04 23:13:51 +000026#include "llvm/Support/CommandLine.h"
Torok Edwindac237e2009-07-08 20:53:28 +000027#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
Chris Lattneraf76e592009-08-22 20:48:53 +000029#include "llvm/MC/MCAsmInfo.h"
Misha Brukmanf2ccb772004-08-17 04:55:41 +000030
Dan Gohman82bcd232010-04-15 17:20:57 +000031namespace llvm {
Bill Wendling4a66e9a2008-03-10 22:49:16 +000032extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
33extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
Dan Gohman82bcd232010-04-15 17:20:57 +000034}
35
36using namespace llvm;
Bill Wendling880d0f62008-03-04 23:13:51 +000037
Chris Lattnerb1d26f62006-06-17 00:01:04 +000038PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
Chris Lattner64105522008-01-01 01:03:04 +000039 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
Evan Cheng7ce45782006-11-13 23:36:35 +000040 RI(*TM.getSubtargetImpl(), *this) {}
Chris Lattnerb1d26f62006-06-17 00:01:04 +000041
Andrew Trick6e8f4c42010-12-24 04:28:06 +000042unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
Chris Lattner9c09c9e2006-03-16 22:24:02 +000043 int &FrameIndex) const {
Chris Lattner40839602006-02-02 20:12:32 +000044 switch (MI->getOpcode()) {
45 default: break;
46 case PPC::LD:
47 case PPC::LWZ:
48 case PPC::LFS:
49 case PPC::LFD:
Dan Gohmand735b802008-10-03 15:45:36 +000050 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
51 MI->getOperand(2).isFI()) {
Chris Lattner8aa797a2007-12-30 23:10:15 +000052 FrameIndex = MI->getOperand(2).getIndex();
Chris Lattner40839602006-02-02 20:12:32 +000053 return MI->getOperand(0).getReg();
54 }
55 break;
56 }
57 return 0;
Chris Lattner65242872006-02-02 20:16:12 +000058}
Chris Lattner40839602006-02-02 20:12:32 +000059
Andrew Trick6e8f4c42010-12-24 04:28:06 +000060unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattner65242872006-02-02 20:16:12 +000061 int &FrameIndex) const {
62 switch (MI->getOpcode()) {
63 default: break;
Nate Begeman3b478b32006-02-02 21:07:50 +000064 case PPC::STD:
Chris Lattner65242872006-02-02 20:16:12 +000065 case PPC::STW:
66 case PPC::STFS:
67 case PPC::STFD:
Dan Gohmand735b802008-10-03 15:45:36 +000068 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
69 MI->getOperand(2).isFI()) {
Chris Lattner8aa797a2007-12-30 23:10:15 +000070 FrameIndex = MI->getOperand(2).getIndex();
Chris Lattner65242872006-02-02 20:16:12 +000071 return MI->getOperand(0).getReg();
72 }
73 break;
74 }
75 return 0;
76}
Chris Lattner40839602006-02-02 20:12:32 +000077
Chris Lattner043870d2005-09-09 18:17:41 +000078// commuteInstruction - We can commute rlwimi instructions, but only if the
79// rotate amt is zero. We also have to munge the immediates a bit.
Evan Cheng58dcb0e2008-06-16 07:33:11 +000080MachineInstr *
81PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +000082 MachineFunction &MF = *MI->getParent()->getParent();
83
Chris Lattner043870d2005-09-09 18:17:41 +000084 // Normal instructions can be commuted the obvious way.
85 if (MI->getOpcode() != PPC::RLWIMI)
Evan Cheng58dcb0e2008-06-16 07:33:11 +000086 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Andrew Trick6e8f4c42010-12-24 04:28:06 +000087
Chris Lattner043870d2005-09-09 18:17:41 +000088 // Cannot commute if it has a non-zero rotate count.
Chris Lattner9a1ceae2007-12-30 20:49:49 +000089 if (MI->getOperand(3).getImm() != 0)
Chris Lattner043870d2005-09-09 18:17:41 +000090 return 0;
Andrew Trick6e8f4c42010-12-24 04:28:06 +000091
Chris Lattner043870d2005-09-09 18:17:41 +000092 // If we have a zero rotate count, we have:
93 // M = mask(MB,ME)
94 // Op0 = (Op1 & ~M) | (Op2 & M)
95 // Change this to:
96 // M = mask((ME+1)&31, (MB-1)&31)
97 // Op0 = (Op2 & ~M) | (Op1 & M)
98
99 // Swap op1/op2
Evan Chenga4d16a12008-02-13 02:46:49 +0000100 unsigned Reg0 = MI->getOperand(0).getReg();
Chris Lattner043870d2005-09-09 18:17:41 +0000101 unsigned Reg1 = MI->getOperand(1).getReg();
102 unsigned Reg2 = MI->getOperand(2).getReg();
Evan Cheng6ce7dc22006-11-15 20:58:11 +0000103 bool Reg1IsKill = MI->getOperand(1).isKill();
104 bool Reg2IsKill = MI->getOperand(2).isKill();
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000105 bool ChangeReg0 = false;
Evan Chenga4d16a12008-02-13 02:46:49 +0000106 // If machine instrs are no longer in two-address forms, update
107 // destination register as well.
108 if (Reg0 == Reg1) {
109 // Must be two address instruction!
110 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
111 "Expecting a two-address instruction!");
Evan Chenga4d16a12008-02-13 02:46:49 +0000112 Reg2IsKill = false;
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000113 ChangeReg0 = true;
Evan Chenga4d16a12008-02-13 02:46:49 +0000114 }
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000115
116 // Masks.
117 unsigned MB = MI->getOperand(4).getImm();
118 unsigned ME = MI->getOperand(5).getImm();
119
120 if (NewMI) {
121 // Create a new instruction.
122 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
123 bool Reg0IsDead = MI->getOperand(0).isDead();
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000124 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
Bill Wendling587daed2009-05-13 21:33:08 +0000125 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
126 .addReg(Reg2, getKillRegState(Reg2IsKill))
127 .addReg(Reg1, getKillRegState(Reg1IsKill))
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000128 .addImm((ME+1) & 31)
129 .addImm((MB-1) & 31);
130 }
131
132 if (ChangeReg0)
133 MI->getOperand(0).setReg(Reg2);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000134 MI->getOperand(2).setReg(Reg1);
135 MI->getOperand(1).setReg(Reg2);
Chris Lattnerf7382302007-12-30 21:56:09 +0000136 MI->getOperand(2).setIsKill(Reg1IsKill);
137 MI->getOperand(1).setIsKill(Reg2IsKill);
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000138
Chris Lattner043870d2005-09-09 18:17:41 +0000139 // Swap the mask around.
Chris Lattner9a1ceae2007-12-30 20:49:49 +0000140 MI->getOperand(4).setImm((ME+1) & 31);
141 MI->getOperand(5).setImm((MB-1) & 31);
Chris Lattner043870d2005-09-09 18:17:41 +0000142 return MI;
143}
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000144
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000145void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000146 MachineBasicBlock::iterator MI) const {
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000147 DebugLoc DL;
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000148 BuildMI(MBB, MI, DL, get(PPC::NOP));
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000149}
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000150
151
152// Branch analysis.
153bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
154 MachineBasicBlock *&FBB,
Evan Chengdc54d312009-02-09 07:14:22 +0000155 SmallVectorImpl<MachineOperand> &Cond,
156 bool AllowModify) const {
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000157 // If the block has no terminators, it just falls into the block after it.
158 MachineBasicBlock::iterator I = MBB.end();
Dale Johannesen93d6a7e2010-04-02 01:38:09 +0000159 if (I == MBB.begin())
160 return false;
161 --I;
162 while (I->isDebugValue()) {
163 if (I == MBB.begin())
164 return false;
165 --I;
166 }
167 if (!isUnpredicatedTerminator(I))
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000168 return false;
169
170 // Get the last instruction in the block.
171 MachineInstr *LastInst = I;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000172
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000173 // If there is only one terminator instruction, process it.
Evan Chengbfd2ec42007-06-08 21:59:56 +0000174 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000175 if (LastInst->getOpcode() == PPC::B) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000176 if (!LastInst->getOperand(0).isMBB())
177 return true;
Chris Lattner8aa797a2007-12-30 23:10:15 +0000178 TBB = LastInst->getOperand(0).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000179 return false;
Chris Lattner289c2d52006-11-17 22:14:47 +0000180 } else if (LastInst->getOpcode() == PPC::BCC) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000181 if (!LastInst->getOperand(2).isMBB())
182 return true;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000183 // Block ends with fall-through condbranch.
Chris Lattner8aa797a2007-12-30 23:10:15 +0000184 TBB = LastInst->getOperand(2).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000185 Cond.push_back(LastInst->getOperand(0));
186 Cond.push_back(LastInst->getOperand(1));
Chris Lattner7c4fe252006-10-21 06:03:11 +0000187 return false;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000188 }
189 // Otherwise, don't know what this is.
190 return true;
191 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000192
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000193 // Get the instruction before it if it's a terminator.
194 MachineInstr *SecondLastInst = I;
195
196 // If there are three terminators, we don't know what sort of block this is.
197 if (SecondLastInst && I != MBB.begin() &&
Evan Chengbfd2ec42007-06-08 21:59:56 +0000198 isUnpredicatedTerminator(--I))
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000199 return true;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000200
Chris Lattner289c2d52006-11-17 22:14:47 +0000201 // If the block ends with PPC::B and PPC:BCC, handle it.
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000202 if (SecondLastInst->getOpcode() == PPC::BCC &&
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000203 LastInst->getOpcode() == PPC::B) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000204 if (!SecondLastInst->getOperand(2).isMBB() ||
205 !LastInst->getOperand(0).isMBB())
206 return true;
Chris Lattner8aa797a2007-12-30 23:10:15 +0000207 TBB = SecondLastInst->getOperand(2).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000208 Cond.push_back(SecondLastInst->getOperand(0));
209 Cond.push_back(SecondLastInst->getOperand(1));
Chris Lattner8aa797a2007-12-30 23:10:15 +0000210 FBB = LastInst->getOperand(0).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000211 return false;
212 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000213
Dale Johannesen13e8b512007-06-13 17:59:52 +0000214 // If the block ends with two PPC:Bs, handle it. The second one is not
215 // executed, so remove it.
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000216 if (SecondLastInst->getOpcode() == PPC::B &&
Dale Johannesen13e8b512007-06-13 17:59:52 +0000217 LastInst->getOpcode() == PPC::B) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000218 if (!SecondLastInst->getOperand(0).isMBB())
219 return true;
Chris Lattner8aa797a2007-12-30 23:10:15 +0000220 TBB = SecondLastInst->getOperand(0).getMBB();
Dale Johannesen13e8b512007-06-13 17:59:52 +0000221 I = LastInst;
Evan Chengdc54d312009-02-09 07:14:22 +0000222 if (AllowModify)
223 I->eraseFromParent();
Dale Johannesen13e8b512007-06-13 17:59:52 +0000224 return false;
225 }
226
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000227 // Otherwise, can't handle this.
228 return true;
229}
230
Evan Chengb5cdaa22007-05-18 00:05:48 +0000231unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000232 MachineBasicBlock::iterator I = MBB.end();
Evan Chengb5cdaa22007-05-18 00:05:48 +0000233 if (I == MBB.begin()) return 0;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000234 --I;
Dale Johannesen93d6a7e2010-04-02 01:38:09 +0000235 while (I->isDebugValue()) {
236 if (I == MBB.begin())
237 return 0;
238 --I;
239 }
Chris Lattner289c2d52006-11-17 22:14:47 +0000240 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
Evan Chengb5cdaa22007-05-18 00:05:48 +0000241 return 0;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000242
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000243 // Remove the branch.
244 I->eraseFromParent();
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000245
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000246 I = MBB.end();
247
Evan Chengb5cdaa22007-05-18 00:05:48 +0000248 if (I == MBB.begin()) return 1;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000249 --I;
Chris Lattner289c2d52006-11-17 22:14:47 +0000250 if (I->getOpcode() != PPC::BCC)
Evan Chengb5cdaa22007-05-18 00:05:48 +0000251 return 1;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000252
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000253 // Remove the branch.
254 I->eraseFromParent();
Evan Chengb5cdaa22007-05-18 00:05:48 +0000255 return 2;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000256}
257
Evan Chengb5cdaa22007-05-18 00:05:48 +0000258unsigned
259PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
260 MachineBasicBlock *FBB,
Stuart Hastings3bf91252010-06-17 22:43:56 +0000261 const SmallVectorImpl<MachineOperand> &Cond,
262 DebugLoc DL) const {
Chris Lattner2dc77232006-10-17 18:06:55 +0000263 // Shouldn't be a fall through.
264 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000265 assert((Cond.size() == 2 || Cond.size() == 0) &&
Chris Lattner54108062006-10-21 05:36:13 +0000266 "PPC branch conditions have two components!");
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000267
Chris Lattner54108062006-10-21 05:36:13 +0000268 // One-way branch.
Chris Lattner2dc77232006-10-17 18:06:55 +0000269 if (FBB == 0) {
Chris Lattner54108062006-10-21 05:36:13 +0000270 if (Cond.empty()) // Unconditional branch
Stuart Hastings3bf91252010-06-17 22:43:56 +0000271 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
Chris Lattner54108062006-10-21 05:36:13 +0000272 else // Conditional branch
Stuart Hastings3bf91252010-06-17 22:43:56 +0000273 BuildMI(&MBB, DL, get(PPC::BCC))
Chris Lattner18258c62006-11-17 22:37:34 +0000274 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
Evan Chengb5cdaa22007-05-18 00:05:48 +0000275 return 1;
Chris Lattner2dc77232006-10-17 18:06:55 +0000276 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000277
Chris Lattner879d09c2006-10-21 05:42:09 +0000278 // Two-way Conditional Branch.
Stuart Hastings3bf91252010-06-17 22:43:56 +0000279 BuildMI(&MBB, DL, get(PPC::BCC))
Chris Lattner18258c62006-11-17 22:37:34 +0000280 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
Stuart Hastings3bf91252010-06-17 22:43:56 +0000281 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
Evan Chengb5cdaa22007-05-18 00:05:48 +0000282 return 2;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000283}
284
Jakob Stoklund Olesen27689b02010-07-11 07:31:00 +0000285void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator I, DebugLoc DL,
287 unsigned DestReg, unsigned SrcReg,
288 bool KillSrc) const {
289 unsigned Opc;
290 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
291 Opc = PPC::OR;
292 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
293 Opc = PPC::OR8;
294 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
295 Opc = PPC::FMR;
296 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
297 Opc = PPC::MCRF;
298 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
299 Opc = PPC::VOR;
300 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
301 Opc = PPC::CROR;
302 else
303 llvm_unreachable("Impossible reg-to-reg copy");
Owen Andersond10fd972007-12-31 06:32:00 +0000304
Jakob Stoklund Olesen27689b02010-07-11 07:31:00 +0000305 const TargetInstrDesc &TID = get(Opc);
306 if (TID.getNumOperands() == 3)
307 BuildMI(MBB, I, DL, TID, DestReg)
308 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
309 else
310 BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
Owen Andersond10fd972007-12-31 06:32:00 +0000311}
312
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000313bool
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000314PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
315 unsigned SrcReg, bool isKill,
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000316 int FrameIdx,
317 const TargetRegisterClass *RC,
318 SmallVectorImpl<MachineInstr*> &NewMIs) const{
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000319 DebugLoc DL;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000320 if (RC == PPC::GPRCRegisterClass) {
321 if (SrcReg != PPC::LR) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000322 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
Bill Wendling587daed2009-05-13 21:33:08 +0000323 .addReg(SrcReg,
324 getKillRegState(isKill)),
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000325 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000326 } else {
327 // FIXME: this spills LR immediately to memory in one step. To do this,
328 // we use R11, which we know cannot be used in the prolog/epilog. This is
329 // a hack.
Dale Johannesen21b55412009-02-12 23:08:38 +0000330 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
331 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
Bill Wendling587daed2009-05-13 21:33:08 +0000332 .addReg(PPC::R11,
333 getKillRegState(isKill)),
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000334 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000335 }
336 } else if (RC == PPC::G8RCRegisterClass) {
337 if (SrcReg != PPC::LR8) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000338 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
Bill Wendling587daed2009-05-13 21:33:08 +0000339 .addReg(SrcReg,
340 getKillRegState(isKill)),
341 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000342 } else {
343 // FIXME: this spills LR immediately to memory in one step. To do this,
344 // we use R11, which we know cannot be used in the prolog/epilog. This is
345 // a hack.
Dale Johannesen21b55412009-02-12 23:08:38 +0000346 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
347 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
Bill Wendling587daed2009-05-13 21:33:08 +0000348 .addReg(PPC::X11,
349 getKillRegState(isKill)),
350 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000351 }
352 } else if (RC == PPC::F8RCRegisterClass) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000353 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
Bill Wendling587daed2009-05-13 21:33:08 +0000354 .addReg(SrcReg,
355 getKillRegState(isKill)),
356 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000357 } else if (RC == PPC::F4RCRegisterClass) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000358 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
Bill Wendling587daed2009-05-13 21:33:08 +0000359 .addReg(SrcReg,
360 getKillRegState(isKill)),
361 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000362 } else if (RC == PPC::CRRCRegisterClass) {
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000363 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
364 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
365 // FIXME (64-bit): Enable
Dale Johannesen21b55412009-02-12 23:08:38 +0000366 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
Bill Wendling587daed2009-05-13 21:33:08 +0000367 .addReg(SrcReg,
368 getKillRegState(isKill)),
Chris Lattner71a2cb22008-03-20 01:22:40 +0000369 FrameIdx));
Bill Wendling7194aaf2008-03-03 22:19:16 +0000370 return true;
371 } else {
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000372 // FIXME: We need a scatch reg here. The trouble with using R0 is that
373 // it's possible for the stack frame to be so big the save location is
374 // out of range of immediate offsets, necessitating another register.
375 // We hack this on Darwin by reserving R2. It's probably broken on Linux
376 // at the moment.
377
378 // We need to store the CR in the low 4-bits of the saved value. First,
379 // issue a MFCR to save all of the CRBits.
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000380 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000381 PPC::R2 : PPC::R0;
Dale Johannesen5f07d522010-05-20 17:48:26 +0000382 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
383 .addReg(SrcReg, getKillRegState(isKill)));
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000384
Bill Wendling7194aaf2008-03-03 22:19:16 +0000385 // If the saved register wasn't CR0, shift the bits left so that they are
386 // in CR0's slot.
387 if (SrcReg != PPC::CR0) {
388 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000389 // rlwinm scratch, scratch, ShiftBits, 0, 31.
390 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
391 .addReg(ScratchReg).addImm(ShiftBits)
392 .addImm(0).addImm(31));
Bill Wendling7194aaf2008-03-03 22:19:16 +0000393 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000394
Dale Johannesen21b55412009-02-12 23:08:38 +0000395 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000396 .addReg(ScratchReg,
Bill Wendling587daed2009-05-13 21:33:08 +0000397 getKillRegState(isKill)),
Bill Wendling7194aaf2008-03-03 22:19:16 +0000398 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000399 }
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000400 } else if (RC == PPC::CRBITRCRegisterClass) {
401 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
402 // backend currently only uses CR1EQ as an individual bit, this should
403 // not cause any bug. If we need other uses of CR bits, the following
404 // code may be invalid.
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000405 unsigned Reg = 0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000406 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
407 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000408 Reg = PPC::CR0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000409 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
410 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000411 Reg = PPC::CR1;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000412 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
413 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000414 Reg = PPC::CR2;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000415 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
416 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000417 Reg = PPC::CR3;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000418 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
419 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000420 Reg = PPC::CR4;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000421 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
422 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000423 Reg = PPC::CR5;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000424 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
425 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000426 Reg = PPC::CR6;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000427 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
428 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000429 Reg = PPC::CR7;
430
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000431 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000432 PPC::CRRCRegisterClass, NewMIs);
433
Owen Andersonf6372aa2008-01-01 21:11:32 +0000434 } else if (RC == PPC::VRRCRegisterClass) {
435 // We don't have indexed addressing for vector loads. Emit:
436 // R0 = ADDI FI#
437 // STVX VAL, 0, R0
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000438 //
Owen Andersonf6372aa2008-01-01 21:11:32 +0000439 // FIXME: We use R0 here, because it isn't available for RA.
Dale Johannesen21b55412009-02-12 23:08:38 +0000440 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000441 FrameIdx, 0, 0));
Dale Johannesen21b55412009-02-12 23:08:38 +0000442 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
Bill Wendling587daed2009-05-13 21:33:08 +0000443 .addReg(SrcReg, getKillRegState(isKill))
444 .addReg(PPC::R0)
445 .addReg(PPC::R0));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000446 } else {
Torok Edwinc23197a2009-07-14 16:55:14 +0000447 llvm_unreachable("Unknown regclass!");
Owen Andersonf6372aa2008-01-01 21:11:32 +0000448 }
Bill Wendling7194aaf2008-03-03 22:19:16 +0000449
450 return false;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000451}
452
453void
454PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Bill Wendling7194aaf2008-03-03 22:19:16 +0000455 MachineBasicBlock::iterator MI,
456 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Cheng746ad692010-05-06 19:06:44 +0000457 const TargetRegisterClass *RC,
458 const TargetRegisterInfo *TRI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000459 MachineFunction &MF = *MBB.getParent();
Owen Andersonf6372aa2008-01-01 21:11:32 +0000460 SmallVector<MachineInstr*, 4> NewMIs;
Bill Wendling7194aaf2008-03-03 22:19:16 +0000461
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000462 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
463 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
Bill Wendling7194aaf2008-03-03 22:19:16 +0000464 FuncInfo->setSpillsCR();
465 }
466
Owen Andersonf6372aa2008-01-01 21:11:32 +0000467 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
468 MBB.insert(MI, NewMIs[i]);
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000469
470 const MachineFrameInfo &MFI = *MF.getFrameInfo();
471 MachineMemOperand *MMO =
Chris Lattner59db5492010-09-21 04:39:43 +0000472 MF.getMachineMemOperand(
473 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
474 MachineMemOperand::MOStore,
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000475 MFI.getObjectSize(FrameIdx),
476 MFI.getObjectAlignment(FrameIdx));
477 NewMIs.back()->addMemOperand(MF, MMO);
Owen Andersonf6372aa2008-01-01 21:11:32 +0000478}
479
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000480void
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000481PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000482 unsigned DestReg, int FrameIdx,
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000483 const TargetRegisterClass *RC,
484 SmallVectorImpl<MachineInstr*> &NewMIs)const{
Owen Andersonf6372aa2008-01-01 21:11:32 +0000485 if (RC == PPC::GPRCRegisterClass) {
486 if (DestReg != PPC::LR) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000487 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
488 DestReg), FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000489 } else {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000490 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
491 PPC::R11), FrameIdx));
492 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000493 }
494 } else if (RC == PPC::G8RCRegisterClass) {
495 if (DestReg != PPC::LR8) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000496 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000497 FrameIdx));
498 } else {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000499 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
500 PPC::R11), FrameIdx));
501 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000502 }
503 } else if (RC == PPC::F8RCRegisterClass) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000504 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000505 FrameIdx));
506 } else if (RC == PPC::F4RCRegisterClass) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000507 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000508 FrameIdx));
509 } else if (RC == PPC::CRRCRegisterClass) {
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000510 // FIXME: We need a scatch reg here. The trouble with using R0 is that
511 // it's possible for the stack frame to be so big the save location is
512 // out of range of immediate offsets, necessitating another register.
513 // We hack this on Darwin by reserving R2. It's probably broken on Linux
514 // at the moment.
515 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
516 PPC::R2 : PPC::R0;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000517 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000518 ScratchReg), FrameIdx));
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000519
Owen Andersonf6372aa2008-01-01 21:11:32 +0000520 // If the reloaded register isn't CR0, shift the bits right so that they are
521 // in the right CR's slot.
522 if (DestReg != PPC::CR0) {
523 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
524 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000525 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
526 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
527 .addImm(31));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000528 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000529
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000530 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
531 .addReg(ScratchReg));
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000532 } else if (RC == PPC::CRBITRCRegisterClass) {
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000533
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000534 unsigned Reg = 0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000535 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
536 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000537 Reg = PPC::CR0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000538 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
539 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000540 Reg = PPC::CR1;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000541 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
542 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000543 Reg = PPC::CR2;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000544 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
545 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000546 Reg = PPC::CR3;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000547 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
548 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000549 Reg = PPC::CR4;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000550 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
551 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000552 Reg = PPC::CR5;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000553 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
554 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000555 Reg = PPC::CR6;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000556 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
557 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000558 Reg = PPC::CR7;
559
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000560 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000561 PPC::CRRCRegisterClass, NewMIs);
562
Owen Andersonf6372aa2008-01-01 21:11:32 +0000563 } else if (RC == PPC::VRRCRegisterClass) {
564 // We don't have indexed addressing for vector loads. Emit:
565 // R0 = ADDI FI#
566 // Dest = LVX 0, R0
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000567 //
Owen Andersonf6372aa2008-01-01 21:11:32 +0000568 // FIXME: We use R0 here, because it isn't available for RA.
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000569 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000570 FrameIdx, 0, 0));
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000571 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
Owen Andersonf6372aa2008-01-01 21:11:32 +0000572 .addReg(PPC::R0));
573 } else {
Torok Edwinc23197a2009-07-14 16:55:14 +0000574 llvm_unreachable("Unknown regclass!");
Owen Andersonf6372aa2008-01-01 21:11:32 +0000575 }
576}
577
578void
579PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Bill Wendling7194aaf2008-03-03 22:19:16 +0000580 MachineBasicBlock::iterator MI,
581 unsigned DestReg, int FrameIdx,
Evan Cheng746ad692010-05-06 19:06:44 +0000582 const TargetRegisterClass *RC,
583 const TargetRegisterInfo *TRI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000584 MachineFunction &MF = *MBB.getParent();
Owen Andersonf6372aa2008-01-01 21:11:32 +0000585 SmallVector<MachineInstr*, 4> NewMIs;
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000586 DebugLoc DL;
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000587 if (MI != MBB.end()) DL = MI->getDebugLoc();
588 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
Owen Andersonf6372aa2008-01-01 21:11:32 +0000589 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
590 MBB.insert(MI, NewMIs[i]);
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000591
592 const MachineFrameInfo &MFI = *MF.getFrameInfo();
593 MachineMemOperand *MMO =
Chris Lattner59db5492010-09-21 04:39:43 +0000594 MF.getMachineMemOperand(
595 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
596 MachineMemOperand::MOLoad,
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000597 MFI.getObjectSize(FrameIdx),
598 MFI.getObjectAlignment(FrameIdx));
599 NewMIs.back()->addMemOperand(MF, MMO);
Owen Andersonf6372aa2008-01-01 21:11:32 +0000600}
601
Evan Cheng09652172010-04-26 07:39:36 +0000602MachineInstr*
603PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
Evan Cheng8601a3d2010-04-29 01:13:30 +0000604 int FrameIx, uint64_t Offset,
Evan Cheng09652172010-04-26 07:39:36 +0000605 const MDNode *MDPtr,
606 DebugLoc DL) const {
607 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
608 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
609 return &*MIB;
610}
611
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000612bool PPCInstrInfo::
Owen Anderson44eb65c2008-08-14 22:49:33 +0000613ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner7c4fe252006-10-21 06:03:11 +0000614 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
615 // Leave the CR# the same, but invert the condition.
Chris Lattner18258c62006-11-17 22:37:34 +0000616 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
Chris Lattner7c4fe252006-10-21 06:03:11 +0000617 return false;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000618}
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000619
620/// GetInstSize - Return the number of bytes of code the specified
621/// instruction may be. This returns the maximum number of bytes.
622///
623unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
624 switch (MI->getOpcode()) {
625 case PPC::INLINEASM: { // Inline Asm: Variable size.
626 const MachineFunction *MF = MI->getParent()->getParent();
627 const char *AsmStr = MI->getOperand(0).getSymbolName();
Chris Lattneraf76e592009-08-22 20:48:53 +0000628 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000629 }
Bill Wendling7431bea2010-07-16 22:20:36 +0000630 case PPC::PROLOG_LABEL:
Dan Gohman44066042008-07-01 00:05:16 +0000631 case PPC::EH_LABEL:
632 case PPC::GC_LABEL:
Dale Johannesen375be772010-04-07 19:51:44 +0000633 case PPC::DBG_VALUE:
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000634 return 0;
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000635 default:
636 return 4; // PowerPC instructions are all 4 bytes
637 }
638}