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3<html>
4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]61 <li><a href="#regalloc">Register Allocation</a>
62 <ul>
63 <li><a href="#regAlloc_represent">How registers are represented in
64 LLVM</a></li>
65 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
66 registers</a></li>
67 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
68 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
69 <li><a href="#regAlloc_fold">Instruction folding</a></li>
70 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
71 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]72 <li><a href="#codeemit">Code Emission</a>
73 <ul>
74 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
75 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
76 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]77 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]78 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]79 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]80 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]81 <li><a href="#x86">The X86 backend</a></li>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]82 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]83 </li>
84
85</ol>
86
87<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]88 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
89 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>, and
90 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
91 Pereira</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]92</div>
93
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]94<div class="doc_warning">
95 <p>Warning: This is a work in progress.</p>
96</div>
97
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]98<!-- *********************************************************************** -->
99<div class="doc_section">
100 <a name="introduction">Introduction</a>
101</div>
102<!-- *********************************************************************** -->
103
104<div class="doc_text">
105
106<p>The LLVM target-independent code generator is a framework that provides a
107suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]108the machine code for a specified target&mdash;either in assembly form (suitable
109for a static compiler) or in binary machine code format (usable for a JIT
110compiler). The LLVM target-independent code generator consists of five main
111components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]112
113<ol>
114<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]115capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]116of how they will be used. These interfaces are defined in
117<tt>include/llvm/Target/</tt>.</li>
118
119<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]120generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]121represent the machine code for <i>any</i> target machine. These classes are
122defined in <tt>include/llvm/CodeGen/</tt>.</li>
123
124<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
125various phases of native code generation (register allocation, scheduling, stack
126frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
127
128<li><a href="#targetimpls">Implementations of the abstract target description
129interfaces</a> for particular targets. These machine descriptions make use of
130the components provided by LLVM, and can optionally provide custom
131target-specific passes, to build complete code generators for a specific target.
132Target descriptions live in <tt>lib/Target/</tt>.</li>
133
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]134<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
135completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
136interface for target-specific issues. The code for the target-independent
137JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
138
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]139</ol>
140
141<p>
142Depending on which part of the code generator you are interested in working on,
143different pieces of this will be useful to you. In any case, you should be
144familiar with the <a href="#targetdesc">target description</a> and <a
145href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]146a backend for a new target, you will need to <a href="#targetimpls">implement the
147target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]148href="LangRef.html">LLVM code representation</a>. If you are interested in
149implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
150should only depend on the target-description and machine code representation
151classes, ensuring that it is portable.
152</p>
153
154</div>
155
156<!-- ======================================================================= -->
157<div class="doc_subsection">
158 <a name="required">Required components in the code generator</a>
159</div>
160
161<div class="doc_text">
162
163<p>The two pieces of the LLVM code generator are the high-level interface to the
164code generator and the set of reusable components that can be used to build
165target-specific backends. The two most important interfaces (<a
166href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]167href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]168required to be defined for a backend to fit into the LLVM system, but the others
169must be defined if the reusable code generator components are going to be
170used.</p>
171
172<p>This design has two important implications. The first is that LLVM can
173support completely non-traditional code generation targets. For example, the C
174backend does not require register allocation, instruction selection, or any of
175the other standard components provided by the system. As such, it only
176implements these two interfaces, and does its own thing. Another example of a
177code generator like this is a (purely hypothetical) backend that converts LLVM
178to the GCC RTL form and uses GCC to emit machine code for a target.</p>
179
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]180<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]181implement radically different code generators in the LLVM system that do not
182make use of any of the built-in components. Doing so is not recommended at all,
183but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]184LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]185
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]186</div>
187
188<!-- ======================================================================= -->
189<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]190 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]191</div>
192
193<div class="doc_text">
194
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]195<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]196quality code generation for standard register-based microprocessors. Code
197generation in this model is divided into the following stages:</p>
198
199<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]200<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
201determines an efficient way to express the input LLVM code in the target
202instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]203This stage produces the initial code for the program in the target instruction
204set, then makes use of virtual registers in SSA form and physical registers that
205represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]206conventions. This step turns the LLVM code into a DAG of target
207instructions.</li>
208
209<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
210phase takes the DAG of target instructions produced by the instruction selection
211phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]212as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
213that we describe this in the <a href="#instselect">instruction selection
214section</a> because it operates on a <a
215href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]216</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]217
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]218<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
219optional stage consists of a series of machine-code optimizations that
220operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]221like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]222</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]223
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]224<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]225target code is transformed from an infinite virtual register file in SSA form
226to the concrete register file used by the target. This phase introduces spill
227code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]228
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]229<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]230machine code has been generated for the function and the amount of stack space
231required is known (used for LLVM alloca's and spill slots), the prolog and
232epilog code for the function can be inserted and "abstract stack location
233references" can be eliminated. This stage is responsible for implementing
234optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]235
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]236<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]237that operate on "final" machine code can go here, such as spill code scheduling
238and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]239
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]240<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]241puts out the code for the current function, either in the target assembler
242format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]243
244</ol>
245
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]246<p>The code generator is based on the assumption that the instruction selector
247will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]248native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]249expansion and aggressive iterative peephole optimization are much slower. This
250design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]251aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]252components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]253compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]254
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]255<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]256target-specific passes into the flow. For example, the X86 target uses a
257special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]258targets with unusual requirements can be supported with custom passes as
259needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]260
261</div>
262
263
264<!-- ======================================================================= -->
265<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]266 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]267</div>
268
269<div class="doc_text">
270
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]271<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]272architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]273information (e.g., an <tt>add</tt> instruction is almost identical to a
274<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]275In order to allow the maximum amount of commonality to be factored out, the LLVM
276code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]277describe big chunks of the target machine, which allows the use of
278domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]279repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]280
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]281<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]282of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]283number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]284LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]285surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]286can get something working. Second, it makes it easier to change things. In
287particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
288only need a change in one place (<tt>tblgen</tt>) to update all of the targets
289to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]290
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]291</div>
292
293<!-- *********************************************************************** -->
294<div class="doc_section">
295 <a name="targetdesc">Target description classes</a>
296</div>
297<!-- *********************************************************************** -->
298
299<div class="doc_text">
300
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]301<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]302<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]303target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]304designed to capture the <i>abstract</i> properties of the target (such as the
305instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]306of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]307
308<p>All of the target description classes (except the <tt><a
309href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
310the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]311get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]312href="#targetmachine">TargetMachine</a></tt> class provides accessors that
313should be implemented by the target.</p>
314
315</div>
316
317<!-- ======================================================================= -->
318<div class="doc_subsection">
319 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
320</div>
321
322<div class="doc_text">
323
324<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
325access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]326classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
327<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
328designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]329a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
330implements the various virtual methods. The only required target description
331class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
332code generator components are to be used, the other interfaces should be
333implemented as well.</p>
334
335</div>
336
337
338<!-- ======================================================================= -->
339<div class="doc_subsection">
340 <a name="targetdata">The <tt>TargetData</tt> class</a>
341</div>
342
343<div class="doc_text">
344
345<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]346and it is the only class that is not extensible (you cannot derived a new
347class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]348lays out memory for structures, the alignment requirements for various data
349types, the size of pointers in the target, and whether the target is
350little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]351
352</div>
353
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]354<!-- ======================================================================= -->
355<div class="doc_subsection">
356 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
357</div>
358
359<div class="doc_text">
360
361<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
362selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]363operations. Among other things, this class indicates:</p>
364
365<ul>
366 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]367 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]368 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]369 <li>the type to use for shift amounts</li>
370 <li>various high-level characteristics, like whether it is profitable to turn
371 division by a constant into a multiplication sequence</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]372</ol>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]373
374</div>
375
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]376<!-- ======================================================================= -->
377<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]378 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]379</div>
380
381<div class="doc_text">
382
383<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
384<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
385target and any interactions between the registers.</p>
386
387<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]388unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]389description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]390large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]391
392<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]393<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
394register (used for assembly output and debugging dumps) and a set of aliases
395(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]396</p>
397
398<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
399exposes a set of processor specific register classes (instances of the
400<tt>TargetRegisterClass</tt> class). Each register class contains sets of
401registers that have the same properties (for example, they are all 32-bit
402integer registers). Each SSA virtual register created by the instruction
403selector has an associated register class. When the register allocator runs, it
404replaces virtual registers with a physical register in the set.</p>
405
406<p>
407The target-specific implementations of these classes is auto-generated from a <a
408href="TableGenFundamentals.html">TableGen</a> description of the register file.
409</p>
410
411</div>
412
413<!-- ======================================================================= -->
414<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]415 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]416</div>
417
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]418<div class="doc_text">
419 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
420 instructions supported by the target. It is essentially an array of
421 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
422 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]423 for the opcode, the number of operands, the list of implicit register uses
424 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]425 (accesses memory, is commutable, etc), and holds any target-specific
426 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]427</div>
428
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]429<!-- ======================================================================= -->
430<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]431 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]432</div>
433
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]434<div class="doc_text">
435 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
436 stack frame layout of the target. It holds the direction of stack growth,
437 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]438 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]439 pointer on function entry to the first location where function data (local
440 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]441</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]442
443<!-- ======================================================================= -->
444<div class="doc_subsection">
445 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
446</div>
447
448<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]449 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
450 specific chip set being targeted. A sub-target informs code generation of
451 which instructions are supported, instruction latencies and instruction
452 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]453 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]454</div>
455
456
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]457<!-- ======================================================================= -->
458<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]459 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]460</div>
461
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]462<div class="doc_text">
463 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
464 Just-In-Time code generator to perform target-specific activities, such as
465 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
466 should provide one of these objects through the <tt>getJITInfo</tt>
467 method.</p>
468</div>
469
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]470<!-- *********************************************************************** -->
471<div class="doc_section">
472 <a name="codegendesc">Machine code description classes</a>
473</div>
474<!-- *********************************************************************** -->
475
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]476<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]477
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]478<p>At the high-level, LLVM code is translated to a machine specific
479representation formed out of
480<a href="#machinefunction"><tt>MachineFunction</tt></a>,
481<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]482href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]483(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
484target agnostic, representing instructions in their most abstract form: an
485opcode and a series of operands. This representation is designed to support
486both an SSA representation for machine code, as well as a register allocated,
487non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]488
489</div>
490
491<!-- ======================================================================= -->
492<div class="doc_subsection">
493 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
494</div>
495
496<div class="doc_text">
497
498<p>Target machine instructions are represented as instances of the
499<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]500representing machine instructions. In particular, it only keeps track of
501an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]502
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]503<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]504specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]505the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]506are auto-generated from this description. The <tt>MachineInstr</tt> class does
507not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]508semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]509<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
510
511<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]512a register reference, a constant integer, a basic block reference, etc. In
513addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]514(though only registers are allowed to be defs).</p>
515
516<p>By convention, the LLVM code generator orders instruction operands so that
517all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]518that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]519instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
520and stores the result into the "%i3" register. In the LLVM code generator,
521the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
522first.</p>
523
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]524<p>Keeping destination (definition) operands at the beginning of the operand
525list has several advantages. In particular, the debugging printer will print
526the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]527
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]528<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]529<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]530%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]531</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]532</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]533
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]534<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]535href="#buildmi">create instructions</a> whose only def is the first
536operand.</p>
537
538</div>
539
540<!-- _______________________________________________________________________ -->
541<div class="doc_subsubsection">
542 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
543</div>
544
545<div class="doc_text">
546
547<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
548located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
549<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]550instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]551
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]552<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]553<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]554// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
555// instruction. The '1' specifies how many operands will be added.
556MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]557
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]558// Create the same instr, but insert it at the end of a basic block.
559MachineBasicBlock &amp;MBB = ...
560BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]561
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]562// Create the same instr, but insert it before a specified iterator point.
563MachineBasicBlock::iterator MBBI = ...
564BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]565
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]566// Create a 'cmp Reg, 0' instruction, no destination reg.
567MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
568// Create an 'sahf' instruction which takes no operands and stores nothing.
569MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]570
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]571// Create a self looping branch instruction.
572BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]573</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]574</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]575
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]576<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
577have to specify the number of operands that the machine instruction will take.
578This allows for efficient memory allocation. You also need to specify if
579operands default to be uses of values, not definitions. If you need to add a
580definition operand (other than the optional destination register), you must
581explicitly mark it as such:</p>
582
583<div class="doc_code">
584<pre>
585MI.addReg(Reg, MachineOperand::Def);
586</pre>
587</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]588
589</div>
590
591<!-- _______________________________________________________________________ -->
592<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]593 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]594</div>
595
596<div class="doc_text">
597
598<p>One important issue that the code generator needs to be aware of is the
599presence of fixed registers. In particular, there are often places in the
600instruction stream where the register allocator <em>must</em> arrange for a
601particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]602limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]603with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
604conventions. In any case, the instruction selector should emit code that
605copies a virtual register into or out of a physical register when needed.</p>
606
607<p>For example, consider this simple LLVM example:</p>
608
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]609<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]610<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]611int %test(int %X, int %Y) {
612 %Z = div int %X, %Y
613 ret int %Z
614}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]615</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]616</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]617
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]618<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
619and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]620"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
621
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]622<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]623<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]624;; Start of div
625%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
626%reg1027 = sar %reg1024, 31
627%EDX = mov %reg1027 ;; Sign extend X into EDX
628idiv %reg1025 ;; Divide by Y (in reg1025)
629%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]630
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]631;; Start of ret
632%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
633ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]634</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]635</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]636
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]637<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]638the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]639following code:</p>
640
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]641<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]642<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]643;; X is in EAX, Y is in ECX
644mov %EAX, %EDX
645sar %EDX, 31
646idiv %ECX
647ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]648</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]649</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]650
651<p>This approach is extremely general (if it can handle the X86 architecture,
652it can handle anything!) and allows all of the target specific
653knowledge about the instruction stream to be isolated in the instruction
654selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]655code generation, and all physical registers are assumed dead on entry to and
656exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]657to be live across basic block boundaries, it <em>must</em> live in a virtual
658register.</p>
659
660</div>
661
662<!-- _______________________________________________________________________ -->
663<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]664 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]665</div>
666
667<div class="doc_text">
668
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]669<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]670are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]671part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]672become machine code PHI nodes, and virtual registers are only allowed to have a
673single definition.</p>
674
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]675<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]676are no virtual registers left in the code.</p>
677
678</div>
679
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]680<!-- ======================================================================= -->
681<div class="doc_subsection">
682 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
683</div>
684
685<div class="doc_text">
686
687<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]688(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
689corresponds to the LLVM code input to the instruction selector, but there can be
690a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
691basic blocks). The <tt>MachineBasicBlock</tt> class has a
692"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
693comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]694
695</div>
696
697<!-- ======================================================================= -->
698<div class="doc_subsection">
699 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
700</div>
701
702<div class="doc_text">
703
704<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]705(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
706corresponds one-to-one with the LLVM function input to the instruction selector.
707In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
708a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
709<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
710live out registers for the function. See
711<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]712
713</div>
714
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]715<!-- *********************************************************************** -->
716<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]717 <a name="codegenalgs">Target-independent code generation algorithms</a>
718</div>
719<!-- *********************************************************************** -->
720
721<div class="doc_text">
722
723<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]724href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]725explains how they work and some of the rationale behind their design.</p>
726
727</div>
728
729<!-- ======================================================================= -->
730<div class="doc_subsection">
731 <a name="instselect">Instruction Selection</a>
732</div>
733
734<div class="doc_text">
735<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]736Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]737code generator into target-specific machine instructions. There are several
738well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]739the SelectionDAG based instruction selector framework and an old-style 'simple'
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]740instruction selector, which effectively peephole selects each LLVM instruction
741into a series of machine instructions. We recommend that all targets use the
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]742SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]743</p>
744
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]745<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]746description (<tt>*.td</tt>) files. Our goal is for the entire instruction
747selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]748</div>
749
750<!-- _______________________________________________________________________ -->
751<div class="doc_subsubsection">
752 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
753</div>
754
755<div class="doc_text">
756
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]757<p>The SelectionDAG provides an abstraction for code representation in a way
758that is amenable to instruction selection using automatic techniques
759(e.g. dynamic-programming based optimal pattern matching selectors). It is also
760well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]761instruction scheduling (SelectionDAG's are very close to scheduling DAGs
762post-selection). Additionally, the SelectionDAG provides a host representation
763where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]764<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]765performed; ones which require extensive information about the instructions
766efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]767
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]768<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]769<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]770operation code (Opcode) that indicates what operation the node performs and
771the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]772The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]773<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]774
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]775<p>Although most operations define a single value, each node in the graph may
776define multiple values. For example, a combined div/rem operation will define
777both the dividend and the remainder. Many other situations require multiple
778values as well. Each node also has some number of operands, which are edges
779to the node defining the used value. Because nodes may define multiple values,
780edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]781a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
782value being used, respectively. Each value produced by an <tt>SDNode</tt> has
783an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]784
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]785<p>SelectionDAGs contain two different kinds of values: those that represent
786data flow and those that represent control flow dependencies. Data values are
787simple edges with an integer or floating point value type. Control edges are
788represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
789provide an ordering between nodes that have side effects (such as
790loads, stores, calls, returns, etc). All nodes that have side effects should
791take a token chain as input and produce a new one as output. By convention,
792token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]793value produced by an operation.</p>
794
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]795<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
796always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
797is the final side-effecting node in the token chain. For example, in a single
798basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]799
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]800<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
801"illegal" DAG. A legal DAG for a target is one that only uses supported
802operations and supported types. On a 32-bit PowerPC, for example, a DAG with
803a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
804SREM or UREM operation. The
805<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
806an illegal DAG into a legal DAG.</p>
807
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]808</div>
809
810<!-- _______________________________________________________________________ -->
811<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]812 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]813</div>
814
815<div class="doc_text">
816
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]817<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]818
819<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]820<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
821 performs a simple translation from the input LLVM code to an illegal
822 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]823<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]824 performs simple optimizations on the SelectionDAG to simplify it, and
825 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
826 pairs) for targets that support these meta operations. This makes the
827 resultant code more efficient and the <a href="#selectiondag_select">select
828 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]829<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]830 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]831 unsupported operations and data types.</li>
832<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]833 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]834 eliminate inefficiencies introduced by legalization.</li>
835<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
836 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]837 instructions. This process translates the target-independent input DAG into
838 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]839<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]840 - The last phase assigns a linear order to the instructions in the
841 target-instruction DAG and emits them into the MachineFunction being
842 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]843</ol>
844
845<p>After all of these steps are complete, the SelectionDAG is destroyed and the
846rest of the code generation passes are run.</p>
847
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]848<p>One great way to visualize what is going on here is to take advantage of a
849few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
850option pops up a window with the SelectionDAG input to the Select phase for all
851of the code compiled (if you only get errors printed to the console while using
852this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
853your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
854views the SelectionDAG output from the Select phase and input to the Scheduler
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]855phase.</p>
856
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]857</div>
858
859<!-- _______________________________________________________________________ -->
860<div class="doc_subsubsection">
861 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
862</div>
863
864<div class="doc_text">
865
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]866<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
867input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]868<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
869pass is to expose as much low-level, target-specific details to the SelectionDAG
870as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
871into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
872obvious arithmetic). This pass requires target-specific hooks to lower calls,
873returns, varargs, etc. For these features, the
874<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]875
876</div>
877
878<!-- _______________________________________________________________________ -->
879<div class="doc_subsubsection">
880 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
881</div>
882
883<div class="doc_text">
884
885<p>The Legalize phase is in charge of converting a DAG to only use the types and
886operations that are natively supported by the target. This involves two major
887tasks:</p>
888
889<ol>
890<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]891 <p>There are two main ways of doing this: converting small types to
892 larger types ("promoting"), and breaking up large integer types
893 into smaller ones ("expanding"). For example, a target might require
894 that all f32 values are promoted to f64 and that all i1/i8/i16 values
895 are promoted to i32. The same target might require that all i64 values
896 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]897 extensions as needed to make sure that the final code has the same
898 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]899 <p>A target implementation tells the legalizer which types are supported
900 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]901 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]902</li>
903
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]904<li><p>Eliminate operations that are not supported by the target.</p>
905 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]906 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]907 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]908 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]909 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]910 promoting one type to a larger type that supports the operation
911 ("promotion"), or by using a target-specific hook to implement the
912 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]913 <p>A target implementation tells the legalizer which operations are not
914 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]915 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
916 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]917</li>
918</ol>
919
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]920<p>Prior to the existance of the Legalize pass, we required that every target
921<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]922operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]923the Legalize phase allows all of the cannonicalization patterns to be shared
924across targets, and makes it very easy to optimize the cannonicalized code
925because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]926
927</div>
928
929<!-- _______________________________________________________________________ -->
930<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]931 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
932 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]933</div>
934
935<div class="doc_text">
936
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]937<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]938immediately after the DAG is built and once after legalization. The first run
939of the pass allows the initial code to be cleaned up (e.g. performing
940optimizations that depend on knowing that the operators have restricted type
941inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]942Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]943code legal instead of focusing on generating <em>good</em> and legal code).</p>
944
945<p>One important class of optimizations performed is optimizing inserted sign
946and zero extension instructions. We currently use ad-hoc techniques, but could
947move to more rigorous techniques in the future. Here are some good papers on
948the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]949
950<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]951 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
952 integer arithmetic</a>"<br>
953 Kevin Redwine and Norman Ramsey<br>
954 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]955</p>
956
957
958<p>
959 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
960 sign extension elimination</a>"<br>
961 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
962 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
963 and Implementation.
964</p>
965
966</div>
967
968<!-- _______________________________________________________________________ -->
969<div class="doc_subsubsection">
970 <a name="selectiondag_select">SelectionDAG Select Phase</a>
971</div>
972
973<div class="doc_text">
974
975<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]976selection. This phase takes a legal SelectionDAG as input, pattern matches the
977instructions supported by the target to this DAG, and produces a new DAG of
978target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]979
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]980<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]981<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]982%t1 = add float %W, %X
983%t2 = mul float %t1, %Y
984%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]985</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]986</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]987
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]988<p>This LLVM code corresponds to a SelectionDAG that looks basically like
989this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]990
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]991<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]992<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]993(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]994</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]995</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]996
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]997<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]998of the adds can be merged with the multiply. On the PowerPC, for example, the
999output of the instruction selector might look like this DAG:</p>
1000
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1001<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1002<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1003(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1004</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1005</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1006
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1007<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1008first two operands and adds the third (as single-precision floating-point
1009numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1010add instruction. To perform this pattern match, the PowerPC backend includes
1011the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1012
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1013<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1014<pre>
1015def FMADDS : AForm_1&lt;59, 29,
1016 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1017 "fmadds $FRT, $FRA, $FRC, $FRB",
1018 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1019 F4RC:$FRB))</b>]&gt;;
1020def FADDS : AForm_2&lt;59, 21,
1021 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1022 "fadds $FRT, $FRA, $FRB",
1023 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1024</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1025</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1026
1027<p>The portion of the instruction definition in bold indicates the pattern used
1028to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1029are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1030"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1031
1032<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1033patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1034matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1035
1036<ul>
1037<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1038 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1039<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1040 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1041 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1042 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1043 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1044<li>It knows several important identities for the patterns defined. For
1045 example, it knows that addition is commutative, so it allows the
1046 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1047 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1048 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1049<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1050 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1051 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1052 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1053 was able to infer and propagate this knowledge from the fact that
1054 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1055<li>Targets can define their own (and rely on built-in) "pattern fragments".
1056 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1057 patterns during compiler-compiler time. For example, the integer
1058 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1059 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1060 native '<tt>not</tt>' operation. Targets can define their own short-hand
1061 fragments as they see fit. See the definition of '<tt>not</tt>' and
1062 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1063<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1064 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1065 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1066 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1067 <br>
1068 <br>
1069 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1070 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1071// Arbitrary immediate support. Implement in terms of LIS/ORI.
1072def : Pat&lt;(i32 imm:$imm),
1073 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1074 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1075 </div>
1076 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1077 If none of the single-instruction patterns for loading an immediate into a
1078 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1079 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1080 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1081 left 16 bits') instruction". To make this work, the
1082 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1083 input immediate (in this case, take the high or low 16-bits of the
1084 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1085<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1086 C++ code to match special cases if there is something that is hard to
1087 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1088</ul>
1089
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1090<p>While it has many strengths, the system currently has some limitations,
1091primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1092
1093<ul>
1094<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1095 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1096 etc). This is the biggest reason that you currently still <em>have to</em>
1097 write custom C++ code for your instruction selector.</li>
1098<li>There is no great way to support matching complex addressing modes yet. In
1099 the future, we will extend pattern fragments to allow them to define
1100 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1101 addressing mode</a>). In addition, we'll extend fragments so that a
1102 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1103<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1104<li>We don't automatically generate the set of supported registers and
1105 operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
1106<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1107</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1108
1109<p>Despite these limitations, the instruction selector generator is still quite
1110useful for most of the binary and logical operations in typical instruction
1111sets. If you run into any problems or can't figure out how to do something,
1112please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1113
1114</div>
1115
1116<!-- _______________________________________________________________________ -->
1117<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1118 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1119</div>
1120
1121<div class="doc_text">
1122
1123<p>The scheduling phase takes the DAG of target instructions from the selection
1124phase and assigns an order. The scheduler can pick an order depending on
1125various constraints of the machines (i.e. order for minimal register pressure or
1126try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1127converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1128the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1129
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1130<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1131phase, but is tied to it closely in the code because it operates on
1132SelectionDAGs.</p>
1133
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1134</div>
1135
1136<!-- _______________________________________________________________________ -->
1137<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1138 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1139</div>
1140
1141<div class="doc_text">
1142
1143<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1144<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1145<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1146</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1147</ol>
1148
1149</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1150
1151<!-- ======================================================================= -->
1152<div class="doc_subsection">
1153 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1154</div>
1155<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1156
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1157<!-- ======================================================================= -->
1158<div class="doc_subsection">
1159 <a name="regalloc">Register Allocation</a>
1160</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1161
1162<div class="doc_text">
1163
1164<p>The <i>Register Allocation problem</i> consists in mapping a
1165program <i>P<sub>v</sub></i>, that can use an unbounded number of
1166virtual registers, to a program <i>P<sub>p</sub></i> that contains a
1167finite (possibly small) number of physical registers. Each target
1168architecture has a different number of physical registers. If the
1169number of physical registers is not enough to accommodate all the
1170virtual registers, some of them will have to be mapped into
1171memory. These virtuals are called <i>spilled virtuals</i>.</p>
1172
1173</div>
1174
1175<!-- _______________________________________________________________________ -->
1176
1177<div class="doc_subsubsection">
1178 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1179</div>
1180
1181<div class="doc_text">
1182
1183<p>In LLVM, physical registers are denoted by integer numbers that
1184normally range from 1 to 1023. To see how this numbering is defined
1185for a particular architecture, you can read the
1186<tt>GenRegisterNames.inc</tt> file for that architecture. For
1187instance, by inspecting
1188<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1189register <tt>EAX</tt> is denoted by 15, and the MMX register
1190<tt>MM0</tt> is mapped to 48.</p>
1191
1192<p>Some architectures contain registers that share the same physical
1193location. A notable example is the X86 platform. For instance, in the
1194X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1195<tt>AL</tt> share the first eight bits. These physical registers are
1196marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1197can check which registers are aliased by inspecting its
1198<tt>RegisterInfo.td</tt> file. Moreover, the method
1199<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1200all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1201
1202<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1203Elements in the same register class are functionally equivalent, and can
1204be interchangeably used. Each virtual register can only be mapped to
1205physical registers of a particular class. For instance, in the X86
1206architecture, some virtuals can only be allocated to 8 bit registers.
1207A register class is described by <tt>TargetRegisterClass</tt> objects.
1208To discover if a virtual register is compatible with a given physical,
1209this code can be used:
1210</p>
1211
1212<div class="doc_code">
1213<pre>
1214bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1215 unsigned v_reg,
1216 unsigned p_reg) {
1217 assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
1218 "Target register must be physical");
1219 const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
1220 return trc->contains(p_reg);
1221}
1222</pre>
1223</div>
1224
1225<p>Sometimes, mostly for debugging purposes, it is useful to change
1226the number of physical registers available in the target
1227architecture. This must be done statically, inside the
1228<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1229<tt>RegisterClass</tt>, the last parameter of which is a list of
1230registers. Just commenting some out is one simple way to avoid them
1231being used. A more polite way is to explicitly exclude some registers
1232from the <i>allocation order</i>. See the definition of the
1233<tt>GR</tt> register class in
1234<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1235(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1236
1237<p>Virtual registers are also denoted by integer numbers. Contrary to
1238physical registers, different virtual registers never share the same
1239number. The smallest virtual register is normally assigned the number
12401024. This may change, so, in order to know which is the first virtual
1241register, you should access
1242<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1243number is greater than or equal to
1244<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1245register. Whereas physical registers are statically defined in a
1246<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1247application developer, that is not the case with virtual registers.
1248In order to create new virtual registers, use the method
1249<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
1250virtual register with the highest code.
1251</p>
1252
1253<p>Before register allocation, the operands of an instruction are
1254mostly virtual registers, although physical registers may also be
1255used. In order to check if a given machine operand is a register, use
1256the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1257the integer code of a register, use
1258<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1259register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1260defines the registers 1024, and uses registers 1025 and 1026. Given a
1261register operand, the method <tt>MachineOperand::isUse()</tt> informs
1262if that register is being used by the instruction. The method
1263<tt>MachineOperand::isDef()</tt> informs if that registers is being
1264defined.</p>
1265
1266<p>We will call physical registers present in the LLVM bytecode before
1267register allocation <i>pre-colored registers</i>. Pre-colored
1268registers are used in many different situations, for instance, to pass
1269parameters of functions calls, and to store results of particular
1270instructions. There are two types of pre-colored registers: the ones
1271<i>implicitly</i> defined, and those <i>explicitly</i>
1272defined. Explicitly defined registers are normal operands, and can be
1273accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1274order to check which registers are implicitly defined by an
1275instruction, use the
1276<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1277<tt>opcode</tt> is the opcode of the target instruction. One important
1278difference between explicit and implicit physical registers is that
1279the latter are defined statically for each instruction, whereas the
1280former may vary depending on the program being compiled. For example,
1281an instruction that represents a function call will always implicitly
1282define or use the same set of physical registers. To read the
1283registers implicitly used by an instruction, use
1284<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1285registers impose constraints on any register allocation algorithm. The
1286register allocator must make sure that none of them is been
1287overwritten by the values of virtual registers while still alive.</p>
1288
1289</div>
1290
1291<!-- _______________________________________________________________________ -->
1292
1293<div class="doc_subsubsection">
1294 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1295</div>
1296
1297<div class="doc_text">
1298
1299<p>There are two ways to map virtual registers to physical registers (or to
1300memory slots). The first way, that we will call <i>direct mapping</i>,
1301is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
1302and <tt>MachineOperand</tt>. The second way, that we will call
1303<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1304order to insert loads and stores sending and getting values to and from
1305memory.</p>
1306
1307<p>The direct mapping provides more flexibility to the developer of
1308the register allocator; however, it is more error prone, and demands
1309more implementation work. Basically, the programmer will have to
1310specify where load and store instructions should be inserted in the
1311target function being compiled in order to get and store values in
1312memory. To assign a physical register to a virtual register present in
1313a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1314a store instruction, use
1315<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1316instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
1317
1318<p>The indirect mapping shields the application developer from the
1319complexities of inserting load and store instructions. In order to map
1320a virtual register to a physical one, use
1321<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1322certain virtual register to memory, use
1323<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1324return the stack slot where <tt>vreg</tt>'s value will be located. If
1325it is necessary to map another virtual register to the same stack
1326slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1327stack_location)</tt>. One important point to consider when using the
1328indirect mapping, is that even if a virtual register is mapped to
1329memory, it still needs to be mapped to a physical register. This
1330physical register is the location where the virtual register is
1331supposed to be found before being stored or after being reloaded.</p>
1332
1333<p>If the indirect strategy is used, after all the virtual registers
1334have been mapped to physical registers or stack slots, it is necessary
1335to use a spiller object to place load and store instructions in the
1336code. Every virtual that has been mapped to a stack slot will be
1337stored to memory after been defined and will be loaded before being
1338used. The implementation of the spiller tries to recycle load/store
1339instructions, avoiding unnecessary instructions. For an example of how
1340to invoke the spiller, see
1341<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1342<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1343
1344</div>
1345
1346<!-- _______________________________________________________________________ -->
1347<div class="doc_subsubsection">
1348 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1349</div>
1350
1351<div class="doc_text">
1352
1353<p>With very rare exceptions (e.g., function calls), the LLVM machine
1354code instructions are three address instructions. That is, each
1355instruction is expected to define at most one register, and to use at
1356most two registers. However, some architectures use two address
1357instructions. In this case, the defined register is also one of the
1358used register. For instance, an instruction such as <tt>ADD %EAX,
1359%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1360%EBX</tt>.</p>
1361
1362<p>In order to produce correct code, LLVM must convert three address
1363instructions that represent two address instructions into true two
1364address instructions. LLVM provides the pass
1365<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1366be run before register allocation takes place. After its execution,
1367the resulting code may no longer be in SSA form. This happens, for
1368instance, in situations where an instruction such as <tt>%a = ADD %b
1369%c</tt> is converted to two instructions such as:</p>
1370
1371<div class="doc_code">
1372<pre>
1373%a = MOVE %b
1374%a = ADD %a %b
1375</pre>
1376</div>
1377
1378<p>Notice that, internally, the second instruction is represented as
1379<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1380both used and defined by the instruction.</p>
1381
1382</div>
1383
1384<!-- _______________________________________________________________________ -->
1385<div class="doc_subsubsection">
1386 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1387</div>
1388
1389<div class="doc_text">
1390
1391<p>An important transformation that happens during register allocation is called
1392the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1393analyses that are performed on the control flow graph of
1394programs. However, traditional instruction sets do not implement
1395PHI instructions. Thus, in order to generate executable code, compilers
1396must replace PHI instructions with other instructions that preserve their
1397semantics.</p>
1398
1399<p>There are many ways in which PHI instructions can safely be removed
1400from the target code. The most traditional PHI deconstruction
1401algorithm replaces PHI instructions with copy instructions. That is
1402the strategy adopted by LLVM. The SSA deconstruction algorithm is
1403implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1404invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1405marked as required in the code of the register allocator.</p>
1406
1407</div>
1408
1409<!-- _______________________________________________________________________ -->
1410<div class="doc_subsubsection">
1411 <a name="regAlloc_fold">Instruction folding</a>
1412</div>
1413
1414<div class="doc_text">
1415
1416<p><i>Instruction folding</i> is an optimization performed during
1417register allocation that removes unnecessary copy instructions. For
1418instance, a sequence of instructions such as:</p>
1419
1420<div class="doc_code">
1421<pre>
1422%EBX = LOAD %mem_address
1423%EAX = COPY %EBX
1424</pre>
1425</div>
1426
1427<p>can be safely substituted by the single instruction:
1428
1429<div class="doc_code">
1430<pre>
1431%EAX = LOAD %mem_address
1432</pre>
1433</div>
1434
1435<p>Instructions can be folded with the
1436<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1437taken when folding instructions; a folded instruction can be quite
1438different from the original instruction. See
1439<tt>LiveIntervals::addIntervalsForSpills</tt> in
1440<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1441
1442</div>
1443
1444<!-- _______________________________________________________________________ -->
1445
1446<div class="doc_subsubsection">
1447 <a name="regAlloc_builtIn">Built in register allocators</a>
1448</div>
1449
1450<div class="doc_text">
1451
1452<p>The LLVM infrastructure provides the application developer with
1453three different register allocators:</p>
1454
1455<ul>
1456 <li><i>Simple</i> - This is a very simple implementation that does
1457 not keep values in registers across instructions. This register
1458 allocator immediately spills every value right after it is
1459 computed, and reloads all used operands from memory to temporary
1460 registers before each instruction.</li>
1461 <li><i>Local</i> - This register allocator is an improvement on the
1462 <i>Simple</i> implementation. It allocates registers on a basic
1463 block level, attempting to keep values in registers and reusing
1464 registers as appropriate.</li>
1465 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1466 well-know linear scan register allocator. Whereas the
1467 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1468 implementation technique, the <i>Linear Scan</i> implementation
1469 uses a spiller in order to place load and stores.</li>
1470</ul>
1471
1472<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1473command line option <tt>-regalloc=...</tt>:</p>
1474
1475<div class="doc_code">
1476<pre>
1477$ llc -f -regalloc=simple file.bc -o sp.s;
1478$ llc -f -regalloc=local file.bc -o lc.s;
1479$ llc -f -regalloc=linearscan file.bc -o ln.s;
1480</pre>
1481</div>
1482
1483</div>
1484
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1485<!-- ======================================================================= -->
1486<div class="doc_subsection">
1487 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1488</div>
1489<div class="doc_text"><p>To Be Written</p></div>
1490<!-- ======================================================================= -->
1491<div class="doc_subsection">
1492 <a name="latemco">Late Machine Code Optimizations</a>
1493</div>
1494<div class="doc_text"><p>To Be Written</p></div>
1495<!-- ======================================================================= -->
1496<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1497 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1498</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1499<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1500<!-- _______________________________________________________________________ -->
1501<div class="doc_subsubsection">
1502 <a name="codeemit_asm">Generating Assembly Code</a>
1503</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1504<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1505<!-- _______________________________________________________________________ -->
1506<div class="doc_subsubsection">
1507 <a name="codeemit_bin">Generating Binary Machine Code</a>
1508</div>
1509
1510<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1511 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1512</div>
1513
1514
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1515<!-- *********************************************************************** -->
1516<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1517 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1518</div>
1519<!-- *********************************************************************** -->
1520
1521<div class="doc_text">
1522
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1523<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1524are specific to the code generator for a particular target.</p>
1525
1526</div>
1527
1528
1529<!-- ======================================================================= -->
1530<div class="doc_subsection">
1531 <a name="x86">The X86 backend</a>
1532</div>
1533
1534<div class="doc_text">
1535
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1536<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1537code generator currently targets a generic P6-like processor. As such, it
1538produces a few P6-and-above instructions (like conditional moves), but it does
1539not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1540will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1541implementations.</p>
1542
1543</div>
1544
1545<!-- _______________________________________________________________________ -->
1546<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1547 <a name="x86_tt">X86 Target Triples Supported</a>
1548</div>
1549
1550<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1551
1552<p>The following are the known target triples that are supported by the X86
1553backend. This is not an exhaustive list, and it would be useful to add those
1554that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1555
1556<ul>
1557<li><b>i686-pc-linux-gnu</b> - Linux</li>
1558<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1559<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1560<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1561<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1562</ul>
1563
1564</div>
1565
1566<!-- _______________________________________________________________________ -->
1567<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1568 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1569</div>
1570
1571<div class="doc_text">
1572
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1573<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1574forming memory addresses of the following expression directly in integer
1575instructions (which use ModR/M addressing):</p>
1576
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1577<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1578<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1579Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1580</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1581</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1582
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1583<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1584memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1585has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1586
1587<pre>
1588Index: 0 | 1 2 3 4
1589Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1590OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1591</pre>
1592
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1593<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1594same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1595
1596</div>
1597
1598<!-- _______________________________________________________________________ -->
1599<div class="doc_subsubsection">
1600 <a name="x86_names">Instruction naming</a>
1601</div>
1602
1603<div class="doc_text">
1604
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1605<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1606a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1607
1608<p>
1609<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1610<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1611<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1612<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1613</p>
1614
1615</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1616
1617<!-- *********************************************************************** -->
1618<hr>
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1624
1625 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]1626 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1627 Last modified: $Date$
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