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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
2 "http://www.w3.org/TR/html4/strict.dtd">
3<html>
4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]61 <li><a href="#codeemit">Code Emission</a>
62 <ul>
63 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
64 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
65 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]66 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]67 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]68 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]69 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]70 <li><a href="#x86">The X86 backend</a></li>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]71 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]72 </li>
73
74</ol>
75
76<div class="doc_author">
77 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
78</div>
79
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]80<div class="doc_warning">
81 <p>Warning: This is a work in progress.</p>
82</div>
83
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84<!-- *********************************************************************** -->
85<div class="doc_section">
86 <a name="introduction">Introduction</a>
87</div>
88<!-- *********************************************************************** -->
89
90<div class="doc_text">
91
92<p>The LLVM target-independent code generator is a framework that provides a
93suite of reusable components for translating the LLVM internal representation to
94the machine code for a specified target -- either in assembly form (suitable for
95a static compiler) or in binary machine code format (usable for a JIT compiler).
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]96The LLVM target-independent code generator consists of five main components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]97
98<ol>
99<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]100capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]101of how they will be used. These interfaces are defined in
102<tt>include/llvm/Target/</tt>.</li>
103
104<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]105generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]106represent the machine code for <i>any</i> target machine. These classes are
107defined in <tt>include/llvm/CodeGen/</tt>.</li>
108
109<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
110various phases of native code generation (register allocation, scheduling, stack
111frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
112
113<li><a href="#targetimpls">Implementations of the abstract target description
114interfaces</a> for particular targets. These machine descriptions make use of
115the components provided by LLVM, and can optionally provide custom
116target-specific passes, to build complete code generators for a specific target.
117Target descriptions live in <tt>lib/Target/</tt>.</li>
118
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]119<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
120completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
121interface for target-specific issues. The code for the target-independent
122JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
123
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]124</ol>
125
126<p>
127Depending on which part of the code generator you are interested in working on,
128different pieces of this will be useful to you. In any case, you should be
129familiar with the <a href="#targetdesc">target description</a> and <a
130href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]131a backend for a new target, you will need to <a href="#targetimpls">implement the
132target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]133href="LangRef.html">LLVM code representation</a>. If you are interested in
134implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
135should only depend on the target-description and machine code representation
136classes, ensuring that it is portable.
137</p>
138
139</div>
140
141<!-- ======================================================================= -->
142<div class="doc_subsection">
143 <a name="required">Required components in the code generator</a>
144</div>
145
146<div class="doc_text">
147
148<p>The two pieces of the LLVM code generator are the high-level interface to the
149code generator and the set of reusable components that can be used to build
150target-specific backends. The two most important interfaces (<a
151href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]152href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]153required to be defined for a backend to fit into the LLVM system, but the others
154must be defined if the reusable code generator components are going to be
155used.</p>
156
157<p>This design has two important implications. The first is that LLVM can
158support completely non-traditional code generation targets. For example, the C
159backend does not require register allocation, instruction selection, or any of
160the other standard components provided by the system. As such, it only
161implements these two interfaces, and does its own thing. Another example of a
162code generator like this is a (purely hypothetical) backend that converts LLVM
163to the GCC RTL form and uses GCC to emit machine code for a target.</p>
164
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]165<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]166implement radically different code generators in the LLVM system that do not
167make use of any of the built-in components. Doing so is not recommended at all,
168but could be required for radically different targets that do not fit into the
169LLVM machine description model: programmable FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]170
171<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
172generator uses almost entirely different code paths than described in this
173document. For this reason, there are some deprecated interfaces (such as
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]174<tt>TargetSchedInfo</tt>), which are only used by the
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]175V9 backend and should not be used by any other targets. Also, all code in the
176<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
177deprecated, and should not be used as the basis for future code generator work.
Misha Brukmanf3709d62004-06-03 16:55:57 +0000[diff] [blame]178The SparcV9 backend is slowly being merged into the rest of the
179target-independent code generators, but this is a low-priority process with no
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]180predictable completion date.</p>
181
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]182</div>
183
184<!-- ======================================================================= -->
185<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]186 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]187</div>
188
189<div class="doc_text">
190
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]191<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]192quality code generation for standard register-based microprocessors. Code
193generation in this model is divided into the following stages:</p>
194
195<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]196<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
197determines an efficient way to express the input LLVM code in the target
198instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]199This stage produces the initial code for the program in the target instruction
200set, then makes use of virtual registers in SSA form and physical registers that
201represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]202conventions. This step turns the LLVM code into a DAG of target
203instructions.</li>
204
205<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
206phase takes the DAG of target instructions produced by the instruction selection
207phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]208as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
209that we describe this in the <a href="#instselect">instruction selection
210section</a> because it operates on a <a
211href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]212</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]213
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]214<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
215optional stage consists of a series of machine-code optimizations that
216operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]217like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]218</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]219
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]220<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]221target code is transformed from an infinite virtual register file in SSA form
222to the concrete register file used by the target. This phase introduces spill
223code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]224
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]225<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]226machine code has been generated for the function and the amount of stack space
227required is known (used for LLVM alloca's and spill slots), the prolog and
228epilog code for the function can be inserted and "abstract stack location
229references" can be eliminated. This stage is responsible for implementing
230optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]231
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]232<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]233that operate on "final" machine code can go here, such as spill code scheduling
234and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]235
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]236<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]237puts out the code for the current function, either in the target assembler
238format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]239
240</ol>
241
242<p>
243The code generator is based on the assumption that the instruction selector will
244use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]245native instructions. Alternative code generator designs based on pattern
246expansion and
247aggressive iterative peephole optimization are much slower. This design
248permits efficient compilation (important for JIT environments) and
249aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]250components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]251compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]252
253<p>
254In addition to these stages, target implementations can insert arbitrary
255target-specific passes into the flow. For example, the X86 target uses a
256special pass to handle the 80x87 floating point stack architecture. Other
257targets with unusual requirements can be supported with custom passes as needed.
258</p>
259
260</div>
261
262
263<!-- ======================================================================= -->
264<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]265 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]266</div>
267
268<div class="doc_text">
269
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]270<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]271architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]272information (e.g., an <tt>add</tt> instruction is almost identical to a
273<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]274In order to allow the maximum amount of commonality to be factored out, the LLVM
275code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]276describe big chunks of the target machine, which allows the use of
277domain-specific and target-specific abstractions to reduce the amount of
278repetition.
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]279</p>
280
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]281<p>As LLVM continues to be developed and refined, we plan to move more and more
282of the target description to be in <tt>.td</tt> form. Doing so gives us a
283number of advantages. The most important is that it makes it easier to port
284LLVM, because it reduces the amount of C++ code that has to be written and the
285surface area of the code generator that needs to be understood before someone
286can get in an get something working. Second, it is also important to us because
287it makes it easier to change things: in particular, if tables and other things
288are all emitted by tblgen, we only need to change one place (tblgen) to update
289all of the targets to a new interface.</p>
290
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]291</div>
292
293<!-- *********************************************************************** -->
294<div class="doc_section">
295 <a name="targetdesc">Target description classes</a>
296</div>
297<!-- *********************************************************************** -->
298
299<div class="doc_text">
300
301<p>The LLVM target description classes (which are located in the
302<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]303target machine; independent of any particular client. These classes are
304designed to capture the <i>abstract</i> properties of the target (such as the
305instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]306of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]307
308<p>All of the target description classes (except the <tt><a
309href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
310the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]311get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]312href="#targetmachine">TargetMachine</a></tt> class provides accessors that
313should be implemented by the target.</p>
314
315</div>
316
317<!-- ======================================================================= -->
318<div class="doc_subsection">
319 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
320</div>
321
322<div class="doc_text">
323
324<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
325access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]326classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
327<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
328designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]329a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
330implements the various virtual methods. The only required target description
331class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
332code generator components are to be used, the other interfaces should be
333implemented as well.</p>
334
335</div>
336
337
338<!-- ======================================================================= -->
339<div class="doc_subsection">
340 <a name="targetdata">The <tt>TargetData</tt> class</a>
341</div>
342
343<div class="doc_text">
344
345<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]346and it is the only class that is not extensible (you cannot derived a new
347class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]348lays out memory for structures, the alignment requirements for various data
349types, the size of pointers in the target, and whether the target is
350little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]351
352</div>
353
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]354<!-- ======================================================================= -->
355<div class="doc_subsection">
356 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
357</div>
358
359<div class="doc_text">
360
361<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
362selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]363operations. Among other things, this class indicates:
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]364<ul><li>an initial register class to use for various ValueTypes</li>
365 <li>which operations are natively supported by the target machine</li>
366 <li>the return type of setcc operations</li>
367 <li>the type to use for shift amounts</li>
368 <li>various high-level characteristics, like whether it is profitable to turn
369 division by a constant into a multiplication sequence</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]370</ol></p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]371
372</div>
373
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]374<!-- ======================================================================= -->
375<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]376 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]377</div>
378
379<div class="doc_text">
380
381<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
382<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
383target and any interactions between the registers.</p>
384
385<p>Registers in the code generator are represented in the code generator by
386unsigned numbers. Physical registers (those that actually exist in the target
387description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]388large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]389
390<p>Each register in the processor description has an associated
Chris Lattner88a06d22005-09-30 17:46:55 +0000[diff] [blame]391<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the register
392(used for assembly output and debugging dumps) and a set of aliases (used to
393indicate that one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]394</p>
395
396<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
397exposes a set of processor specific register classes (instances of the
398<tt>TargetRegisterClass</tt> class). Each register class contains sets of
399registers that have the same properties (for example, they are all 32-bit
400integer registers). Each SSA virtual register created by the instruction
401selector has an associated register class. When the register allocator runs, it
402replaces virtual registers with a physical register in the set.</p>
403
404<p>
405The target-specific implementations of these classes is auto-generated from a <a
406href="TableGenFundamentals.html">TableGen</a> description of the register file.
407</p>
408
409</div>
410
411<!-- ======================================================================= -->
412<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]413 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]414</div>
415
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]416<div class="doc_text">
417 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
418 instructions supported by the target. It is essentially an array of
419 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
420 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]421 for the opcode, the number of operands, the list of implicit register uses
422 and defs, whether the instruction has certain target-independent properties
423 (accesses memory, is commutable, etc), and holds any target-specific flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]424</div>
425
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]426<!-- ======================================================================= -->
427<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]428 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]429</div>
430
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]431<div class="doc_text">
432 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
433 stack frame layout of the target. It holds the direction of stack growth,
434 the known stack alignment on entry to each function, and the offset to the
435 locals area. The offset to the local area is the offset from the stack
436 pointer on function entry to the first location where function data (local
437 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]438</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]439
440<!-- ======================================================================= -->
441<div class="doc_subsection">
442 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
443</div>
444
445<div class="doc_text">
446 <p>
447 TODO
448 </p>
449</div>
450
451
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]452<!-- ======================================================================= -->
453<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]454 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]455</div>
456
457<!-- *********************************************************************** -->
458<div class="doc_section">
459 <a name="codegendesc">Machine code description classes</a>
460</div>
461<!-- *********************************************************************** -->
462
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]463<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]464
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]465<p>
466At the high-level, LLVM code is translated to a machine specific representation
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]467formed out of <a href="#machinefunction">MachineFunction</a>,
468<a href="#machinebasicblock">MachineBasicBlock</a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]469href="#machineinstr"><tt>MachineInstr</tt></a> instances
470(defined in include/llvm/CodeGen). This representation is completely target
471agnostic, representing instructions in their most abstract form: an opcode and a
472series of operands. This representation is designed to support both SSA
473representation for machine code, as well as a register allocated, non-SSA form.
474</p>
475
476</div>
477
478<!-- ======================================================================= -->
479<div class="doc_subsection">
480 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
481</div>
482
483<div class="doc_text">
484
485<p>Target machine instructions are represented as instances of the
486<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]487representing machine instructions. In particular, it only keeps track of
488an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]489
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]490<p>The opcode number is a simple unsigned number that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]491specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]492the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]493are auto-generated from this description. The <tt>MachineInstr</tt> class does
494not have any information about how to interpret the instruction (i.e., what the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]495semantics of the instruction are): for that you must refer to the
496<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
497
498<p>The operands of a machine instruction can be of several different types:
499they can be a register reference, constant integer, basic block reference, etc.
500In addition, a machine operand should be marked as a def or a use of the value
501(though only registers are allowed to be defs).</p>
502
503<p>By convention, the LLVM code generator orders instruction operands so that
504all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]505that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]506instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
507and stores the result into the "%i3" register. In the LLVM code generator,
508the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
509first.</p>
510
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]511<p>Keeping destination (definition) operands at the beginning of the operand
512list has several advantages. In particular, the debugging printer will print
513the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]514
515<pre>
516 %r3 = add %i1, %i2
517</pre>
518
519<p>If the first operand is a def, and it is also easier to <a
520href="#buildmi">create instructions</a> whose only def is the first
521operand.</p>
522
523</div>
524
525<!-- _______________________________________________________________________ -->
526<div class="doc_subsubsection">
527 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
528</div>
529
530<div class="doc_text">
531
532<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
533located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
534<tt>BuildMI</tt> functions make it easy to build arbitrary machine
535instructions. Usage of the <tt>BuildMI</tt> functions look like this:
536</p>
537
538<pre>
539 // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
540 // instruction. The '1' specifies how many operands will be added.
541 MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
542
543 // Create the same instr, but insert it at the end of a basic block.
544 MachineBasicBlock &amp;MBB = ...
545 BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
546
547 // Create the same instr, but insert it before a specified iterator point.
548 MachineBasicBlock::iterator MBBI = ...
549 BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
550
551 // Create a 'cmp Reg, 0' instruction, no destination reg.
552 MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
553 // Create an 'sahf' instruction which takes no operands and stores nothing.
554 MI = BuildMI(X86::SAHF, 0);
555
556 // Create a self looping branch instruction.
557 BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
558</pre>
559
560<p>
561The key thing to remember with the <tt>BuildMI</tt> functions is that you have
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]562to specify the number of operands that the machine instruction will take. This
563allows for efficient memory allocation. You also need to specify if operands
564default to be uses of values, not definitions. If you need to add a definition
565operand (other than the optional destination register), you must explicitly
566mark it as such.
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]567</p>
568
569</div>
570
571<!-- _______________________________________________________________________ -->
572<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]573 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]574</div>
575
576<div class="doc_text">
577
578<p>One important issue that the code generator needs to be aware of is the
579presence of fixed registers. In particular, there are often places in the
580instruction stream where the register allocator <em>must</em> arrange for a
581particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]582limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]583with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
584conventions. In any case, the instruction selector should emit code that
585copies a virtual register into or out of a physical register when needed.</p>
586
587<p>For example, consider this simple LLVM example:</p>
588
589<pre>
590 int %test(int %X, int %Y) {
591 %Z = div int %X, %Y
592 ret int %Z
593 }
594</pre>
595
596<p>The X86 instruction selector produces this machine code for the div
597and ret (use
598"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
599
600<pre>
601 ;; Start of div
602 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
603 %reg1027 = sar %reg1024, 31
604 %EDX = mov %reg1027 ;; Sign extend X into EDX
605 idiv %reg1025 ;; Divide by Y (in reg1025)
606 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
607
608 ;; Start of ret
609 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
610 ret
611</pre>
612
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]613<p>By the end of code generation, the register allocator has coalesced
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]614the registers and deleted the resultant identity moves, producing the
615following code:</p>
616
617<pre>
618 ;; X is in EAX, Y is in ECX
619 mov %EAX, %EDX
620 sar %EDX, 31
621 idiv %ECX
622 ret
623</pre>
624
625<p>This approach is extremely general (if it can handle the X86 architecture,
626it can handle anything!) and allows all of the target specific
627knowledge about the instruction stream to be isolated in the instruction
628selector. Note that physical registers should have a short lifetime for good
629code generation, and all physical registers are assumed dead on entry and
630exit of basic blocks (before register allocation). Thus if you need a value
631to be live across basic block boundaries, it <em>must</em> live in a virtual
632register.</p>
633
634</div>
635
636<!-- _______________________________________________________________________ -->
637<div class="doc_subsubsection">
638 <a name="ssa">Machine code SSA form</a>
639</div>
640
641<div class="doc_text">
642
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]643<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]644are maintained in SSA-form until register allocation happens. For the most
645part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
646become machine code PHI nodes, and virtual registers are only allowed to have a
647single definition.</p>
648
649<p>After register allocation, machine code is no longer in SSA-form, as there
650are no virtual registers left in the code.</p>
651
652</div>
653
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]654<!-- ======================================================================= -->
655<div class="doc_subsection">
656 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
657</div>
658
659<div class="doc_text">
660
661<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
662(<a href="#machineinstr">MachineInstr</a> instances). It roughly corresponds to
663the LLVM code input to the instruction selector, but there can be a one-to-many
664mapping (i.e. one LLVM basic block can map to multiple machine basic blocks).
665The MachineBasicBlock class has a "<tt>getBasicBlock</tt>" method, which returns
666the LLVM basic block that it comes from.
667</p>
668
669</div>
670
671<!-- ======================================================================= -->
672<div class="doc_subsection">
673 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
674</div>
675
676<div class="doc_text">
677
678<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
679(<a href="#machinebasicblock">MachineBasicBlock</a> instances). It corresponds
680one-to-one with the LLVM function input to the instruction selector. In
681addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
682the MachineConstantPool, MachineFrameInfo, MachineFunctionInfo,
683SSARegMap, and a set of live in and live out registers for the function. See
684<tt>MachineFunction.h</tt> for more information.
685</p>
686
687</div>
688
689
690
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]691<!-- *********************************************************************** -->
692<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]693 <a name="codegenalgs">Target-independent code generation algorithms</a>
694</div>
695<!-- *********************************************************************** -->
696
697<div class="doc_text">
698
699<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]700href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]701explains how they work and some of the rationale behind their design.</p>
702
703</div>
704
705<!-- ======================================================================= -->
706<div class="doc_subsection">
707 <a name="instselect">Instruction Selection</a>
708</div>
709
710<div class="doc_text">
711<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]712Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]713code generator into target-specific machine instructions. There are several
714well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]715the SelectionDAG based instruction selector framework and an old-style 'simple'
716instruction selector (which effectively peephole selects each LLVM instruction
717into a series of machine instructions). We recommend that all targets use the
718SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]719</p>
720
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]721<p>Portions of the DAG instruction selector are generated from the target
722description files (<tt>*.td</tt>) files. Eventually, we aim for the entire
723instruction selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]724</div>
725
726<!-- _______________________________________________________________________ -->
727<div class="doc_subsubsection">
728 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
729</div>
730
731<div class="doc_text">
732
733<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]734The SelectionDAG provides an abstraction for code representation in a way that
735is amenable to instruction selection using automatic techniques
736(e.g. dynamic-programming based optimal pattern matching selectors), It is also
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]737well suited to other phases of code generation; in particular,
738instruction scheduling (SelectionDAG's are very close to scheduling DAGs
739post-selection). Additionally, the SelectionDAG provides a host representation
740where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]741<a href="#selectiondag_optimize">optimizations</a> may be
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]742performed: ones which require extensive information about the instructions
743efficiently supported by the target.
744</p>
745
746<p>
747The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]748<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]749operation code (Opcode) that indicates what operation the node performs and
750the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]751The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]752<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]753
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]754<p>Although most operations define a single value, each node in the graph may
755define multiple values. For example, a combined div/rem operation will define
756both the dividend and the remainder. Many other situations require multiple
757values as well. Each node also has some number of operands, which are edges
758to the node defining the used value. Because nodes may define multiple values,
759edges are represented by instances of the <tt>SDOperand</tt> class, which is
760a &lt;SDNode, unsigned&gt; pair, indicating the node and result
761value being used, respectively. Each value produced by an SDNode has an
762associated MVT::ValueType, indicating what type the value is.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]763</p>
764
765<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]766SelectionDAGs contain two different kinds of values: those that represent data
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]767flow and those that represent control flow dependencies. Data values are simple
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]768edges with an integer or floating point value type. Control edges are
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]769represented as "chain" edges which are of type MVT::Other. These edges provide
770an ordering between nodes that have side effects (such as
771loads/stores/calls/return/etc). All nodes that have side effects should take a
772token chain as input and produce a new one as output. By convention, token
773chain inputs are always operand #0, and chain results are always the last
774value produced by an operation.</p>
775
776<p>
777A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Chris Lattnere0c13172005-05-09 15:41:03 +0000[diff] [blame]778always a marker node with an Opcode of ISD::EntryToken. The Root node is the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]779final side-effecting node in the token chain. For example, in a single basic
780block function, this would be the return node.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]781</p>
782
783<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]784One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]785DAG. A legal DAG for a target is one that only uses supported operations and
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]786supported types. On a 32-bit PowerPC, for example, a DAG with any values of i1,
787i8, i16,
788or i64 type would be illegal, as would a DAG that uses a SREM or UREM operation.
789The <a href="#selectiondag_legalize">legalize</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]790phase is responsible for turning an illegal DAG into a legal DAG.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]791</p>
792</div>
793
794<!-- _______________________________________________________________________ -->
795<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]796 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]797</div>
798
799<div class="doc_text">
800
801<p>
802SelectionDAG-based instruction selection consists of the following steps:
803</p>
804
805<ol>
806<li><a href="#selectiondag_build">Build initial DAG</a> - This stage performs
807 a simple translation from the input LLVM code to an illegal SelectionDAG.
808 </li>
809<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
810 performs simple optimizations on the SelectionDAG to simplify it and
811 recognize meta instructions (like rotates and div/rem pairs) for
812 targets that support these meta operations. This makes the resultant code
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]813 more efficient and the 'select instructions from DAG' phase (below) simpler.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]814</li>
815<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
816 converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
817 unsupported operations and data types.</li>
818<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
819 second run of the SelectionDAG optimized the newly legalized DAG, to
820 eliminate inefficiencies introduced by legalization.</li>
821<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
822 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]823 instructions. This process translates the target-independent input DAG into
824 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]825<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]826 - The last phase assigns a linear order to the instructions in the
827 target-instruction DAG and emits them into the MachineFunction being
828 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]829</ol>
830
831<p>After all of these steps are complete, the SelectionDAG is destroyed and the
832rest of the code generation passes are run.</p>
833
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]834<p>One great way to visualize what is going on here is to take advantage of a
835few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
836option pops up a window with the SelectionDAG input to the Select phase for all
837of the code compiled (if you only get errors printed to the console while using
838this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
839your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
840views the SelectionDAG output from the Select phase and input to the Scheduler
841phase.
842</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]843</div>
844
845<!-- _______________________________________________________________________ -->
846<div class="doc_subsubsection">
847 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
848</div>
849
850<div class="doc_text">
851
852<p>
853The initial SelectionDAG is naively peephole expanded from the LLVM input by
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]854the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file. The
855intent of this pass is to expose as much low-level, target-specific details
856to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
857add turns into an SDNode add while a geteelementptr is expanded into the obvious
858arithmetic). This pass requires target-specific hooks to lower calls and
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]859returns, varargs, etc. For these features, the <a
860href="#targetlowering">TargetLowering</a> interface is
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]861used.
862</p>
863
864</div>
865
866<!-- _______________________________________________________________________ -->
867<div class="doc_subsubsection">
868 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
869</div>
870
871<div class="doc_text">
872
873<p>The Legalize phase is in charge of converting a DAG to only use the types and
874operations that are natively supported by the target. This involves two major
875tasks:</p>
876
877<ol>
878<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]879 <p>There are two main ways of doing this: converting small types to
880 larger types ("promoting"), and breaking up large integer types
881 into smaller ones ("expanding"). For example, a target might require
882 that all f32 values are promoted to f64 and that all i1/i8/i16 values
883 are promoted to i32. The same target might require that all i64 values
884 be expanded into i32 values. These changes can insert sign and zero
885 extensions as
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]886 needed to make sure that the final code has the same behavior as the
887 input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]888 <p>A target implementation tells the legalizer which types are supported
889 (and which register class to use for them) by calling the
890 "addRegisterClass" method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]891</li>
892
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]893<li><p>Eliminate operations that are not supported by the target.</p>
894 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]895 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]896 conditional moves and PowerPC does not support sign-extending loads from
897 a 16-bit memory location). Legalize takes care by open-coding
898 another sequence of operations to emulate the operation ("expansion"), by
899 promoting to a larger type that supports the operation
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]900 (promotion), or using a target-specific hook to implement the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]901 legalization (custom).</p>
902 <p>A target implementation tells the legalizer which operations are not
903 supported (and which of the above three actions to take) by calling the
904 "setOperationAction" method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]905</li>
906</ol>
907
908<p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]909Prior to the existance of the Legalize pass, we required that every
910target <a href="#selectiondag_optimize">selector</a> supported and handled every
911operator and type even if they are not natively supported. The introduction of
912the Legalize phase allows all of the
913cannonicalization patterns to be shared across targets, and makes it very
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]914easy to optimize the cannonicalized code because it is still in the form of
915a DAG.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]916</p>
917
918</div>
919
920<!-- _______________________________________________________________________ -->
921<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]922 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
923 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]924</div>
925
926<div class="doc_text">
927
928<p>
929The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]930immediately after the DAG is built and once after legalization. The first run
931of the pass allows the initial code to be cleaned up (e.g. performing
932optimizations that depend on knowing that the operators have restricted type
933inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]934Legalize pass, which allows Legalize to be very simple (it can focus on making
935code legal instead of focusing on generating <i>good</i> and legal code).
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]936</p>
937
938<p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]939One important class of optimizations performed is optimizing inserted sign and
940zero extension instructions. We currently use ad-hoc techniques, but could move
941to more rigorous techniques in the future. Here are some good
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]942papers on the subject:</p>
943
944<p>
945"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
946integer arithmetic</a>"<br>
947Kevin Redwine and Norman Ramsey<br>
948International Conference on Compiler Construction (CC) 2004
949</p>
950
951
952<p>
953 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
954 sign extension elimination</a>"<br>
955 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
956 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
957 and Implementation.
958</p>
959
960</div>
961
962<!-- _______________________________________________________________________ -->
963<div class="doc_subsubsection">
964 <a name="selectiondag_select">SelectionDAG Select Phase</a>
965</div>
966
967<div class="doc_text">
968
969<p>The Select phase is the bulk of the target-specific code for instruction
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]970selection. This phase takes a legal SelectionDAG as input,
971pattern matches the instructions supported by the target to this DAG, and
972produces a new DAG of target code. For example, consider the following LLVM
973fragment:</p>
974
975<pre>
976 %t1 = add float %W, %X
977 %t2 = mul float %t1, %Y
978 %t3 = add float %t2, %Z
979</pre>
980
981<p>This LLVM code corresponds to a SelectionDAG that looks basically like this:
982</p>
983
984<pre>
985 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
986</pre>
987
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame^]988<p>If a target supports floating pointer multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]989of the adds can be merged with the multiply. On the PowerPC, for example, the
990output of the instruction selector might look like this DAG:</p>
991
992<pre>
993 (FMADDS (FADDS W, X), Y, Z)
994</pre>
995
996<p>
997The FMADDS instruction is a ternary instruction that multiplies its first two
998operands and adds the third (as single-precision floating-point numbers). The
999FADDS instruction is a simple binary single-precision add instruction. To
1000perform this pattern match, the PowerPC backend includes the following
1001instruction definitions:
1002</p>
1003
1004<pre>
1005def FMADDS : AForm_1&lt;59, 29,
1006 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1007 "fmadds $FRT, $FRA, $FRC, $FRB",
1008 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1009 F4RC:$FRB))</b>]&gt;;
1010def FADDS : AForm_2&lt;59, 21,
1011 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1012 "fadds $FRT, $FRA, $FRB",
1013 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1014</pre>
1015
1016<p>The portion of the instruction definition in bold indicates the pattern used
1017to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1018are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1019"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1020
1021<p>The TableGen DAG instruction selector generator reads the instruction
1022patterns in the .td and automatically builds parts of the pattern matching code
1023for your target. It has the following strengths:</p>
1024
1025<ul>
1026<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame^]1027 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1028<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame^]1029 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1030 that is a 13-bit sign-extended value". For examples, see the
1031 <tt>immSExt16</tt> and related tblgen classes in the PowerPC backend.</li>
1032<li>It knows several important identities for the patterns defined. For
1033 example, it knows that addition is commutative, so it allows the
1034 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1035 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1036 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame^]1037<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1038 rarely have to explicitly tell the system what type parts of your patterns
1039 are. In the FMADDS case above, we didn't have to tell tblgen that all of
1040 the nodes in the pattern are of type 'f32'. It was able to infer and
1041 propagate this knowledge from the fact that F4RC has type 'f32'.</li>
1042<li>Targets can define their own (and rely on built-in) "pattern fragments".
1043 Pattern fragments are chunks of reusable patterns that get inlined into your
1044 patterns during compiler-compiler time. For example, the integer "(not x)"
1045 operation is actually defined as a pattern fragment that expands as
1046 "(xor x, -1)", since the SelectionDAG does not have a native 'not'
1047 operation. Targets can define their own short-hand fragments as they see
1048 fit. See the definition of 'not' and 'ineg' for examples.</li>
1049<li>In addition to instructions, targets can specify arbitrary patterns that
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame^]1050 map to one or more instructions, using the 'Pat' class. For example,
1051 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1052 register in one instruction. To tell tblgen how to do this, it defines:
1053
1054 <pre>
1055 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1056 def : Pat&lt;(i32 imm:$imm),
1057 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
1058 </pre>
1059
1060 If none of the single-instruction patterns for loading an immediate into a
1061 register match, this will be used. This rule says "match an arbitrary i32
1062 immediate, turning it into an ORI ('or a 16-bit immediate') and an LIS
1063 ('load 16-bit immediate, where the immediate is shifted to the left 16
1064 bits') instruction". To make this work, the LO16/HI16 node transformations
1065 are used to manipulate the input immediate (in this case, take the high or
1066 low 16-bits of the immediate).
1067 </li>
1068<li>While the system does automate a lot, it still allows you to write custom
1069 C++ code to match special cases, in case there is something that is hard
1070 to express.</li>
1071</ul>
1072
1073<p>
1074While it has many strengths, the system currently has some limitations,
1075primarily because it is a work in progress and is not yet finished:
1076</p>
1077
1078<ul>
1079<li>Overall, there is no way to define or match SelectionDAG nodes that define
1080 multiple values (e.g. ADD_PARTS, LOAD, CALL, etc). This is the biggest
1081 reason that you currently still <i>have to</i> write custom C++ code for
1082 your instruction selector.</li>
1083<li>There is no great way to support match complex addressing modes yet. In the
1084 future, we will extend pattern fragments to allow them to define multiple
1085 values (e.g. the four operands of the <a href="#x86_memory">X86 addressing
1086 mode</a>). In addition, we'll extend fragments so that a fragment can match
1087 multiple different patterns.</li>
1088<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1089<li>We don't automatically generate the set of supported registers and
1090 operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
1091<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame^]1092</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1093
1094<p>Despite these limitations, the instruction selector generator is still quite
1095useful for most of the binary and logical operations in typical instruction
1096sets. If you run into any problems or can't figure out how to do something,
1097please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1098
1099</div>
1100
1101<!-- _______________________________________________________________________ -->
1102<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1103 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1104</div>
1105
1106<div class="doc_text">
1107
1108<p>The scheduling phase takes the DAG of target instructions from the selection
1109phase and assigns an order. The scheduler can pick an order depending on
1110various constraints of the machines (i.e. order for minimal register pressure or
1111try to cover instruction latencies). Once an order is established, the DAG is
1112converted to a list of <a href="#machineinstr">MachineInstr</a>s and the
1113Selection DAG is destroyed.
1114</p>
1115
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1116<p>Note that this phase is logically seperate from the instruction selection
1117phase, but is tied to it closely in the code because it operates on
1118SelectionDAGs.</p>
1119
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1120</div>
1121
1122<!-- _______________________________________________________________________ -->
1123<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1124 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1125</div>
1126
1127<div class="doc_text">
1128
1129<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1130<li>Optional function-at-a-time selection.</li>
1131<li>Auto-generate entire selector from .td file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1132</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1133</ol>
1134
1135</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1136
1137<!-- ======================================================================= -->
1138<div class="doc_subsection">
1139 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1140</div>
1141<div class="doc_text"><p>To Be Written</p></div>
1142<!-- ======================================================================= -->
1143<div class="doc_subsection">
1144 <a name="regalloc">Register Allocation</a>
1145</div>
1146<div class="doc_text"><p>To Be Written</p></div>
1147<!-- ======================================================================= -->
1148<div class="doc_subsection">
1149 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1150</div>
1151<div class="doc_text"><p>To Be Written</p></div>
1152<!-- ======================================================================= -->
1153<div class="doc_subsection">
1154 <a name="latemco">Late Machine Code Optimizations</a>
1155</div>
1156<div class="doc_text"><p>To Be Written</p></div>
1157<!-- ======================================================================= -->
1158<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1159 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1160</div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1161
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1162
1163<!-- _______________________________________________________________________ -->
1164<div class="doc_subsubsection">
1165 <a name="codeemit_asm">Generating Assembly Code</a>
1166</div>
1167
1168<div class="doc_text">
1169
1170</div>
1171
1172
1173<!-- _______________________________________________________________________ -->
1174<div class="doc_subsubsection">
1175 <a name="codeemit_bin">Generating Binary Machine Code</a>
1176</div>
1177
1178<div class="doc_text">
1179 <p>For the JIT or .o file writer</p>
1180</div>
1181
1182
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1183<!-- *********************************************************************** -->
1184<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1185 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1186</div>
1187<!-- *********************************************************************** -->
1188
1189<div class="doc_text">
1190
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1191<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1192are specific to the code generator for a particular target.</p>
1193
1194</div>
1195
1196
1197<!-- ======================================================================= -->
1198<div class="doc_subsection">
1199 <a name="x86">The X86 backend</a>
1200</div>
1201
1202<div class="doc_text">
1203
1204<p>
1205The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
1206code generator currently targets a generic P6-like processor. As such, it
1207produces a few P6-and-above instructions (like conditional moves), but it does
1208not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1209will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1210implementations.</p>
1211
1212</div>
1213
1214<!-- _______________________________________________________________________ -->
1215<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1216 <a name="x86_tt">X86 Target Triples Supported</a>
1217</div>
1218
1219<div class="doc_text">
1220<p>
1221The following are the known target triples that are supported by the X86
1222backend. This is not an exhaustive list, but it would be useful to add those
1223that people test.
1224</p>
1225
1226<ul>
1227<li><b>i686-pc-linux-gnu</b> - Linux</li>
1228<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1229<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1230<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1231<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1232</ul>
1233
1234</div>
1235
1236<!-- _______________________________________________________________________ -->
1237<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1238 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1239</div>
1240
1241<div class="doc_text">
1242
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1243<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1244forming memory addresses of the following expression directly in integer
1245instructions (which use ModR/M addressing):</p>
1246
1247<pre>
1248 Base+[1,2,4,8]*IndexReg+Disp32
1249</pre>
1250
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1251<p>In order to represent this, LLVM tracks no less than 4 operands for each
1252memory operand of this form. This means that the "load" form of 'mov' has the
1253following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1254
1255<pre>
1256Index: 0 | 1 2 3 4
1257Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1258OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1259</pre>
1260
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1261<p>Stores, and all other instructions, treat the four memory operands in the
1262same way, in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1263
1264</div>
1265
1266<!-- _______________________________________________________________________ -->
1267<div class="doc_subsubsection">
1268 <a name="x86_names">Instruction naming</a>
1269</div>
1270
1271<div class="doc_text">
1272
1273<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1274An instruction name consists of the base name, a default operand size, and a
1275a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1276
1277<p>
1278<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1279<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1280<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1281<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1282</p>
1283
1284</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1285
1286<!-- *********************************************************************** -->
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1294 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
1295 <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
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