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3<html>
4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame^]61 <ul>
62 <li><a href="#regalloc">Register Allocation</a>
63 <ul>
64 <li><a href="#regAlloc_represent">How registers are represented in
65 LLVM</a></li>
66 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
67 registers</a></li>
68 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
69 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
70 <li><a href="#regAlloc_fold">Instruction folding</a></li>
71 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
72 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]73 <li><a href="#codeemit">Code Emission</a>
74 <ul>
75 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
76 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
77 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]78 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]79 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]80 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]81 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]82 <li><a href="#x86">The X86 backend</a></li>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]83 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84 </li>
85
86</ol>
87
88<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame^]89 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
90 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>, and
91 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
92 Pereira</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]93</div>
94
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]95<div class="doc_warning">
96 <p>Warning: This is a work in progress.</p>
97</div>
98
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]99<!-- *********************************************************************** -->
100<div class="doc_section">
101 <a name="introduction">Introduction</a>
102</div>
103<!-- *********************************************************************** -->
104
105<div class="doc_text">
106
107<p>The LLVM target-independent code generator is a framework that provides a
108suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]109the machine code for a specified target&mdash;either in assembly form (suitable
110for a static compiler) or in binary machine code format (usable for a JIT
111compiler). The LLVM target-independent code generator consists of five main
112components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]113
114<ol>
115<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]116capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]117of how they will be used. These interfaces are defined in
118<tt>include/llvm/Target/</tt>.</li>
119
120<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]121generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]122represent the machine code for <i>any</i> target machine. These classes are
123defined in <tt>include/llvm/CodeGen/</tt>.</li>
124
125<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
126various phases of native code generation (register allocation, scheduling, stack
127frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
128
129<li><a href="#targetimpls">Implementations of the abstract target description
130interfaces</a> for particular targets. These machine descriptions make use of
131the components provided by LLVM, and can optionally provide custom
132target-specific passes, to build complete code generators for a specific target.
133Target descriptions live in <tt>lib/Target/</tt>.</li>
134
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]135<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
136completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
137interface for target-specific issues. The code for the target-independent
138JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
139
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]140</ol>
141
142<p>
143Depending on which part of the code generator you are interested in working on,
144different pieces of this will be useful to you. In any case, you should be
145familiar with the <a href="#targetdesc">target description</a> and <a
146href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]147a backend for a new target, you will need to <a href="#targetimpls">implement the
148target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]149href="LangRef.html">LLVM code representation</a>. If you are interested in
150implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
151should only depend on the target-description and machine code representation
152classes, ensuring that it is portable.
153</p>
154
155</div>
156
157<!-- ======================================================================= -->
158<div class="doc_subsection">
159 <a name="required">Required components in the code generator</a>
160</div>
161
162<div class="doc_text">
163
164<p>The two pieces of the LLVM code generator are the high-level interface to the
165code generator and the set of reusable components that can be used to build
166target-specific backends. The two most important interfaces (<a
167href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]168href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]169required to be defined for a backend to fit into the LLVM system, but the others
170must be defined if the reusable code generator components are going to be
171used.</p>
172
173<p>This design has two important implications. The first is that LLVM can
174support completely non-traditional code generation targets. For example, the C
175backend does not require register allocation, instruction selection, or any of
176the other standard components provided by the system. As such, it only
177implements these two interfaces, and does its own thing. Another example of a
178code generator like this is a (purely hypothetical) backend that converts LLVM
179to the GCC RTL form and uses GCC to emit machine code for a target.</p>
180
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]181<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]182implement radically different code generators in the LLVM system that do not
183make use of any of the built-in components. Doing so is not recommended at all,
184but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]185LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]186
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]187</div>
188
189<!-- ======================================================================= -->
190<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]191 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]192</div>
193
194<div class="doc_text">
195
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]196<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]197quality code generation for standard register-based microprocessors. Code
198generation in this model is divided into the following stages:</p>
199
200<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]201<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
202determines an efficient way to express the input LLVM code in the target
203instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]204This stage produces the initial code for the program in the target instruction
205set, then makes use of virtual registers in SSA form and physical registers that
206represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]207conventions. This step turns the LLVM code into a DAG of target
208instructions.</li>
209
210<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
211phase takes the DAG of target instructions produced by the instruction selection
212phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]213as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
214that we describe this in the <a href="#instselect">instruction selection
215section</a> because it operates on a <a
216href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]217</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]218
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]219<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
220optional stage consists of a series of machine-code optimizations that
221operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]222like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]223</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]224
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]225<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]226target code is transformed from an infinite virtual register file in SSA form
227to the concrete register file used by the target. This phase introduces spill
228code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]229
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]230<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]231machine code has been generated for the function and the amount of stack space
232required is known (used for LLVM alloca's and spill slots), the prolog and
233epilog code for the function can be inserted and "abstract stack location
234references" can be eliminated. This stage is responsible for implementing
235optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]236
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]237<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]238that operate on "final" machine code can go here, such as spill code scheduling
239and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]240
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]241<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]242puts out the code for the current function, either in the target assembler
243format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]244
245</ol>
246
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]247<p>The code generator is based on the assumption that the instruction selector
248will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]249native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]250expansion and aggressive iterative peephole optimization are much slower. This
251design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]252aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]253components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]254compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]255
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]256<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]257target-specific passes into the flow. For example, the X86 target uses a
258special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]259targets with unusual requirements can be supported with custom passes as
260needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]261
262</div>
263
264
265<!-- ======================================================================= -->
266<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]267 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]268</div>
269
270<div class="doc_text">
271
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]272<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]273architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]274information (e.g., an <tt>add</tt> instruction is almost identical to a
275<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]276In order to allow the maximum amount of commonality to be factored out, the LLVM
277code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]278describe big chunks of the target machine, which allows the use of
279domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]280repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]281
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]282<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]283of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]284number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]285LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]286surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]287can get something working. Second, it makes it easier to change things. In
288particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
289only need a change in one place (<tt>tblgen</tt>) to update all of the targets
290to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]291
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]292</div>
293
294<!-- *********************************************************************** -->
295<div class="doc_section">
296 <a name="targetdesc">Target description classes</a>
297</div>
298<!-- *********************************************************************** -->
299
300<div class="doc_text">
301
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]302<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]303<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]304target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]305designed to capture the <i>abstract</i> properties of the target (such as the
306instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]307of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]308
309<p>All of the target description classes (except the <tt><a
310href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
311the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]312get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]313href="#targetmachine">TargetMachine</a></tt> class provides accessors that
314should be implemented by the target.</p>
315
316</div>
317
318<!-- ======================================================================= -->
319<div class="doc_subsection">
320 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
321</div>
322
323<div class="doc_text">
324
325<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
326access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]327classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
328<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
329designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]330a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
331implements the various virtual methods. The only required target description
332class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
333code generator components are to be used, the other interfaces should be
334implemented as well.</p>
335
336</div>
337
338
339<!-- ======================================================================= -->
340<div class="doc_subsection">
341 <a name="targetdata">The <tt>TargetData</tt> class</a>
342</div>
343
344<div class="doc_text">
345
346<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]347and it is the only class that is not extensible (you cannot derived a new
348class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]349lays out memory for structures, the alignment requirements for various data
350types, the size of pointers in the target, and whether the target is
351little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]352
353</div>
354
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]355<!-- ======================================================================= -->
356<div class="doc_subsection">
357 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
358</div>
359
360<div class="doc_text">
361
362<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
363selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]364operations. Among other things, this class indicates:</p>
365
366<ul>
367 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]368 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]369 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]370 <li>the type to use for shift amounts</li>
371 <li>various high-level characteristics, like whether it is profitable to turn
372 division by a constant into a multiplication sequence</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]373</ol>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]374
375</div>
376
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]377<!-- ======================================================================= -->
378<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]379 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]380</div>
381
382<div class="doc_text">
383
384<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
385<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
386target and any interactions between the registers.</p>
387
388<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]389unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]390description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]391large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]392
393<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]394<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
395register (used for assembly output and debugging dumps) and a set of aliases
396(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]397</p>
398
399<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
400exposes a set of processor specific register classes (instances of the
401<tt>TargetRegisterClass</tt> class). Each register class contains sets of
402registers that have the same properties (for example, they are all 32-bit
403integer registers). Each SSA virtual register created by the instruction
404selector has an associated register class. When the register allocator runs, it
405replaces virtual registers with a physical register in the set.</p>
406
407<p>
408The target-specific implementations of these classes is auto-generated from a <a
409href="TableGenFundamentals.html">TableGen</a> description of the register file.
410</p>
411
412</div>
413
414<!-- ======================================================================= -->
415<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]416 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]417</div>
418
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]419<div class="doc_text">
420 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
421 instructions supported by the target. It is essentially an array of
422 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
423 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]424 for the opcode, the number of operands, the list of implicit register uses
425 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]426 (accesses memory, is commutable, etc), and holds any target-specific
427 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]428</div>
429
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]430<!-- ======================================================================= -->
431<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]432 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]433</div>
434
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]435<div class="doc_text">
436 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
437 stack frame layout of the target. It holds the direction of stack growth,
438 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]439 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]440 pointer on function entry to the first location where function data (local
441 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]442</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]443
444<!-- ======================================================================= -->
445<div class="doc_subsection">
446 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
447</div>
448
449<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]450 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
451 specific chip set being targeted. A sub-target informs code generation of
452 which instructions are supported, instruction latencies and instruction
453 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]454 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]455</div>
456
457
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]458<!-- ======================================================================= -->
459<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]460 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]461</div>
462
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]463<div class="doc_text">
464 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
465 Just-In-Time code generator to perform target-specific activities, such as
466 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
467 should provide one of these objects through the <tt>getJITInfo</tt>
468 method.</p>
469</div>
470
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]471<!-- *********************************************************************** -->
472<div class="doc_section">
473 <a name="codegendesc">Machine code description classes</a>
474</div>
475<!-- *********************************************************************** -->
476
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]477<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]478
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]479<p>At the high-level, LLVM code is translated to a machine specific
480representation formed out of
481<a href="#machinefunction"><tt>MachineFunction</tt></a>,
482<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]483href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]484(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
485target agnostic, representing instructions in their most abstract form: an
486opcode and a series of operands. This representation is designed to support
487both an SSA representation for machine code, as well as a register allocated,
488non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]489
490</div>
491
492<!-- ======================================================================= -->
493<div class="doc_subsection">
494 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
495</div>
496
497<div class="doc_text">
498
499<p>Target machine instructions are represented as instances of the
500<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]501representing machine instructions. In particular, it only keeps track of
502an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]503
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]504<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]505specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]506the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]507are auto-generated from this description. The <tt>MachineInstr</tt> class does
508not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]509semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]510<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
511
512<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]513a register reference, a constant integer, a basic block reference, etc. In
514addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]515(though only registers are allowed to be defs).</p>
516
517<p>By convention, the LLVM code generator orders instruction operands so that
518all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]519that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]520instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
521and stores the result into the "%i3" register. In the LLVM code generator,
522the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
523first.</p>
524
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]525<p>Keeping destination (definition) operands at the beginning of the operand
526list has several advantages. In particular, the debugging printer will print
527the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]528
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]529<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]530<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]531%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]532</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]533</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]534
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]535<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]536href="#buildmi">create instructions</a> whose only def is the first
537operand.</p>
538
539</div>
540
541<!-- _______________________________________________________________________ -->
542<div class="doc_subsubsection">
543 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
544</div>
545
546<div class="doc_text">
547
548<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
549located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
550<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]551instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]552
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]553<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]554<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]555// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
556// instruction. The '1' specifies how many operands will be added.
557MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]558
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]559// Create the same instr, but insert it at the end of a basic block.
560MachineBasicBlock &amp;MBB = ...
561BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]562
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]563// Create the same instr, but insert it before a specified iterator point.
564MachineBasicBlock::iterator MBBI = ...
565BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]566
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]567// Create a 'cmp Reg, 0' instruction, no destination reg.
568MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
569// Create an 'sahf' instruction which takes no operands and stores nothing.
570MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]571
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]572// Create a self looping branch instruction.
573BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]574</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]575</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]576
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]577<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
578have to specify the number of operands that the machine instruction will take.
579This allows for efficient memory allocation. You also need to specify if
580operands default to be uses of values, not definitions. If you need to add a
581definition operand (other than the optional destination register), you must
582explicitly mark it as such:</p>
583
584<div class="doc_code">
585<pre>
586MI.addReg(Reg, MachineOperand::Def);
587</pre>
588</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]589
590</div>
591
592<!-- _______________________________________________________________________ -->
593<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]594 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]595</div>
596
597<div class="doc_text">
598
599<p>One important issue that the code generator needs to be aware of is the
600presence of fixed registers. In particular, there are often places in the
601instruction stream where the register allocator <em>must</em> arrange for a
602particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]603limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]604with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
605conventions. In any case, the instruction selector should emit code that
606copies a virtual register into or out of a physical register when needed.</p>
607
608<p>For example, consider this simple LLVM example:</p>
609
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]610<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]611<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]612int %test(int %X, int %Y) {
613 %Z = div int %X, %Y
614 ret int %Z
615}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]616</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]617</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]618
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]619<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
620and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]621"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
622
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]623<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]624<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]625;; Start of div
626%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
627%reg1027 = sar %reg1024, 31
628%EDX = mov %reg1027 ;; Sign extend X into EDX
629idiv %reg1025 ;; Divide by Y (in reg1025)
630%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]631
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]632;; Start of ret
633%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
634ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]635</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]636</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]637
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]638<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]639the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]640following code:</p>
641
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]642<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]643<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]644;; X is in EAX, Y is in ECX
645mov %EAX, %EDX
646sar %EDX, 31
647idiv %ECX
648ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]649</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]650</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]651
652<p>This approach is extremely general (if it can handle the X86 architecture,
653it can handle anything!) and allows all of the target specific
654knowledge about the instruction stream to be isolated in the instruction
655selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]656code generation, and all physical registers are assumed dead on entry to and
657exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]658to be live across basic block boundaries, it <em>must</em> live in a virtual
659register.</p>
660
661</div>
662
663<!-- _______________________________________________________________________ -->
664<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]665 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]666</div>
667
668<div class="doc_text">
669
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]670<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]671are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]672part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]673become machine code PHI nodes, and virtual registers are only allowed to have a
674single definition.</p>
675
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]676<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]677are no virtual registers left in the code.</p>
678
679</div>
680
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]681<!-- ======================================================================= -->
682<div class="doc_subsection">
683 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
684</div>
685
686<div class="doc_text">
687
688<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]689(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
690corresponds to the LLVM code input to the instruction selector, but there can be
691a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
692basic blocks). The <tt>MachineBasicBlock</tt> class has a
693"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
694comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]695
696</div>
697
698<!-- ======================================================================= -->
699<div class="doc_subsection">
700 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
701</div>
702
703<div class="doc_text">
704
705<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]706(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
707corresponds one-to-one with the LLVM function input to the instruction selector.
708In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
709a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
710<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
711live out registers for the function. See
712<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]713
714</div>
715
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]716<!-- *********************************************************************** -->
717<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]718 <a name="codegenalgs">Target-independent code generation algorithms</a>
719</div>
720<!-- *********************************************************************** -->
721
722<div class="doc_text">
723
724<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]725href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]726explains how they work and some of the rationale behind their design.</p>
727
728</div>
729
730<!-- ======================================================================= -->
731<div class="doc_subsection">
732 <a name="instselect">Instruction Selection</a>
733</div>
734
735<div class="doc_text">
736<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]737Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]738code generator into target-specific machine instructions. There are several
739well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]740the SelectionDAG based instruction selector framework and an old-style 'simple'
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]741instruction selector, which effectively peephole selects each LLVM instruction
742into a series of machine instructions. We recommend that all targets use the
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]743SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]744</p>
745
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]746<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]747description (<tt>*.td</tt>) files. Our goal is for the entire instruction
748selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]749</div>
750
751<!-- _______________________________________________________________________ -->
752<div class="doc_subsubsection">
753 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
754</div>
755
756<div class="doc_text">
757
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]758<p>The SelectionDAG provides an abstraction for code representation in a way
759that is amenable to instruction selection using automatic techniques
760(e.g. dynamic-programming based optimal pattern matching selectors). It is also
761well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]762instruction scheduling (SelectionDAG's are very close to scheduling DAGs
763post-selection). Additionally, the SelectionDAG provides a host representation
764where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]765<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]766performed; ones which require extensive information about the instructions
767efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]768
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]769<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]770<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]771operation code (Opcode) that indicates what operation the node performs and
772the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]773The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]774<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]775
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]776<p>Although most operations define a single value, each node in the graph may
777define multiple values. For example, a combined div/rem operation will define
778both the dividend and the remainder. Many other situations require multiple
779values as well. Each node also has some number of operands, which are edges
780to the node defining the used value. Because nodes may define multiple values,
781edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]782a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
783value being used, respectively. Each value produced by an <tt>SDNode</tt> has
784an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]785
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]786<p>SelectionDAGs contain two different kinds of values: those that represent
787data flow and those that represent control flow dependencies. Data values are
788simple edges with an integer or floating point value type. Control edges are
789represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
790provide an ordering between nodes that have side effects (such as
791loads, stores, calls, returns, etc). All nodes that have side effects should
792take a token chain as input and produce a new one as output. By convention,
793token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]794value produced by an operation.</p>
795
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]796<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
797always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
798is the final side-effecting node in the token chain. For example, in a single
799basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]800
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]801<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
802"illegal" DAG. A legal DAG for a target is one that only uses supported
803operations and supported types. On a 32-bit PowerPC, for example, a DAG with
804a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
805SREM or UREM operation. The
806<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
807an illegal DAG into a legal DAG.</p>
808
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]809</div>
810
811<!-- _______________________________________________________________________ -->
812<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]813 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]814</div>
815
816<div class="doc_text">
817
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]818<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]819
820<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]821<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
822 performs a simple translation from the input LLVM code to an illegal
823 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]824<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]825 performs simple optimizations on the SelectionDAG to simplify it, and
826 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
827 pairs) for targets that support these meta operations. This makes the
828 resultant code more efficient and the <a href="#selectiondag_select">select
829 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]830<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]831 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]832 unsupported operations and data types.</li>
833<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]834 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]835 eliminate inefficiencies introduced by legalization.</li>
836<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
837 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]838 instructions. This process translates the target-independent input DAG into
839 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]840<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]841 - The last phase assigns a linear order to the instructions in the
842 target-instruction DAG and emits them into the MachineFunction being
843 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]844</ol>
845
846<p>After all of these steps are complete, the SelectionDAG is destroyed and the
847rest of the code generation passes are run.</p>
848
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]849<p>One great way to visualize what is going on here is to take advantage of a
850few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
851option pops up a window with the SelectionDAG input to the Select phase for all
852of the code compiled (if you only get errors printed to the console while using
853this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
854your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
855views the SelectionDAG output from the Select phase and input to the Scheduler
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]856phase.</p>
857
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]858</div>
859
860<!-- _______________________________________________________________________ -->
861<div class="doc_subsubsection">
862 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
863</div>
864
865<div class="doc_text">
866
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]867<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
868input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]869<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
870pass is to expose as much low-level, target-specific details to the SelectionDAG
871as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
872into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
873obvious arithmetic). This pass requires target-specific hooks to lower calls,
874returns, varargs, etc. For these features, the
875<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]876
877</div>
878
879<!-- _______________________________________________________________________ -->
880<div class="doc_subsubsection">
881 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
882</div>
883
884<div class="doc_text">
885
886<p>The Legalize phase is in charge of converting a DAG to only use the types and
887operations that are natively supported by the target. This involves two major
888tasks:</p>
889
890<ol>
891<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]892 <p>There are two main ways of doing this: converting small types to
893 larger types ("promoting"), and breaking up large integer types
894 into smaller ones ("expanding"). For example, a target might require
895 that all f32 values are promoted to f64 and that all i1/i8/i16 values
896 are promoted to i32. The same target might require that all i64 values
897 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]898 extensions as needed to make sure that the final code has the same
899 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]900 <p>A target implementation tells the legalizer which types are supported
901 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]902 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]903</li>
904
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]905<li><p>Eliminate operations that are not supported by the target.</p>
906 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]907 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]908 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]909 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]910 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]911 promoting one type to a larger type that supports the operation
912 ("promotion"), or by using a target-specific hook to implement the
913 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]914 <p>A target implementation tells the legalizer which operations are not
915 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]916 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
917 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]918</li>
919</ol>
920
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]921<p>Prior to the existance of the Legalize pass, we required that every target
922<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]923operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]924the Legalize phase allows all of the cannonicalization patterns to be shared
925across targets, and makes it very easy to optimize the cannonicalized code
926because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]927
928</div>
929
930<!-- _______________________________________________________________________ -->
931<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]932 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
933 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]934</div>
935
936<div class="doc_text">
937
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]938<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]939immediately after the DAG is built and once after legalization. The first run
940of the pass allows the initial code to be cleaned up (e.g. performing
941optimizations that depend on knowing that the operators have restricted type
942inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]943Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]944code legal instead of focusing on generating <em>good</em> and legal code).</p>
945
946<p>One important class of optimizations performed is optimizing inserted sign
947and zero extension instructions. We currently use ad-hoc techniques, but could
948move to more rigorous techniques in the future. Here are some good papers on
949the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]950
951<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]952 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
953 integer arithmetic</a>"<br>
954 Kevin Redwine and Norman Ramsey<br>
955 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]956</p>
957
958
959<p>
960 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
961 sign extension elimination</a>"<br>
962 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
963 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
964 and Implementation.
965</p>
966
967</div>
968
969<!-- _______________________________________________________________________ -->
970<div class="doc_subsubsection">
971 <a name="selectiondag_select">SelectionDAG Select Phase</a>
972</div>
973
974<div class="doc_text">
975
976<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]977selection. This phase takes a legal SelectionDAG as input, pattern matches the
978instructions supported by the target to this DAG, and produces a new DAG of
979target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]980
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]981<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]982<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]983%t1 = add float %W, %X
984%t2 = mul float %t1, %Y
985%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]986</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]987</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]988
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]989<p>This LLVM code corresponds to a SelectionDAG that looks basically like
990this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]991
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]992<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]993<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]994(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]995</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]996</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]997
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]998<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]999of the adds can be merged with the multiply. On the PowerPC, for example, the
1000output of the instruction selector might look like this DAG:</p>
1001
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1002<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1003<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1004(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1005</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1006</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1007
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1008<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1009first two operands and adds the third (as single-precision floating-point
1010numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1011add instruction. To perform this pattern match, the PowerPC backend includes
1012the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1013
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1014<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1015<pre>
1016def FMADDS : AForm_1&lt;59, 29,
1017 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1018 "fmadds $FRT, $FRA, $FRC, $FRB",
1019 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1020 F4RC:$FRB))</b>]&gt;;
1021def FADDS : AForm_2&lt;59, 21,
1022 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1023 "fadds $FRT, $FRA, $FRB",
1024 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1025</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1026</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1027
1028<p>The portion of the instruction definition in bold indicates the pattern used
1029to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1030are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1031"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1032
1033<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1034patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1035matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1036
1037<ul>
1038<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1039 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1040<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1041 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1042 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1043 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1044 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1045<li>It knows several important identities for the patterns defined. For
1046 example, it knows that addition is commutative, so it allows the
1047 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1048 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1049 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1050<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1051 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1052 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1053 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1054 was able to infer and propagate this knowledge from the fact that
1055 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1056<li>Targets can define their own (and rely on built-in) "pattern fragments".
1057 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1058 patterns during compiler-compiler time. For example, the integer
1059 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1060 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1061 native '<tt>not</tt>' operation. Targets can define their own short-hand
1062 fragments as they see fit. See the definition of '<tt>not</tt>' and
1063 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1064<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1065 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1066 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1067 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1068 <br>
1069 <br>
1070 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1071 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1072// Arbitrary immediate support. Implement in terms of LIS/ORI.
1073def : Pat&lt;(i32 imm:$imm),
1074 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1075 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1076 </div>
1077 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1078 If none of the single-instruction patterns for loading an immediate into a
1079 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1080 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1081 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1082 left 16 bits') instruction". To make this work, the
1083 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1084 input immediate (in this case, take the high or low 16-bits of the
1085 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1086<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1087 C++ code to match special cases if there is something that is hard to
1088 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1089</ul>
1090
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1091<p>While it has many strengths, the system currently has some limitations,
1092primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1093
1094<ul>
1095<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1096 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1097 etc). This is the biggest reason that you currently still <em>have to</em>
1098 write custom C++ code for your instruction selector.</li>
1099<li>There is no great way to support matching complex addressing modes yet. In
1100 the future, we will extend pattern fragments to allow them to define
1101 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1102 addressing mode</a>). In addition, we'll extend fragments so that a
1103 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1104<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1105<li>We don't automatically generate the set of supported registers and
1106 operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
1107<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1108</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1109
1110<p>Despite these limitations, the instruction selector generator is still quite
1111useful for most of the binary and logical operations in typical instruction
1112sets. If you run into any problems or can't figure out how to do something,
1113please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1114
1115</div>
1116
1117<!-- _______________________________________________________________________ -->
1118<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1119 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1120</div>
1121
1122<div class="doc_text">
1123
1124<p>The scheduling phase takes the DAG of target instructions from the selection
1125phase and assigns an order. The scheduler can pick an order depending on
1126various constraints of the machines (i.e. order for minimal register pressure or
1127try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1128converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1129the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1130
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1131<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1132phase, but is tied to it closely in the code because it operates on
1133SelectionDAGs.</p>
1134
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1135</div>
1136
1137<!-- _______________________________________________________________________ -->
1138<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1139 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1140</div>
1141
1142<div class="doc_text">
1143
1144<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1145<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1146<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1147</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1148</ol>
1149
1150</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1151
1152<!-- ======================================================================= -->
1153<div class="doc_subsection">
1154 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1155</div>
1156<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame^]1157
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1158<!-- ======================================================================= -->
1159<div class="doc_subsection">
1160 <a name="regalloc">Register Allocation</a>
1161</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame^]1162
1163<div class="doc_text">
1164
1165<p>The <i>Register Allocation problem</i> consists in mapping a
1166program <i>P<sub>v</sub></i>, that can use an unbounded number of
1167virtual registers, to a program <i>P<sub>p</sub></i> that contains a
1168finite (possibly small) number of physical registers. Each target
1169architecture has a different number of physical registers. If the
1170number of physical registers is not enough to accommodate all the
1171virtual registers, some of them will have to be mapped into
1172memory. These virtuals are called <i>spilled virtuals</i>.</p>
1173
1174</div>
1175
1176<!-- _______________________________________________________________________ -->
1177
1178<div class="doc_subsubsection">
1179 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1180</div>
1181
1182<div class="doc_text">
1183
1184<p>In LLVM, physical registers are denoted by integer numbers that
1185normally range from 1 to 1023. To see how this numbering is defined
1186for a particular architecture, you can read the
1187<tt>GenRegisterNames.inc</tt> file for that architecture. For
1188instance, by inspecting
1189<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1190register <tt>EAX</tt> is denoted by 15, and the MMX register
1191<tt>MM0</tt> is mapped to 48.</p>
1192
1193<p>Some architectures contain registers that share the same physical
1194location. A notable example is the X86 platform. For instance, in the
1195X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1196<tt>AL</tt> share the first eight bits. These physical registers are
1197marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1198can check which registers are aliased by inspecting its
1199<tt>RegisterInfo.td</tt> file. Moreover, the method
1200<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1201all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1202
1203<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1204Elements in the same register class are functionally equivalent, and can
1205be interchangeably used. Each virtual register can only be mapped to
1206physical registers of a particular class. For instance, in the X86
1207architecture, some virtuals can only be allocated to 8 bit registers.
1208A register class is described by <tt>TargetRegisterClass</tt> objects.
1209To discover if a virtual register is compatible with a given physical,
1210this code can be used:
1211</p>
1212
1213<div class="doc_code">
1214<pre>
1215bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1216 unsigned v_reg,
1217 unsigned p_reg) {
1218 assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
1219 "Target register must be physical");
1220 const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
1221 return trc->contains(p_reg);
1222}
1223</pre>
1224</div>
1225
1226<p>Sometimes, mostly for debugging purposes, it is useful to change
1227the number of physical registers available in the target
1228architecture. This must be done statically, inside the
1229<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1230<tt>RegisterClass</tt>, the last parameter of which is a list of
1231registers. Just commenting some out is one simple way to avoid them
1232being used. A more polite way is to explicitly exclude some registers
1233from the <i>allocation order</i>. See the definition of the
1234<tt>GR</tt> register class in
1235<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1236(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1237
1238<p>Virtual registers are also denoted by integer numbers. Contrary to
1239physical registers, different virtual registers never share the same
1240number. The smallest virtual register is normally assigned the number
12411024. This may change, so, in order to know which is the first virtual
1242register, you should access
1243<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1244number is greater than or equal to
1245<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1246register. Whereas physical registers are statically defined in a
1247<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1248application developer, that is not the case with virtual registers.
1249In order to create new virtual registers, use the method
1250<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
1251virtual register with the highest code.
1252</p>
1253
1254<p>Before register allocation, the operands of an instruction are
1255mostly virtual registers, although physical registers may also be
1256used. In order to check if a given machine operand is a register, use
1257the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1258the integer code of a register, use
1259<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1260register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1261defines the registers 1024, and uses registers 1025 and 1026. Given a
1262register operand, the method <tt>MachineOperand::isUse()</tt> informs
1263if that register is being used by the instruction. The method
1264<tt>MachineOperand::isDef()</tt> informs if that registers is being
1265defined.</p>
1266
1267<p>We will call physical registers present in the LLVM bytecode before
1268register allocation <i>pre-colored registers</i>. Pre-colored
1269registers are used in many different situations, for instance, to pass
1270parameters of functions calls, and to store results of particular
1271instructions. There are two types of pre-colored registers: the ones
1272<i>implicitly</i> defined, and those <i>explicitly</i>
1273defined. Explicitly defined registers are normal operands, and can be
1274accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1275order to check which registers are implicitly defined by an
1276instruction, use the
1277<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1278<tt>opcode</tt> is the opcode of the target instruction. One important
1279difference between explicit and implicit physical registers is that
1280the latter are defined statically for each instruction, whereas the
1281former may vary depending on the program being compiled. For example,
1282an instruction that represents a function call will always implicitly
1283define or use the same set of physical registers. To read the
1284registers implicitly used by an instruction, use
1285<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1286registers impose constraints on any register allocation algorithm. The
1287register allocator must make sure that none of them is been
1288overwritten by the values of virtual registers while still alive.</p>
1289
1290</div>
1291
1292<!-- _______________________________________________________________________ -->
1293
1294<div class="doc_subsubsection">
1295 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1296</div>
1297
1298<div class="doc_text">
1299
1300<p>There are two ways to map virtual registers to physical registers (or to
1301memory slots). The first way, that we will call <i>direct mapping</i>,
1302is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
1303and <tt>MachineOperand</tt>. The second way, that we will call
1304<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1305order to insert loads and stores sending and getting values to and from
1306memory.</p>
1307
1308<p>The direct mapping provides more flexibility to the developer of
1309the register allocator; however, it is more error prone, and demands
1310more implementation work. Basically, the programmer will have to
1311specify where load and store instructions should be inserted in the
1312target function being compiled in order to get and store values in
1313memory. To assign a physical register to a virtual register present in
1314a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1315a store instruction, use
1316<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1317instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
1318
1319<p>The indirect mapping shields the application developer from the
1320complexities of inserting load and store instructions. In order to map
1321a virtual register to a physical one, use
1322<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1323certain virtual register to memory, use
1324<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1325return the stack slot where <tt>vreg</tt>'s value will be located. If
1326it is necessary to map another virtual register to the same stack
1327slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1328stack_location)</tt>. One important point to consider when using the
1329indirect mapping, is that even if a virtual register is mapped to
1330memory, it still needs to be mapped to a physical register. This
1331physical register is the location where the virtual register is
1332supposed to be found before being stored or after being reloaded.</p>
1333
1334<p>If the indirect strategy is used, after all the virtual registers
1335have been mapped to physical registers or stack slots, it is necessary
1336to use a spiller object to place load and store instructions in the
1337code. Every virtual that has been mapped to a stack slot will be
1338stored to memory after been defined and will be loaded before being
1339used. The implementation of the spiller tries to recycle load/store
1340instructions, avoiding unnecessary instructions. For an example of how
1341to invoke the spiller, see
1342<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1343<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1344
1345</div>
1346
1347<!-- _______________________________________________________________________ -->
1348<div class="doc_subsubsection">
1349 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1350</div>
1351
1352<div class="doc_text">
1353
1354<p>With very rare exceptions (e.g., function calls), the LLVM machine
1355code instructions are three address instructions. That is, each
1356instruction is expected to define at most one register, and to use at
1357most two registers. However, some architectures use two address
1358instructions. In this case, the defined register is also one of the
1359used register. For instance, an instruction such as <tt>ADD %EAX,
1360%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1361%EBX</tt>.</p>
1362
1363<p>In order to produce correct code, LLVM must convert three address
1364instructions that represent two address instructions into true two
1365address instructions. LLVM provides the pass
1366<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1367be run before register allocation takes place. After its execution,
1368the resulting code may no longer be in SSA form. This happens, for
1369instance, in situations where an instruction such as <tt>%a = ADD %b
1370%c</tt> is converted to two instructions such as:</p>
1371
1372<div class="doc_code">
1373<pre>
1374%a = MOVE %b
1375%a = ADD %a %b
1376</pre>
1377</div>
1378
1379<p>Notice that, internally, the second instruction is represented as
1380<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1381both used and defined by the instruction.</p>
1382
1383</div>
1384
1385<!-- _______________________________________________________________________ -->
1386<div class="doc_subsubsection">
1387 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1388</div>
1389
1390<div class="doc_text">
1391
1392<p>An important transformation that happens during register allocation is called
1393the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1394analyses that are performed on the control flow graph of
1395programs. However, traditional instruction sets do not implement
1396PHI instructions. Thus, in order to generate executable code, compilers
1397must replace PHI instructions with other instructions that preserve their
1398semantics.</p>
1399
1400<p>There are many ways in which PHI instructions can safely be removed
1401from the target code. The most traditional PHI deconstruction
1402algorithm replaces PHI instructions with copy instructions. That is
1403the strategy adopted by LLVM. The SSA deconstruction algorithm is
1404implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1405invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1406marked as required in the code of the register allocator.</p>
1407
1408</div>
1409
1410<!-- _______________________________________________________________________ -->
1411<div class="doc_subsubsection">
1412 <a name="regAlloc_fold">Instruction folding</a>
1413</div>
1414
1415<div class="doc_text">
1416
1417<p><i>Instruction folding</i> is an optimization performed during
1418register allocation that removes unnecessary copy instructions. For
1419instance, a sequence of instructions such as:</p>
1420
1421<div class="doc_code">
1422<pre>
1423%EBX = LOAD %mem_address
1424%EAX = COPY %EBX
1425</pre>
1426</div>
1427
1428<p>can be safely substituted by the single instruction:
1429
1430<div class="doc_code">
1431<pre>
1432%EAX = LOAD %mem_address
1433</pre>
1434</div>
1435
1436<p>Instructions can be folded with the
1437<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1438taken when folding instructions; a folded instruction can be quite
1439different from the original instruction. See
1440<tt>LiveIntervals::addIntervalsForSpills</tt> in
1441<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1442
1443</div>
1444
1445<!-- _______________________________________________________________________ -->
1446
1447<div class="doc_subsubsection">
1448 <a name="regAlloc_builtIn">Built in register allocators</a>
1449</div>
1450
1451<div class="doc_text">
1452
1453<p>The LLVM infrastructure provides the application developer with
1454three different register allocators:</p>
1455
1456<ul>
1457 <li><i>Simple</i> - This is a very simple implementation that does
1458 not keep values in registers across instructions. This register
1459 allocator immediately spills every value right after it is
1460 computed, and reloads all used operands from memory to temporary
1461 registers before each instruction.</li>
1462 <li><i>Local</i> - This register allocator is an improvement on the
1463 <i>Simple</i> implementation. It allocates registers on a basic
1464 block level, attempting to keep values in registers and reusing
1465 registers as appropriate.</li>
1466 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1467 well-know linear scan register allocator. Whereas the
1468 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1469 implementation technique, the <i>Linear Scan</i> implementation
1470 uses a spiller in order to place load and stores.</li>
1471</ul>
1472
1473<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1474command line option <tt>-regalloc=...</tt>:</p>
1475
1476<div class="doc_code">
1477<pre>
1478$ llc -f -regalloc=simple file.bc -o sp.s;
1479$ llc -f -regalloc=local file.bc -o lc.s;
1480$ llc -f -regalloc=linearscan file.bc -o ln.s;
1481</pre>
1482</div>
1483
1484</div>
1485
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1486<!-- ======================================================================= -->
1487<div class="doc_subsection">
1488 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1489</div>
1490<div class="doc_text"><p>To Be Written</p></div>
1491<!-- ======================================================================= -->
1492<div class="doc_subsection">
1493 <a name="latemco">Late Machine Code Optimizations</a>
1494</div>
1495<div class="doc_text"><p>To Be Written</p></div>
1496<!-- ======================================================================= -->
1497<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1498 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1499</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1500<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1501<!-- _______________________________________________________________________ -->
1502<div class="doc_subsubsection">
1503 <a name="codeemit_asm">Generating Assembly Code</a>
1504</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1505<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1506<!-- _______________________________________________________________________ -->
1507<div class="doc_subsubsection">
1508 <a name="codeemit_bin">Generating Binary Machine Code</a>
1509</div>
1510
1511<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1512 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1513</div>
1514
1515
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1516<!-- *********************************************************************** -->
1517<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1518 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1519</div>
1520<!-- *********************************************************************** -->
1521
1522<div class="doc_text">
1523
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1524<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1525are specific to the code generator for a particular target.</p>
1526
1527</div>
1528
1529
1530<!-- ======================================================================= -->
1531<div class="doc_subsection">
1532 <a name="x86">The X86 backend</a>
1533</div>
1534
1535<div class="doc_text">
1536
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1537<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1538code generator currently targets a generic P6-like processor. As such, it
1539produces a few P6-and-above instructions (like conditional moves), but it does
1540not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1541will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1542implementations.</p>
1543
1544</div>
1545
1546<!-- _______________________________________________________________________ -->
1547<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1548 <a name="x86_tt">X86 Target Triples Supported</a>
1549</div>
1550
1551<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1552
1553<p>The following are the known target triples that are supported by the X86
1554backend. This is not an exhaustive list, and it would be useful to add those
1555that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1556
1557<ul>
1558<li><b>i686-pc-linux-gnu</b> - Linux</li>
1559<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1560<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1561<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1562<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1563</ul>
1564
1565</div>
1566
1567<!-- _______________________________________________________________________ -->
1568<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1569 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1570</div>
1571
1572<div class="doc_text">
1573
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1574<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1575forming memory addresses of the following expression directly in integer
1576instructions (which use ModR/M addressing):</p>
1577
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1578<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1579<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1580Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1581</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1582</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1583
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1584<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1585memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1586has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1587
1588<pre>
1589Index: 0 | 1 2 3 4
1590Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1591OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1592</pre>
1593
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1594<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1595same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1596
1597</div>
1598
1599<!-- _______________________________________________________________________ -->
1600<div class="doc_subsubsection">
1601 <a name="x86_names">Instruction naming</a>
1602</div>
1603
1604<div class="doc_text">
1605
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1606<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1607a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1608
1609<p>
1610<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1611<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1612<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1613<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1614</p>
1615
1616</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1617
1618<!-- *********************************************************************** -->
1619<hr>
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1625
1626 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]1627 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1628 Last modified: $Date$
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