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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5a0e60425f4f942afb7e901b401a130da48a4d21 / . / lib / Target / Hexagon / HexagonInstrInfo.h
blob: d1209dec3b3a1b4e661cdf0828c31bd25fb9a6e5 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
Craig Topper79aa3412012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoonc635ebd2012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame]19#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]20#include "llvm/Target/TargetFrameLowering.h"
Jyotsna Vermaf945d092013-05-02 15:39:30 +0000[diff] [blame]21#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
28class HexagonInstrInfo : public HexagonGenInstrInfo {
29 const HexagonRegisterInfo RI;
30 const HexagonSubtarget& Subtarget;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame]31 typedef unsigned Opcode_t;
32
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]33public:
34 explicit HexagonInstrInfo(HexagonSubtarget &ST);
35
36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
37 /// such, whenever a client has an instance of instruction info, it should
38 /// always be able to get register info as well (through this method).
39 ///
40 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
41
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const;
49
50 /// isStoreToStackSlot - If the specified machine instruction is a direct
51 /// store to a stack slot, return the virtual or physical register number of
52 /// the source reg along with the FrameIndex of the loaded stack slot. If
53 /// not, return 0. This predicate must return 0 if the instruction has
54 /// any side effects other than storing to the stack slot.
55 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
56 int &FrameIndex) const;
57
58
59 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
60 MachineBasicBlock *&FBB,
61 SmallVectorImpl<MachineOperand> &Cond,
62 bool AllowModify) const;
63
64 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
65
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
69 DebugLoc DL) const;
70
Krzysztof Parzyszekce55d912013-02-11 20:04:29 +0000[diff] [blame]71 virtual bool analyzeCompare(const MachineInstr *MI,
72 unsigned &SrcReg, unsigned &SrcReg2,
73 int &Mask, int &Value) const;
74
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]75 virtual void copyPhysReg(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator I, DebugLoc DL,
77 unsigned DestReg, unsigned SrcReg,
78 bool KillSrc) const;
79
80 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MBBI,
82 unsigned SrcReg, bool isKill, int FrameIndex,
83 const TargetRegisterClass *RC,
84 const TargetRegisterInfo *TRI) const;
85
86 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
87 SmallVectorImpl<MachineOperand> &Addr,
88 const TargetRegisterClass *RC,
89 SmallVectorImpl<MachineInstr*> &NewMIs) const;
90
91 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MBBI,
93 unsigned DestReg, int FrameIndex,
94 const TargetRegisterClass *RC,
95 const TargetRegisterInfo *TRI) const;
96
97 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
98 SmallVectorImpl<MachineOperand> &Addr,
99 const TargetRegisterClass *RC,
100 SmallVectorImpl<MachineInstr*> &NewMIs) const;
101
102 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
103 MachineInstr* MI,
104 const SmallVectorImpl<unsigned> &Ops,
105 int FrameIndex) const;
106
107 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
108 MachineInstr* MI,
109 const SmallVectorImpl<unsigned> &Ops,
110 MachineInstr* LoadMI) const {
111 return 0;
112 }
113
114 unsigned createVR(MachineFunction* MF, MVT VT) const;
115
Jyotsna Verma1a7eab32013-05-06 18:49:23 +0000[diff] [blame]116 virtual bool isBranch(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]117 virtual bool isPredicable(MachineInstr *MI) const;
118 virtual bool
119 PredicateInstruction(MachineInstr *MI,
120 const SmallVectorImpl<MachineOperand> &Cond) const;
121
Kay Tiong Khoo575e90e2012-06-13 15:53:04 +0000[diff] [blame]122 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]123 unsigned ExtraPredCycles,
124 const BranchProbability &Probability) const;
125
126 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
127 unsigned NumTCycles, unsigned ExtraTCycles,
128 MachineBasicBlock &FMBB,
129 unsigned NumFCycles, unsigned ExtraFCycles,
130 const BranchProbability &Probability) const;
131
132 virtual bool isPredicated(const MachineInstr *MI) const;
Jyotsna Verma1a7eab32013-05-06 18:49:23 +0000[diff] [blame]133 virtual bool isPredicated(unsigned Opcode) const;
134 virtual bool isPredicatedTrue(const MachineInstr *MI) const;
135 virtual bool isPredicatedTrue(unsigned Opcode) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame]136 virtual bool isPredicatedNew(const MachineInstr *MI) const;
Jyotsna Verma1a7eab32013-05-06 18:49:23 +0000[diff] [blame]137 virtual bool isPredicatedNew(unsigned Opcode) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]138 virtual bool DefinesPredicate(MachineInstr *MI,
139 std::vector<MachineOperand> &Pred) const;
140 virtual bool
141 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
142 const SmallVectorImpl<MachineOperand> &Pred2) const;
143
144 virtual bool
145 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
146
147 virtual bool
148 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
149 const BranchProbability &Probability) const;
150
Jyotsna Verma2a885552013-03-29 21:09:53 +0000[diff] [blame]151 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
152 int FrameIx,
153 uint64_t Offset,
154 const MDNode *MDPtr,
155 DebugLoc DL) const;
Andrew Trickee498d32012-02-01 22:13:57 +0000[diff] [blame]156 virtual DFAPacketizer*
157 CreateTargetScheduleState(const TargetMachine *TM,
158 const ScheduleDAG *DAG) const;
159
160 virtual bool isSchedulingBoundary(const MachineInstr *MI,
161 const MachineBasicBlock *MBB,
162 const MachineFunction &MF) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]163 bool isValidOffset(const int Opcode, const int Offset) const;
164 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
165 bool isMemOp(const MachineInstr *MI) const;
166 bool isSpillPredRegOp(const MachineInstr *MI) const;
167 bool isU6_3Immediate(const int value) const;
168 bool isU6_2Immediate(const int value) const;
169 bool isU6_1Immediate(const int value) const;
170 bool isU6_0Immediate(const int value) const;
171 bool isS4_3Immediate(const int value) const;
172 bool isS4_2Immediate(const int value) const;
173 bool isS4_1Immediate(const int value) const;
174 bool isS4_0Immediate(const int value) const;
175 bool isS12_Immediate(const int value) const;
176 bool isU6_Immediate(const int value) const;
177 bool isS8_Immediate(const int value) const;
178 bool isS6_Immediate(const int value) const;
179
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]180 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
181 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]182 bool isConditionalALU32 (const MachineInstr* MI) const;
183 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]184 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Verma9feabc22013-03-05 18:51:42 +0000[diff] [blame]185 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma1a7eab32013-05-06 18:49:23 +0000[diff] [blame]186 bool isNewValue(const MachineInstr* MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame]187 bool isDotNewInst(const MachineInstr* MI) const;
Jyotsna Vermacdfb55d2013-05-10 20:58:11 +0000[diff] [blame]188 int GetDotOldOp(const int opc) const;
Jyotsna Verma1a35b8e2013-05-10 20:27:34 +0000[diff] [blame]189 int GetDotNewOp(const MachineInstr* MI) const;
Jyotsna Verma80d81aa2013-05-09 19:16:07 +0000[diff] [blame]190 int GetDotNewPredOp(MachineInstr *MI,
191 const MachineBranchProbabilityInfo
192 *MBPI) const;
Jyotsna Vermacdfb55d2013-05-10 20:58:11 +0000[diff] [blame]193 bool mayBeNewStore(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]194 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]195 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]196 bool isExtendable(const MachineInstr* MI) const;
197 bool isExtended(const MachineInstr* MI) const;
198 bool isPostIncrement(const MachineInstr* MI) const;
199 bool isNewValueStore(const MachineInstr* MI) const;
Jyotsna Verma1a35b8e2013-05-10 20:27:34 +0000[diff] [blame]200 bool isNewValueStore(unsigned Opcode) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]201 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pandeb3385702012-05-12 05:10:30 +0000[diff] [blame]202 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]203
Jyotsna Vermaef94c6c2013-03-01 17:37:13 +0000[diff] [blame]204
205 void immediateExtend(MachineInstr *MI) const;
206 bool isConstExtended(MachineInstr *MI) const;
Jyotsna Vermaf945d092013-05-02 15:39:30 +0000[diff] [blame]207 int getDotNewPredJumpOp(MachineInstr *MI,
208 const MachineBranchProbabilityInfo *MBPI) const;
Jyotsna Vermaef94c6c2013-03-01 17:37:13 +0000[diff] [blame]209 unsigned getAddrMode(const MachineInstr* MI) const;
210 bool isOperandExtended(const MachineInstr *MI,
211 unsigned short OperandNum) const;
212 unsigned short getCExtOpNum(const MachineInstr *MI) const;
213 int getMinValue(const MachineInstr *MI) const;
214 int getMaxValue(const MachineInstr *MI) const;
215 bool NonExtEquivalentExists (const MachineInstr *MI) const;
216 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame]217 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
218 bool PredOpcodeHasNot(Opcode_t Opcode) const;
219
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]220private:
221 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
222
223};
224
225}
226
227#endif