Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 30 | // Unary and binary operator instructions that set EFLAGS as a side-effect. |
Chris Lattner | 74c8d67 | 2010-03-24 00:47:47 +0000 | [diff] [blame] | 31 | def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, |
| 32 | [SDTCisInt<0>, SDTCisVT<1, i32>]>; |
| 33 | |
Chris Lattner | 1aec4d7 | 2010-03-24 00:49:29 +0000 | [diff] [blame] | 34 | def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, |
| 35 | [SDTCisSameAs<0, 2>, |
| 36 | SDTCisSameAs<0, 3>, |
| 37 | SDTCisInt<0>, SDTCisVT<1, i32>]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 38 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 39 | [SDTCisVT<0, OtherVT>, |
| 40 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 41 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 42 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 43 | [SDTCisVT<0, i8>, |
| 44 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 45 | def SDTX86SetCC_C : SDTypeProfile<1, 2, |
| 46 | [SDTCisInt<0>, |
| 47 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 48 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 49 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
| 50 | SDTCisVT<2, i8>]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 51 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 52 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 53 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 54 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 55 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 56 | |
Sean Callanan | 1c97ceb | 2009-06-23 23:25:37 +0000 | [diff] [blame] | 57 | def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; |
| 58 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, |
| 59 | SDTCisVT<1, i32>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 60 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 61 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 62 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 63 | def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, |
| 64 | SDTCisVT<1, iPTR>, |
| 65 | SDTCisVT<2, iPTR>]>; |
| 66 | |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 67 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 68 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 69 | def SDTX86Void : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 70 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 71 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 72 | |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 73 | def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 74 | |
Eric Christopher | 30ef0e5 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 75 | def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
| 76 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 77 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 78 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 79 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 80 | |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 81 | def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; |
| 82 | def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 83 | |
| 84 | def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, |
| 85 | [SDNPHasChain]>; |
| 86 | def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE, |
| 87 | [SDNPHasChain]>; |
| 88 | def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, |
| 89 | [SDNPHasChain]>; |
| 90 | def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, |
| 91 | [SDNPHasChain]>; |
| 92 | def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, |
| 93 | [SDNPHasChain]>; |
| 94 | |
| 95 | |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 96 | def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; |
| 97 | def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 98 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 99 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 100 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 101 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 102 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; |
| 103 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 104 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 105 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 106 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 107 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 108 | def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 109 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 110 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
| 111 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
Chris Lattner | 8864155 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 112 | SDNPMayLoad, SDNPMemOperand]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 113 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, |
| 114 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
Chris Lattner | 8864155 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 115 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 116 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
| 117 | [SDNPHasChain, SDNPMayStore, |
| 118 | SDNPMayLoad, SDNPMemOperand]>; |
| 119 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
| 120 | [SDNPHasChain, SDNPMayStore, |
| 121 | SDNPMayLoad, SDNPMemOperand]>; |
| 122 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
| 123 | [SDNPHasChain, SDNPMayStore, |
| 124 | SDNPMayLoad, SDNPMemOperand]>; |
| 125 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
| 126 | [SDNPHasChain, SDNPMayStore, |
| 127 | SDNPMayLoad, SDNPMemOperand]>; |
| 128 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
| 129 | [SDNPHasChain, SDNPMayStore, |
| 130 | SDNPMayLoad, SDNPMemOperand]>; |
| 131 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
| 132 | [SDNPHasChain, SDNPMayStore, |
| 133 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 134 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
| 135 | [SDNPHasChain, SDNPMayStore, |
| 136 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 137 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 138 | [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 139 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 140 | def X86vastart_save_xmm_regs : |
| 141 | SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", |
| 142 | SDT_X86VASTART_SAVE_XMM_REGS, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 143 | [SDNPHasChain, SDNPVariadic]>; |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 144 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 145 | def X86callseq_start : |
| 146 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 147 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 148 | def X86callseq_end : |
| 149 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 150 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 151 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 152 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 153 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag, |
| 154 | SDNPVariadic]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 155 | |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 156 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 157 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>; |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 158 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 159 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 160 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 161 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 162 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 163 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 164 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 165 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 166 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 167 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 168 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 169 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 170 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 171 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 172 | [SDNPHasChain]>; |
| 173 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 174 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 175 | [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 176 | |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 177 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 178 | [SDNPCommutative]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 179 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 180 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 181 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 182 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 183 | [SDNPCommutative]>; |
Chris Lattner | 74c8d67 | 2010-03-24 00:47:47 +0000 | [diff] [blame] | 184 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 185 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; |
| 186 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 187 | def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 188 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 189 | def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 190 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 191 | def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 192 | [SDNPCommutative]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 193 | |
Evan Cheng | 73f24c9 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 194 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; |
| 195 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 196 | def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void, |
| 197 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Eric Christopher | 30ef0e5 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 198 | |
| 199 | def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, |
| 200 | []>; |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 201 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 202 | //===----------------------------------------------------------------------===// |
| 203 | // X86 Operand Definitions. |
| 204 | // |
| 205 | |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 206 | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for |
| 207 | // the index operand of an address, to conform to x86 encoding restrictions. |
| 208 | def ptr_rc_nosp : PointerLikeRegClass<1>; |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 209 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 210 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 211 | // |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 212 | def X86MemAsmOperand : AsmOperandClass { |
| 213 | let Name = "Mem"; |
Daniel Dunbar | 54ddf3d | 2010-05-22 21:02:29 +0000 | [diff] [blame] | 214 | let SuperClasses = []; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 215 | } |
Daniel Dunbar | c26ae5a | 2010-05-06 22:39:14 +0000 | [diff] [blame] | 216 | def X86AbsMemAsmOperand : AsmOperandClass { |
| 217 | let Name = "AbsMem"; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 218 | let SuperClasses = [X86MemAsmOperand]; |
Daniel Dunbar | c26ae5a | 2010-05-06 22:39:14 +0000 | [diff] [blame] | 219 | } |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 220 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 221 | let PrintMethod = printMethod; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 222 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 223 | let ParserMatchClass = X86MemAsmOperand; |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 224 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 225 | |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 226 | def opaque32mem : X86MemOperand<"printopaquemem">; |
| 227 | def opaque48mem : X86MemOperand<"printopaquemem">; |
| 228 | def opaque80mem : X86MemOperand<"printopaquemem">; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 229 | def opaque512mem : X86MemOperand<"printopaquemem">; |
| 230 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 231 | def i8mem : X86MemOperand<"printi8mem">; |
| 232 | def i16mem : X86MemOperand<"printi16mem">; |
| 233 | def i32mem : X86MemOperand<"printi32mem">; |
| 234 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 235 | def i128mem : X86MemOperand<"printi128mem">; |
Bruno Cardoso Lopes | 94143ee | 2010-07-19 23:32:44 +0000 | [diff] [blame] | 236 | def i256mem : X86MemOperand<"printi256mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 237 | def f32mem : X86MemOperand<"printf32mem">; |
| 238 | def f64mem : X86MemOperand<"printf64mem">; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 239 | def f80mem : X86MemOperand<"printf80mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 240 | def f128mem : X86MemOperand<"printf128mem">; |
Bruno Cardoso Lopes | e86b01c | 2010-07-09 18:27:43 +0000 | [diff] [blame] | 241 | def f256mem : X86MemOperand<"printf256mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 242 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 243 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of |
| 244 | // plain GR64, so that it doesn't potentially require a REX prefix. |
| 245 | def i8mem_NOREX : Operand<i64> { |
| 246 | let PrintMethod = "printi8mem"; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 247 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 248 | let ParserMatchClass = X86MemAsmOperand; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 249 | } |
| 250 | |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 251 | // Special i32mem for addresses of load folding tail calls. These are not |
| 252 | // allowed to use callee-saved registers since they must be scheduled |
| 253 | // after callee-saved register are popped. |
| 254 | def i32mem_TC : Operand<i32> { |
| 255 | let PrintMethod = "printi32mem"; |
| 256 | let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm); |
| 257 | let ParserMatchClass = X86MemAsmOperand; |
| 258 | } |
| 259 | |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 260 | // Special i64mem for addresses of load folding tail calls. These are not |
| 261 | // allowed to use callee-saved registers since they must be scheduled |
| 262 | // after callee-saved register are popped. |
| 263 | def i64mem_TC : Operand<i64> { |
| 264 | let PrintMethod = "printi64mem"; |
| 265 | let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm); |
| 266 | let ParserMatchClass = X86MemAsmOperand; |
| 267 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 268 | |
Daniel Dunbar | b834f5d | 2010-01-30 01:02:48 +0000 | [diff] [blame] | 269 | let ParserMatchClass = X86AbsMemAsmOperand, |
| 270 | PrintMethod = "print_pcrel_imm" in { |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame] | 271 | def i32imm_pcrel : Operand<i32>; |
Chris Lattner | 9fc0522 | 2010-07-07 22:27:31 +0000 | [diff] [blame] | 272 | def i16imm_pcrel : Operand<i16>; |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame] | 273 | |
| 274 | def offset8 : Operand<i64>; |
| 275 | def offset16 : Operand<i64>; |
| 276 | def offset32 : Operand<i64>; |
| 277 | def offset64 : Operand<i64>; |
| 278 | |
| 279 | // Branch targets have OtherVT type and print as pc-relative values. |
| 280 | def brtarget : Operand<OtherVT>; |
| 281 | def brtarget8 : Operand<OtherVT>; |
| 282 | |
| 283 | } |
| 284 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 285 | def SSECC : Operand<i8> { |
| 286 | let PrintMethod = "printSSECC"; |
| 287 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 288 | |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 289 | class ImmSExtAsmOperandClass : AsmOperandClass { |
Daniel Dunbar | 54ddf3d | 2010-05-22 21:02:29 +0000 | [diff] [blame] | 290 | let SuperClasses = [ImmAsmOperand]; |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 291 | let RenderMethod = "addImmOperands"; |
Daniel Dunbar | 1fe591d | 2010-05-20 20:20:39 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 294 | // Sign-extended immediate classes. We don't need to define the full lattice |
| 295 | // here because there is no instruction with an ambiguity between ImmSExti64i32 |
| 296 | // and ImmSExti32i8. |
| 297 | // |
| 298 | // The strange ranges come from the fact that the assembler always works with |
| 299 | // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" |
| 300 | // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). |
| 301 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 302 | // [0, 0x7FFFFFFF] | |
| 303 | // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 304 | def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { |
| 305 | let Name = "ImmSExti64i32"; |
| 306 | } |
| 307 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 308 | // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | |
| 309 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 310 | def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { |
| 311 | let Name = "ImmSExti16i8"; |
| 312 | let SuperClasses = [ImmSExti64i32AsmOperand]; |
| 313 | } |
| 314 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 315 | // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | |
| 316 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 317 | def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { |
| 318 | let Name = "ImmSExti32i8"; |
| 319 | } |
| 320 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 321 | // [0, 0x0000007F] | |
| 322 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 323 | def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { |
| 324 | let Name = "ImmSExti64i8"; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 325 | let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, |
| 326 | ImmSExti64i32AsmOperand]; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 327 | } |
| 328 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 329 | // A couple of more descriptive operand definitions. |
| 330 | // 16-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 331 | def i16i8imm : Operand<i16> { |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 332 | let ParserMatchClass = ImmSExti16i8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 333 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 334 | // 32-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 335 | def i32i8imm : Operand<i32> { |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 336 | let ParserMatchClass = ImmSExti32i8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 337 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 338 | |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 339 | // 64-bits but only 32 bits are significant. |
| 340 | def i64i32imm : Operand<i64> { |
| 341 | let ParserMatchClass = ImmSExti64i32AsmOperand; |
| 342 | } |
| 343 | |
| 344 | // 64-bits but only 32 bits are significant, and those bits are treated as being |
| 345 | // pc relative. |
| 346 | def i64i32imm_pcrel : Operand<i64> { |
| 347 | let PrintMethod = "print_pcrel_imm"; |
| 348 | let ParserMatchClass = X86AbsMemAsmOperand; |
| 349 | } |
| 350 | |
| 351 | // 64-bits but only 8 bits are significant. |
| 352 | def i64i8imm : Operand<i64> { |
| 353 | let ParserMatchClass = ImmSExti64i8AsmOperand; |
| 354 | } |
| 355 | |
| 356 | def lea64_32mem : Operand<i32> { |
| 357 | let PrintMethod = "printi32mem"; |
| 358 | let AsmOperandLowerMethod = "lower_lea64_32mem"; |
| 359 | let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm); |
| 360 | let ParserMatchClass = X86MemAsmOperand; |
| 361 | } |
| 362 | |
| 363 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 364 | //===----------------------------------------------------------------------===// |
| 365 | // X86 Complex Pattern Definitions. |
| 366 | // |
| 367 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 368 | // Define X86 specific addressing mode. |
Chris Lattner | b86faa1 | 2010-09-21 22:07:31 +0000 | [diff] [blame] | 369 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 370 | def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", |
Dan Gohman | a98634b | 2009-08-02 16:09:17 +0000 | [diff] [blame] | 371 | [add, sub, mul, X86mul_imm, shl, or, frameindex], |
| 372 | []>; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 373 | def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 374 | [tglobaltlsaddr], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 375 | |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 376 | def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", |
| 377 | [add, sub, mul, X86mul_imm, shl, or, frameindex, |
| 378 | X86WrapperRIP], []>; |
| 379 | |
| 380 | def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", |
| 381 | [tglobaltlsaddr], []>; |
| 382 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 383 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 384 | // X86 Instruction Predicate Definitions. |
Chris Lattner | 314a113 | 2010-03-14 18:31:44 +0000 | [diff] [blame] | 385 | def HasCMov : Predicate<"Subtarget->hasCMov()">; |
| 386 | def NoCMov : Predicate<"!Subtarget->hasCMov()">; |
Bruno Cardoso Lopes | 3c45734 | 2010-07-26 21:01:18 +0000 | [diff] [blame] | 387 | |
| 388 | // FIXME: temporary hack to let codegen assert or generate poor code in case |
| 389 | // no AVX version of the desired intructions is present, this is better for |
| 390 | // incremental dev (without fallbacks it's easier to spot what's missing) |
Bruno Cardoso Lopes | 5b7dab8 | 2010-07-30 19:41:24 +0000 | [diff] [blame] | 391 | def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">; |
Chris Lattner | 548abfc | 2010-10-03 18:08:05 +0000 | [diff] [blame] | 392 | def Has3DNow : Predicate<"Subtarget->has3DNow()">; |
| 393 | def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; |
Bruno Cardoso Lopes | 5b7dab8 | 2010-07-30 19:41:24 +0000 | [diff] [blame] | 394 | def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; |
| 395 | def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; |
| 396 | def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; |
| 397 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; |
| 398 | def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; |
| 399 | def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; |
| 400 | def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">; |
Bruno Cardoso Lopes | 3c45734 | 2010-07-26 21:01:18 +0000 | [diff] [blame] | 401 | |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 402 | def HasAVX : Predicate<"Subtarget->hasAVX()">; |
Bruno Cardoso Lopes | cdae7e8 | 2010-07-23 01:17:51 +0000 | [diff] [blame] | 403 | def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 404 | def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; |
| 405 | def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 406 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 407 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 408 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 409 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
Anton Korobeynikov | cf6b739 | 2009-08-03 08:12:53 +0000 | [diff] [blame] | 410 | def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; |
| 411 | def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 412 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 413 | def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; |
| 414 | def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" |
Anton Korobeynikov | 186fa1d | 2009-08-06 09:11:19 +0000 | [diff] [blame] | 415 | "TM.getCodeModel() != CodeModel::Kernel">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 416 | def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" |
| 417 | "TM.getCodeModel() == CodeModel::Kernel">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 418 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | cb0f06e | 2010-03-25 00:10:31 +0000 | [diff] [blame] | 419 | def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; |
Evan Cheng | b1f4981 | 2009-12-22 17:47:23 +0000 | [diff] [blame] | 420 | def OptForSize : Predicate<"OptForSize">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 421 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 422 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 423 | def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; |
Eric Christopher | 6d1cd1c | 2010-04-02 21:54:27 +0000 | [diff] [blame] | 424 | def HasAES : Predicate<"Subtarget->hasAES()">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 425 | |
| 426 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 427 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 428 | // |
| 429 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 430 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 431 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 432 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 433 | // Pattern fragments... |
| 434 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 435 | |
| 436 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 437 | // X86InstrInfo.h. They must be kept in synch. |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 438 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE |
| 439 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC |
| 440 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C |
| 441 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA |
| 442 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z |
| 443 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE |
| 444 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL |
| 445 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE |
| 446 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG |
| 447 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 448 | def X86_COND_NO : PatLeaf<(i8 10)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 449 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 450 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 451 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 452 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE |
| 453 | def X86_COND_S : PatLeaf<(i8 15)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 454 | |
Jakob Stoklund Olesen | 3061c44 | 2010-09-03 00:35:18 +0000 | [diff] [blame] | 455 | def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 456 | |
Chris Lattner | 1840991 | 2010-03-03 01:45:01 +0000 | [diff] [blame] | 457 | def i16immSExt8 : PatLeaf<(i16 immSext8)>; |
| 458 | def i32immSExt8 : PatLeaf<(i32 immSext8)>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 459 | def i64immSExt8 : PatLeaf<(i64 immSext8)>; |
| 460 | def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>; |
| 461 | def i64immZExt32 : PatLeaf<(i64 imm), [{ |
| 462 | // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit |
| 463 | // unsignedsign extended field. |
| 464 | return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue(); |
| 465 | }]>; |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 466 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 467 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 468 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 469 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 470 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 471 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 472 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 473 | if (ExtType == ISD::NON_EXTLOAD) |
| 474 | return true; |
| 475 | if (ExtType == ISD::EXTLOAD) |
| 476 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 477 | return false; |
| 478 | }]>; |
| 479 | |
Chris Lattner | f85eff7 | 2010-03-03 01:52:59 +0000 | [diff] [blame] | 480 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 481 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 482 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 483 | if (ExtType == ISD::EXTLOAD) |
| 484 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 485 | return false; |
| 486 | }]>; |
| 487 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 488 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 489 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 490 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 491 | if (ExtType == ISD::NON_EXTLOAD) |
| 492 | return true; |
| 493 | if (ExtType == ISD::EXTLOAD) |
| 494 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 495 | return false; |
| 496 | }]>; |
| 497 | |
Chris Lattner | b86faa1 | 2010-09-21 22:07:31 +0000 | [diff] [blame] | 498 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 499 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; |
| 500 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 501 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
| 502 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 503 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 504 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 505 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 506 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 507 | def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; |
| 508 | def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; |
| 509 | def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 510 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 511 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 512 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 513 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 514 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 515 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 516 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 517 | def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; |
| 518 | def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; |
| 519 | def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; |
| 520 | def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 521 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 522 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 523 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 524 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 525 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 526 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 527 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 528 | def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; |
| 529 | def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; |
| 530 | def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; |
| 531 | def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 532 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 533 | |
| 534 | // An 'and' node with a single use. |
| 535 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 536 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 537 | }]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 538 | // An 'srl' node with a single use. |
| 539 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ |
| 540 | return N->hasOneUse(); |
| 541 | }]>; |
| 542 | // An 'trunc' node with a single use. |
| 543 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ |
| 544 | return N->hasOneUse(); |
| 545 | }]>; |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 546 | |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 547 | // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. |
| 548 | def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ |
| 549 | if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) |
| 550 | return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); |
Chris Lattner | fdac0b6 | 2010-03-24 00:12:57 +0000 | [diff] [blame] | 551 | |
| 552 | unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); |
| 553 | APInt Mask = APInt::getAllOnesValue(BitWidth); |
| 554 | APInt KnownZero0, KnownOne0; |
| 555 | CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0); |
| 556 | APInt KnownZero1, KnownOne1; |
| 557 | CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0); |
| 558 | return (~KnownZero0 & ~KnownZero1) == 0; |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 559 | }]>; |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 560 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 561 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 562 | // Instruction list. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 563 | // |
| 564 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 565 | // Nop |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 566 | let neverHasSideEffects = 1 in { |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 567 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 568 | def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), |
| 569 | "nop{w}\t$zero", []>, TB, OpSize; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 570 | def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 571 | "nop{l}\t$zero", []>, TB; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 572 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 573 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 574 | |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 575 | // Constructing a stack frame. |
Chris Lattner | 40cc3f8 | 2010-09-17 18:02:29 +0000 | [diff] [blame] | 576 | def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), |
| 577 | "enter\t$len, $lvl", []>; |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 578 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 579 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 580 | def LEAVE : I<0xC9, RawFrm, |
Daniel Dunbar | df4c47b | 2010-07-19 07:21:01 +0000 | [diff] [blame] | 581 | (outs), (ins), "leave", []>, Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 582 | |
Chris Lattner | 5673e1d | 2010-10-05 06:41:40 +0000 | [diff] [blame] | 583 | let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in |
| 584 | def LEAVE64 : I<0xC9, RawFrm, |
| 585 | (outs), (ins), "leave", []>, Requires<[In64BitMode]>; |
| 586 | |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 587 | //===----------------------------------------------------------------------===// |
Chris Lattner | 5673e1d | 2010-10-05 06:41:40 +0000 | [diff] [blame] | 588 | // Miscellaneous Instructions. |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 589 | // |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 590 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 591 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 592 | let mayLoad = 1 in { |
| 593 | def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 594 | OpSize; |
| 595 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 596 | def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 597 | OpSize; |
| 598 | def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>, |
| 599 | OpSize; |
| 600 | def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 601 | def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 602 | |
| 603 | def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize; |
| 604 | def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, |
| 605 | Requires<[In32BitMode]>; |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 606 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 607 | |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 608 | let mayStore = 1 in { |
| 609 | def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 610 | OpSize; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 611 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 612 | def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 613 | OpSize; |
| 614 | def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>, |
| 615 | OpSize; |
| 616 | def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
| 617 | def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>; |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 618 | |
Kevin Enderby | 3c979b0 | 2010-05-03 20:45:05 +0000 | [diff] [blame] | 619 | def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 620 | "push{l}\t$imm", []>; |
Kevin Enderby | 3c979b0 | 2010-05-03 20:45:05 +0000 | [diff] [blame] | 621 | def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
| 622 | "push{w}\t$imm", []>, OpSize; |
| 623 | def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 624 | "push{l}\t$imm", []>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 625 | |
Dan Gohman | e5e4ff9 | 2010-05-20 16:16:00 +0000 | [diff] [blame] | 626 | def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize; |
| 627 | def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, |
| 628 | Requires<[In32BitMode]>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 629 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 630 | } |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 631 | } |
| 632 | |
| 633 | let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { |
| 634 | let mayLoad = 1 in { |
| 635 | def POP64r : I<0x58, AddRegFrm, |
| 636 | (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; |
| 637 | def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; |
| 638 | def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>; |
| 639 | } |
| 640 | let mayStore = 1 in { |
| 641 | def PUSH64r : I<0x50, AddRegFrm, |
| 642 | (outs), (ins GR64:$reg), "push{q}\t$reg", []>; |
| 643 | def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>; |
| 644 | def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>; |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in { |
| 649 | def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm), |
| 650 | "push{q}\t$imm", []>; |
| 651 | def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
| 652 | "push{q}\t$imm", []>; |
| 653 | def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm), |
| 654 | "push{q}\t$imm", []>; |
| 655 | } |
| 656 | |
| 657 | let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in |
| 658 | def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, |
| 659 | Requires<[In64BitMode]>; |
| 660 | let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in |
| 661 | def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, |
| 662 | Requires<[In64BitMode]>; |
| 663 | |
| 664 | |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 665 | |
Nico Weber | 50b9efc | 2010-06-23 20:00:58 +0000 | [diff] [blame] | 666 | let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], |
| 667 | mayLoad=1, neverHasSideEffects=1 in { |
| 668 | def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>, |
| 669 | Requires<[In32BitMode]>; |
| 670 | } |
| 671 | let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], |
| 672 | mayStore=1, neverHasSideEffects=1 in { |
| 673 | def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>, |
| 674 | Requires<[In32BitMode]>; |
| 675 | } |
| 676 | |
Chris Lattner | 8917cd3 | 2010-10-05 06:52:26 +0000 | [diff] [blame] | 677 | let Constraints = "$src = $dst" in { // GR32 = bswap GR32 |
| 678 | def BSWAP32r : I<0xC8, AddRegFrm, |
| 679 | (outs GR32:$dst), (ins GR32:$src), |
| 680 | "bswap{l}\t$dst", |
| 681 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 682 | |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 683 | def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), |
| 684 | "bswap{q}\t$dst", |
| 685 | [(set GR64:$dst, (bswap GR64:$src))]>, TB; |
Chris Lattner | 8917cd3 | 2010-10-05 06:52:26 +0000 | [diff] [blame] | 686 | } // Constraints = "$src = $dst" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 687 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 688 | // Bit scan instructions. |
| 689 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 690 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 691 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 692 | [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 693 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 694 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 695 | [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB, |
| 696 | OpSize; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 697 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 698 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 699 | [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 700 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 701 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 702 | [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 703 | def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 704 | "bsf{q}\t{$src, $dst|$dst, $src}", |
| 705 | [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB; |
| 706 | def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 707 | "bsf{q}\t{$src, $dst|$dst, $src}", |
| 708 | [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 709 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 710 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 711 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 712 | [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 713 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 714 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 715 | [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB, |
| 716 | OpSize; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 717 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 718 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 719 | [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 720 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 721 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 722 | [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 723 | def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 724 | "bsr{q}\t{$src, $dst|$dst, $src}", |
| 725 | [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB; |
| 726 | def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 727 | "bsr{q}\t{$src, $dst|$dst, $src}", |
| 728 | [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 729 | } // Defs = [EFLAGS] |
| 730 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 731 | let neverHasSideEffects = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 732 | def LEA16r : I<0x8D, MRMSrcMem, |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 733 | (outs GR16:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 734 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; |
Evan Cheng | e771ebd | 2008-03-27 01:41:09 +0000 | [diff] [blame] | 735 | let isReMaterializable = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 736 | def LEA32r : I<0x8D, MRMSrcMem, |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 737 | (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 738 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 739 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 740 | |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 741 | def LEA64_32r : I<0x8D, MRMSrcMem, |
| 742 | (outs GR32:$dst), (ins lea64_32mem:$src), |
| 743 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
| 744 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>; |
| 745 | |
| 746 | let isReMaterializable = 1 in |
| 747 | def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 748 | "lea{q}\t{$src|$dst}, {$dst|$src}", |
| 749 | [(set GR64:$dst, lea64addr:$src)]>; |
| 750 | |
| 751 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 752 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 753 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI |
| 754 | let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { |
| 755 | def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>; |
| 756 | def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize; |
| 757 | def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 758 | def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 759 | } |
| 760 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 761 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI |
| 762 | let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in |
| 763 | def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>; |
| 764 | let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in |
| 765 | def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize; |
| 766 | let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in |
| 767 | def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 768 | let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in |
| 769 | def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 770 | |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 771 | def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>; |
| 772 | def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize; |
| 773 | def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 774 | def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>; |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 775 | |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 776 | def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>; |
| 777 | def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize; |
| 778 | def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 779 | def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>; |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 780 | |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 781 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 782 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 783 | // Move Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 784 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 785 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 786 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 787 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 788 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 789 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 790 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 791 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 792 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 793 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 794 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 795 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 796 | [(set GR8:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 797 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 798 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 799 | [(set GR16:$dst, imm:$src)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 800 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 801 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 802 | [(set GR32:$dst, imm:$src)]>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 803 | } |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 804 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 805 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 806 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 807 | [(store (i8 imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 808 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 809 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 810 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 811 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 812 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 813 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 814 | |
Chris Lattner | b5505d0 | 2010-05-13 00:02:47 +0000 | [diff] [blame] | 815 | /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a |
| 816 | /// 32-bit offset from the PC. These are only valid in x86-32 mode. |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 817 | def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 818 | "mov{b}\t{$src, %al|%al, $src}", []>, |
| 819 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 820 | def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 821 | "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize, |
| 822 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 823 | def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 824 | "mov{l}\t{$src, %eax|%eax, $src}", []>, |
| 825 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 826 | def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 827 | "mov{b}\t{%al, $dst|$dst, %al}", []>, |
| 828 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 829 | def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 830 | "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize, |
| 831 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 832 | def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 833 | "mov{l}\t{%eax, $dst|$dst, %eax}", []>, |
| 834 | Requires<[In32BitMode]>; |
Chris Lattner | b5505d0 | 2010-05-13 00:02:47 +0000 | [diff] [blame] | 835 | |
Sean Callanan | 38fee0e | 2009-09-15 18:47:29 +0000 | [diff] [blame] | 836 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 837 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 838 | def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), |
| 839 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
| 840 | def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 841 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
| 842 | def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 843 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 844 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 845 | |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 846 | let canFoldAsLoad = 1, isReMaterializable = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 847 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 848 | "mov{b}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 849 | [(set GR8:$dst, (loadi8 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 850 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 851 | "mov{w}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 852 | [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 853 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 854 | "mov{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 855 | [(set GR32:$dst, (loadi32 addr:$src))]>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 856 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 857 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 858 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 859 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 860 | [(store GR8:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 861 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 862 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 863 | [(store GR16:$src, addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 864 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 865 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 866 | [(store GR32:$src, addr:$dst)]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 867 | |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 868 | /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC. |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 869 | let isCodeGenOnly = 1 in { |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 870 | let neverHasSideEffects = 1 in |
| 871 | def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src), |
| 872 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
| 873 | |
| 874 | let mayLoad = 1, |
| 875 | canFoldAsLoad = 1, isReMaterializable = 1 in |
| 876 | def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src), |
| 877 | "mov{l}\t{$src, $dst|$dst, $src}", |
| 878 | []>; |
| 879 | |
| 880 | let mayStore = 1 in |
| 881 | def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src), |
| 882 | "mov{l}\t{$src, $dst|$dst, $src}", |
| 883 | []>; |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 884 | } |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 885 | |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 886 | // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so |
| 887 | // that they can be used for copying and storing h registers, which can't be |
| 888 | // encoded when a REX prefix is present. |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 889 | let isCodeGenOnly = 1 in { |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 890 | let neverHasSideEffects = 1 in |
Dan Gohman | df7dfc7 | 2009-04-15 19:48:57 +0000 | [diff] [blame] | 891 | def MOV8rr_NOREX : I<0x88, MRMDestReg, |
| 892 | (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 893 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 894 | let mayStore = 1 in |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 895 | def MOV8mr_NOREX : I<0x88, MRMDestMem, |
| 896 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), |
| 897 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 898 | let mayLoad = 1, |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 899 | canFoldAsLoad = 1, isReMaterializable = 1 in |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 900 | def MOV8rm_NOREX : I<0x8A, MRMSrcMem, |
| 901 | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), |
| 902 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 903 | } |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 904 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 905 | //===----------------------------------------------------------------------===// |
| 906 | // Fixed-Register Multiplication and Division Instructions... |
| 907 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 908 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 909 | // Extra precision multiplication |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 910 | |
Eric Christopher | 5cb33a3 | 2010-08-09 22:52:47 +0000 | [diff] [blame] | 911 | // AL is really implied by AX, but the registers in Defs must match the |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 912 | // SDNode results (i8, i32). |
| 913 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 914 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 915 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 916 | // This probably ought to be moved to a def : Pat<> if the |
| 917 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 918 | [(set AL, (mul AL, GR8:$src)), |
| 919 | (implicit EFLAGS)]>; // AL,AH = AL*GR8 |
| 920 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 921 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 922 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), |
| 923 | "mul{w}\t$src", |
| 924 | []>, OpSize; // AX,DX = AX*GR16 |
| 925 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 926 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 927 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), |
| 928 | "mul{l}\t$src", |
| 929 | []>; // EAX,EDX = EAX*GR32 |
| 930 | |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 931 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 932 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 933 | "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 934 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 935 | // This probably ought to be moved to a def : Pat<> if the |
| 936 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 937 | [(set AL, (mul AL, (loadi8 addr:$src))), |
| 938 | (implicit EFLAGS)]>; // AL,AH = AL*[mem8] |
| 939 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 940 | let mayLoad = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 941 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 942 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 943 | "mul{w}\t$src", |
| 944 | []>, OpSize; // AX,DX = AX*[mem16] |
| 945 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 946 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 947 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 948 | "mul{l}\t$src", |
| 949 | []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 950 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 951 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 952 | let neverHasSideEffects = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 953 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 954 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>; |
| 955 | // AL,AH = AL*GR8 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 956 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 957 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 958 | OpSize; // AX,DX = AX*GR16 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 959 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 960 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>; |
| 961 | // EAX,EDX = EAX*GR32 |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 962 | let mayLoad = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 963 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 964 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 965 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 966 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 967 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 968 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
Eli Friedman | ba7b1c4 | 2009-12-26 20:08:30 +0000 | [diff] [blame] | 969 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 970 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 971 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 972 | } |
Dan Gohman | c99da13 | 2008-11-18 21:29:14 +0000 | [diff] [blame] | 973 | } // neverHasSideEffects |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 974 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 975 | // unsigned division/remainder |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 976 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 977 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 978 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 979 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 980 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 981 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 982 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 983 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 984 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 985 | let mayLoad = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 986 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 987 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 988 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 989 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 990 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 991 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 992 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 993 | // EDX:EAX/[mem32] = EAX,EDX |
| 994 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 995 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 996 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 997 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 998 | // Signed division/remainder. |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 999 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1000 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1001 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1002 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1003 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1004 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1005 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1006 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1007 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1008 | let mayLoad = 1, mayLoad = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 1009 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1010 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1011 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1012 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1013 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1014 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1015 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1016 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), |
| 1017 | // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1018 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1019 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1020 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1021 | //===----------------------------------------------------------------------===// |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1022 | // Two address Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1023 | // |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1024 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1025 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1026 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1027 | let CodeSize = 2 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1028 | let Defs = [EFLAGS] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1029 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 1030 | "neg{b}\t$dst", |
| 1031 | [(set GR8:$dst, (ineg GR8:$src1)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1032 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1033 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
| 1034 | "neg{w}\t$dst", |
| 1035 | [(set GR16:$dst, (ineg GR16:$src1)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1036 | (implicit EFLAGS)]>, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1037 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
| 1038 | "neg{l}\t$dst", |
| 1039 | [(set GR32:$dst, (ineg GR32:$src1)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1040 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1041 | |
| 1042 | let Constraints = "" in { |
| 1043 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), |
| 1044 | "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1045 | [(store (ineg (loadi8 addr:$dst)), addr:$dst), |
| 1046 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1047 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), |
| 1048 | "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1049 | [(store (ineg (loadi16 addr:$dst)), addr:$dst), |
| 1050 | (implicit EFLAGS)]>, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1051 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), |
| 1052 | "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1053 | [(store (ineg (loadi32 addr:$dst)), addr:$dst), |
| 1054 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1055 | } // Constraints = "" |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1056 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1057 | |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1058 | // Match xor -1 to not. Favors these over a move imm + xor to save code size. |
| 1059 | let AddedComplexity = 15 in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1060 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 1061 | "not{b}\t$dst", |
| 1062 | [(set GR8:$dst, (not GR8:$src1))]>; |
| 1063 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
| 1064 | "not{w}\t$dst", |
| 1065 | [(set GR16:$dst, (not GR16:$src1))]>, OpSize; |
| 1066 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
| 1067 | "not{l}\t$dst", |
| 1068 | [(set GR32:$dst, (not GR32:$src1))]>; |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1069 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1070 | let Constraints = "" in { |
| 1071 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), |
| 1072 | "not{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1073 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1074 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), |
| 1075 | "not{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1076 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1077 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), |
| 1078 | "not{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1079 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1080 | } // Constraints = "" |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1081 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1082 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1083 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1084 | let Defs = [EFLAGS] in { |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1085 | let CodeSize = 2 in |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1086 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 1087 | "inc{b}\t$dst", |
| 1088 | [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>; |
Chris Lattner | c54a2f1 | 2010-03-24 01:02:12 +0000 | [diff] [blame] | 1089 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1090 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1091 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1092 | "inc{w}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1093 | [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1094 | OpSize, Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1095 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1096 | "inc{l}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1097 | [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>, |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1098 | Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1099 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1100 | let Constraints = "", CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1101 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1102 | [(store (add (loadi8 addr:$dst), 1), addr:$dst), |
| 1103 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1104 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1105 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
| 1106 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1107 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1108 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1109 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
| 1110 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1111 | Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1112 | } // Constraints = "", CodeSize = 2 |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1113 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1114 | let CodeSize = 2 in |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1115 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 1116 | "dec{b}\t$dst", |
| 1117 | [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1118 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1119 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1120 | "dec{w}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1121 | [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1122 | OpSize, Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1123 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1124 | "dec{l}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1125 | [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>, |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1126 | Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1127 | } // CodeSize = 2 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1128 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1129 | let Constraints = "", CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1130 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1131 | [(store (add (loadi8 addr:$dst), -1), addr:$dst), |
| 1132 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1133 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1134 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
| 1135 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1136 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1137 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1138 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
| 1139 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1140 | Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1141 | } // Constraints = "", CodeSize = 2 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1142 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1143 | |
| 1144 | // Logical operators... |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1145 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1146 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1147 | def AND8rr : I<0x20, MRMDestReg, |
| 1148 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1149 | "and{b}\t{$src2, $dst|$dst, $src2}", |
| 1150 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>; |
| 1151 | def AND16rr : I<0x21, MRMDestReg, |
| 1152 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1153 | "and{w}\t{$src2, $dst|$dst, $src2}", |
| 1154 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1155 | GR16:$src2))]>, OpSize; |
| 1156 | def AND32rr : I<0x21, MRMDestReg, |
| 1157 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1158 | "and{l}\t{$src2, $dst|$dst, $src2}", |
| 1159 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1160 | GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1161 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1162 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1163 | // AND instructions with the destination register in REG and the source register |
| 1164 | // in R/M. Included for the disassembler. |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1165 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1166 | def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1167 | "and{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1168 | def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst), |
| 1169 | (ins GR16:$src1, GR16:$src2), |
| 1170 | "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1171 | def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst), |
| 1172 | (ins GR32:$src1, GR32:$src2), |
| 1173 | "and{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1174 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1175 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1176 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1177 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1178 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1179 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, |
| 1180 | (loadi8 addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1181 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1182 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1183 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1184 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1185 | (loadi16 addr:$src2)))]>, |
| 1186 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1187 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1188 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1189 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1190 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1191 | (loadi32 addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1192 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1193 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1194 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1195 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1196 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, |
| 1197 | imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1198 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1199 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1200 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1201 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1202 | imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1203 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1204 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1205 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1206 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1207 | imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1208 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1209 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1210 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1211 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1212 | i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1213 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1214 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1215 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1216 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1217 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1218 | i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1219 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1220 | let Constraints = "" in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1221 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1222 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1223 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1224 | [(store (and (load addr:$dst), GR8:$src), addr:$dst), |
| 1225 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1226 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1227 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1228 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1229 | [(store (and (load addr:$dst), GR16:$src), addr:$dst), |
| 1230 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1231 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1232 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1233 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1234 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1235 | [(store (and (load addr:$dst), GR32:$src), addr:$dst), |
| 1236 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1237 | def AND8mi : Ii8<0x80, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1238 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1239 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1240 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1241 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1242 | def AND16mi : Ii16<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1243 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1244 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1245 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1246 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1247 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1248 | def AND32mi : Ii32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1249 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1250 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1251 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1252 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1253 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1254 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1255 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1256 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1257 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1258 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1259 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1260 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1261 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1262 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1263 | (implicit EFLAGS)]>; |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1264 | |
| 1265 | def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src), |
| 1266 | "and{b}\t{$src, %al|%al, $src}", []>; |
| 1267 | def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src), |
| 1268 | "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1269 | def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src), |
| 1270 | "and{l}\t{$src, %eax|%eax, $src}", []>; |
| 1271 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1272 | } // Constraints = "" |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1273 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1274 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1275 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1276 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), |
| 1277 | (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1278 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1279 | [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1280 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), |
| 1281 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1282 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1283 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>, |
| 1284 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1285 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), |
| 1286 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1287 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1288 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1289 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1290 | |
| 1291 | // OR instructions with the destination register in REG and the source register |
| 1292 | // in R/M. Included for the disassembler. |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1293 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1294 | def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1295 | "or{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1296 | def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst), |
| 1297 | (ins GR16:$src1, GR16:$src2), |
| 1298 | "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1299 | def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst), |
| 1300 | (ins GR32:$src1, GR32:$src2), |
| 1301 | "or{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1302 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1303 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1304 | def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1305 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1306 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1307 | [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, |
| 1308 | (load addr:$src2)))]>; |
| 1309 | def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1310 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1311 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1312 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1, |
| 1313 | (load addr:$src2)))]>, |
| 1314 | OpSize; |
| 1315 | def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1316 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1317 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1318 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1, |
| 1319 | (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1320 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1321 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), |
| 1322 | (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1323 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1324 | [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1325 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), |
| 1326 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1327 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1328 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1, |
| 1329 | imm:$src2))]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1330 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), |
| 1331 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1332 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1333 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1, |
| 1334 | imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1335 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1336 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), |
| 1337 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1338 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1339 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1, |
| 1340 | i16immSExt8:$src2))]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1341 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), |
| 1342 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1343 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1344 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1, |
| 1345 | i32immSExt8:$src2))]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1346 | let Constraints = "" in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1347 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1348 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1349 | [(store (or (load addr:$dst), GR8:$src), addr:$dst), |
| 1350 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1351 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1352 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1353 | [(store (or (load addr:$dst), GR16:$src), addr:$dst), |
| 1354 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1355 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1356 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1357 | [(store (or (load addr:$dst), GR32:$src), addr:$dst), |
| 1358 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1359 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1360 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1361 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1362 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1363 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1364 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1365 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1366 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1367 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1368 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1369 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1370 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1371 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1372 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1373 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1374 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1375 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1376 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1377 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1378 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1379 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1380 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1381 | |
| 1382 | def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src), |
| 1383 | "or{b}\t{$src, %al|%al, $src}", []>; |
| 1384 | def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src), |
| 1385 | "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1386 | def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src), |
| 1387 | "or{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1388 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1389 | |
| 1390 | |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1391 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1392 | def XOR8rr : I<0x30, MRMDestReg, |
| 1393 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1394 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1395 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, |
| 1396 | GR8:$src2))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1397 | def XOR16rr : I<0x31, MRMDestReg, |
| 1398 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1399 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1400 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1401 | GR16:$src2))]>, OpSize; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1402 | def XOR32rr : I<0x31, MRMDestReg, |
| 1403 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1404 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1405 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1406 | GR32:$src2))]>; |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1407 | } // isCommutable = 1 |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1408 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1409 | // XOR instructions with the destination register in REG and the source register |
| 1410 | // in R/M. Included for the disassembler. |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1411 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1412 | def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1413 | "xor{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1414 | def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst), |
| 1415 | (ins GR16:$src1, GR16:$src2), |
| 1416 | "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1417 | def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst), |
| 1418 | (ins GR32:$src1, GR32:$src2), |
| 1419 | "xor{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1420 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1421 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1422 | def XOR8rm : I<0x32, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1423 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1424 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1425 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, |
| 1426 | (load addr:$src2)))]>; |
| 1427 | def XOR16rm : I<0x33, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1428 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1429 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1430 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1431 | (load addr:$src2)))]>, |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1432 | OpSize; |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1433 | def XOR32rm : I<0x33, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1434 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1435 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1436 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1437 | (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1438 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1439 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1440 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1441 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
| 1442 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>; |
| 1443 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1444 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 1445 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
| 1446 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1447 | imm:$src2))]>, OpSize; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1448 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1449 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 1450 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1451 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1452 | imm:$src2))]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1453 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 1454 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 1455 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1456 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1457 | i16immSExt8:$src2))]>, |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1458 | OpSize; |
| 1459 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 1460 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 1461 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1462 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1463 | i32immSExt8:$src2))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1464 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1465 | let Constraints = "" in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1466 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1467 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1468 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1469 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst), |
| 1470 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1471 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1472 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1473 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1474 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst), |
| 1475 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1476 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1477 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1478 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1479 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1480 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst), |
| 1481 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1482 | def XOR8mi : Ii8<0x80, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1483 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1484 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1485 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1486 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1487 | def XOR16mi : Ii16<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1488 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1489 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1490 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1491 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1492 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1493 | def XOR32mi : Ii32<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1494 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1495 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1496 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1497 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1498 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1499 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1500 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1501 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1502 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1503 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1504 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1505 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1506 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1507 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1508 | (implicit EFLAGS)]>; |
Sean Callanan | 7893ec6 | 2009-09-10 19:52:26 +0000 | [diff] [blame] | 1509 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1510 | def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src), |
| 1511 | "xor{b}\t{$src, %al|%al, $src}", []>; |
| 1512 | def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src), |
| 1513 | "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1514 | def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src), |
| 1515 | "xor{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1516 | } // Constraints = "" |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1517 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1518 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1519 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1520 | // Arithmetic. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1521 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1522 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1523 | // Register-Register Addition |
| 1524 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), |
| 1525 | (ins GR8 :$src1, GR8 :$src2), |
| 1526 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1527 | [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1528 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1529 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1530 | // Register-Register Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1531 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), |
| 1532 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1533 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1534 | [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1, |
| 1535 | GR16:$src2))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1536 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), |
| 1537 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1538 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1539 | [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1, |
| 1540 | GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1541 | } // end isConvertibleToThreeAddress |
| 1542 | } // end isCommutable |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1543 | |
Daniel Dunbar | f291be3 | 2010-03-09 22:50:46 +0000 | [diff] [blame] | 1544 | // These are alternate spellings for use by the disassembler, we mark them as |
| 1545 | // code gen only to ensure they aren't matched by the assembler. |
| 1546 | let isCodeGenOnly = 1 in { |
| 1547 | def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1548 | "add{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1549 | def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
| 1550 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
Evan Cheng | 18ac410 | 2010-04-05 22:21:09 +0000 | [diff] [blame] | 1551 | def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2), |
Daniel Dunbar | f291be3 | 2010-03-09 22:50:46 +0000 | [diff] [blame] | 1552 | "add{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 1553 | } |
| 1554 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1555 | // Register-Memory Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1556 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), |
| 1557 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1558 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1559 | [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, |
| 1560 | (load addr:$src2)))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1561 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), |
| 1562 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1563 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1564 | [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1, |
| 1565 | (load addr:$src2)))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1566 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), |
| 1567 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1568 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1569 | [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1, |
| 1570 | (load addr:$src2)))]>; |
Sean Callanan | 37be590 | 2009-09-15 20:53:57 +0000 | [diff] [blame] | 1571 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1572 | // Register-Integer Addition |
| 1573 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1574 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1575 | [(set GR8:$dst, EFLAGS, |
| 1576 | (X86add_flag GR8:$src1, imm:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1577 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1578 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1579 | // Register-Integer Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1580 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), |
| 1581 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1582 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1583 | [(set GR16:$dst, EFLAGS, |
| 1584 | (X86add_flag GR16:$src1, imm:$src2))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1585 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), |
| 1586 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1587 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1588 | [(set GR32:$dst, EFLAGS, |
| 1589 | (X86add_flag GR32:$src1, imm:$src2))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1590 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), |
| 1591 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1592 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1593 | [(set GR16:$dst, EFLAGS, |
| 1594 | (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1595 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), |
| 1596 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1597 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1598 | [(set GR32:$dst, EFLAGS, |
| 1599 | (X86add_flag GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 1600 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1601 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1602 | let Constraints = "" in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1603 | // Memory-Register Addition |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1604 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1605 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1606 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst), |
| 1607 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1608 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1609 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1610 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst), |
| 1611 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1612 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1613 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1614 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst), |
| 1615 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1616 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1617 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1618 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 1619 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1620 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1621 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1622 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst), |
| 1623 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1624 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1625 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1626 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst), |
| 1627 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1628 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1629 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1630 | [(store (add (load addr:$dst), i16immSExt8:$src2), |
| 1631 | addr:$dst), |
| 1632 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1633 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1634 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1635 | [(store (add (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1636 | addr:$dst), |
| 1637 | (implicit EFLAGS)]>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 1638 | |
| 1639 | // addition to rAX |
| 1640 | def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1641 | "add{b}\t{$src, %al|%al, $src}", []>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 1642 | def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1643 | "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 1644 | def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1645 | "add{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1646 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1647 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 1648 | let Uses = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1649 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1650 | def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1651 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1652 | [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1653 | def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), |
| 1654 | (ins GR16:$src1, GR16:$src2), |
| 1655 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1656 | [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1657 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), |
| 1658 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1659 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1660 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1661 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1662 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1663 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1664 | def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1665 | "adc{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1666 | def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst), |
| 1667 | (ins GR16:$src1, GR16:$src2), |
| 1668 | "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1669 | def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst), |
| 1670 | (ins GR32:$src1, GR32:$src2), |
| 1671 | "adc{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1672 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1673 | |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1674 | def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), |
| 1675 | (ins GR8:$src1, i8mem:$src2), |
| 1676 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1677 | [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1678 | def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), |
| 1679 | (ins GR16:$src1, i16mem:$src2), |
| 1680 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1681 | [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 1682 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1683 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), |
| 1684 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1685 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1686 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
| 1687 | def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1688 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1689 | [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1690 | def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), |
| 1691 | (ins GR16:$src1, i16imm:$src2), |
| 1692 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1693 | [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1694 | def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), |
| 1695 | (ins GR16:$src1, i16i8imm:$src2), |
| 1696 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1697 | [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>, |
| 1698 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1699 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), |
| 1700 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1701 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1702 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1703 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), |
| 1704 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1705 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1706 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1707 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1708 | let Constraints = "" in { |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1709 | def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1710 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1711 | [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>; |
| 1712 | def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1713 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1714 | [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>, |
| 1715 | OpSize; |
| 1716 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1717 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1718 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
| 1719 | def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1720 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1721 | [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
| 1722 | def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1723 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1724 | [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
| 1725 | OpSize; |
| 1726 | def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1727 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1728 | [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1729 | OpSize; |
| 1730 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1731 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1732 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
| 1733 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1734 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1735 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1736 | |
| 1737 | def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src), |
| 1738 | "adc{b}\t{$src, %al|%al, $src}", []>; |
| 1739 | def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src), |
| 1740 | "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1741 | def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src), |
| 1742 | "adc{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1743 | } // Constraints = "" |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 1744 | } // Uses = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1745 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1746 | // Register-Register Subtraction |
| 1747 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1748 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1749 | [(set GR8:$dst, EFLAGS, |
| 1750 | (X86sub_flag GR8:$src1, GR8:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1751 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
| 1752 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1753 | [(set GR16:$dst, EFLAGS, |
| 1754 | (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1755 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
| 1756 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1757 | [(set GR32:$dst, EFLAGS, |
| 1758 | (X86sub_flag GR32:$src1, GR32:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1759 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1760 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1761 | def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1762 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1763 | def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst), |
| 1764 | (ins GR16:$src1, GR16:$src2), |
| 1765 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1766 | def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst), |
| 1767 | (ins GR32:$src1, GR32:$src2), |
| 1768 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1769 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1770 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1771 | // Register-Memory Subtraction |
| 1772 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), |
| 1773 | (ins GR8 :$src1, i8mem :$src2), |
| 1774 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1775 | [(set GR8:$dst, EFLAGS, |
| 1776 | (X86sub_flag GR8:$src1, (load addr:$src2)))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1777 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), |
| 1778 | (ins GR16:$src1, i16mem:$src2), |
| 1779 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1780 | [(set GR16:$dst, EFLAGS, |
| 1781 | (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1782 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), |
| 1783 | (ins GR32:$src1, i32mem:$src2), |
| 1784 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1785 | [(set GR32:$dst, EFLAGS, |
| 1786 | (X86sub_flag GR32:$src1, (load addr:$src2)))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1787 | |
| 1788 | // Register-Integer Subtraction |
| 1789 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), |
| 1790 | (ins GR8:$src1, i8imm:$src2), |
| 1791 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1792 | [(set GR8:$dst, EFLAGS, |
| 1793 | (X86sub_flag GR8:$src1, imm:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1794 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), |
| 1795 | (ins GR16:$src1, i16imm:$src2), |
| 1796 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1797 | [(set GR16:$dst, EFLAGS, |
| 1798 | (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1799 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), |
| 1800 | (ins GR32:$src1, i32imm:$src2), |
| 1801 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1802 | [(set GR32:$dst, EFLAGS, |
| 1803 | (X86sub_flag GR32:$src1, imm:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1804 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), |
| 1805 | (ins GR16:$src1, i16i8imm:$src2), |
| 1806 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1807 | [(set GR16:$dst, EFLAGS, |
| 1808 | (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1809 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), |
| 1810 | (ins GR32:$src1, i32i8imm:$src2), |
| 1811 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1812 | [(set GR32:$dst, EFLAGS, |
| 1813 | (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1814 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1815 | let Constraints = "" in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1816 | // Memory-Register Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1817 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1818 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1819 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst), |
| 1820 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1821 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1822 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1823 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst), |
| 1824 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1825 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1826 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1827 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst), |
| 1828 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1829 | |
| 1830 | // Memory-Integer Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1831 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1832 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1833 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 1834 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1835 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1836 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1837 | [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst), |
| 1838 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1839 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1840 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1841 | [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst), |
| 1842 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1843 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1844 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1845 | [(store (sub (load addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1846 | addr:$dst), |
| 1847 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1848 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1849 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1850 | [(store (sub (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1851 | addr:$dst), |
| 1852 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1853 | |
| 1854 | def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src), |
| 1855 | "sub{b}\t{$src, %al|%al, $src}", []>; |
| 1856 | def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src), |
| 1857 | "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1858 | def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src), |
| 1859 | "sub{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1860 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1861 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 1862 | let Uses = [EFLAGS] in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1863 | def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), |
| 1864 | (ins GR8:$src1, GR8:$src2), |
| 1865 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1866 | [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1867 | def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), |
| 1868 | (ins GR16:$src1, GR16:$src2), |
| 1869 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1870 | [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1871 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), |
| 1872 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1873 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1874 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1875 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1876 | let Constraints = "" in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1877 | def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
| 1878 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1879 | [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1880 | def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 1881 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1882 | [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 1883 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1884 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1885 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1886 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Chris Lattner | 8f60e4d | 2010-02-05 22:56:11 +0000 | [diff] [blame] | 1887 | def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), |
| 1888 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1889 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1890 | def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 1891 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1892 | [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 1893 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1894 | def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 1895 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1896 | [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 1897 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1898 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1899 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1900 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1901 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1902 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1903 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1904 | |
| 1905 | def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src), |
| 1906 | "sbb{b}\t{$src, %al|%al, $src}", []>; |
| 1907 | def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src), |
| 1908 | "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1909 | def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src), |
| 1910 | "sbb{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1911 | } // Constraints = "" |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1912 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1913 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1914 | def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1915 | "sbb{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1916 | def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst), |
| 1917 | (ins GR16:$src1, GR16:$src2), |
| 1918 | "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1919 | def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst), |
| 1920 | (ins GR32:$src1, GR32:$src2), |
| 1921 | "sbb{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1922 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1923 | |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1924 | def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), |
| 1925 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1926 | [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1927 | def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), |
| 1928 | (ins GR16:$src1, i16mem:$src2), |
| 1929 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1930 | [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 1931 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1932 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), |
| 1933 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1934 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1935 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1936 | def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1937 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1938 | [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1939 | def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), |
| 1940 | (ins GR16:$src1, i16imm:$src2), |
| 1941 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1942 | [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1943 | def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), |
| 1944 | (ins GR16:$src1, i16i8imm:$src2), |
| 1945 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1946 | [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>, |
| 1947 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1948 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), |
| 1949 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1950 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1951 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 1952 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), |
| 1953 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1954 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 1955 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 1956 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1957 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1958 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1959 | let Defs = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1960 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1961 | // Register-Register Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1962 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1963 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1964 | [(set GR16:$dst, EFLAGS, |
| 1965 | (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1966 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1967 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1968 | [(set GR32:$dst, EFLAGS, |
| 1969 | (X86smul_flag GR32:$src1, GR32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1970 | } |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1971 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1972 | // Register-Memory Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1973 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), |
| 1974 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1975 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1976 | [(set GR16:$dst, EFLAGS, |
| 1977 | (X86smul_flag GR16:$src1, (load addr:$src2)))]>, |
| 1978 | TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1979 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), |
| 1980 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1981 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1982 | [(set GR32:$dst, EFLAGS, |
| 1983 | (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1984 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1985 | } // end Two Address instructions |
| 1986 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1987 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1988 | let Defs = [EFLAGS] in { |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1989 | // Register-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1990 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1991 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1992 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1993 | [(set GR16:$dst, EFLAGS, |
| 1994 | (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1995 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1996 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1997 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1998 | [(set GR32:$dst, EFLAGS, |
| 1999 | (X86smul_flag GR32:$src1, imm:$src2))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2000 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2001 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2002 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2003 | [(set GR16:$dst, EFLAGS, |
| 2004 | (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>, |
| 2005 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2006 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2007 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2008 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2009 | [(set GR32:$dst, EFLAGS, |
| 2010 | (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2011 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2012 | // Memory-Integer Signed Integer Multiply |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2013 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2014 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2015 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2016 | [(set GR16:$dst, EFLAGS, |
| 2017 | (X86smul_flag (load addr:$src1), imm:$src2))]>, |
| 2018 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2019 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2020 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2021 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2022 | [(set GR32:$dst, EFLAGS, |
| 2023 | (X86smul_flag (load addr:$src1), imm:$src2))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2024 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2025 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2026 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2027 | [(set GR16:$dst, EFLAGS, |
| 2028 | (X86smul_flag (load addr:$src1), |
| 2029 | i16immSExt8:$src2))]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2030 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2031 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2032 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2033 | [(set GR32:$dst, EFLAGS, |
| 2034 | (X86smul_flag (load addr:$src1), |
| 2035 | i32immSExt8:$src2))]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2036 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2037 | |
| 2038 | //===----------------------------------------------------------------------===// |
| 2039 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2040 | // |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2041 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2042 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Daniel Dunbar | b93c72c | 2010-03-08 21:10:36 +0000 | [diff] [blame] | 2043 | def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2044 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2045 | [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>; |
Daniel Dunbar | b93c72c | 2010-03-08 21:10:36 +0000 | [diff] [blame] | 2046 | def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2047 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2048 | [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2), |
| 2049 | 0))]>, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2050 | OpSize; |
Daniel Dunbar | b93c72c | 2010-03-08 21:10:36 +0000 | [diff] [blame] | 2051 | def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2052 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2053 | [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2), |
| 2054 | 0))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2055 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2056 | |
Sean Callanan | 4a93b71 | 2009-09-01 18:14:18 +0000 | [diff] [blame] | 2057 | def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src), |
| 2058 | "test{b}\t{$src, %al|%al, $src}", []>; |
| 2059 | def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src), |
| 2060 | "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2061 | def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src), |
| 2062 | "test{l}\t{$src, %eax|%eax, $src}", []>; |
| 2063 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2064 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2065 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2066 | [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)), |
| 2067 | 0))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2068 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2069 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2070 | [(set EFLAGS, (X86cmp (and GR16:$src1, |
| 2071 | (loadi16 addr:$src2)), 0))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2072 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2073 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2074 | [(set EFLAGS, (X86cmp (and GR32:$src1, |
| 2075 | (loadi32 addr:$src2)), 0))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2076 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2077 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2078 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2079 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2080 | [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2081 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2082 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2083 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2084 | [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>, |
| 2085 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2086 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2087 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2088 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2089 | [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2090 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2091 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2092 | (outs), (ins i8mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2093 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2094 | [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2), |
| 2095 | 0))]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2096 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2097 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2098 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2099 | [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2), |
| 2100 | 0))]>, OpSize; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2101 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2102 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2103 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2104 | [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2), |
| 2105 | 0))]>; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2106 | } // Defs = [EFLAGS] |
| 2107 | |
| 2108 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2109 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2110 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2111 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2112 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2113 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2114 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2115 | // Integer comparisons |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2116 | let Defs = [EFLAGS] in { |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2117 | def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src), |
| 2118 | "cmp{b}\t{$src, %al|%al, $src}", []>; |
| 2119 | def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src), |
| 2120 | "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2121 | def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src), |
| 2122 | "cmp{l}\t{$src, %eax|%eax, $src}", []>; |
| 2123 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2124 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2125 | (outs), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2126 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2127 | [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2128 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2129 | (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2130 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2131 | [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2132 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2133 | (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2134 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2135 | [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2136 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2137 | (outs), (ins i8mem :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2138 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2139 | [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2140 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2141 | (outs), (ins i16mem:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2142 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2143 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>, |
| 2144 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2145 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2146 | (outs), (ins i32mem:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2147 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2148 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2149 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2150 | (outs), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2151 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2152 | [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2153 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2154 | (outs), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2155 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2156 | [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>, |
| 2157 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2158 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2159 | (outs), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2160 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2161 | [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>; |
Daniel Dunbar | 1e8ee89 | 2010-03-09 22:50:40 +0000 | [diff] [blame] | 2162 | |
| 2163 | // These are alternate spellings for use by the disassembler, we mark them as |
| 2164 | // code gen only to ensure they aren't matched by the assembler. |
| 2165 | let isCodeGenOnly = 1 in { |
| 2166 | def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2), |
| 2167 | "cmp{b}\t{$src2, $src1|$src1, $src2}", []>; |
| 2168 | def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2169 | "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize; |
| 2170 | def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2171 | "cmp{l}\t{$src2, $src1|$src1, $src2}", []>; |
| 2172 | } |
| 2173 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2174 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2175 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2176 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2177 | [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2178 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2179 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2180 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2181 | [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2182 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2183 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2184 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2185 | [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2186 | def CMP8mi : Ii8 <0x80, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2187 | (outs), (ins i8mem :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2188 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2189 | [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2190 | def CMP16mi : Ii16<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2191 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2192 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2193 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>, |
| 2194 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2195 | def CMP32mi : Ii32<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2196 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2197 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2198 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2199 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2200 | (outs), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2201 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2202 | [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>, |
| 2203 | OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2204 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2205 | (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2206 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2207 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), |
| 2208 | i16immSExt8:$src2))]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2209 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2210 | (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2211 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2212 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), |
| 2213 | i32immSExt8:$src2))]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2214 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2215 | (outs), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2216 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2217 | [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2218 | } // Defs = [EFLAGS] |
| 2219 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2220 | // Bit tests. |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2221 | // TODO: BTC, BTR, and BTS |
| 2222 | let Defs = [EFLAGS] in { |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 2223 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2224 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2225 | [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB; |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 2226 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2227 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2228 | [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB; |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2229 | |
| 2230 | // Unlike with the register+register form, the memory+register form of the |
| 2231 | // bt instruction does not ignore the high bits of the index. From ISel's |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2232 | // perspective, this is pretty bizarre. Make these instructions disassembly |
| 2233 | // only for now. |
| 2234 | |
| 2235 | def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2236 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2237 | // [(X86bt (loadi16 addr:$src1), GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2238 | // (implicit EFLAGS)] |
| 2239 | [] |
| 2240 | >, OpSize, TB, Requires<[FastBTMem]>; |
| 2241 | def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2242 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2243 | // [(X86bt (loadi32 addr:$src1), GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2244 | // (implicit EFLAGS)] |
| 2245 | [] |
| 2246 | >, TB, Requires<[FastBTMem]>; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2247 | |
| 2248 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2249 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2250 | [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, |
| 2251 | OpSize, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2252 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2253 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2254 | [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2255 | // Note that these instructions don't need FastBTMem because that |
| 2256 | // only applies when the other operand is in a register. When it's |
| 2257 | // an immediate, bt is still fast. |
| 2258 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2259 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2260 | [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) |
| 2261 | ]>, OpSize, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2262 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2263 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2264 | [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) |
| 2265 | ]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2266 | |
| 2267 | def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2268 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2269 | def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2270 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2271 | def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2272 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2273 | def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2274 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2275 | def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2276 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2277 | def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2278 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2279 | def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2280 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2281 | def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2282 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2283 | |
| 2284 | def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2285 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2286 | def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2287 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2288 | def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2289 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2290 | def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2291 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2292 | def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2293 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2294 | def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2295 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2296 | def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2297 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2298 | def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2299 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2300 | |
| 2301 | def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2302 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2303 | def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2304 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2305 | def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2306 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2307 | def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2308 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2309 | def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2310 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2311 | def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2312 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2313 | def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2314 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2315 | def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2316 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2317 | } // Defs = [EFLAGS] |
| 2318 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 2319 | |
| 2320 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 2321 | // Atomic support |
| 2322 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2323 | |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 2324 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2325 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 2326 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 2327 | let Constraints = "$val = $dst" in { |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2328 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), |
| 2329 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
| 2330 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2331 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), |
| 2332 | (ins GR16:$val, i16mem:$ptr), |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2333 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
| 2334 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, |
| 2335 | OpSize; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2336 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), |
| 2337 | (ins GR32:$val, i32mem:$ptr), |
| 2338 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
| 2339 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; |
| 2340 | def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), |
| 2341 | (ins GR64:$val,i64mem:$ptr), |
| 2342 | "xchg{q}\t{$val, $ptr|$ptr, $val}", |
| 2343 | [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2344 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2345 | def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), |
| 2346 | "xchg{b}\t{$val, $src|$src, $val}", []>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2347 | def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), |
| 2348 | "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize; |
| 2349 | def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), |
| 2350 | "xchg{l}\t{$val, $src|$src, $val}", []>; |
| 2351 | def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), |
| 2352 | "xchg{q}\t{$val, $src|$src, $val}", []>; |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2353 | } |
| 2354 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2355 | def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), |
| 2356 | "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2357 | def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), |
| 2358 | "xchg{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2359 | def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), |
| 2360 | "xchg{q}\t{$src, %rax|%rax, $src}", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2361 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 2362 | |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2363 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2364 | def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
| 2365 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2366 | def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
| 2367 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2368 | def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 2369 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2370 | def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
| 2371 | "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2372 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2373 | let mayLoad = 1, mayStore = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2374 | def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
| 2375 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2376 | def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
| 2377 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2378 | def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
| 2379 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2380 | def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
| 2381 | "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2382 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2383 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2384 | |
| 2385 | def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
| 2386 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2387 | def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
| 2388 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2389 | def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 2390 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2391 | def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
| 2392 | "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2393 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2394 | let mayLoad = 1, mayStore = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2395 | def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
| 2396 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2397 | def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
| 2398 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2399 | def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
| 2400 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2401 | def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
| 2402 | "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2403 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2404 | |
Evan Cheng | b093bd0 | 2010-01-08 01:29:19 +0000 | [diff] [blame] | 2405 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2406 | def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), |
| 2407 | "cmpxchg8b\t$dst", []>, TB; |
| 2408 | |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2409 | let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in |
| 2410 | def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), |
| 2411 | "cmpxchg16b\t$dst", []>, TB; |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 2412 | |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 2413 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 2414 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 2415 | // Lock instruction prefix |
| 2416 | def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; |
| 2417 | |
| 2418 | // Repeat string operation instruction prefixes |
| 2419 | // These uses the DF flag in the EFLAGS register to inc or dec ECX |
| 2420 | let Defs = [ECX], Uses = [ECX,EFLAGS] in { |
| 2421 | // Repeat (used with INS, OUTS, MOVS, LODS and STOS) |
| 2422 | def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; |
| 2423 | // Repeat while not equal (used with CMPS and SCAS) |
| 2424 | def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; |
| 2425 | } |
| 2426 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 2427 | |
Sean Callanan | 9a86f10 | 2009-09-16 22:59:28 +0000 | [diff] [blame] | 2428 | // String manipulation instructions |
| 2429 | |
| 2430 | def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>; |
| 2431 | def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2432 | def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2433 | def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2434 | |
| 2435 | def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>; |
| 2436 | def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize; |
| 2437 | def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>; |
| 2438 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2439 | |
| 2440 | // Flag instructions |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2441 | def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; |
| 2442 | def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; |
| 2443 | def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; |
| 2444 | def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; |
| 2445 | def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; |
| 2446 | def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; |
| 2447 | def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; |
| 2448 | |
| 2449 | def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; |
| 2450 | |
| 2451 | // Table lookup instructions |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2452 | def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>; |
| 2453 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2454 | |
Dan Gohman | e220c4b | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 2455 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2456 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 2457 | // Subsystems. |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2458 | //===----------------------------------------------------------------------===// |
| 2459 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 2460 | // Floating Point Stack Support |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2461 | include "X86InstrFPStack.td" |
Chris Lattner | 36fe6d2 | 2008-01-10 05:50:42 +0000 | [diff] [blame] | 2462 | include "X86Instr64bit.td" |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 2463 | |
Chris Lattner | 35649fc | 2010-10-05 06:33:16 +0000 | [diff] [blame] | 2464 | include "X86InstrCMovSetCC.td" |
Chris Lattner | 8917cd3 | 2010-10-05 06:52:26 +0000 | [diff] [blame] | 2465 | include "X86InstrExtension.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 2466 | include "X86InstrControl.td" |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame^] | 2467 | include "X86InstrShiftRotate.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 2468 | |
David Greene | 51898d7 | 2010-02-09 23:52:19 +0000 | [diff] [blame] | 2469 | // SIMD support (SSE, MMX and AVX) |
David Greene | 51898d7 | 2010-02-09 23:52:19 +0000 | [diff] [blame] | 2470 | include "X86InstrFragmentsSIMD.td" |
| 2471 | |
Bruno Cardoso Lopes | 6b7e916 | 2010-07-23 00:54:35 +0000 | [diff] [blame] | 2472 | // FMA - Fused Multiply-Add support (requires FMA) |
Bruno Cardoso Lopes | 6b7e916 | 2010-07-23 00:54:35 +0000 | [diff] [blame] | 2473 | include "X86InstrFMA.td" |
| 2474 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 2475 | // SSE, MMX and 3DNow! vector support. |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2476 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 2477 | include "X86InstrMMX.td" |
Chris Lattner | 7330d97 | 2010-10-02 23:06:23 +0000 | [diff] [blame] | 2478 | include "X86Instr3DNow.td" |
| 2479 | |
Chris Lattner | d071b83 | 2010-10-05 06:06:53 +0000 | [diff] [blame] | 2480 | include "X86InstrVMX.td" |
| 2481 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 2482 | // System instructions. |
| 2483 | include "X86InstrSystem.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 2484 | |
| 2485 | // Compiler Pseudo Instructions and Pat Patterns |
| 2486 | include "X86InstrCompiler.td" |
| 2487 | |