Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 901b5750b2af095bb0e359f4d2c3debef3ad57e6 / . / lib / Target / ARM / ARMScheduleV7.td
blob: bbbf41397566fac4cf9cb61f30c041d77841b13d [file] [log] [blame]
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]1//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v7 processors.
11//
12//===----------------------------------------------------------------------===//
13
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]14//
15// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
16//
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]17// Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]18//
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]19def CortexA8Itineraries : ProcessorItineraries<[
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]20
21 // Two fully-pipelined integer ALU pipelines
22 //
23 // No operand cycles
24 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
25 //
26 // Binary Instructions that produce a result
27 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
28 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
29 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
30 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
31 //
32 // Unary Instructions that produce a result
33 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
34 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
35 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
36 //
37 // Compare instructions
38 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
39 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
40 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
41 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
42 //
43 // Move instructions, unconditional
44 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
45 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
47 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
48 //
49 // Move instructions, conditional
50 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
51 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
52 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
53 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
54
55 // Integer multiply pipeline
56 // Result written in E5, but that is relative to the last cycle of multicycle,
57 // so we use 6 for those cases
58 //
59 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
60 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
61 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
62 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
63 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
64 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
65 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
66 InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
67 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
68 InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
69 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
70
71 // Integer load pipeline
72 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]73 // loads have an extra cycle of latency, but are fully pipelined
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]74 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]75 //
76 // Immediate offset
77 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
78 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
79 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
80 //
81 // Register offset
82 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
83 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
84 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
85 //
86 // Scaled register offset, issues over 2 cycles
87 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
88 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]89 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]90 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
91 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
92 //
93 // Immediate offset with update
94 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
95 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
96 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
97 //
98 // Register offset with update
99 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
100 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
101 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
102 //
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
105 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]106 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]107 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
108 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
109 //
110 // Load multiple
111 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
112 InstrStage<2, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]113 InstrStage<2, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]114 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
115 InstrStage<1, [FU_LdSt0]>]>,
116
117 // Integer store pipeline
118 //
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]119 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]120 //
121 // Immediate offset
122 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]123 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
124 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]125 //
126 // Register offset
127 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]128 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
129 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]130 //
131 // Scaled register offset, issues over 2 cycles
132 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
133 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]134 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]135 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
136 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
137 //
138 // Immediate offset with update
139 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
140 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
141 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
142 //
143 // Register offset with update
144 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
145 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
146 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
147 //
148 // Scaled register offset with update, issues over 2 cycles
149 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
150 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]151 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]152 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
153 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
154 //
155 // Store multiple
156 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
157 InstrStage<2, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]158 InstrStage<2, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]159 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
160 InstrStage<1, [FU_LdSt0]>]>,
161
162 // Branch
163 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]164 // no delay slots, so the latency of a branch is unimportant
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]165 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
166
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]167 // VFP
168 // Issue through integer pipeline, and execute in NEON unit. We assume
169 // RunFast mode so that NFP pipeline is used for single-precision when
170 // possible.
171 //
172 // FP Special Register to Integer Register File Move
173 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]174 InstrStage<1, [FU_NLSPipe]>]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]175 //
176 // Single-precision FP Unary
177 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
178 InstrStage<1, [FU_NPipe]>], [7, 1]>,
179 //
180 // Double-precision FP Unary
181 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
182 InstrStage<4, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]183 InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]184 //
185 // Single-precision FP Compare
186 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwineb368aa2009-11-18 18:39:57 +0000[diff] [blame]187 InstrStage<1, [FU_NPipe]>], [1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]188 //
189 // Double-precision FP Compare
190 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
191 InstrStage<4, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]192 InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]193 //
194 // Single to Double FP Convert
195 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
196 InstrStage<7, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]197 InstrStage<7, [FU_NLSPipe]>], [7, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]198 //
199 // Double to Single FP Convert
200 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
201 InstrStage<5, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]202 InstrStage<5, [FU_NLSPipe]>], [5, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]203 //
204 // Single-Precision FP to Integer Convert
205 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
206 InstrStage<1, [FU_NPipe]>], [7, 1]>,
207 //
208 // Double-Precision FP to Integer Convert
209 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
210 InstrStage<8, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]211 InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]212 //
213 // Integer to Single-Precision FP Convert
214 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
215 InstrStage<1, [FU_NPipe]>], [7, 1]>,
216 //
217 // Integer to Double-Precision FP Convert
218 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
219 InstrStage<8, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]220 InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]221 //
222 // Single-precision FP ALU
223 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwineb368aa2009-11-18 18:39:57 +0000[diff] [blame]224 InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]225 //
226 // Double-precision FP ALU
227 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
228 InstrStage<9, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]229 InstrStage<9, [FU_NLSPipe]>], [9, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]230 //
231 // Single-precision FP Multiply
232 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwineb368aa2009-11-18 18:39:57 +0000[diff] [blame]233 InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]234 //
235 // Double-precision FP Multiply
236 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
237 InstrStage<11, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]238 InstrStage<11, [FU_NLSPipe]>], [11, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]239 //
240 // Single-precision FP MAC
241 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwineb368aa2009-11-18 18:39:57 +0000[diff] [blame]242 InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]243 //
244 // Double-precision FP MAC
245 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
246 InstrStage<19, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]247 InstrStage<19, [FU_NLSPipe]>], [19, 2, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]248 //
249 // Single-precision FP DIV
250 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
251 InstrStage<20, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]252 InstrStage<20, [FU_NLSPipe]>], [20, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]253 //
254 // Double-precision FP DIV
255 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
256 InstrStage<29, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]257 InstrStage<29, [FU_NLSPipe]>], [29, 1, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]258 //
259 // Single-precision FP SQRT
260 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
261 InstrStage<19, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]262 InstrStage<19, [FU_NLSPipe]>], [19, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]263 //
264 // Double-precision FP SQRT
265 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
266 InstrStage<29, [FU_NPipe], 0>,
David Goodwindfaea1c2009-11-23 17:34:12 +0000[diff] [blame]267 InstrStage<29, [FU_NLSPipe]>], [29, 1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]268 //
269 // Single-precision FP Load
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]270 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]271 InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]272 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]273 InstrStage<1, [FU_LdSt0], 0>,
274 InstrStage<1, [FU_NLSPipe]>]>,
275 //
276 // Double-precision FP Load
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]277 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]278 InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
279 InstrStage<1, [FU_Pipe0], 0>,
280 InstrStage<1, [FU_Pipe1]>,
281 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
282 InstrStage<1, [FU_LdSt0], 0>,
283 InstrStage<1, [FU_NLSPipe]>]>,
284 //
285 // FP Load Multiple
286 // use FU_Issue to enforce the 1 load/store per cycle limit
287 InstrItinData<IIC_fpLoadm, [InstrStage<3, [FU_Issue], 0>,
288 InstrStage<2, [FU_Pipe0], 0>,
289 InstrStage<2, [FU_Pipe1]>,
290 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
291 InstrStage<1, [FU_LdSt0], 0>,
292 InstrStage<1, [FU_NLSPipe]>]>,
293 //
294 // Single-precision FP Store
295 // use FU_Issue to enforce the 1 load/store per cycle limit
296 InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
297 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
298 InstrStage<1, [FU_LdSt0], 0>,
299 InstrStage<1, [FU_NLSPipe]>]>,
300 //
301 // Double-precision FP Store
302 // use FU_Issue to enforce the 1 load/store per cycle limit
303 InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
304 InstrStage<1, [FU_Pipe0], 0>,
305 InstrStage<1, [FU_Pipe1]>,
306 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
307 InstrStage<1, [FU_LdSt0], 0>,
308 InstrStage<1, [FU_NLSPipe]>]>,
309 //
310 // FP Store Multiple
311 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]312 InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]313 InstrStage<2, [FU_Pipe0], 0>,
314 InstrStage<2, [FU_Pipe1]>,
315 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
316 InstrStage<1, [FU_LdSt0], 0>,
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]317 InstrStage<1, [FU_NLSPipe]>]>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]318
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]319 // NEON
320 // Issue through integer pipeline, and execute in NEON unit.
321 //
322 // VLD1
323 InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>,
324 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
325 InstrStage<1, [FU_LdSt0], 0>,
326 InstrStage<1, [FU_NLSPipe]>]>,
327 //
328 // VLD2
329 InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>,
330 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
331 InstrStage<1, [FU_LdSt0], 0>,
332 InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
333 //
334 // VLD3
335 InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>,
336 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
337 InstrStage<1, [FU_LdSt0], 0>,
338 InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
339 //
340 // VLD4
341 InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>,
342 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
343 InstrStage<1, [FU_LdSt0], 0>,
344 InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
345 //
346 // VST
347 InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>,
348 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
349 InstrStage<1, [FU_LdSt0], 0>,
350 InstrStage<1, [FU_NLSPipe]>]>,
351 //
352 // Double-register FP Unary
353 InstrItinData<IIC_VUNAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
354 InstrStage<1, [FU_NPipe]>], [5, 2]>,
355 //
356 // Quad-register FP Unary
357 // Result written in N5, but that is relative to the last cycle of multicycle,
358 // so we use 6 for those cases
359 InstrItinData<IIC_VUNAQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
360 InstrStage<2, [FU_NPipe]>], [6, 2]>,
361 //
362 // Double-register FP Binary
363 InstrItinData<IIC_VBIND, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
364 InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
365 //
366 // Quad-register FP Binary
367 // Result written in N5, but that is relative to the last cycle of multicycle,
368 // so we use 6 for those cases
369 InstrItinData<IIC_VBINQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
370 InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
371 //
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]372 // Move Immediate
373 InstrItinData<IIC_VMOVImm, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
374 InstrStage<1, [FU_NPipe]>], [3]>,
375 //
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]376 // Double-register Permute Move
377 InstrItinData<IIC_VMOVD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
378 InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
379 //
380 // Quad-register Permute Move
381 // Result written in N2, but that is relative to the last cycle of multicycle,
382 // so we use 3 for those cases
383 InstrItinData<IIC_VMOVQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
384 InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
385 //
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]386 // Integer to Single-precision Move
387 InstrItinData<IIC_VMOVIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
388 InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
389 //
390 // Integer to Double-precision Move
391 InstrItinData<IIC_VMOVID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
392 InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
393 //
394 // Single-precision to Integer Move
395 InstrItinData<IIC_VMOVSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
396 InstrStage<1, [FU_NLSPipe]>], [20, 1]>,
397 //
398 // Double-precision to Integer Move
399 InstrItinData<IIC_VMOVDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
400 InstrStage<1, [FU_NLSPipe]>], [20, 20, 1]>,
401 //
402 // Integer to Lane Move
403 InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
404 InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
405 //
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]406 // Double-register Permute
407 InstrItinData<IIC_VPERMD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
408 InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
409 //
410 // Quad-register Permute
411 // Result written in N2, but that is relative to the last cycle of multicycle,
412 // so we use 3 for those cases
413 InstrItinData<IIC_VPERMQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
414 InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
415 //
416 // Quad-register Permute (3 cycle issue)
417 // Result written in N2, but that is relative to the last cycle of multicycle,
418 // so we use 4 for those cases
419 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
420 InstrStage<1, [FU_NLSPipe]>,
421 InstrStage<1, [FU_NPipe], 0>,
422 InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
423 //
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]424 // Double-register FP Multiple-Accumulate
425 InstrItinData<IIC_VMACD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
426 InstrStage<1, [FU_NPipe]>], [9, 2, 2, 3]>,
427 //
428 // Quad-register FP Multiple-Accumulate
429 // Result written in N9, but that is relative to the last cycle of multicycle,
430 // so we use 10 for those cases
431 InstrItinData<IIC_VMACQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
432 InstrStage<2, [FU_NPipe]>], [10, 2, 2, 3]>,
433 //
434 // Double-register Reciprical Step
435 InstrItinData<IIC_VRECSD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
436 InstrStage<1, [FU_NPipe]>], [9, 2, 2]>,
437 //
438 // Quad-register Reciprical Step
439 InstrItinData<IIC_VRECSQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
440 InstrStage<2, [FU_NPipe]>], [10, 2, 2]>,
441 //
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]442 // Double-register Integer Count
443 InstrItinData<IIC_VCNTiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]444 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]445 //
446 // Quad-register Integer Count
447 // Result written in N3, but that is relative to the last cycle of multicycle,
448 // so we use 4 for those cases
449 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]450 InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]451 //
452 // Double-register Integer Unary
453 InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
454 InstrStage<1, [FU_NPipe]>], [4, 2]>,
455 //
456 // Quad-register Integer Unary
457 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
458 InstrStage<1, [FU_NPipe]>], [4, 2]>,
459 //
460 // Double-register Integer Q-Unary
461 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
462 InstrStage<1, [FU_NPipe]>], [4, 1]>,
463 //
464 // Quad-register Integer CountQ-Unary
465 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
466 InstrStage<1, [FU_NPipe]>], [4, 1]>,
467 //
468 // Double-register Integer Binary
469 InstrItinData<IIC_VBINiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
470 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
471 //
472 // Quad-register Integer Binary
473 InstrItinData<IIC_VBINiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
474 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
475 //
476 // Double-register Integer Binary (4 cycle)
477 InstrItinData<IIC_VBINi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
478 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
479 //
480 // Quad-register Integer Binary (4 cycle)
481 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
482 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
483 //
484 // Double-register Integer Subtract
485 InstrItinData<IIC_VSUBiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
486 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
487 //
488 // Quad-register Integer Subtract
489 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
490 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
491 //
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]492 // Double-register Integer Shift
493 InstrItinData<IIC_VSHLiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
494 InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
495 //
496 // Quad-register Integer Shift
497 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
498 InstrStage<2, [FU_NPipe]>], [4, 1, 1]>,
499 //
500 // Double-register Integer Shift (4 cycle)
501 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
502 InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
503 //
504 // Quad-register Integer Shift (4 cycle)
505 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
506 InstrStage<2, [FU_NPipe]>], [5, 1, 1]>,
507 //
508 // Double-register Integer Pair Add Long
509 InstrItinData<IIC_VPALiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
510 InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
511 //
512 // Quad-register Integer Pair Add Long
513 InstrItinData<IIC_VPALiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
514 InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
515 //
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]516 // Double-register Integer Multiply (.8, .16)
517 InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
518 InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
519 //
520 // Double-register Integer Multiply (.32)
521 InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
522 InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
523 //
524 // Quad-register Integer Multiply (.8, .16)
525 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
526 InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
527 //
528 // Quad-register Integer Multiply (.32)
529 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
530 InstrStage<1, [FU_NPipe]>,
531 InstrStage<2, [FU_NLSPipe], 0>,
David Goodwin36bff0c2009-09-25 18:38:29 +0000[diff] [blame]532 InstrStage<3, [FU_NPipe]>], [9, 2, 1]>,
533 //
534 // Double-register Integer Multiply-Accumulate (.8, .16)
535 InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
536 InstrStage<1, [FU_NPipe]>], [6, 2, 2, 3]>,
537 //
538 // Double-register Integer Multiply-Accumulate (.32)
539 InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
540 InstrStage<2, [FU_NPipe]>], [7, 2, 1, 3]>,
541 //
542 // Quad-register Integer Multiply-Accumulate (.8, .16)
543 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
544 InstrStage<2, [FU_NPipe]>], [7, 2, 2, 3]>,
545 //
546 // Quad-register Integer Multiply-Accumulate (.32)
547 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
548 InstrStage<1, [FU_NPipe]>,
549 InstrStage<2, [FU_NLSPipe], 0>,
550 InstrStage<3, [FU_NPipe]>], [9, 2, 1, 3]>,
551 //
552 // Double-register VEXT
553 InstrItinData<IIC_VEXTD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
554 InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
555 //
556 // Quad-register VEXT
557 InstrItinData<IIC_VEXTQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
558 InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
559 //
560 // VTB
561 InstrItinData<IIC_VTB1, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
562 InstrStage<2, [FU_NLSPipe]>], [3, 2, 1]>,
563 InstrItinData<IIC_VTB2, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
564 InstrStage<2, [FU_NLSPipe]>], [3, 2, 2, 1]>,
565 InstrItinData<IIC_VTB3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
566 InstrStage<1, [FU_NLSPipe]>,
567 InstrStage<1, [FU_NPipe], 0>,
568 InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 1]>,
569 InstrItinData<IIC_VTB4, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
570 InstrStage<1, [FU_NLSPipe]>,
571 InstrStage<1, [FU_NPipe], 0>,
572 InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 3, 1]>,
573 //
574 // VTBX
575 InstrItinData<IIC_VTBX1, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
576 InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 1]>,
577 InstrItinData<IIC_VTBX2, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
578 InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 2, 1]>,
579 InstrItinData<IIC_VTBX3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
580 InstrStage<1, [FU_NLSPipe]>,
581 InstrStage<1, [FU_NPipe], 0>,
582 InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 1]>,
583 InstrItinData<IIC_VTBX4, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
584 InstrStage<1, [FU_NLSPipe]>,
585 InstrStage<1, [FU_NPipe], 0>,
586 InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]587]>;