Jim Grosbach | 31c24bf | 2009-11-07 22:00:39 +0000 | [diff] [blame] | 1 | //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===// |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 10 | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Evan Cheng | b9803a8 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 14 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 15 | #include "ARM.h" |
| 16 | #include "ARMGenInstrInfo.inc" |
| 17 | #include "ARMMachineFunctionInfo.h" |
| 18 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineMemOperand.h" |
| 22 | #include "llvm/CodeGen/PseudoSourceValue.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 23 | #include "llvm/ADT/SmallVector.h" |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 24 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 25 | |
| 26 | using namespace llvm; |
| 27 | |
Anton Korobeynikov | f95215f | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 28 | Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
| 29 | : ARMBaseInstrInfo(STI), RI(*this, STI) { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 30 | } |
| 31 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 32 | unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 33 | return 0; |
| 34 | } |
| 35 | |
Jakob Stoklund Olesen | ac27366 | 2010-07-11 06:33:54 +0000 | [diff] [blame^] | 36 | void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
| 37 | MachineBasicBlock::iterator I, DebugLoc DL, |
| 38 | unsigned DestReg, unsigned SrcReg, |
| 39 | bool KillSrc) const { |
| 40 | bool tDest = ARM::tGPRRegClass.contains(DestReg); |
| 41 | bool tSrc = ARM::tGPRRegClass.contains(SrcReg); |
| 42 | unsigned Opc = ARM::tMOVgpr2gpr; |
| 43 | if (tDest && tSrc) |
| 44 | Opc = ARM::tMOVr; |
| 45 | else if (tSrc) |
| 46 | Opc = ARM::tMOVtgpr2gpr; |
| 47 | else if (tDest) |
| 48 | Opc = ARM::tMOVgpr2tgpr; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 49 | |
Jakob Stoklund Olesen | ac27366 | 2010-07-11 06:33:54 +0000 | [diff] [blame^] | 50 | BuildMI(MBB, I, DL, get(Opc), DestReg) |
| 51 | .addReg(SrcReg, getKillRegState(KillSrc)); |
| 52 | assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && |
| 53 | "Thumb1 can only copy GPR registers"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 54 | } |
| 55 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 56 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 57 | canFoldMemoryOperand(const MachineInstr *MI, |
| 58 | const SmallVectorImpl<unsigned> &Ops) const { |
| 59 | if (Ops.size() != 1) return false; |
| 60 | |
| 61 | unsigned OpNum = Ops[0]; |
| 62 | unsigned Opc = MI->getOpcode(); |
| 63 | switch (Opc) { |
| 64 | default: break; |
| 65 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 66 | case ARM::tMOVtgpr2gpr: |
| 67 | case ARM::tMOVgpr2tgpr: |
| 68 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 69 | if (OpNum == 0) { // move -> store |
| 70 | unsigned SrcReg = MI->getOperand(1).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 71 | if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 72 | !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 73 | // tSpill cannot take a high register operand. |
| 74 | return false; |
| 75 | } else { // move -> load |
| 76 | unsigned DstReg = MI->getOperand(0).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 77 | if (TargetRegisterInfo::isPhysicalRegister(DstReg) && |
| 78 | !isARMLowRegister(DstReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 79 | // tRestore cannot target a high register operand. |
| 80 | return false; |
| 81 | } |
| 82 | return true; |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | return false; |
| 87 | } |
| 88 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 89 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 90 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 91 | unsigned SrcReg, bool isKill, int FI, |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 92 | const TargetRegisterClass *RC, |
| 93 | const TargetRegisterInfo *TRI) const { |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 94 | assert((RC == ARM::tGPRRegisterClass || |
| 95 | (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 96 | isARMLowRegister(SrcReg))) && "Unknown regclass!"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 97 | |
Jim Grosbach | 98793b9 | 2010-01-15 22:21:03 +0000 | [diff] [blame] | 98 | if (RC == ARM::tGPRRegisterClass || |
| 99 | (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 100 | isARMLowRegister(SrcReg))) { |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 101 | DebugLoc DL; |
| 102 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 103 | |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 104 | MachineFunction &MF = *MBB.getParent(); |
| 105 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| 106 | MachineMemOperand *MMO = |
| 107 | MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), |
| 108 | MachineMemOperand::MOStore, 0, |
| 109 | MFI.getObjectSize(FI), |
| 110 | MFI.getObjectAlignment(FI)); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 111 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) |
| 112 | .addReg(SrcReg, getKillRegState(isKill)) |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 113 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 114 | } |
| 115 | } |
| 116 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 117 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 118 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 119 | unsigned DestReg, int FI, |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 120 | const TargetRegisterClass *RC, |
| 121 | const TargetRegisterInfo *TRI) const { |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 122 | assert((RC == ARM::tGPRRegisterClass || |
| 123 | (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
| 124 | isARMLowRegister(DestReg))) && "Unknown regclass!"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 125 | |
Jim Grosbach | 98793b9 | 2010-01-15 22:21:03 +0000 | [diff] [blame] | 126 | if (RC == ARM::tGPRRegisterClass || |
| 127 | (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
| 128 | isARMLowRegister(DestReg))) { |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 129 | DebugLoc DL; |
| 130 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 131 | |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 132 | MachineFunction &MF = *MBB.getParent(); |
| 133 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| 134 | MachineMemOperand *MMO = |
| 135 | MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), |
| 136 | MachineMemOperand::MOLoad, 0, |
| 137 | MFI.getObjectSize(FI), |
| 138 | MFI.getObjectAlignment(FI)); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 139 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 140 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 141 | } |
| 142 | } |
| 143 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 144 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 145 | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 146 | MachineBasicBlock::iterator MI, |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 147 | const std::vector<CalleeSavedInfo> &CSI, |
| 148 | const TargetRegisterInfo *TRI) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 149 | if (CSI.empty()) |
| 150 | return false; |
| 151 | |
Chris Lattner | c7f3ace | 2010-04-02 20:16:16 +0000 | [diff] [blame] | 152 | DebugLoc DL; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 153 | if (MI != MBB.end()) DL = MI->getDebugLoc(); |
| 154 | |
| 155 | MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 156 | AddDefaultPred(MIB); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 157 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 158 | unsigned Reg = CSI[i-1].getReg(); |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 159 | bool isKill = true; |
| 160 | |
| 161 | // Add the callee-saved register as live-in unless it's LR and |
| 162 | // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress |
| 163 | // then it's already added to the function and entry block live-in sets. |
| 164 | if (Reg == ARM::LR) { |
| 165 | MachineFunction &MF = *MBB.getParent(); |
| 166 | if (MF.getFrameInfo()->isReturnAddressTaken() && |
| 167 | MF.getRegInfo().isLiveIn(Reg)) |
| 168 | isKill = false; |
| 169 | } |
| 170 | |
Bob Wilson | a3a2046 | 2010-06-22 22:04:24 +0000 | [diff] [blame] | 171 | if (isKill) |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 172 | MBB.addLiveIn(Reg); |
Bob Wilson | a3a2046 | 2010-06-22 22:04:24 +0000 | [diff] [blame] | 173 | |
| 174 | MIB.addReg(Reg, getKillRegState(isKill)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 175 | } |
| 176 | return true; |
| 177 | } |
| 178 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 179 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 180 | restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 181 | MachineBasicBlock::iterator MI, |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 182 | const std::vector<CalleeSavedInfo> &CSI, |
| 183 | const TargetRegisterInfo *TRI) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 184 | MachineFunction &MF = *MBB.getParent(); |
| 185 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 186 | if (CSI.empty()) |
| 187 | return false; |
| 188 | |
| 189 | bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 190 | DebugLoc DL = MI->getDebugLoc(); |
| 191 | MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); |
| 192 | AddDefaultPred(MIB); |
| 193 | |
John McCall | 6eeccd4 | 2009-12-16 20:31:50 +0000 | [diff] [blame] | 194 | bool NumRegs = false; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 195 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 196 | unsigned Reg = CSI[i-1].getReg(); |
| 197 | if (Reg == ARM::LR) { |
| 198 | // Special epilogue for vararg functions. See emitEpilogue |
| 199 | if (isVarArg) |
| 200 | continue; |
| 201 | Reg = ARM::PC; |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 202 | (*MIB).setDesc(get(ARM::tPOP_RET)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 203 | MI = MBB.erase(MI); |
| 204 | } |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 205 | MIB.addReg(Reg, getDefRegState(true)); |
John McCall | 6eeccd4 | 2009-12-16 20:31:50 +0000 | [diff] [blame] | 206 | NumRegs = true; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | // It's illegal to emit pop instruction without operands. |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 210 | if (NumRegs) |
| 211 | MBB.insert(MI, &*MIB); |
Jeffrey Yasskin | fa72340 | 2010-03-22 16:13:21 +0000 | [diff] [blame] | 212 | else |
| 213 | MF.DeleteMachineInstr(MIB); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 214 | |
| 215 | return true; |
| 216 | } |
| 217 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 218 | MachineInstr *Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 219 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |
| 220 | const SmallVectorImpl<unsigned> &Ops, int FI) const { |
| 221 | if (Ops.size() != 1) return NULL; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 222 | |
| 223 | unsigned OpNum = Ops[0]; |
| 224 | unsigned Opc = MI->getOpcode(); |
| 225 | MachineInstr *NewMI = NULL; |
| 226 | switch (Opc) { |
| 227 | default: break; |
| 228 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 229 | case ARM::tMOVtgpr2gpr: |
| 230 | case ARM::tMOVgpr2tgpr: |
| 231 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 232 | if (OpNum == 0) { // move -> store |
| 233 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 234 | bool isKill = MI->getOperand(1).isKill(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 235 | if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 236 | !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 237 | // tSpill cannot take a high register operand. |
| 238 | break; |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 239 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) |
| 240 | .addReg(SrcReg, getKillRegState(isKill)) |
| 241 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 242 | } else { // move -> load |
| 243 | unsigned DstReg = MI->getOperand(0).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 244 | if (TargetRegisterInfo::isPhysicalRegister(DstReg) && |
| 245 | !isARMLowRegister(DstReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 246 | // tRestore cannot target a high register operand. |
| 247 | break; |
| 248 | bool isDead = MI->getOperand(0).isDead(); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 249 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) |
| 250 | .addReg(DstReg, |
| 251 | RegState::Define | getDeadRegState(isDead)) |
| 252 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 253 | } |
| 254 | break; |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | return NewMI; |
| 259 | } |