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Jim Grosbach31c24bf2009-11-07 22:00:39 +00001//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
Evan Chengb9803a82009-11-06 23:52:48 +000014#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000015#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Cheng2457f2c2010-05-22 01:47:14 +000020#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Chenge3ce8aa2009-11-01 22:04:35 +000021#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/PseudoSourceValue.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000023#include "llvm/ADT/SmallVector.h"
David Goodwinb50ea5c2009-07-02 22:18:33 +000024#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000025
26using namespace llvm;
27
Anton Korobeynikovf95215f2009-11-02 00:10:38 +000028Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
29 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000030}
31
Evan Cheng446c4282009-07-11 06:43:01 +000032unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000033 return 0;
34}
35
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000036void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator I, DebugLoc DL,
38 unsigned DestReg, unsigned SrcReg,
39 bool KillSrc) const {
40 bool tDest = ARM::tGPRRegClass.contains(DestReg);
41 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
42 unsigned Opc = ARM::tMOVgpr2gpr;
43 if (tDest && tSrc)
44 Opc = ARM::tMOVr;
45 else if (tSrc)
46 Opc = ARM::tMOVtgpr2gpr;
47 else if (tDest)
48 Opc = ARM::tMOVgpr2tgpr;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000049
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000050 BuildMI(MBB, I, DL, get(Opc), DestReg)
51 .addReg(SrcReg, getKillRegState(KillSrc));
52 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
53 "Thumb1 can only copy GPR registers");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000054}
55
David Goodwinb50ea5c2009-07-02 22:18:33 +000056bool Thumb1InstrInfo::
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000057canFoldMemoryOperand(const MachineInstr *MI,
58 const SmallVectorImpl<unsigned> &Ops) const {
59 if (Ops.size() != 1) return false;
60
61 unsigned OpNum = Ops[0];
62 unsigned Opc = MI->getOpcode();
63 switch (Opc) {
64 default: break;
65 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +000066 case ARM::tMOVtgpr2gpr:
67 case ARM::tMOVgpr2tgpr:
68 case ARM::tMOVgpr2gpr: {
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000069 if (OpNum == 0) { // move -> store
70 unsigned SrcReg = MI->getOperand(1).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +000071 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
72 !isARMLowRegister(SrcReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000073 // tSpill cannot take a high register operand.
74 return false;
75 } else { // move -> load
76 unsigned DstReg = MI->getOperand(0).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +000077 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
78 !isARMLowRegister(DstReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000079 // tRestore cannot target a high register operand.
80 return false;
81 }
82 return true;
83 }
84 }
85
86 return false;
87}
88
David Goodwinb50ea5c2009-07-02 22:18:33 +000089void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000090storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91 unsigned SrcReg, bool isKill, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000092 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000094 assert((RC == ARM::tGPRRegisterClass ||
95 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
96 isARMLowRegister(SrcReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000097
Jim Grosbach98793b92010-01-15 22:21:03 +000098 if (RC == ARM::tGPRRegisterClass ||
99 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
100 isARMLowRegister(SrcReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +0000101 DebugLoc DL;
102 if (I != MBB.end()) DL = I->getDebugLoc();
103
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000104 MachineFunction &MF = *MBB.getParent();
105 MachineFrameInfo &MFI = *MF.getFrameInfo();
106 MachineMemOperand *MMO =
107 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
108 MachineMemOperand::MOStore, 0,
109 MFI.getObjectSize(FI),
110 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000111 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
112 .addReg(SrcReg, getKillRegState(isKill))
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000113 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000114 }
115}
116
David Goodwinb50ea5c2009-07-02 22:18:33 +0000117void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000118loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
119 unsigned DestReg, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +0000120 const TargetRegisterClass *RC,
121 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000122 assert((RC == ARM::tGPRRegisterClass ||
123 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
124 isARMLowRegister(DestReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000125
Jim Grosbach98793b92010-01-15 22:21:03 +0000126 if (RC == ARM::tGPRRegisterClass ||
127 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
128 isARMLowRegister(DestReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +0000129 DebugLoc DL;
130 if (I != MBB.end()) DL = I->getDebugLoc();
131
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000132 MachineFunction &MF = *MBB.getParent();
133 MachineFrameInfo &MFI = *MF.getFrameInfo();
134 MachineMemOperand *MMO =
135 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
136 MachineMemOperand::MOLoad, 0,
137 MFI.getObjectSize(FI),
138 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000139 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000141 }
142}
143
David Goodwinb50ea5c2009-07-02 22:18:33 +0000144bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000145spillCalleeSavedRegisters(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator MI,
Evan Cheng2457f2c2010-05-22 01:47:14 +0000147 const std::vector<CalleeSavedInfo> &CSI,
148 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000149 if (CSI.empty())
150 return false;
151
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000152 DebugLoc DL;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000153 if (MI != MBB.end()) DL = MI->getDebugLoc();
154
155 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
Evan Cheng4b322e52009-08-11 21:11:32 +0000156 AddDefaultPred(MIB);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000157 for (unsigned i = CSI.size(); i != 0; --i) {
158 unsigned Reg = CSI[i-1].getReg();
Evan Cheng2457f2c2010-05-22 01:47:14 +0000159 bool isKill = true;
160
161 // Add the callee-saved register as live-in unless it's LR and
162 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
163 // then it's already added to the function and entry block live-in sets.
164 if (Reg == ARM::LR) {
165 MachineFunction &MF = *MBB.getParent();
166 if (MF.getFrameInfo()->isReturnAddressTaken() &&
167 MF.getRegInfo().isLiveIn(Reg))
168 isKill = false;
169 }
170
Bob Wilsona3a20462010-06-22 22:04:24 +0000171 if (isKill)
Evan Cheng2457f2c2010-05-22 01:47:14 +0000172 MBB.addLiveIn(Reg);
Bob Wilsona3a20462010-06-22 22:04:24 +0000173
174 MIB.addReg(Reg, getKillRegState(isKill));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000175 }
176 return true;
177}
178
David Goodwinb50ea5c2009-07-02 22:18:33 +0000179bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000180restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MI,
Evan Cheng2457f2c2010-05-22 01:47:14 +0000182 const std::vector<CalleeSavedInfo> &CSI,
183 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000184 MachineFunction &MF = *MBB.getParent();
185 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
186 if (CSI.empty())
187 return false;
188
189 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
Evan Cheng4b322e52009-08-11 21:11:32 +0000190 DebugLoc DL = MI->getDebugLoc();
191 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
192 AddDefaultPred(MIB);
193
John McCall6eeccd42009-12-16 20:31:50 +0000194 bool NumRegs = false;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000195 for (unsigned i = CSI.size(); i != 0; --i) {
196 unsigned Reg = CSI[i-1].getReg();
197 if (Reg == ARM::LR) {
198 // Special epilogue for vararg functions. See emitEpilogue
199 if (isVarArg)
200 continue;
201 Reg = ARM::PC;
Evan Cheng4b322e52009-08-11 21:11:32 +0000202 (*MIB).setDesc(get(ARM::tPOP_RET));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000203 MI = MBB.erase(MI);
204 }
Evan Cheng4b322e52009-08-11 21:11:32 +0000205 MIB.addReg(Reg, getDefRegState(true));
John McCall6eeccd42009-12-16 20:31:50 +0000206 NumRegs = true;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000207 }
208
209 // It's illegal to emit pop instruction without operands.
Evan Cheng4b322e52009-08-11 21:11:32 +0000210 if (NumRegs)
211 MBB.insert(MI, &*MIB);
Jeffrey Yasskinfa723402010-03-22 16:13:21 +0000212 else
213 MF.DeleteMachineInstr(MIB);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000214
215 return true;
216}
217
David Goodwinb50ea5c2009-07-02 22:18:33 +0000218MachineInstr *Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000219foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
220 const SmallVectorImpl<unsigned> &Ops, int FI) const {
221 if (Ops.size() != 1) return NULL;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000222
223 unsigned OpNum = Ops[0];
224 unsigned Opc = MI->getOpcode();
225 MachineInstr *NewMI = NULL;
226 switch (Opc) {
227 default: break;
228 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +0000229 case ARM::tMOVtgpr2gpr:
230 case ARM::tMOVgpr2tgpr:
231 case ARM::tMOVgpr2gpr: {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000232 if (OpNum == 0) { // move -> store
233 unsigned SrcReg = MI->getOperand(1).getReg();
234 bool isKill = MI->getOperand(1).isKill();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000235 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
236 !isARMLowRegister(SrcReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000237 // tSpill cannot take a high register operand.
238 break;
Evan Cheng446c4282009-07-11 06:43:01 +0000239 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
240 .addReg(SrcReg, getKillRegState(isKill))
241 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000242 } else { // move -> load
243 unsigned DstReg = MI->getOperand(0).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000244 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
245 !isARMLowRegister(DstReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000246 // tRestore cannot target a high register operand.
247 break;
248 bool isDead = MI->getOperand(0).isDead();
Evan Cheng446c4282009-07-11 06:43:01 +0000249 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
250 .addReg(DstReg,
251 RegState::Define | getDeadRegState(isDead))
252 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000253 }
254 break;
255 }
256 }
257
258 return NewMI;
259}