Blame - lib/Target/PowerPC/PPC.td - fp2-dev/platform/external/llvm

2005-10-14 23:37:35 +0000

[diff] [blame]

3

// The LLVM Compiler Infrastructure

4

//

Chris Lattner

4ee451d

2007-12-29 20:36:04 +0000

[diff] [blame]

5

// This file is distributed under the University of Illinois Open Source

6

// License. See LICENSE.TXT for details.

Jia Liu

31d157a

2012-02-18 12:03:15 +0000

[diff] [blame]

7

//

Chris Lattner

2005-10-14 23:37:35 +0000

[diff] [blame]

8

//===----------------------------------------------------------------------===//

9

//

10

// This is the top level entry point for the PowerPC target.

11

//

12

//===----------------------------------------------------------------------===//

13

14

// Get the target-independent interfaces which we are implementing.

15

//

Evan Cheng

027fdbe

2008-11-24 07:34:46 +0000

[diff] [blame]

16

include "llvm/Target/Target.td"

Chris Lattner

2005-10-14 23:37:35 +0000

[diff] [blame]

17

18

//===----------------------------------------------------------------------===//

Jim Laskey

5476b9b

2005-10-22 08:04:24 +0000

[diff] [blame]

19

// PowerPC Subtarget features.

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

20

//

21

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

22

//===----------------------------------------------------------------------===//

23

// CPU Directives //

24

//===----------------------------------------------------------------------===//

25

Hal Finkel

c6d08f1

2011-10-17 04:03:49 +0000

[diff] [blame]

26

def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

27

def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;

28

def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;

29

def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;

30

def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;

31

def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;

32

def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;

33

def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;

34

def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;

35

def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;

36

def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;

Hal Finkel

4d989ac

2012-04-01 19:22:40 +0000

[diff] [blame]

37

def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;

Hal Finkel

621b77a

2012-08-28 16:12:39 +0000

[diff] [blame]

38

def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",

39

"PPC::DIR_E500mc", "">;

40

def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",

41

"PPC::DIR_E5500", "">;

Bill Schmidt

2013-02-01 22:59:51 +0000

[diff] [blame]

42

def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;

43

def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;

44

def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;

45

def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;

Hal Finkel

2012-06-11 15:43:08 +0000

[diff] [blame]

46

def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;

Bill Schmidt

2013-02-01 22:59:51 +0000

[diff] [blame]

47

def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;

Hal Finkel

2012-06-11 15:43:08 +0000

[diff] [blame]

48

def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

49

Chris Lattner

a7a5854

2006-06-16 17:34:12 +0000

[diff] [blame]

50

def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",

Chris Lattner

2e1f823

2005-10-23 05:28:51 +0000

[diff] [blame]

51

"Enable 64-bit instructions">;

Chris Lattner

a7a5854

2006-06-16 17:34:12 +0000

[diff] [blame]

52

def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",

53

"Enable 64-bit registers usage for ppc32 [beta]">;

Evan Cheng

19c9550

2006-01-27 08:09:42 +0000

[diff] [blame]

54

def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",

Chris Lattner

2e1f823

2005-10-23 05:28:51 +0000

[diff] [blame]

55

"Enable Altivec instructions">;

Hal Finkel

2012-06-11 19:57:01 +0000

[diff] [blame]

56

def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",

57

"Enable the MFOCRF instruction">;

Evan Cheng

19c9550

2006-01-27 08:09:42 +0000

[diff] [blame]

58

def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",

Hal Finkel

8ee53e2

2011-10-14 18:54:13 +0000

[diff] [blame]

59

"Enable the fsqrt instruction">;

Chris Lattner

bf751e2

2006-02-28 07:08:22 +0000

[diff] [blame]

60

def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",

Hal Finkel

8ee53e2

2011-10-14 18:54:13 +0000

[diff] [blame]

61

"Enable the stfiwx instruction">;

Hal Finkel

2012-06-22 23:10:08 +0000

[diff] [blame]

62

def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",

63

"Enable the isel instruction">;

Hal Finkel

c6d08f1

2011-10-17 04:03:49 +0000

[diff] [blame]

64

def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",

65

"Enable Book E instructions">;

Hal Finkel

5bb16fd

2013-01-30 21:17:42 +0000

[diff] [blame]

66

def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",

67

"Enable QPX instructions">;

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

68

Bill Schmidt

dbc86b9

2013-02-01 23:10:09 +0000

[diff] [blame^]

69

// Note: Future features to add when support is extended to more

70

// recent ISA levels:

71

//

72

// CMPB p6, p6x, p7 cmpb

73

// DFP p6, p6x, p7 decimal floating-point instructions

74

// FLT_CVT p7 fcfids, fcfidu, fcfidus, fcfiduz, fctiwuz

75

// FPRND p5x, p6, p6x, p7 frim, frin, frip, friz

76

// FRE p5 through p7 fre (vs. fres, available since p3)

77

// FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3)

78

// LDBRX p7 load with byte reversal

79

// LFIWAX p6, p6x, p7 lfiwax

80

// LFIWZX p7 lfiwzx

81

// POPCNTB p5 through p7 popcntb and related instructions

82

// POPCNTD p7 popcntd and related instructions

83

// RECIP_PREC p6, p6x, p7 higher precision reciprocal estimates

84

// VSX p7 vector-scalar instruction set

85

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

86

//===----------------------------------------------------------------------===//

Chris Lattner

c8d2889

2005-10-23 22:08:13 +0000

[diff] [blame]

87

// Register File Description

88

//===----------------------------------------------------------------------===//

89

90

include "PPCRegisterInfo.td"

91

include "PPCSchedule.td"

92

include "PPCInstrInfo.td"

93

94

//===----------------------------------------------------------------------===//

95

// PowerPC processors supported.

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

96

//

97

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

98

def : Processor<"generic", G3Itineraries, [Directive32]>;

Hal Finkel

2012-06-22 23:10:08 +0000

[diff] [blame]

99

def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,

100

FeatureBookE]>;

101

def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,

102

FeatureBookE]>;

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

103

def : Processor<"601", G3Itineraries, [Directive601]>;

104

def : Processor<"602", G3Itineraries, [Directive602]>;

105

def : Processor<"603", G3Itineraries, [Directive603]>;

106

def : Processor<"603e", G3Itineraries, [Directive603]>;

107

def : Processor<"603ev", G3Itineraries, [Directive603]>;

108

def : Processor<"604", G3Itineraries, [Directive604]>;

109

def : Processor<"604e", G3Itineraries, [Directive604]>;

110

def : Processor<"620", G3Itineraries, [Directive620]>;

Hal Finkel

6670c82

2012-06-12 16:39:23 +0000

[diff] [blame]

111

def : Processor<"750", G4Itineraries, [Directive750]>;

112

def : Processor<"g3", G3Itineraries, [Directive750]>;

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

113

def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;

114

def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;

115

def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;

Hal Finkel

6670c82

2012-06-12 16:39:23 +0000

[diff] [blame]

116

def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

117

def : Processor<"970", G5Itineraries,

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

118

[Directive970, FeatureAltivec,

Hal Finkel

2012-06-11 19:57:01 +0000

[diff] [blame]

119

FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,

Jim Laskey

5476b9b

2005-10-22 08:04:24 +0000

[diff] [blame]

120

Feature64Bit /*, Feature64BitRegs */]>;

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

121

def : Processor<"g5", G5Itineraries,

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

122

[Directive970, FeatureAltivec,

Hal Finkel

2012-06-11 19:57:01 +0000

[diff] [blame]

123

FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

124

Feature64Bit /*, Feature64BitRegs */]>;

Hal Finkel

621b77a

2012-08-28 16:12:39 +0000

[diff] [blame]

125

def : ProcessorModel<"e500mc", PPCE500mcModel,

126

[DirectiveE500mc, FeatureMFOCRF,

127

FeatureSTFIWX, FeatureBookE, FeatureISEL]>;

128

def : ProcessorModel<"e5500", PPCE5500Model,

129

[DirectiveE5500, FeatureMFOCRF, Feature64Bit,

130

FeatureSTFIWX, FeatureBookE, FeatureISEL]>;

Hal Finkel

2012-06-22 23:10:08 +0000

[diff] [blame]

131

def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,

132

FeatureMFOCRF, FeatureFSqrt,

133

FeatureSTFIWX, FeatureISEL,

134

Feature64Bit

135

/*, Feature64BitRegs */]>;

Hal Finkel

5bb16fd

2013-01-30 21:17:42 +0000

[diff] [blame]

136

def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,

137

FeatureMFOCRF, FeatureFSqrt,

138

FeatureSTFIWX, FeatureISEL,

139

Feature64Bit /*, Feature64BitRegs */,

140

FeatureQPX]>;

Bill Schmidt

2013-02-01 22:59:51 +0000

[diff] [blame]

141

def : Processor<"pwr3", G5Itineraries,

142

[DirectivePwr3, FeatureAltivec, FeatureMFOCRF,

143

FeatureSTFIWX, Feature64Bit]>;

144

def : Processor<"pwr4", G5Itineraries,

145

[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,

146

FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;

147

def : Processor<"pwr5", G5Itineraries,

148

[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,

149

FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;

150

def : Processor<"pwr5x", G5Itineraries,

151

[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,

152

FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;

Hal Finkel

2012-06-11 15:43:08 +0000

[diff] [blame]

153

def : Processor<"pwr6", G5Itineraries,

154

[DirectivePwr6, FeatureAltivec,

Hal Finkel

2012-06-11 19:57:01 +0000

[diff] [blame]

155

FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,

Hal Finkel

2012-06-11 15:43:08 +0000

[diff] [blame]

156

Feature64Bit /*, Feature64BitRegs */]>;

Bill Schmidt

2013-02-01 22:59:51 +0000

[diff] [blame]

157

def : Processor<"pwr6x", G5Itineraries,

158

[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,

159

FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;

Hal Finkel

2012-06-11 15:43:08 +0000

[diff] [blame]

160

def : Processor<"pwr7", G5Itineraries,

161

[DirectivePwr7, FeatureAltivec,

Hal Finkel

2012-06-11 19:57:01 +0000

[diff] [blame]

162

FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,

Hal Finkel

2012-06-22 23:10:08 +0000

[diff] [blame]

163

FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>;

Jim Laskey

2006-12-12 20:57:08 +0000

[diff] [blame]

164

def : Processor<"ppc", G3Itineraries, [Directive32]>;

165

def : Processor<"ppc64", G5Itineraries,

166

[Directive64, FeatureAltivec,

Hal Finkel

2012-06-11 19:57:01 +0000

[diff] [blame]

167

FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,

Jim Laskey

5476b9b

2005-10-22 08:04:24 +0000

[diff] [blame]

168

Feature64Bit /*, Feature64BitRegs */]>;

Jim Laskey

2005-10-19 19:51:16 +0000

[diff] [blame]

169

170

Chris Lattner

b9a7bea

2007-03-06 00:59:59 +0000

[diff] [blame]

171

//===----------------------------------------------------------------------===//

172

// Calling Conventions

173

//===----------------------------------------------------------------------===//

174

175

include "PPCCallingConv.td"

176

Chris Lattner

2006-03-12 09:13:49 +0000

[diff] [blame]

177

def PPCInstrInfo : InstrInfo {

Chris Lattner

2006-03-12 09:13:49 +0000

[diff] [blame]

178

let isLittleEndianEncoding = 1;

179

}

180

Chris Lattner

84a04ad

2010-11-15 03:53:53 +0000

[diff] [blame]

181

def PPCAsmWriter : AsmWriter {

182

string AsmWriterClassName = "InstPrinter";

183

bit isMCAsmWriter = 1;

184

}

Chris Lattner

2006-03-12 09:13:49 +0000

[diff] [blame]

185

Chris Lattner

2005-10-14 23:37:35 +0000

[diff] [blame]

186

def PPC : Target {

Chris Lattner

2006-03-12 09:13:49 +0000

[diff] [blame]

187

// Information about the instructions.

188

let InstructionSet = PPCInstrInfo;

Chris Lattner

84a04ad

2010-11-15 03:53:53 +0000

[diff] [blame]

189

190

let AssemblyWriters = [PPCAsmWriter];

Chris Lattner