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Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -08001/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
Chandan Uddaraju78ae6752010-10-19 12:57:10 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -080012 * * Neither the name of The Linux Foundation nor the names of its
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070013 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#include <reg.h>
Shashank Mittalcbd271d2011-01-14 15:18:33 -080031#include <endian.h>
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070032#include <mipi_dsi.h>
33#include <dev/fbcon.h>
Greg Griscod6250552011-06-29 14:40:23 -070034#include <stdlib.h>
Greg Grisco1073a5e2011-07-28 18:59:18 -070035#include <string.h>
Kinson Chike5c93432011-06-17 09:10:29 -070036#include <debug.h>
Kinson Chikfe931032011-07-21 10:01:34 -070037#include <target/display.h>
38#include <platform/iomap.h>
39#include <platform/clock.h>
Greg Grisco1073a5e2011-07-28 18:59:18 -070040#include <platform/timer.h>
Shashank Mittal4bfb2e32012-04-16 10:56:27 -070041#include <err.h>
42#include <msm_panel.h>
Kinson Chikfe931032011-07-21 10:01:34 -070043
44extern void mdp_disable(void);
Ajay Dudanib01e5062011-12-03 23:23:42 -080045extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
46 unsigned short num_of_lanes);
Kinson Chikfe931032011-07-21 10:01:34 -070047extern void mdp_shutdown(void);
48extern void mdp_start_dma(void);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070049
Siddhartha Agrawal1b2ed842013-05-29 18:02:28 -070050#if (DISPLAY_TYPE_MDSS == 0)
51#define MIPI_DSI0_BASE MIPI_DSI_BASE
52#define MIPI_DSI1_BASE MIPI_DSI_BASE
53#endif
54
Chandan Uddarajufe93e822010-11-21 20:44:47 -080055#if DISPLAY_MIPI_PANEL_TOSHIBA
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070056static struct fbcon_config mipi_fb_cfg = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080057 .height = TSH_MIPI_FB_HEIGHT,
58 .width = TSH_MIPI_FB_WIDTH,
59 .stride = TSH_MIPI_FB_WIDTH,
60 .format = FB_FORMAT_RGB888,
61 .bpp = 24,
62 .update_start = NULL,
63 .update_done = NULL,
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070064};
Ajay Dudanib01e5062011-12-03 23:23:42 -080065
Kinson Chike5c93432011-06-17 09:10:29 -070066struct mipi_dsi_panel_config toshiba_panel_info = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080067 .mode = MIPI_VIDEO_MODE,
68 .num_of_lanes = 1,
69 .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl,
70 .panel_cmds = toshiba_panel_video_mode_cmds,
71 .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds),
Kinson Chike5c93432011-06-17 09:10:29 -070072};
Chandan Uddarajufe93e822010-11-21 20:44:47 -080073#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
74static struct fbcon_config mipi_fb_cfg = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080075 .height = NOV_MIPI_FB_HEIGHT,
76 .width = NOV_MIPI_FB_WIDTH,
77 .stride = NOV_MIPI_FB_WIDTH,
78 .format = FB_FORMAT_RGB888,
79 .bpp = 24,
80 .update_start = NULL,
81 .update_done = NULL,
Chandan Uddarajufe93e822010-11-21 20:44:47 -080082};
Ajay Dudanib01e5062011-12-03 23:23:42 -080083
Kinson Chike5c93432011-06-17 09:10:29 -070084struct mipi_dsi_panel_config novatek_panel_info = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080085 .mode = MIPI_CMD_MODE,
86 .num_of_lanes = 2,
87 .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl,
88 .panel_cmds = novatek_panel_cmd_mode_cmds,
89 .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds),
Kinson Chike5c93432011-06-17 09:10:29 -070090};
Chandan Uddarajufe93e822010-11-21 20:44:47 -080091#else
92static struct fbcon_config mipi_fb_cfg = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080093 .height = 0,
94 .width = 0,
95 .stride = 0,
96 .format = 0,
97 .bpp = 0,
98 .update_start = NULL,
99 .update_done = NULL,
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800100};
101#endif
102
103static int cmd_mode_status = 0;
Greg Griscod6250552011-06-29 14:40:23 -0700104void secure_writel(uint32_t, uint32_t);
105uint32_t secure_readl(uint32_t);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700106
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800107struct mipi_dsi_panel_config *get_panel_info(void)
108{
109#if DISPLAY_MIPI_PANEL_TOSHIBA
Ajay Dudanib01e5062011-12-03 23:23:42 -0800110 return &toshiba_panel_info;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800111#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
Ajay Dudanib01e5062011-12-03 23:23:42 -0800112 return &novatek_panel_info;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800113#endif
Ajay Dudanib01e5062011-12-03 23:23:42 -0800114 return NULL;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800115}
116
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700117int mdss_dual_dsi_cmd_dma_trigger_for_panel()
118{
119 uint32_t ReadValue;
120 uint32_t count = 0;
121 int status = 0;
122
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400123#if (DISPLAY_TYPE_MDSS == 1)
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700124 writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL);
125 writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER);
126 dsb();
127
128 writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL);
129 writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER);
130 dsb();
131
132 ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001;
133 while (ReadValue != 0x00000001) {
134 ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001;
135 count++;
136 if (count > 0xffff) {
137 status = FAIL;
138 dprintf(CRITICAL,
139 "Panel CMD: command mode dma test failed\n");
140 return status;
141 }
142 }
143
144 writel((readl(MIPI_DSI1_BASE + INT_CTRL) | 0x01000001),
145 MIPI_DSI1_BASE + INT_CTRL);
146 dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400147#endif
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700148 return status;
149}
150
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700151int dsi_cmd_dma_trigger_for_panel()
152{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800153 unsigned long ReadValue;
154 unsigned long count = 0;
155 int status = 0;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700156
Ajay Dudanib01e5062011-12-03 23:23:42 -0800157 writel(0x03030303, DSI_INT_CTRL);
158 writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
159 dsb();
160 ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
161 while (ReadValue != 0x00000001) {
162 ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
163 count++;
164 if (count > 0xffff) {
165 status = FAIL;
166 dprintf(CRITICAL,
167 "Panel CMD: command mode dma test failed\n");
168 return status;
169 }
170 }
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700171
Ajay Dudanib01e5062011-12-03 23:23:42 -0800172 writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
173 dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
174 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700175}
176
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700177int mdss_dual_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
178{
179 int ret = 0;
180 struct mipi_dsi_cmd *cm;
181 int i = 0;
182 char pload[256];
183 uint32_t off;
184
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400185#if (DISPLAY_TYPE_MDSS == 1)
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700186 /* Align pload at 8 byte boundry */
187 off = pload;
188 off &= 0x07;
189 if (off)
190 off = 8 - off;
191 off += pload;
192
193 cm = cmds;
194 for (i = 0; i < count; i++) {
195 memcpy((void *)off, (cm->payload), cm->size);
196 writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET);
197 writel(cm->size, MIPI_DSI0_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build
198 writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET);
199 writel(cm->size, MIPI_DSI1_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build
200 dsb();
201 ret += mdss_dual_dsi_cmd_dma_trigger_for_panel();
Dhaval Patel607a6242013-10-29 12:37:24 -0700202 if (cm->wait)
203 mdelay(cm->wait);
204 else
205 udelay(80);
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700206 cm++;
207 }
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400208#endif
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700209 return ret;
210}
211
Casey Piper84036752013-09-05 14:56:37 -0700212int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len)
213{
214 uint32_t *lp, data;
215 char *dp;
216 int i, off;
217 int rlen, res;
218
219 if (rdbk_len > rp_len) {
220 return 0;
221 }
222
223 if (rdbk_len <= 2)
224 rlen = 4; /* short read */
225 else
226 rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
227
228 if (rlen > MIPI_DSI_REG_LEN) {
229 return 0;
230 }
231
232 res = rlen & 0x03;
233
234 rlen += res; /* 4 byte align */
235 lp = *rp;
236
237 rlen += 3;
238 rlen >>= 2;
239
240 if (rlen > 4)
241 rlen = 4; /* 4 x 32 bits registers only */
242
243 off = DSI_RDBK_DATA0;
244 off += ((rlen - 1) * 4);
245
246 for (i = 0; i < rlen; i++) {
247 data = readl(MIPI_DSI_BASE + off);
248 *lp = ntohl(data); /* to network byte order */
249 lp++;
250
251 off -= 4;
252 }
253
254 if (rdbk_len > 2) {
255 /*First 4 bytes + paded bytes will be header next len bytes would be payload */
256 for (i = 0; i < rdbk_len; i++) {
257 dp = *rp;
258 dp[i] = dp[(res + i) >> 2];
259 }
260 }
261 return rdbk_len;
262}
263
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800264int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700265{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800266 int ret = 0;
267 struct mipi_dsi_cmd *cm;
268 int i = 0;
269 char pload[256];
270 uint32_t off;
Deepa Dinamania080a402011-11-05 18:59:26 -0700271
Ajay Dudanib01e5062011-12-03 23:23:42 -0800272 /* Align pload at 8 byte boundry */
273 off = pload;
274 off &= 0x07;
275 if (off)
276 off = 8 - off;
277 off += pload;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700278
Ajay Dudanib01e5062011-12-03 23:23:42 -0800279 cm = cmds;
280 for (i = 0; i < count; i++) {
281 memcpy((void *)off, (cm->payload), cm->size);
282 writel(off, DSI_DMA_CMD_OFFSET);
283 writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
284 dsb();
285 ret += dsi_cmd_dma_trigger_for_panel();
Sangani Suryanarayana Raju769f9ac2013-04-30 19:05:06 +0530286 dsb();
287 if (cm->wait)
288 mdelay(cm->wait);
289 else
290 udelay(80);
Ajay Dudanib01e5062011-12-03 23:23:42 -0800291 cm++;
292 }
293 return ret;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800294}
295
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800296/*
297 * mipi_dsi_cmd_rx: can receive at most 16 bytes
298 * per transaction since it only have 4 32bits reigsters
299 * to hold data.
300 * therefore Maximum Return Packet Size need to be set to 16.
301 * any return data more than MRPS need to be break down
302 * to multiple transactions.
303 */
304int mipi_dsi_cmds_rx(char **rp, int len)
305{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800306 uint32_t *lp, data;
307 char *dp;
308 int i, off, cnt;
309 int rlen, res;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800310
Ajay Dudanib01e5062011-12-03 23:23:42 -0800311 if (len <= 2)
312 rlen = 4; /* short read */
313 else
314 rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800315
Ajay Dudanib01e5062011-12-03 23:23:42 -0800316 if (rlen > MIPI_DSI_REG_LEN) {
317 return 0;
318 }
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800319
Ajay Dudanib01e5062011-12-03 23:23:42 -0800320 res = rlen & 0x03;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800321
Ajay Dudanib01e5062011-12-03 23:23:42 -0800322 rlen += res; /* 4 byte align */
323 lp = (uint32_t *) (*rp);
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800324
Ajay Dudanib01e5062011-12-03 23:23:42 -0800325 cnt = rlen;
326 cnt += 3;
327 cnt >>= 2;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800328
Ajay Dudanib01e5062011-12-03 23:23:42 -0800329 if (cnt > 4)
330 cnt = 4; /* 4 x 32 bits registers only */
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800331
Ajay Dudanib01e5062011-12-03 23:23:42 -0800332 off = 0x068; /* DSI_RDBK_DATA0 */
333 off += ((cnt - 1) * 4);
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800334
Ajay Dudanib01e5062011-12-03 23:23:42 -0800335 for (i = 0; i < cnt; i++) {
336 data = (uint32_t) readl(MIPI_DSI_BASE + off);
337 *lp++ = ntohl(data); /* to network byte order */
338 off -= 4;
339 }
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800340
Ajay Dudanib01e5062011-12-03 23:23:42 -0800341 if (len > 2) {
342 /*First 4 bytes + paded bytes will be header next len bytes would be payload */
343 for (i = 0; i < len; i++) {
344 dp = *rp;
345 dp[i] = dp[4 + res + i];
346 }
347 }
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800348
Ajay Dudanib01e5062011-12-03 23:23:42 -0800349 return len;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800350}
351
352static int mipi_dsi_cmd_bta_sw_trigger(void)
353{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800354 uint32_t data;
355 int cnt = 0;
356 int err = 0;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800357
Ajay Dudanib01e5062011-12-03 23:23:42 -0800358 writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */
359 while (cnt < 10000) {
360 data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */
361 if ((data & 0x0010) == 0)
362 break;
363 cnt++;
364 }
365 if (cnt == 10000)
366 err = 1;
367 return err;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800368}
369
370static uint32_t mipi_novatek_manufacture_id(void)
371{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800372 char rec_buf[24];
373 char *rp = rec_buf;
374 uint32_t *lp, data;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800375
Ajay Dudanib01e5062011-12-03 23:23:42 -0800376 mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1);
377 mipi_dsi_cmds_rx(&rp, 3);
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800378
Ajay Dudanib01e5062011-12-03 23:23:42 -0800379 lp = (uint32_t *) rp;
380 data = (uint32_t) * lp;
381 data = ntohl(data);
382 data = data >> 8;
383 return data;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800384}
385
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700386int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
387 broadcast)
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700388{
389 uint8_t DMA_STREAM1 = 0; // for mdp display processor path
390 uint8_t EMBED_MODE1 = 1; // from frame buffer
391 uint8_t POWER_MODE2 = 1; // from frame buffer
392 uint8_t PACK_TYPE1; // long packet
393 uint8_t VC1 = 0;
394 uint8_t DT1 = 0; // non embedded mode
395 uint8_t WC1 = 0; // for non embedded mode only
396 int status = 0;
397 uint8_t DLNx_EN;
Siddhartha Agrawal2679a822013-05-31 19:15:12 -0700398 uint8_t lane_swap = 0;
Siddhartha Agrawalb6c861f2013-05-31 19:36:44 -0700399 uint32_t timing_ctl = 0;
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700400
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400401#if (DISPLAY_TYPE_MDSS == 1)
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700402 switch (pinfo->num_of_lanes) {
403 default:
404 case 1:
405 DLNx_EN = 1; // 1 lane
406 break;
407 case 2:
408 DLNx_EN = 3; // 2 lane
409 break;
410 case 3:
411 DLNx_EN = 7; // 3 lane
412 break;
413 case 4:
414 DLNx_EN = 0x0F; /* 4 lanes */
415 break;
416 }
417
418 PACK_TYPE1 = pinfo->pack;
Siddhartha Agrawal2679a822013-05-31 19:15:12 -0700419 lane_swap = pinfo->lane_swap;
Siddhartha Agrawalb6c861f2013-05-31 19:36:44 -0700420 timing_ctl = ((pinfo->t_clk_post << 8) | pinfo->t_clk_pre);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700421
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700422 if (broadcast) {
423 writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET);
424 writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700425
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700426 writel((0 << 16) | 0x3f, MIPI_DSI1_BASE + CLK_CTRL); /* Turn on all DSI Clks */
427 writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI1_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw
428 // trigger 0x4; dma stream1
429
430 writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI1_BASE + CTRL); // reg 0x00 for this
431 // build
432 writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
433 | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
434 MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL);
Siddhartha Agrawal2679a822013-05-31 19:15:12 -0700435
436 writel(lane_swap, MIPI_DSI1_BASE + LANE_SWAP_CTL);
Siddhartha Agrawalb6c861f2013-05-31 19:36:44 -0700437 writel(timing_ctl, MIPI_DSI1_BASE + TIMING_CTL);
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700438 }
439
440 writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET);
441 writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET);
442
443 writel((0 << 16) | 0x3f, MIPI_DSI0_BASE + CLK_CTRL); /* Turn on all DSI Clks */
444 writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI0_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700445 // trigger 0x4; dma stream1
446
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700447 writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI0_BASE + CTRL); // reg 0x00 for this
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700448 // build
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700449 writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700450 | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700451 MIPI_DSI0_BASE + COMMAND_MODE_DMA_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700452
Siddhartha Agrawal2679a822013-05-31 19:15:12 -0700453 writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL);
Siddhartha Agrawalb6c861f2013-05-31 19:36:44 -0700454 writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL);
Siddhartha Agrawal2679a822013-05-31 19:15:12 -0700455
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700456 if (pinfo->panel_cmds) {
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700457
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700458 if (broadcast) {
459 status = mdss_dual_dsi_cmds_tx(pinfo->panel_cmds,
460 pinfo->num_of_panel_cmds);
461
462 } else {
463 status = mipi_dsi_cmds_tx(pinfo->panel_cmds,
464 pinfo->num_of_panel_cmds);
Casey Piper84036752013-09-05 14:56:37 -0700465 if (!status && target_panel_auto_detect_enabled())
466 status =
467 target_read_panel_signature(pinfo->signature);
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700468 }
469 }
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400470#endif
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700471 return status;
472}
473
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800474int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
475{
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800476 uint8_t DMA_STREAM1 = 0; // for mdp display processor path
477 uint8_t EMBED_MODE1 = 1; // from frame buffer
478 uint8_t POWER_MODE2 = 1; // from frame buffer
479 uint8_t PACK_TYPE1; // long packet
480 uint8_t VC1 = 0;
481 uint8_t DT1 = 0; // non embedded mode
482 uint8_t WC1 = 0; // for non embedded mode only
Ajay Dudanib01e5062011-12-03 23:23:42 -0800483 int status = 0;
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800484 uint8_t DLNx_EN;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700485
Ajay Dudanib01e5062011-12-03 23:23:42 -0800486 switch (pinfo->num_of_lanes) {
487 default:
488 case 1:
489 DLNx_EN = 1; // 1 lane
490 break;
491 case 2:
492 DLNx_EN = 3; // 2 lane
493 break;
494 case 3:
495 DLNx_EN = 7; // 3 lane
496 break;
Amir Samuelov2d4ba162012-07-22 11:53:14 +0300497 case 4:
498 DLNx_EN = 0x0F; /* 4 lanes */
499 break;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800500 }
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800501
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800502 PACK_TYPE1 = pinfo->pack;
503
Ajay Dudanib01e5062011-12-03 23:23:42 -0800504 writel(0x0001, DSI_SOFT_RESET);
505 writel(0x0000, DSI_SOFT_RESET);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800506
Ajay Dudanib01e5062011-12-03 23:23:42 -0800507 writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */
508 writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
509 // trigger 0x4; dma stream1
Kinson Chike5c93432011-06-17 09:10:29 -0700510
Ajay Dudanib01e5062011-12-03 23:23:42 -0800511 writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this
512 // build
513 writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
514 | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
515 DSI_COMMAND_MODE_DMA_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700516
Amir Samuelov2d4ba162012-07-22 11:53:14 +0300517 if (pinfo->panel_cmds)
518 status = mipi_dsi_cmds_tx(pinfo->panel_cmds,
519 pinfo->num_of_panel_cmds);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700520
Ajay Dudanib01e5062011-12-03 23:23:42 -0800521 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700522}
523
Kinson Chike5c93432011-06-17 09:10:29 -0700524//TODO: Clean up arguments being passed in not being used
Ajay Dudanib01e5062011-12-03 23:23:42 -0800525int
526config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height,
527 unsigned short img_width, unsigned short img_height,
528 unsigned short hsync_porch0_fp,
529 unsigned short hsync_porch0_bp,
530 unsigned short vsync_porch0_fp,
531 unsigned short vsync_porch0_bp,
532 unsigned short hsync_width,
533 unsigned short vsync_width, unsigned short dst_format,
534 unsigned short traffic_mode, unsigned short datalane_num)
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700535{
536
Ajay Dudanib01e5062011-12-03 23:23:42 -0800537 unsigned char DST_FORMAT;
538 unsigned char TRAFIC_MODE;
539 unsigned char DLNx_EN;
540 // video mode data ctrl
541 int status = 0;
542 unsigned long low_pwr_stop_mode = 0;
543 unsigned char eof_bllp_pwr = 0x9;
544 unsigned char interleav = 0;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700545
Ajay Dudanib01e5062011-12-03 23:23:42 -0800546 // disable mdp first
547 mdp_disable();
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700548
Ajay Dudanib01e5062011-12-03 23:23:42 -0800549 writel(0x00000000, DSI_CLK_CTRL);
550 writel(0x00000000, DSI_CLK_CTRL);
551 writel(0x00000000, DSI_CLK_CTRL);
552 writel(0x00000000, DSI_CLK_CTRL);
553 writel(0x00000002, DSI_CLK_CTRL);
554 writel(0x00000006, DSI_CLK_CTRL);
555 writel(0x0000000e, DSI_CLK_CTRL);
556 writel(0x0000001e, DSI_CLK_CTRL);
557 writel(0x0000003e, DSI_CLK_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700558
Ajay Dudanib01e5062011-12-03 23:23:42 -0800559 writel(0, DSI_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700560
Ajay Dudanib01e5062011-12-03 23:23:42 -0800561 writel(0, DSI_ERR_INT_MASK0);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700562
Ajay Dudanib01e5062011-12-03 23:23:42 -0800563 DST_FORMAT = 0; // RGB565
564 dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n");
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700565
Ajay Dudanib01e5062011-12-03 23:23:42 -0800566 DLNx_EN = 1; // 1 lane with clk programming
567 dprintf(SPEW, "Data Lane: 1 lane\n");
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700568
Ajay Dudanib01e5062011-12-03 23:23:42 -0800569 TRAFIC_MODE = 0; // non burst mode with sync pulses
570 dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700571
Ajay Dudanib01e5062011-12-03 23:23:42 -0800572 writel(0x02020202, DSI_INT_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700573
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800574 writel(((hsync_width + img_width + hsync_porch0_bp) << 16)
575 | (hsync_width + hsync_porch0_bp),
Ajay Dudanib01e5062011-12-03 23:23:42 -0800576 DSI_VIDEO_MODE_ACTIVE_H);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700577
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800578 writel(((vsync_width + img_height + vsync_porch0_bp) << 16)
579 | (vsync_width + vsync_porch0_bp),
Ajay Dudanib01e5062011-12-03 23:23:42 -0800580 DSI_VIDEO_MODE_ACTIVE_V);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700581
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800582 writel(((vsync_width + img_height + vsync_porch0_fp + vsync_porch0_bp - 1) << 16)
583 | (hsync_width + img_width + hsync_porch0_fp + hsync_porch0_bp - 1),
Ajay Dudanib01e5062011-12-03 23:23:42 -0800584 DSI_VIDEO_MODE_TOTAL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700585
Ajay Dudanib01e5062011-12-03 23:23:42 -0800586 writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700587
Ajay Dudanib01e5062011-12-03 23:23:42 -0800588 writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700589
Ajay Dudanib01e5062011-12-03 23:23:42 -0800590 writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700591
Ajay Dudanib01e5062011-12-03 23:23:42 -0800592 writel(1, DSI_EOT_PACKET_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700593
Ajay Dudanib01e5062011-12-03 23:23:42 -0800594 writel(0x00000100, DSI_MISR_VIDEO_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700595
Ajay Dudanib01e5062011-12-03 23:23:42 -0800596 writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8
597 | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700598
Ajay Dudanib01e5062011-12-03 23:23:42 -0800599 writel(0x67, DSI_CAL_STRENGTH_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700600
Ajay Dudanib01e5062011-12-03 23:23:42 -0800601 writel(0x80006711, DSI_CAL_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700602
Ajay Dudanib01e5062011-12-03 23:23:42 -0800603 writel(0x00010100, DSI_MISR_VIDEO_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700604
Ajay Dudanib01e5062011-12-03 23:23:42 -0800605 writel(0x00010100, DSI_INT_CTRL);
606 writel(0x02010202, DSI_INT_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700607
Ajay Dudanib01e5062011-12-03 23:23:42 -0800608 writel(0x02030303, DSI_INT_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700609
Ajay Dudanib01e5062011-12-03 23:23:42 -0800610 writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4
611 | 0x103, DSI_CTRL);
612 mdelay(10);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700613
Ajay Dudanib01e5062011-12-03 23:23:42 -0800614 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700615}
616
Ajay Dudanib01e5062011-12-03 23:23:42 -0800617int
618config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height,
619 unsigned short img_width, unsigned short img_height,
620 unsigned short dst_format,
621 unsigned short traffic_mode, unsigned short datalane_num)
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800622{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800623 unsigned char DST_FORMAT;
624 unsigned char TRAFIC_MODE;
625 unsigned char DLNx_EN;
626 // video mode data ctrl
627 int status = 0;
Greg Griscod6250552011-06-29 14:40:23 -0700628 unsigned char interleav = 0;
629 unsigned char ystride = 0x03;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800630 // disable mdp first
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800631
Ajay Dudanib01e5062011-12-03 23:23:42 -0800632 writel(0x00000000, DSI_CLK_CTRL);
633 writel(0x00000000, DSI_CLK_CTRL);
634 writel(0x00000000, DSI_CLK_CTRL);
635 writel(0x00000000, DSI_CLK_CTRL);
636 writel(0x00000002, DSI_CLK_CTRL);
637 writel(0x00000006, DSI_CLK_CTRL);
638 writel(0x0000000e, DSI_CLK_CTRL);
639 writel(0x0000001e, DSI_CLK_CTRL);
640 writel(0x0000003e, DSI_CLK_CTRL);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800641
Ajay Dudanib01e5062011-12-03 23:23:42 -0800642 writel(0x10000000, DSI_ERR_INT_MASK0);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800643
Ajay Dudanib01e5062011-12-03 23:23:42 -0800644 // writel(0, DSI_CTRL);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800645
Ajay Dudanib01e5062011-12-03 23:23:42 -0800646 // writel(0, DSI_ERR_INT_MASK0);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800647
Ajay Dudanib01e5062011-12-03 23:23:42 -0800648 DST_FORMAT = 8; // RGB888
649 dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800650
Ajay Dudanib01e5062011-12-03 23:23:42 -0800651 DLNx_EN = 3; // 2 lane with clk programming
652 dprintf(SPEW, "Data Lane: 2 lane\n");
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800653
Ajay Dudanib01e5062011-12-03 23:23:42 -0800654 TRAFIC_MODE = 0; // non burst mode with sync pulses
655 dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800656
Ajay Dudanib01e5062011-12-03 23:23:42 -0800657 writel(0x02020202, DSI_INT_CTRL);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800658
Ajay Dudanib01e5062011-12-03 23:23:42 -0800659 writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
660 writel((img_width * ystride + 1) << 16 | 0x0039,
661 DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
662 writel((img_width * ystride + 1) << 16 | 0x0039,
663 DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
664 writel(img_height << 16 | img_width,
665 DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
666 writel(img_height << 16 | img_width,
667 DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
668 writel(0xEE, DSI_CAL_STRENGTH_CTRL);
669 writel(0x80000000, DSI_CAL_CTRL);
670 writel(0x40, DSI_TRIG_CTRL);
671 writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
672 writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
673 DSI_CTRL);
674 mdelay(10);
675 writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
676 writel(0x10000000, DSI_MISR_CMD_CTRL);
677 writel(0x00000040, DSI_ERR_INT_MASK0);
678 writel(0x1, DSI_EOT_PACKET_CTRL);
679 // writel(0x0, MDP_OVERLAYPROC0_START);
680 mdp_start_dma();
681 mdelay(10);
682 writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800683
Ajay Dudanib01e5062011-12-03 23:23:42 -0800684 status = 1;
685 return status;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800686}
687
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800688int mipi_dsi_video_config(unsigned short num_of_lanes)
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700689{
690
Ajay Dudanib01e5062011-12-03 23:23:42 -0800691 int status = 0;
692 unsigned long ReadValue;
693 unsigned long count = 0;
694 unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from
695 // bit16, high spd mode 0x0
696 unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or
697 // let cmd mode eng send packets in hs
698 // or lp mode
699 unsigned short image_wd = mipi_fb_cfg.width;
700 unsigned short image_ht = mipi_fb_cfg.height;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800701 unsigned short display_wd = mipi_fb_cfg.width;
702 unsigned short display_ht = mipi_fb_cfg.height;
703 unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
704 unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
705 unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
706 unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
707 unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
708 unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
709 unsigned short dst_format = 0;
710 unsigned short traffic_mode = 0;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800711 unsigned short pack_pattern = 0x12; //BGR
712 unsigned char ystride = 3;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700713
Ajay Dudanib01e5062011-12-03 23:23:42 -0800714 low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA,
715 // bit24:HFP, bit28:PULSE MODE, need enough
716 // time for swithc from LP to HS
717 eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send
718 // packets in hs or lp mode
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700719
Ajay Dudanib01e5062011-12-03 23:23:42 -0800720 status +=
721 config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht,
722 hsync_porch_fp, hsync_porch_bp,
723 vsync_porch_fp, vsync_porch_bp, hsync_width,
724 vsync_width, dst_format, traffic_mode,
725 num_of_lanes);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700726
Ajay Dudanib01e5062011-12-03 23:23:42 -0800727 status +=
728 mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd,
729 image_ht, hsync_porch_fp, hsync_porch_bp,
730 vsync_porch_fp, vsync_porch_bp,
731 hsync_width, vsync_width, MIPI_FB_ADDR,
732 image_wd, pack_pattern, ystride);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700733
Ajay Dudanib01e5062011-12-03 23:23:42 -0800734 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
735 while (ReadValue != 0x00010000) {
736 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
737 count++;
738 if (count > 0xffff) {
739 status = FAIL;
740 dprintf(CRITICAL, "Video lane test failed\n");
741 return status;
742 }
743 }
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700744
Ajay Dudanib01e5062011-12-03 23:23:42 -0800745 dprintf(SPEW, "Video lane tested successfully\n");
746 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700747}
748
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800749int is_cmd_mode_enabled(void)
750{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800751 return cmd_mode_status;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800752}
753
Kinson Chike5c93432011-06-17 09:10:29 -0700754#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800755void mipi_dsi_cmd_mode_trigger(void)
756{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800757 int status = 0;
758 unsigned short display_wd = mipi_fb_cfg.width;
759 unsigned short display_ht = mipi_fb_cfg.height;
760 unsigned short image_wd = mipi_fb_cfg.width;
761 unsigned short image_ht = mipi_fb_cfg.height;
762 unsigned short dst_format = 0;
763 unsigned short traffic_mode = 0;
764 struct mipi_dsi_panel_config *panel_info = &novatek_panel_info;
765 status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes);
766 mdelay(50);
767 config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht,
768 dst_format, traffic_mode,
769 panel_info->num_of_lanes /* num_of_lanes */ );
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800770}
Kinson Chike5c93432011-06-17 09:10:29 -0700771#endif
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800772
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700773void mipi_dsi_shutdown(void)
774{
Amol Jadi6834f1a2012-06-29 14:42:59 -0700775 if(!target_cont_splash_screen())
776 {
777 mdp_shutdown();
778 writel(0x01010101, DSI_INT_CTRL);
779 writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700780
781#if (DISPLAY_MIPI_PANEL_NOVATEK_BLUE \
Amol Jadi6834f1a2012-06-29 14:42:59 -0700782 || DISPLAY_MIPI_PANEL_TOSHIBA)
783 secure_writel(0x0, DSI_CC_REG);
784 secure_writel(0x0, DSI_PIXEL_CC_REG);
Kinson Chike5c93432011-06-17 09:10:29 -0700785#endif
Amol Jadi6834f1a2012-06-29 14:42:59 -0700786
787 writel(0, DSI_CLK_CTRL);
788 writel(0, DSI_CTRL);
789 writel(0, DSIPHY_PLL_CTRL(0));
790 }
791 else
792 {
Chandan Uddaraju4877d372011-07-21 12:51:51 -0700793 /* To keep the splash screen displayed till kernel driver takes
794 control, do not turn off the video mode engine and clocks.
795 Only disabling the MIPI DSI IRQs */
796 writel(0x01010101, DSI_INT_CTRL);
797 writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
Amol Jadi6834f1a2012-06-29 14:42:59 -0700798 }
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700799}
800
801struct fbcon_config *mipi_init(void)
802{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800803 int status = 0;
804 struct mipi_dsi_panel_config *panel_info = get_panel_info();
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530805
806 if (panel_info == NULL) {
807 dprintf(CRITICAL, "Panel info is null\n");
808 return NULL;
809 }
810
Ajay Dudanib01e5062011-12-03 23:23:42 -0800811 /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */
Terence Hampsonf49ff4e2013-06-18 15:11:31 -0400812#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610)
Ajay Dudanib01e5062011-12-03 23:23:42 -0800813 writel(0x00001800, MMSS_SFPB_GPREG);
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530814#endif
Kinson Chike5c93432011-06-17 09:10:29 -0700815
816#if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
Ajay Dudanib01e5062011-12-03 23:23:42 -0800817 mipi_dsi_phy_init(panel_info);
Kinson Chike5c93432011-06-17 09:10:29 -0700818#else
Ajay Dudanib01e5062011-12-03 23:23:42 -0800819 mipi_dsi_phy_ctrl_config(panel_info);
Kinson Chike5c93432011-06-17 09:10:29 -0700820#endif
821
Ajay Dudanib01e5062011-12-03 23:23:42 -0800822 status += mipi_dsi_panel_initialize(panel_info);
Kinson Chike5c93432011-06-17 09:10:29 -0700823
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800824#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
Ajay Dudanib01e5062011-12-03 23:23:42 -0800825 mipi_dsi_cmd_bta_sw_trigger();
826 mipi_novatek_manufacture_id();
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800827#endif
Ajay Dudanib01e5062011-12-03 23:23:42 -0800828 mipi_fb_cfg.base = MIPI_FB_ADDR;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700829
Ajay Dudanib01e5062011-12-03 23:23:42 -0800830 if (panel_info->mode == MIPI_VIDEO_MODE)
831 status += mipi_dsi_video_config(panel_info->num_of_lanes);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800832
Ajay Dudanib01e5062011-12-03 23:23:42 -0800833 if (panel_info->mode == MIPI_CMD_MODE)
834 cmd_mode_status = 1;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800835
Ajay Dudanib01e5062011-12-03 23:23:42 -0800836 return &mipi_fb_cfg;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700837}
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700838
839int mipi_config(struct msm_fb_panel_data *panel)
840{
841 int ret = NO_ERROR;
842 struct msm_panel_info *pinfo;
843 struct mipi_dsi_panel_config mipi_pinfo;
844
845 if (!panel)
846 return ERR_INVALID_ARGS;
847
848 pinfo = &(panel->panel_info);
849 mipi_pinfo.mode = pinfo->mipi.mode;
850 mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
851 mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db;
852 mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds;
853 mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds;
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530854 mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800855 mipi_pinfo.pack = 1;
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700856
857 /* Enable MMSS_AHB_ARB_MATER_PORT_E for
858 arbiter master0 and master 1 request */
Terence Hampsonf49ff4e2013-06-18 15:11:31 -0400859#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610)
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700860 writel(0x00001800, MMSS_SFPB_GPREG);
861#endif
862
863 mipi_dsi_phy_init(&mipi_pinfo);
864
865 ret += mipi_dsi_panel_initialize(&mipi_pinfo);
866
Channagoud Kadabi01c91822012-06-06 15:53:30 +0530867 if (pinfo->rotate && panel->rotate)
868 pinfo->rotate();
869
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700870 return ret;
871}
872
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700873int mdss_dsi_video_mode_config(uint16_t disp_width,
874 uint16_t disp_height,
875 uint16_t img_width,
876 uint16_t img_height,
877 uint16_t hsync_porch0_fp,
878 uint16_t hsync_porch0_bp,
879 uint16_t vsync_porch0_fp,
880 uint16_t vsync_porch0_bp,
881 uint16_t hsync_width,
882 uint16_t vsync_width,
883 uint16_t dst_format,
884 uint16_t traffic_mode,
885 uint8_t lane_en,
886 uint16_t low_pwr_stop_mode,
887 uint8_t eof_bllp_pwr,
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700888 uint8_t interleav,
889 uint32_t ctl_base)
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700890{
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700891 int status = 0;
892
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400893#if (DISPLAY_TYPE_MDSS == 1)
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700894 /* disable mdp first */
895 mdp_disable();
896
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700897 writel(0x00000000, ctl_base + CLK_CTRL);
898 writel(0x00000002, ctl_base + CLK_CTRL);
899 writel(0x00000006, ctl_base + CLK_CTRL);
900 writel(0x0000000e, ctl_base + CLK_CTRL);
901 writel(0x0000001e, ctl_base + CLK_CTRL);
902 writel(0x0000023f, ctl_base + CLK_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700903
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700904 writel(0, ctl_base + CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700905
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700906 writel(0, ctl_base + DSI_ERR_INT_MASK0);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700907
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700908 writel(0x02020202, ctl_base + INT_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700909
910 writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700911 ctl_base + VIDEO_MODE_ACTIVE_H);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700912
913 writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700914 ctl_base + VIDEO_MODE_ACTIVE_V);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700915
Terence Hampson7385f6a2013-08-16 15:31:25 -0400916 if (mdp_get_revision() >= MDP_REV_41 ||
917 mdp_get_revision() == MDP_REV_304) {
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700918 writel(((disp_height + vsync_porch0_fp
919 + vsync_porch0_bp - 1) << 16)
920 | (disp_width + hsync_porch0_fp
921 + hsync_porch0_bp - 1),
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700922 ctl_base + VIDEO_MODE_TOTAL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700923 } else {
924 writel(((disp_height + vsync_porch0_fp
925 + vsync_porch0_bp) << 16)
926 | (disp_width + hsync_porch0_fp
927 + hsync_porch0_bp),
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700928 ctl_base + VIDEO_MODE_TOTAL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700929 }
930
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700931 writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700932
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700933 writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700934
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700935 writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700936
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700937 writel(0x0, ctl_base + EOT_PACKET_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700938
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700939 writel(0x00000100, ctl_base + MISR_VIDEO_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700940
941 if (mdp_get_revision() >= MDP_REV_41) {
942 writel(low_pwr_stop_mode << 16 |
943 eof_bllp_pwr << 12 | traffic_mode << 8
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700944 | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700945 } else {
946 writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
947 eof_bllp_pwr << 12 | traffic_mode << 8
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700948 | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700949 }
950
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700951 writel(0x3fd08, ctl_base + HS_TIMER_CTRL);
952 writel(0x00010100, ctl_base + MISR_VIDEO_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700953
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700954 writel(0x00010100, ctl_base + INT_CTRL);
955 writel(0x02010202, ctl_base + INT_CTRL);
956 writel(0x02030303, ctl_base + INT_CTRL);
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700957
958 writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
Siddhartha Agrawal6e760042013-05-30 21:10:18 -0700959 | 0x103, ctl_base + CTRL);
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400960#endif
Siddhartha Agrawal06bb82f2013-05-24 12:32:33 -0700961
962 return status;
963}
964
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800965int mdss_dsi_config(struct msm_fb_panel_data *panel)
966{
967 int ret = NO_ERROR;
968 struct msm_panel_info *pinfo;
969 struct mipi_dsi_panel_config mipi_pinfo;
970
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400971#if (DISPLAY_TYPE_MDSS == 1)
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800972 if (!panel)
973 return ERR_INVALID_ARGS;
974
975 pinfo = &(panel->panel_info);
976 mipi_pinfo.mode = pinfo->mipi.mode;
977 mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
978 mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db;
979 mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds;
980 mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds;
981 mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
982 mipi_pinfo.pack = 0;
Siddhartha Agrawalb6c861f2013-05-31 19:36:44 -0700983 mipi_pinfo.t_clk_pre = pinfo->mipi.t_clk_pre;
984 mipi_pinfo.t_clk_post = pinfo->mipi.t_clk_post;
Casey Piper84036752013-09-05 14:56:37 -0700985 mipi_pinfo.signature = pinfo->mipi.signature;
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800986
Siddhartha Agrawal1b2ed842013-05-29 18:02:28 -0700987 mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE);
988 if (pinfo->mipi.dual_dsi)
989 mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE);
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800990
Siddhartha Agrawal980b5ee2013-05-30 12:17:50 -0700991 ret += mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800992
993 if (pinfo->rotate && panel->rotate)
994 pinfo->rotate();
Terence Hampsoncc3345c2013-06-27 15:30:10 -0400995#endif
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -0800996
997 return ret;
998}
999
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001000int mipi_dsi_video_mode_config(unsigned short disp_width,
1001 unsigned short disp_height,
1002 unsigned short img_width,
1003 unsigned short img_height,
1004 unsigned short hsync_porch0_fp,
1005 unsigned short hsync_porch0_bp,
1006 unsigned short vsync_porch0_fp,
1007 unsigned short vsync_porch0_bp,
1008 unsigned short hsync_width,
1009 unsigned short vsync_width,
1010 unsigned short dst_format,
1011 unsigned short traffic_mode,
1012 unsigned char lane_en,
1013 unsigned low_pwr_stop_mode,
1014 unsigned char eof_bllp_pwr,
1015 unsigned char interleav)
1016{
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001017 int status = 0;
1018
1019 /* disable mdp first */
1020 mdp_disable();
1021
1022 writel(0x00000000, DSI_CLK_CTRL);
1023 writel(0x00000000, DSI_CLK_CTRL);
1024 writel(0x00000000, DSI_CLK_CTRL);
1025 writel(0x00000000, DSI_CLK_CTRL);
1026 writel(0x00000002, DSI_CLK_CTRL);
1027 writel(0x00000006, DSI_CLK_CTRL);
1028 writel(0x0000000e, DSI_CLK_CTRL);
1029 writel(0x0000001e, DSI_CLK_CTRL);
Chandan Uddarajueb1decb2013-04-23 14:27:49 -07001030 writel(0x0000023f, DSI_CLK_CTRL);
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001031
1032 writel(0, DSI_CTRL);
1033
1034 writel(0, DSI_ERR_INT_MASK0);
1035
1036 writel(0x02020202, DSI_INT_CTRL);
1037
1038 writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
1039 DSI_VIDEO_MODE_ACTIVE_H);
1040
1041 writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
1042 DSI_VIDEO_MODE_ACTIVE_V);
1043
1044 if (mdp_get_revision() >= MDP_REV_41) {
1045 writel(((disp_height + vsync_porch0_fp
1046 + vsync_porch0_bp - 1) << 16)
1047 | (disp_width + hsync_porch0_fp
1048 + hsync_porch0_bp - 1),
1049 DSI_VIDEO_MODE_TOTAL);
1050 } else {
1051 writel(((disp_height + vsync_porch0_fp
1052 + vsync_porch0_bp) << 16)
1053 | (disp_width + hsync_porch0_fp
1054 + hsync_porch0_bp),
1055 DSI_VIDEO_MODE_TOTAL);
1056 }
1057
1058 writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
1059
1060 writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
1061
1062 writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
1063
Chandan Uddarajueb1decb2013-04-23 14:27:49 -07001064 writel(0x0, DSI_EOT_PACKET_CTRL);
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001065
1066 writel(0x00000100, DSI_MISR_VIDEO_CTRL);
1067
Channagoud Kadabi539ef722012-03-29 16:02:50 +05301068 if (mdp_get_revision() >= MDP_REV_41) {
1069 writel(low_pwr_stop_mode << 16 |
1070 eof_bllp_pwr << 12 | traffic_mode << 8
1071 | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
1072 } else {
1073 writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
1074 eof_bllp_pwr << 12 | traffic_mode << 8
1075 | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
1076 }
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001077
Chandan Uddarajueb1decb2013-04-23 14:27:49 -07001078 writel(0x3fd08, DSI_HS_TIMER_CTRL);
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001079 writel(0x67, DSI_CAL_STRENGTH_CTRL);
1080 writel(0x80006711, DSI_CAL_CTRL);
1081 writel(0x00010100, DSI_MISR_VIDEO_CTRL);
1082
1083 writel(0x00010100, DSI_INT_CTRL);
1084 writel(0x02010202, DSI_INT_CTRL);
1085 writel(0x02030303, DSI_INT_CTRL);
1086
1087 writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
1088 | 0x103, DSI_CTRL);
1089
1090 return status;
1091}
1092
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001093int mdss_dsi_cmd_mode_config(uint16_t disp_width,
1094 uint16_t disp_height,
1095 uint16_t img_width,
1096 uint16_t img_height,
1097 uint16_t dst_format,
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -04001098 uint8_t ystride,
1099 uint8_t lane_en,
1100 uint8_t interleav)
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001101{
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -04001102 uint16_t dst_fmt = 0;
1103
1104 switch (dst_format) {
1105 case DSI_VIDEO_DST_FORMAT_RGB565:
1106 dst_fmt = DSI_CMD_DST_FORMAT_RGB565;
1107 break;
1108 case DSI_VIDEO_DST_FORMAT_RGB666:
1109 case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE:
1110 dst_fmt = DSI_CMD_DST_FORMAT_RGB666;
1111 break;
1112 case DSI_VIDEO_DST_FORMAT_RGB888:
1113 dst_fmt = DSI_CMD_DST_FORMAT_RGB888;
1114 break;
1115 default:
1116 dprintf(CRITICAL, "unsupported dst format\n");
1117 return ERROR;
1118 }
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001119
Terence Hampsoncc3345c2013-06-27 15:30:10 -04001120#if (DISPLAY_TYPE_MDSS == 1)
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001121 writel(0x00000000, DSI_CLK_CTRL);
1122 writel(0x00000000, DSI_CLK_CTRL);
1123 writel(0x00000000, DSI_CLK_CTRL);
1124 writel(0x00000000, DSI_CLK_CTRL);
1125 writel(0x00000002, DSI_CLK_CTRL);
1126 writel(0x00000006, DSI_CLK_CTRL);
1127 writel(0x0000000e, DSI_CLK_CTRL);
1128 writel(0x0000001e, DSI_CLK_CTRL);
1129 writel(0x0000023f, DSI_CLK_CTRL);
1130
1131 writel(0, DSI_CTRL);
1132
1133 writel(0, DSI_ERR_INT_MASK0);
1134
1135 writel(0x02020202, DSI_INT_CTRL);
1136
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -04001137 writel(dst_fmt, DSI_COMMAND_MODE_MDP_CTRL);
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001138 writel((img_width * ystride + 1) << 16 | 0x0039,
1139 DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
1140 writel((img_width * ystride + 1) << 16 | 0x0039,
1141 DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
1142 writel(img_height << 16 | img_width,
1143 DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
1144 writel(img_height << 16 | img_width,
1145 DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
1146 writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -04001147 writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001148 DSI_CTRL);
1149 writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
1150 writel(0x10000000, DSI_MISR_CMD_CTRL);
Terence Hampsoncc3345c2013-06-27 15:30:10 -04001151#endif
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001152
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -04001153 return 0;
Siddhartha Agrawal7317e482013-04-21 16:16:57 -07001154}
1155
Channagoud Kadabi10189fd2012-05-25 13:33:39 +05301156int mipi_dsi_cmd_mode_config(unsigned short disp_width,
1157 unsigned short disp_height,
1158 unsigned short img_width,
1159 unsigned short img_height,
1160 unsigned short dst_format,
1161 unsigned short traffic_mode)
1162{
1163 unsigned char DST_FORMAT;
1164 unsigned char TRAFIC_MODE;
1165 unsigned char DLNx_EN;
1166 // video mode data ctrl
1167 int status = 0;
1168 unsigned char interleav = 0;
1169 unsigned char ystride = 0x03;
1170 // disable mdp first
1171
1172 writel(0x00000000, DSI_CLK_CTRL);
1173 writel(0x00000000, DSI_CLK_CTRL);
1174 writel(0x00000000, DSI_CLK_CTRL);
1175 writel(0x00000000, DSI_CLK_CTRL);
1176 writel(0x00000002, DSI_CLK_CTRL);
1177 writel(0x00000006, DSI_CLK_CTRL);
1178 writel(0x0000000e, DSI_CLK_CTRL);
1179 writel(0x0000001e, DSI_CLK_CTRL);
1180 writel(0x0000003e, DSI_CLK_CTRL);
1181
1182 writel(0x10000000, DSI_ERR_INT_MASK0);
1183
1184
1185 DST_FORMAT = 8; // RGB888
1186 dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
1187
1188 DLNx_EN = 3; // 2 lane with clk programming
1189 dprintf(SPEW, "Data Lane: 2 lane\n");
1190
1191 TRAFIC_MODE = 0; // non burst mode with sync pulses
1192 dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
1193
1194 writel(0x02020202, DSI_INT_CTRL);
1195
1196 writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
1197 writel((img_width * ystride + 1) << 16 | 0x0039,
1198 DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
1199 writel((img_width * ystride + 1) << 16 | 0x0039,
1200 DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
1201 writel(img_height << 16 | img_width,
1202 DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
1203 writel(img_height << 16 | img_width,
1204 DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
1205 writel(0xEE, DSI_CAL_STRENGTH_CTRL);
1206 writel(0x80000000, DSI_CAL_CTRL);
1207 writel(0x40, DSI_TRIG_CTRL);
1208 writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
1209 writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
1210 DSI_CTRL);
1211 writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
1212 writel(0x10000000, DSI_MISR_CMD_CTRL);
1213 writel(0x00000040, DSI_ERR_INT_MASK0);
1214 writel(0x1, DSI_EOT_PACKET_CTRL);
1215
1216 return NO_ERROR;
1217}
1218
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001219int mipi_dsi_on()
1220{
1221 int ret = NO_ERROR;
1222 unsigned long ReadValue;
1223 unsigned long count = 0;
1224
1225 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
1226
1227 mdelay(10);
1228
1229 while (ReadValue != 0x00010000) {
1230 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
1231 count++;
1232 if (count > 0xffff) {
1233 dprintf(CRITICAL, "Video lane test failed\n");
1234 return ERROR;
1235 }
1236 }
1237
Amir Samuelov2d4ba162012-07-22 11:53:14 +03001238 dprintf(INFO, "Video lane tested successfully\n");
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001239 return ret;
1240}
1241
Siddhartha Agrawal24d81b52013-07-01 11:13:32 -07001242int mipi_dsi_off(struct msm_panel_info *pinfo)
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001243{
Amol Jadi6834f1a2012-06-29 14:42:59 -07001244 if(!target_cont_splash_screen())
1245 {
1246 writel(0, DSI_CLK_CTRL);
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -08001247 writel(0x1F1, DSI_CTRL);
Siddhartha Agrawal3e694ea2013-01-23 17:01:31 -08001248 mdelay(10);
1249 writel(0x0001, DSI_SOFT_RESET);
1250 writel(0x0000, DSI_SOFT_RESET);
Siddhartha Agrawale0033a12013-02-23 15:37:42 -08001251 writel(0x1115501, DSI_INT_CTRL);
Amol Jadi6834f1a2012-06-29 14:42:59 -07001252 writel(0, DSI_CTRL);
Siddhartha Agrawale0033a12013-02-23 15:37:42 -08001253 }
1254
1255 writel(0x1115501, DSI_INT_CTRL);
Siddhartha Agrawal24d81b52013-07-01 11:13:32 -07001256 if (pinfo->mipi.broadcast)
1257 writel(0x1115501, DSI_INT_CTRL + 0x600);
Shashank Mittal4bfb2e32012-04-16 10:56:27 -07001258
1259 return NO_ERROR;
1260}
Channagoud Kadabi10189fd2012-05-25 13:33:39 +05301261
1262int mipi_cmd_trigger()
1263{
1264 writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
1265
1266 return NO_ERROR;
1267}