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gerrit-public.fairphone.software / kernel / lk / 8d925a0e7721625ad400b87c59f6a33fcb359e73 / . / platform / msm8994 / include / platform / iomap.h
blob: 383d231ad673ee4780270ec67ea6017f846ca5f3 [file] [log] [blame]
Jeevan Shriram89b72f42015-01-07 16:33:25 -0800[diff] [blame]1/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
Channagoud Kadabi608b6a72014-04-14 13:58:03 -0700[diff] [blame]29#ifndef _PLATFORM_MSM8994_IOMAP_H_
30#define _PLATFORM_MSM8994_IOMAP_H_
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]31
Channagoud Kadabi4983cf02014-05-06 17:34:52 -0700[diff] [blame]32#define MSM_SHARED_BASE 0x06A00000
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]33
34#define MSM_IOMAP_BASE 0xF9000000
35#define MSM_IOMAP_END 0xFEFFFFFF
36
37#define SYSTEM_IMEM_BASE 0xFE800000
38#define MSM_SHARED_IMEM_BASE 0xFE87F000
Sridhar Parasuram39419a32014-09-12 18:11:05 -0700[diff] [blame]39#define MSM_SHARED_IMEM_BASE2 0xFE80F000
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]40#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Sridhar Parasuram39419a32014-09-12 18:11:05 -0700[diff] [blame]41#define RESTART_REASON_ADDR2 (MSM_SHARED_IMEM_BASE2 + 0x65C)
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]42
Sridhar Parasuram39419a32014-09-12 18:11:05 -0700[diff] [blame]43#define BS_INFO_OFFSET (0x6B0)
44#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
45#define BS_INFO_ADDR2 (MSM_SHARED_IMEM_BASE2 + BS_INFO_OFFSET)
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]46
47#define KPSS_BASE 0xF9000000
48
49#define MSM_GIC_DIST_BASE KPSS_BASE
50#define MSM_GIC_CPU_BASE (KPSS_BASE + 0x00002000)
51#define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000)
52#define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000)
53#define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000)
54#define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000)
55#define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000)
56#define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000)
Sundarajan Srinivasan19b95c72014-07-24 16:37:04 -0700[diff] [blame]57#define APCS_ALIAS0_IPC_INTERRUPT (KPSS_BASE + 0x0000D008)
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]58#define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE
59
60#define PERIPH_SS_BASE 0xF9800000
61
62#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
63#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
64#define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000)
65#define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
66#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
67#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
68#define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000)
69#define MSM_SDC4_SDHCI_BASE (PERIPH_SS_BASE + 0x000E4900)
70
71#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
72#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
73#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000)
74#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
75#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
76#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
77
78#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
79
80#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
Sundarajan Srinivasan0ebf2fc2014-04-23 16:45:18 -0700[diff] [blame]81#define USB2_PHY_SEL 0xFD4AB000
82
83/* QUSB2 PHY */
84#define QUSB2_PHY_BASE (PERIPH_SS_BASE + 0x00339000)
85
Channagoud Kadabi3dcc4ed2014-04-10 14:59:41 -0700[diff] [blame]86#define MSM_USB30_BASE 0xF9200000
87#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
88
89/* SS QMP (Qulacomm Multi Protocol) */
90#define QMP_PHY_BASE 0xF9B38000
91
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]92/* Clocks */
93#define CLK_CTL_BASE 0xFC400000
94
95/* GPLL */
96#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
97#define GPLL4_MODE (CLK_CTL_BASE + 0x1DC0)
98#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
99#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
100
101/* UART */
102#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
103#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
104#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
105#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
106#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
107#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
108#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
109#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
110#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
111#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
112#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
113#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
114#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
115#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
116
117/* USB */
118#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
119
120#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
121#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
122#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
123#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
124
Channagoud Kadabi3dcc4ed2014-04-10 14:59:41 -0700[diff] [blame]125/* USB3 clocks */
126#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x03FC)
127#define USB2B_PHY_SLEEP_CBCR (CLK_CTL_BASE + 0x04AC)
128#define USB2B_PHY_BCR (CLK_CTL_BASE + 0x04A8)
129#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x03D4)
130#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x03D8)
131#define USB30_MASTER_M (CLK_CTL_BASE + 0x03DC)
132#define USB30_MASTER_N (CLK_CTL_BASE + 0x03E0)
133#define USB30_MASTER_D (CLK_CTL_BASE + 0x03E4)
134#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x03C8)
135#define USB_30_BCR (CLK_CTL_BASE + 0x03C0)
136#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x03E8)
137#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x03EC)
138#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x03D0)
139#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x03CC)
140#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x1414)
141#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x1418)
142#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x1408)
143#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x140C)
144#define USB30_PHY_BCR (CLK_CTL_BASE + 0x1400)
145#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x1404)
146#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x03C4)
Sundarajan Srinivasan0ebf2fc2014-04-23 16:45:18 -0700[diff] [blame]147#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x04B8)
Channagoud Kadabi3c2be1c2014-06-01 18:59:21 -0700[diff] [blame]148#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x1A84)
Channagoud Kadabi3dcc4ed2014-04-10 14:59:41 -0700[diff] [blame]149
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]150/* SDCC */
151#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
152#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
153#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
154#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
155#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
156#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
157#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
158#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
159
Channagoud Kadabie804d642014-08-20 17:43:57 -0700[diff] [blame]160/* SDCC2 */
161#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
162#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
163#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508)
164#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
165#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */
166#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */
167#define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */
168#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
169#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
170
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]171/* SDCC3 */
172#define SDCC3_BCR (CLK_CTL_BASE + 0x540) /* block reset */
173#define SDCC3_APPS_CBCR (CLK_CTL_BASE + 0x544) /* branch control */
174#define SDCC3_AHB_CBCR (CLK_CTL_BASE + 0x548)
175#define SDCC3_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x54C)
176#define SDCC3_CMD_RCGR (CLK_CTL_BASE + 0x550) /* cmd */
177#define SDCC3_CFG_RCGR (CLK_CTL_BASE + 0x554) /* cfg */
178#define SDCC3_M (CLK_CTL_BASE + 0x558) /* m */
179#define SDCC3_N (CLK_CTL_BASE + 0x55C) /* n */
180#define SDCC3_D (CLK_CTL_BASE + 0x560) /* d */
181
182
183#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
184
185#define UFS_BASE (0xFC590000 + 0x00004000)
186
187#define SPMI_BASE 0xFC4C0000
188#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
189#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
190
Channagoud Kadabi27ff9342014-06-16 11:19:29 -0700[diff] [blame]191#define MSM_CE2_BAM_BASE 0xFD444000
192#define MSM_CE2_BASE 0xFD45A000
Channagoud Kadabi2c488742014-12-02 11:37:18 -0800[diff] [blame]193#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]194
195#define TLMM_BASE_ADDR 0xFD510000
196#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
197#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
198
199#define MPM2_MPM_CTRL_BASE 0xFC4A1000
200#define MPM2_MPM_PS_HOLD 0xFC4AB000
201#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
202
203/* DRV strength for sdcc */
204#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
Channagoud Kadabie804d642014-08-20 17:43:57 -0700[diff] [blame]205#define SDC2_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002048)
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]206
207/* SDHCI */
208#define SDCC_MCI_HC_MODE (0x00000078)
209#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
210#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
211#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
212#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
213
214/* Boot config */
215#define SEC_CTRL_CORE_BASE 0xFC4B8000
216#define BOOT_CONFIG_OFFSET 0x00006034
217#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
218
219#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
220
Channagoud Kadabi3dcc4ed2014-04-10 14:59:41 -0700[diff] [blame]221#define TCSR_PHSS_USB2_PHY_SEL 0xFD4AB000
222#define PLATFORM_QMP_OFFSET 0x8
223
Channagoud Kadabi9e574882014-06-24 16:15:23 -0700[diff] [blame]224#define SMEM_TARG_INFO_ADDR 0xFE805FF0
Channagoud Kadabib4c64b82014-07-24 17:18:46 -0700[diff] [blame]225
Sridhar Parasuram8d925a02015-05-21 21:28:32 -0700[diff] [blame^]226
227/* RPMB send receive buffer needs to be mapped
228 * as device memory, define the start address
229 * and size in MB
230 */
231#define RPMB_SND_RCV_BUF 0x10000000
232#define RPMB_SND_RCV_BUF_SZ 0x1
233
234/* QSEECOM: Secure app region notification */
235#define APP_REGION_ADDR 0x6500000
236#define APP_REGION_SIZE 0x500000
237
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]238/* MDSS */
239#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
Channagoud Kadabi5f42b272014-08-21 18:40:39 -0700[diff] [blame]240#define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x502C)
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]241#define MIPI_DSI_BASE (0xFD998000)
242#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
243#define MIPI_DSI1_BASE (0xFD9A0000)
244#define DSI0_PHY_BASE (0xFD998500)
245#define DSI1_PHY_BASE (0xFD9A0500)
246#define DSI0_PLL_BASE (0xFD998300)
247#define DSI1_PLL_BASE (0xFD9A0300)
Jeevan Shriram89b72f42015-01-07 16:33:25 -0800[diff] [blame]248#define DSI0_REGULATOR_BASE (0xFD998780)
249#define DSI1_REGULATOR_BASE (0xFD9A0780)
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]250
Huaibin Yang928201b2015-01-15 10:40:21 -0800[diff] [blame]251#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
252#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
253
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]254#define MDP_BASE (0xfd900000)
255
Siddhartha Agrawal869809e2014-09-25 10:18:59 -0700[diff] [blame]256
257#ifdef MDP_PP_0_BASE
258#undef MDP_PP_0_BASE
259#endif
260#define MDP_PP_0_BASE REG_MDP(0x71000)
261
262#ifdef MDP_PP_1_BASE
263#undef MDP_PP_1_BASE
264#endif
265#define MDP_PP_1_BASE REG_MDP(0x71800)
266
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]267#define REG_MDP(off) (MDP_BASE + (off))
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]268
269#ifdef MDP_HW_REV
270#undef MDP_HW_REV
271#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]272#define MDP_HW_REV REG_MDP(0x1000)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]273
274#ifdef MDP_INTR_EN
275#undef MDP_INTR_EN
276#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]277#define MDP_INTR_EN REG_MDP(0x1010)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]278
279#ifdef MDP_INTR_CLEAR
280#undef MDP_INTR_CLEAR
281#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]282#define MDP_INTR_CLEAR REG_MDP(0x1018)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]283
284#ifdef MDP_HIST_INTR_EN
285#undef MDP_HIST_INTR_EN
286#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]287#define MDP_HIST_INTR_EN REG_MDP(0x101C)
288
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]289#ifdef MDP_DISP_INTF_SEL
290#undef MDP_DISP_INTF_SEL
291#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]292#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]293
294#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
295#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
296#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]297#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]298
299#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
300#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
301#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]302#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]303
304#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
305#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
306#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]307#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
308
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]309#ifdef MDP_INTF_0_TIMING_ENGINE_EN
310#undef MDP_INTF_0_TIMING_ENGINE_EN
311#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]312#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]313
314#ifdef MDP_INTF_1_TIMING_ENGINE_EN
315#undef MDP_INTF_1_TIMING_ENGINE_EN
316#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]317#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
Veera Sundaram Sankaranbacb4012014-12-16 18:16:44 -0800[diff] [blame]318
319#ifdef MDP_INTF_2_TIMING_ENGINE_EN
320#undef MDP_INTF_2_TIMING_ENGINE_EN
321#endif
Aravind Venkateswaran982bdd82014-12-08 12:03:11 -0800[diff] [blame]322#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]323
Casey Piper47ea5dd2015-03-20 15:39:49 -0700[diff] [blame]324#ifdef MDP_INTF_3_TIMING_ENGINE_EN
325#undef MDP_INTF_3_TIMING_ENGINE_EN
326#endif
327#define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x6C800)
328
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]329#ifdef MDP_CTL_0_BASE
330#undef MDP_CTL_0_BASE
331#endif
332#define MDP_CTL_0_BASE REG_MDP(0x2000)
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]333
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]334#ifdef MDP_CTL_1_BASE
335#undef MDP_CTL_1_BASE
336#endif
337#define MDP_CTL_1_BASE REG_MDP(0x2200)
338
339#ifdef MDP_REG_SPLIT_DISPLAY_EN
340#undef MDP_REG_SPLIT_DISPLAY_EN
341#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]342#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]343
344#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
345#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
346#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]347#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]348
349#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
350#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
351#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]352#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
353
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]354#ifdef MDP_INTF_0_BASE
355#undef MDP_INTF_0_BASE
356#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]357#define MDP_INTF_0_BASE REG_MDP(0x6b000)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]358
359#ifdef MDP_INTF_1_BASE
360#undef MDP_INTF_1_BASE
361#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]362#define MDP_INTF_1_BASE REG_MDP(0x6b800)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]363
364#ifdef MDP_INTF_2_BASE
365#undef MDP_INTF_2_BASE
366#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]367#define MDP_INTF_2_BASE REG_MDP(0x6c000)
368
Casey Piper47ea5dd2015-03-20 15:39:49 -0700[diff] [blame]369#ifdef MDP_INTF_3_BASE
370#undef MDP_INTF_3_BASE
371#endif
372#define MDP_INTF_3_BASE REG_MDP(0x6c800)
373
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]374#ifdef MDP_CLK_CTRL0
375#undef MDP_CLK_CTRL0
376#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]377#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]378
379#ifdef MDP_CLK_CTRL1
380#undef MDP_CLK_CTRL1
381#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]382#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]383
384#ifdef MDP_CLK_CTRL2
385#undef MDP_CLK_CTRL2
386#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]387#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]388
389#ifdef MDP_CLK_CTRL3
390#undef MDP_CLK_CTRL3
391#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]392#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]393
394#ifdef MDP_CLK_CTRL4
395#undef MDP_CLK_CTRL4
396#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]397#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]398
399#ifdef MDP_CLK_CTRL5
400#undef MDP_CLK_CTRL5
401#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]402#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]403
404#ifdef MDP_CLK_CTRL6
405#undef MDP_CLK_CTRL6
406#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]407#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]408
409#ifdef MDP_CLK_CTRL7
410#undef MDP_CLK_CTRL7
411#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]412#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
413
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]414#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
415#undef MMSS_MDP_SMP_ALLOC_W_BASE
416#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]417#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]418
419#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
420#undef MMSS_MDP_SMP_ALLOC_R_BASE
421#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]422#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
423
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]424#ifdef MDP_QOS_REMAPPER_CLASS_0
425#undef MDP_QOS_REMAPPER_CLASS_0
426#endif
Ingrid Gallardo998ea442014-09-10 17:22:08 -0700[diff] [blame]427#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]428
429#ifdef MDP_QOS_REMAPPER_CLASS_1
430#undef MDP_QOS_REMAPPER_CLASS_1
431#endif
Ingrid Gallardo998ea442014-09-10 17:22:08 -0700[diff] [blame]432#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]433
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]434#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
435#undef VBIF_VBIF_DDR_FORCE_CLK_ON
436#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]437#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]438
439#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
440#undef VBIF_VBIF_DDR_OUT_MAX_BURST
441#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]442#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]443
444#ifdef VBIF_VBIF_DDR_ARB_CTRL
445#undef VBIF_VBIF_DDR_ARB_CTRL
446#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]447#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]448
449#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
450#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
451#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]452#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]453
454#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
455#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
456#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]457#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]458
459#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
460#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
461#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]462#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]463
464#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
465#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
466#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]467#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]468
469#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
470#undef VBIF_VBIF_DDR_OUT_AX_AOOO
471#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]472#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]473
474#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
475#undef VBIF_VBIF_IN_RD_LIM_CONF0
476#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]477#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]478
479#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
480#undef VBIF_VBIF_IN_RD_LIM_CONF1
481#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]482#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]483
484#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
485#undef VBIF_VBIF_IN_RD_LIM_CONF2
486#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]487#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]488
489#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
490#undef VBIF_VBIF_IN_RD_LIM_CONF3
491#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]492#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]493
494#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
495#undef VBIF_VBIF_IN_WR_LIM_CONF0
496#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]497#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]498
499#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
500#undef VBIF_VBIF_IN_WR_LIM_CONF1
501#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]502#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]503
504#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
505#undef VBIF_VBIF_IN_WR_LIM_CONF2
506#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]507#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]508
509#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
510#undef VBIF_VBIF_IN_WR_LIM_CONF3
511#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]512#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]513
514#ifdef VBIF_VBIF_ABIT_SHORT
515#undef VBIF_VBIF_ABIT_SHORT
516#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]517#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]518
519#ifdef VBIF_VBIF_ABIT_SHORT_CONF
520#undef VBIF_VBIF_ABIT_SHORT_CONF
521#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]522#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
Veera Sundaram Sankaran602d95a2014-12-09 17:55:04 -0800[diff] [blame]523
524#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
525#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
526#endif
Dhaval Patelddce3012014-08-12 14:08:31 -0700[diff] [blame]527#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
528
529#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
530#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
531#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
532#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
533#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
534#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
535#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
536#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
537
538#define DMA_CMD_OFFSET 0x048
539#define DMA_CMD_LENGTH 0x04C
540
541#define INT_CTRL 0x110
542#define CMD_MODE_DMA_SW_TRIGGER 0x090
543
544#define EOT_PACKET_CTRL 0x0CC
545#define MISR_CMD_CTRL 0x0A0
546#define MISR_VIDEO_CTRL 0x0A4
547#define VIDEO_MODE_CTRL 0x010
548#define HS_TIMER_CTRL 0x0BC
Channagoud Kadabib4c64b82014-07-24 17:18:46 -0700[diff] [blame]549
550#define SOFT_RESET 0x118
551#define CLK_CTRL 0x11C
552#define TRIG_CTRL 0x084
553#define CTRL 0x004
554#define COMMAND_MODE_DMA_CTRL 0x03C
555#define COMMAND_MODE_MDP_CTRL 0x040
556#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
557#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
558#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
559#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
560#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
561#define ERR_INT_MASK0 0x10C
562
Ray Zhangd1cd0852015-01-20 15:31:33 +0800[diff] [blame]563#define LANE_CTL 0x0AC
Channagoud Kadabib4c64b82014-07-24 17:18:46 -0700[diff] [blame]564#define LANE_SWAP_CTL 0x0B0
565#define TIMING_CTL 0x0C4
566
567#define VIDEO_MODE_ACTIVE_H 0x024
568#define VIDEO_MODE_ACTIVE_V 0x028
569#define VIDEO_MODE_TOTAL 0x02C
570#define VIDEO_MODE_HSYNC 0x030
571#define VIDEO_MODE_VSYNC 0x034
572#define VIDEO_MODE_VSYNC_VPOS 0x038
573
Shimrit Malichi561a5e52015-01-20 09:58:40 +0200[diff] [blame]574#define QPNP_LED_CTRL_BASE 0xD000
575#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
576#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
577#define QPNP_RED_LPG_CTRL_BASE 0xB300
578
Casey Piper47ea5dd2015-03-20 15:39:49 -0700[diff] [blame]579/* HDMI reg addresses */
580#define HDMI_BASE 0xFD9A8000
581#define REG_HDMI(off) (HDMI_BASE + (off))
582
583#define HDMI_ACR_32_0 REG_HDMI(0xC4)
584#define HDMI_ACR_32_1 REG_HDMI(0xC8)
585#define HDMI_ACR_44_0 REG_HDMI(0xCC)
586#define HDMI_ACR_44_1 REG_HDMI(0xD0)
587#define HDMI_ACR_48_0 REG_HDMI(0xD4)
588#define HDMI_ACR_48_1 REG_HDMI(0xD8)
589#define HDMI_AUDIO_PKT_CTRL2 REG_HDMI(0x44)
590#define HDMI_ACR_PKT_CTRL REG_HDMI(0x24)
591#define HDMI_INFOFRAME_CTRL0 REG_HDMI(0x2C)
592#define HDMI_AUDIO_INFO0 REG_HDMI(0xE4)
593#define HDMI_AUDIO_INFO1 REG_HDMI(0xE8)
594#define HDMI_AUDIO_PKT_CTRL REG_HDMI(0x20)
595#define HDMI_VBI_PKT_CTRL REG_HDMI(0x28)
596#define HDMI_GEN_PKT_CTRL REG_HDMI(0x34)
597#define HDMI_GC REG_HDMI(0x40)
598#define HDMI_AUDIO_CFG REG_HDMI(0x1D0)
599
600#define HDMI_DDC_SPEED REG_HDMI(0x220)
601#define HDMI_DDC_SETUP REG_HDMI(0x224)
602#define HDMI_DDC_REF REG_HDMI(0x27C)
603#define HDMI_DDC_DATA REG_HDMI(0x238)
604#define HDMI_DDC_TRANS0 REG_HDMI(0x228)
605#define HDMI_DDC_TRANS1 REG_HDMI(0x22C)
606#define HDMI_DDC_CTRL REG_HDMI(0x20C)
607#define HDMI_DDC_INT_CTRL REG_HDMI(0x214)
608#define HDMI_DDC_SW_STATUS REG_HDMI(0x218)
609#define HDMI_DDC_ARBITRATION REG_HDMI(0x210)
610
611#define HDMI_USEC_REFTIMER REG_HDMI(0x208)
612#define HDMI_CTRL REG_HDMI(0x000)
613#define HDMI_HPD_INT_STATUS REG_HDMI(0x250)
614#define HDMI_HPD_INT_CTRL REG_HDMI(0x254)
615#define HDMI_HPD_CTRL REG_HDMI(0x258)
616#define HDMI_PHY_CTRL REG_HDMI(0x2D4)
617#define HDMI_TOTAL REG_HDMI(0x2C0)
618#define HDMI_ACTIVE_H REG_HDMI(0x2B4)
619#define HDMI_ACTIVE_V REG_HDMI(0x2B8)
620#define HDMI_V_TOTAL_F2 REG_HDMI(0x2C4)
621#define HDMI_ACTIVE_V_F2 REG_HDMI(0x2BC)
622#define HDMI_FRAME_CTRL REG_HDMI(0x2C8)
623
624#define HDMI_AVI_INFO0 REG_HDMI(0x06C)
625#define HDMI_AVI_INFO1 REG_HDMI(0x070)
626#define HDMI_AVI_INFO2 REG_HDMI(0x074)
627#define HDMI_AVI_INFO3 REG_HDMI(0x078)
628
629#define LPASS_LPAIF_RDDMA_CTL0 0xFE0D2000
630#define LPASS_LPAIF_RDDMA_BASE0 0xFE0D2004
631#define LPASS_LPAIF_RDDMA_BUFF_LEN0 0xFE0D2008
632#define LPASS_LPAIF_RDDMA_PER_LEN0 0xFE0D2010
633#define LPASS_LPAIF_DEBUG_CTL 0xFE0DE004
634
Channagoud Kadabi123c9722014-02-06 13:22:50 -0800[diff] [blame]635#endif