Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
Ajay Dudani | 79d0d40 | 2010-04-21 12:38:45 -0700 | [diff] [blame] | 23 | |
| 24 | #define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5 |
| 25 | #define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5 |
| 26 | |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 27 | .text |
| 28 | .globl _start |
| 29 | _start: |
| 30 | b reset |
| 31 | b arm_undefined |
| 32 | b arm_syscall |
| 33 | b arm_prefetch_abort |
| 34 | b arm_data_abort |
| 35 | b arm_reserved |
| 36 | b arm_irq |
| 37 | b arm_fiq |
| 38 | |
| 39 | reset: |
Subbaraman Narayanamurthy | 8bcd5fd | 2011-01-17 17:18:44 -0800 | [diff] [blame] | 40 | |
| 41 | #ifdef ENABLE_TRUSTZONE |
| 42 | /*Add reference to TZ symbol so linker includes it in final image */ |
| 43 | ldr r7, =_binary_tzbsp_tzbsp_bin_start |
| 44 | #endif |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 45 | /* do some cpu setup */ |
| 46 | #if ARM_WITH_CP15 |
| 47 | mrc p15, 0, r0, c1, c0, 0 |
| 48 | /* XXX this is currently for arm926, revist with armv6 cores */ |
| 49 | /* new thumb behavior, low exception vectors, i/d cache disable, mmu disabled */ |
| 50 | bic r0, r0, #(1<<15| 1<<13 | 1<<12) |
| 51 | bic r0, r0, #(1<<2 | 1<<0) |
| 52 | /* enable alignment faults */ |
| 53 | orr r0, r0, #(1<<1) |
| 54 | mcr p15, 0, r0, c1, c0, 0 |
Subbaraman Narayanamurthy | 8bcd5fd | 2011-01-17 17:18:44 -0800 | [diff] [blame] | 55 | #ifdef ENABLE_TRUSTZONE |
| 56 | /*nkazi: not needed ? Setting VBAR to location of new vector table : 0x80000 */ |
| 57 | ldr r0, =0x00080000 |
| 58 | mcr p15, 0, r0, c12, c0, 0 |
| 59 | #endif |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 60 | #endif |
| 61 | |
Brian Swetland | a8cf2b8 | 2009-01-01 03:29:51 -0800 | [diff] [blame] | 62 | #if WITH_CPU_EARLY_INIT |
| 63 | /* call platform/arch/etc specific init code */ |
Subbaraman Narayanamurthy | 8bcd5fd | 2011-01-17 17:18:44 -0800 | [diff] [blame] | 64 | #ifndef ENABLE_TRUSTZONE |
| 65 | /* Not needed when TrustZone is the first bootloader that runs.*/ |
Brian Swetland | a8cf2b8 | 2009-01-01 03:29:51 -0800 | [diff] [blame] | 66 | bl __cpu_early_init |
Subbaraman Narayanamurthy | 8bcd5fd | 2011-01-17 17:18:44 -0800 | [diff] [blame] | 67 | #endif |
Ajay Dudani | 083d0dd | 2010-07-08 13:16:13 -0700 | [diff] [blame] | 68 | /* declare return address as global to avoid using stack */ |
| 69 | .globl _cpu_early_init_complete |
| 70 | _cpu_early_init_complete: |
| 71 | |
Travis Geiselbrecht | c322611 | 2008-09-02 02:47:40 -0700 | [diff] [blame] | 72 | #endif |
| 73 | |
Chandan Uddaraju | 6cc1e3d | 2009-12-15 15:21:06 -0800 | [diff] [blame] | 74 | #if (!ENABLE_NANDWRITE) |
Harry Yang | 953ff70 | 2009-12-03 21:49:00 -0800 | [diff] [blame] | 75 | #if WITH_CPU_WARM_BOOT |
| 76 | ldr r0, warm_boot_tag |
| 77 | cmp r0, #1 |
| 78 | |
| 79 | /* if set, warm boot */ |
| 80 | ldreq pc, =BASE_ADDR |
| 81 | |
| 82 | mov r0, #1 |
| 83 | str r0, warm_boot_tag |
| 84 | #endif |
Chandan Uddaraju | 6cc1e3d | 2009-12-15 15:21:06 -0800 | [diff] [blame] | 85 | #endif |
Harry Yang | 953ff70 | 2009-12-03 21:49:00 -0800 | [diff] [blame] | 86 | |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 87 | /* see if we need to relocate */ |
| 88 | mov r0, pc |
| 89 | sub r0, r0, #(.Laddr - _start) |
| 90 | .Laddr: |
| 91 | ldr r1, =_start |
| 92 | cmp r0, r1 |
| 93 | beq .Lstack_setup |
| 94 | |
| 95 | /* we need to relocate ourselves to the proper spot */ |
| 96 | ldr r2, =__data_end |
| 97 | |
| 98 | .Lrelocate_loop: |
| 99 | ldr r3, [r0], #4 |
| 100 | str r3, [r1], #4 |
| 101 | cmp r1, r2 |
| 102 | bne .Lrelocate_loop |
| 103 | |
| 104 | /* we're relocated, jump to the right address */ |
| 105 | ldr r0, =.Lstack_setup |
| 106 | bx r0 |
| 107 | |
| 108 | .ltorg |
Harry Yang | 953ff70 | 2009-12-03 21:49:00 -0800 | [diff] [blame] | 109 | #if WITH_CPU_WARM_BOOT |
| 110 | warm_boot_tag: |
| 111 | .word 0 |
| 112 | #endif |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 113 | |
| 114 | .Lstack_setup: |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 115 | /* set up the stack for irq, fiq, abort, undefined, system/user, and lastly supervisor mode */ |
| 116 | mrs r0, cpsr |
| 117 | bic r0, r0, #0x1f |
| 118 | |
| 119 | ldr r2, =abort_stack_top |
| 120 | orr r1, r0, #0x12 // irq |
| 121 | msr cpsr_c, r1 |
| 122 | ldr r13, =irq_save_spot /* save a pointer to a temporary dumping spot used during irq delivery */ |
| 123 | |
| 124 | orr r1, r0, #0x11 // fiq |
| 125 | msr cpsr_c, r1 |
| 126 | mov sp, r2 |
| 127 | |
| 128 | orr r1, r0, #0x17 // abort |
| 129 | msr cpsr_c, r1 |
| 130 | mov sp, r2 |
| 131 | |
| 132 | orr r1, r0, #0x1b // undefined |
| 133 | msr cpsr_c, r1 |
| 134 | mov sp, r2 |
| 135 | |
| 136 | orr r1, r0, #0x1f // system |
| 137 | msr cpsr_c, r1 |
| 138 | mov sp, r2 |
| 139 | |
| 140 | orr r1, r0, #0x13 // supervisor |
| 141 | msr cpsr_c, r1 |
| 142 | mov sp, r2 |
| 143 | |
| 144 | /* copy the initialized data segment out of rom if necessary */ |
| 145 | ldr r0, =__data_start_rom |
| 146 | ldr r1, =__data_start |
| 147 | ldr r2, =__data_end |
| 148 | |
| 149 | cmp r0, r1 |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 150 | beq .L__do_bss |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 151 | |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 152 | .L__copy_loop: |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 153 | cmp r1, r2 |
| 154 | ldrlt r3, [r0], #4 |
| 155 | strlt r3, [r1], #4 |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 156 | blt .L__copy_loop |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 157 | |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 158 | .L__do_bss: |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 159 | /* clear out the bss */ |
| 160 | ldr r0, =__bss_start |
| 161 | ldr r1, =_end |
| 162 | mov r2, #0 |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 163 | .L__bss_loop: |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 164 | cmp r0, r1 |
| 165 | strlt r2, [r0], #4 |
Travis Geiselbrecht | 887061f | 2008-09-05 01:47:07 -0700 | [diff] [blame] | 166 | blt .L__bss_loop |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 167 | |
Ajay Dudani | 79d0d40 | 2010-04-21 12:38:45 -0700 | [diff] [blame] | 168 | #ifdef ARM_CPU_CORTEX_A8 |
| 169 | DSB |
| 170 | ISB |
| 171 | #endif |
| 172 | |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 173 | bl kmain |
| 174 | b . |
| 175 | |
| 176 | .ltorg |
| 177 | |
| 178 | .bss |
| 179 | .align 2 |
| 180 | /* the abort stack is for unrecoverable errors. |
| 181 | * also note the initial working stack is set to here. |
| 182 | * when the threading system starts up it'll switch to a new |
| 183 | * dynamically allocated stack, so we don't need it for very long |
| 184 | */ |
| 185 | abort_stack: |
| 186 | .skip 1024 |
| 187 | abort_stack_top: |