Channagoud Kadabi | 0d1a7dc | 2015-03-16 14:42:37 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <mmc.h> |
| 33 | #include <clock.h> |
Sridhar Parasuram | 540d019 | 2014-12-05 10:34:56 -0800 | [diff] [blame] | 34 | #include <pm8x41.h> |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
Sridhar Parasuram | 540d019 | 2014-12-05 10:34:56 -0800 | [diff] [blame] | 37 | #include <platform/timer.h> |
Channagoud Kadabi | 2c48874 | 2014-12-02 11:37:18 -0800 | [diff] [blame] | 38 | #include <rpm-smd.h> |
| 39 | #include <regulator.h> |
Channagoud Kadabi | 0d1a7dc | 2015-03-16 14:42:37 -0700 | [diff] [blame] | 40 | #include <platform.h> |
Channagoud Kadabi | 2c48874 | 2014-12-02 11:37:18 -0800 | [diff] [blame] | 41 | |
| 42 | #define RPM_CE_CLK_TYPE 0x6563 |
| 43 | #define CE2_CLK_ID 0x1 |
| 44 | #define RPM_SMD_KEY_RATE 0x007A484B |
| 45 | |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 46 | #define MAX_LOOPS 500 |
| 47 | |
Channagoud Kadabi | 2c48874 | 2014-12-02 11:37:18 -0800 | [diff] [blame] | 48 | uint32_t CE2_CLK[][8]= |
| 49 | { |
| 50 | { |
| 51 | RPM_CE_CLK_TYPE, CE2_CLK_ID, |
| 52 | KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE, |
| 53 | RPM_SMD_KEY_RATE, 4, 0, |
| 54 | }, |
| 55 | { |
| 56 | RPM_CE_CLK_TYPE, CE2_CLK_ID, |
| 57 | KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE, |
| 58 | RPM_SMD_KEY_RATE, 4, 176128, |
| 59 | }, |
| 60 | }; |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 61 | |
| 62 | void hsusb_clock_init(void) |
| 63 | { |
| 64 | int ret; |
| 65 | struct clk *iclk, *cclk; |
| 66 | |
| 67 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 68 | if(ret) |
| 69 | { |
| 70 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 71 | ASSERT(0); |
| 72 | } |
| 73 | |
| 74 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 75 | if(ret) |
| 76 | { |
| 77 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 78 | ASSERT(0); |
| 79 | } |
| 80 | |
| 81 | /* Wait for the clocks to be stable since we are disabling soon after. */ |
| 82 | mdelay(1); |
| 83 | |
| 84 | iclk = clk_get("usb_iface_clk"); |
| 85 | cclk = clk_get("usb_core_clk"); |
| 86 | |
| 87 | clk_disable(iclk); |
| 88 | clk_disable(cclk); |
| 89 | |
| 90 | /* Wait for the clock disable to complete. */ |
| 91 | mdelay(1); |
| 92 | |
| 93 | /* Start the block reset for usb */ |
| 94 | writel(1, USB_HS_BCR); |
| 95 | |
| 96 | /* Wait for reset to complete. */ |
| 97 | mdelay(1); |
| 98 | |
| 99 | /* Take usb block out of reset */ |
| 100 | writel(0, USB_HS_BCR); |
| 101 | |
| 102 | /* Wait for the block to be brought out of reset. */ |
| 103 | mdelay(1); |
| 104 | |
| 105 | ret = clk_enable(iclk); |
| 106 | |
| 107 | if(ret) |
| 108 | { |
| 109 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 110 | ASSERT(0); |
| 111 | } |
| 112 | |
| 113 | ret = clk_enable(cclk); |
| 114 | |
| 115 | if(ret) |
| 116 | { |
| 117 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 118 | ASSERT(0); |
| 119 | } |
| 120 | |
Tanya Finkel | 90abab7 | 2014-07-30 09:55:23 +0300 | [diff] [blame] | 121 | ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1); |
| 122 | if(ret) |
| 123 | { |
| 124 | dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret); |
| 125 | ASSERT(0); |
| 126 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | void clock_init_mmc(uint32_t interface) |
| 130 | { |
| 131 | char clk_name[64]; |
| 132 | int ret; |
| 133 | |
| 134 | snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface); |
| 135 | |
| 136 | /* enable interface clock */ |
| 137 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 138 | if(ret) |
| 139 | { |
| 140 | dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret); |
| 141 | ASSERT(0); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | /* Configure MMC clock */ |
| 146 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 147 | { |
Sridhar Parasuram | 540d019 | 2014-12-05 10:34:56 -0800 | [diff] [blame] | 148 | int ret = 0; |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 149 | char clk_name[64]; |
| 150 | |
| 151 | snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface); |
| 152 | |
| 153 | if(freq == MMC_CLK_400KHZ) |
| 154 | { |
| 155 | ret = clk_get_set_enable(clk_name, 400000, 1); |
| 156 | } |
| 157 | else if(freq == MMC_CLK_50MHZ) |
| 158 | { |
| 159 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
| 160 | } |
| 161 | else if(freq == MMC_CLK_96MHZ) |
| 162 | { |
| 163 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 164 | } |
| 165 | else if(freq == MMC_CLK_192MHZ) |
| 166 | { |
Channagoud Kadabi | 0d1a7dc | 2015-03-16 14:42:37 -0700 | [diff] [blame] | 167 | if (platform_is_msm8992()) |
| 168 | ret = clk_get_set_enable(clk_name, 172000000, 1); |
| 169 | else |
| 170 | ret = clk_get_set_enable(clk_name, 192000000, 1); |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 171 | } |
Channagoud Kadabi | e804d64 | 2014-08-20 17:43:57 -0700 | [diff] [blame] | 172 | else if(freq == MMC_CLK_200MHZ) |
| 173 | { |
| 174 | ret = clk_get_set_enable(clk_name, 200000000, 1); |
| 175 | } |
Channagoud Kadabi | 6b3a998 | 2014-06-05 12:59:46 -0700 | [diff] [blame] | 176 | else if(freq == MMC_CLK_400MHZ) |
| 177 | { |
Channagoud Kadabi | 0d1a7dc | 2015-03-16 14:42:37 -0700 | [diff] [blame] | 178 | if (platform_is_msm8992()) |
| 179 | ret = clk_get_set_enable(clk_name, 344000000, 1); |
| 180 | else |
| 181 | ret = clk_get_set_enable(clk_name, 384000000, 1); |
Channagoud Kadabi | 6b3a998 | 2014-06-05 12:59:46 -0700 | [diff] [blame] | 182 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 183 | else |
| 184 | { |
| 185 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
| 186 | ASSERT(0); |
| 187 | } |
| 188 | |
| 189 | |
| 190 | if(ret) |
| 191 | { |
| 192 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
| 193 | ASSERT(0); |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | /* Configure UART clock based on the UART block id*/ |
| 198 | void clock_config_uart_dm(uint8_t id) |
| 199 | { |
| 200 | int ret; |
| 201 | char iclk[64]; |
| 202 | char cclk[64]; |
| 203 | |
| 204 | snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id); |
| 205 | snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id); |
| 206 | |
| 207 | ret = clk_get_set_enable(iclk, 0, 1); |
| 208 | if(ret) |
| 209 | { |
| 210 | dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret); |
| 211 | ASSERT(0); |
| 212 | } |
| 213 | |
| 214 | ret = clk_get_set_enable(cclk, 7372800, 1); |
| 215 | if(ret) |
| 216 | { |
| 217 | dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret); |
| 218 | ASSERT(0); |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | /* Function to asynchronously reset CE (Crypto Engine). |
| 223 | * Function assumes that all the CE clocks are off. |
| 224 | */ |
| 225 | static void ce_async_reset(uint8_t instance) |
| 226 | { |
Channagoud Kadabi | 2c48874 | 2014-12-02 11:37:18 -0800 | [diff] [blame] | 227 | if (instance == 2) |
| 228 | { |
| 229 | /* Start the block reset for CE */ |
| 230 | writel(1, GCC_CE2_BCR); |
| 231 | udelay(2); |
| 232 | /* Take CE block out of reset */ |
| 233 | writel(0, GCC_CE2_BCR); |
| 234 | udelay(2); |
| 235 | } |
| 236 | else |
| 237 | { |
| 238 | dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance); |
| 239 | ASSERT(0); |
| 240 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | void clock_ce_enable(uint8_t instance) |
| 244 | { |
Channagoud Kadabi | 2c48874 | 2014-12-02 11:37:18 -0800 | [diff] [blame] | 245 | if (instance == 2) |
| 246 | rpm_send_data(&CE2_CLK[GENERIC_ENABLE][0], 24, RPM_REQUEST_TYPE); |
| 247 | else |
| 248 | { |
| 249 | dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance); |
| 250 | ASSERT(0); |
| 251 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | void clock_ce_disable(uint8_t instance) |
| 255 | { |
Channagoud Kadabi | 2c48874 | 2014-12-02 11:37:18 -0800 | [diff] [blame] | 256 | if (instance == 2) |
| 257 | rpm_send_data(&CE2_CLK[GENERIC_DISABLE][0], 24, RPM_REQUEST_TYPE); |
| 258 | else |
| 259 | { |
| 260 | dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance); |
| 261 | ASSERT(0); |
| 262 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | void clock_config_ce(uint8_t instance) |
| 266 | { |
| 267 | /* Need to enable the clock before disabling since the clk_disable() |
| 268 | * has a check to default to nop when the clk_enable() is not called |
| 269 | * on that particular clock. |
| 270 | */ |
| 271 | clock_ce_enable(instance); |
| 272 | |
| 273 | clock_ce_disable(instance); |
| 274 | |
| 275 | ce_async_reset(instance); |
| 276 | |
| 277 | clock_ce_enable(instance); |
| 278 | |
| 279 | } |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 280 | |
| 281 | void clock_usb30_gdsc_enable(void) |
| 282 | { |
| 283 | uint32_t reg = readl(GCC_USB30_GDSCR); |
| 284 | |
| 285 | reg &= ~(0x1); |
| 286 | |
| 287 | writel(reg, GCC_USB30_GDSCR); |
| 288 | } |
| 289 | |
| 290 | /* enables usb30 clocks */ |
| 291 | void clock_usb30_init(void) |
| 292 | { |
| 293 | int ret; |
| 294 | |
| 295 | ret = clk_get_set_enable("usb30_iface_clk", 0, 1); |
| 296 | if(ret) |
| 297 | { |
| 298 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 299 | ASSERT(0); |
| 300 | } |
| 301 | |
| 302 | clock_usb30_gdsc_enable(); |
| 303 | |
| 304 | ret = clk_get_set_enable("usb30_master_clk", 125000000, 1); |
| 305 | if(ret) |
| 306 | { |
| 307 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 308 | ASSERT(0); |
| 309 | } |
| 310 | |
| 311 | ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, 1); |
| 312 | if(ret) |
| 313 | { |
| 314 | dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret); |
| 315 | ASSERT(0); |
| 316 | } |
| 317 | |
| 318 | ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1); |
| 319 | if(ret) |
| 320 | { |
| 321 | dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret); |
| 322 | ASSERT(0); |
| 323 | } |
| 324 | |
| 325 | ret = clk_get_set_enable("usb30_sleep_clk", 0, 1); |
| 326 | if(ret) |
| 327 | { |
| 328 | dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret); |
| 329 | ASSERT(0); |
| 330 | } |
| 331 | |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 332 | ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1); |
| 333 | if(ret) |
| 334 | { |
| 335 | dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret); |
| 336 | ASSERT(0); |
| 337 | } |
| 338 | |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 339 | pm8x41_lnbb_clock_ctrl(1); |
| 340 | } |
| 341 | |
| 342 | void clock_bumpup_pipe3_clk() |
| 343 | { |
| 344 | int ret = 0; |
| 345 | |
| 346 | ret = clk_get_set_enable("usb30_pipe_clk", 0, 1); |
| 347 | if(ret) |
| 348 | { |
| 349 | dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret); |
| 350 | ASSERT(0); |
| 351 | } |
| 352 | |
| 353 | return; |
| 354 | } |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 355 | |
| 356 | void mdp_gdsc_ctrl(uint8_t enable) |
| 357 | { |
| 358 | uint32_t reg = 0; |
| 359 | reg = readl(MDP_GDSCR); |
| 360 | if (enable) { |
| 361 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 362 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 363 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 364 | writel(reg, MDP_GDSCR); |
| 365 | while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 366 | } else { |
| 367 | dprintf(INFO, "MDP GDSC already enabled\n"); |
| 368 | } |
| 369 | } else { |
| 370 | reg |= BIT(0); |
| 371 | writel(reg, MDP_GDSCR); |
| 372 | while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | /* Configure MDP clock */ |
| 377 | void mdp_clock_enable(void) |
| 378 | { |
| 379 | int ret; |
| 380 | |
| 381 | /* Set MDP clock to 240MHz */ |
| 382 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 383 | if(ret) |
| 384 | { |
| 385 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 386 | ASSERT(0); |
| 387 | } |
| 388 | |
Siddhartha Agrawal | e24a18a | 2014-10-13 17:07:43 -0700 | [diff] [blame] | 389 | ret = clk_get_set_enable("mdss_mdp_clk_src", 300000000, 1); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 390 | if(ret) |
| 391 | { |
| 392 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 393 | ASSERT(0); |
| 394 | } |
| 395 | |
| 396 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 397 | if(ret) |
| 398 | { |
| 399 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 400 | ASSERT(0); |
| 401 | } |
| 402 | |
| 403 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 404 | if(ret) |
| 405 | { |
| 406 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 407 | ASSERT(0); |
| 408 | } |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 409 | } |
| 410 | |
| 411 | void mdp_clock_disable() |
| 412 | { |
| 413 | clk_disable(clk_get("mdss_vsync_clk")); |
| 414 | clk_disable(clk_get("mdss_mdp_clk")); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 415 | clk_disable(clk_get("mdss_mdp_clk_src")); |
| 416 | clk_disable(clk_get("mdp_ahb_clk")); |
| 417 | |
| 418 | } |
| 419 | |
| 420 | void mmss_bus_clock_enable(void) |
| 421 | { |
| 422 | int ret; |
| 423 | /* Configure MMSSNOC AXI clock */ |
Siddhartha Agrawal | e24a18a | 2014-10-13 17:07:43 -0700 | [diff] [blame] | 424 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 300000000, 1); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 425 | if(ret) |
| 426 | { |
| 427 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 428 | ASSERT(0); |
| 429 | } |
| 430 | |
| 431 | /* Configure S0 AXI clock */ |
Siddhartha Agrawal | e24a18a | 2014-10-13 17:07:43 -0700 | [diff] [blame] | 432 | ret = clk_get_set_enable("mmss_s0_axi_clk", 300000000, 1); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 433 | if(ret) |
| 434 | { |
| 435 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 436 | ASSERT(0); |
| 437 | } |
| 438 | |
| 439 | /* Configure AXI clock */ |
Siddhartha Agrawal | e24a18a | 2014-10-13 17:07:43 -0700 | [diff] [blame] | 440 | ret = clk_get_set_enable("mdss_axi_clk", 300000000, 1); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 441 | if(ret) |
| 442 | { |
| 443 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 444 | ASSERT(0); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | void mmss_bus_clock_disable(void) |
| 449 | { |
| 450 | /* Disable MDSS AXI clock */ |
| 451 | clk_disable(clk_get("mdss_axi_clk")); |
| 452 | |
| 453 | /* Disable MMSSNOC S0AXI clock */ |
| 454 | clk_disable(clk_get("mmss_s0_axi_clk")); |
| 455 | |
| 456 | /* Disable MMSSNOC AXI clock */ |
| 457 | clk_disable(clk_get("mmss_mmssnoc_axi_clk")); |
| 458 | } |
| 459 | |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 460 | static void rcg_update_config(uint32_t reg) |
| 461 | { |
| 462 | int i; |
| 463 | |
| 464 | for (i = 0; i < MAX_LOOPS; i++) { |
| 465 | if (!(readl(reg) & BIT(0))) |
| 466 | return; |
| 467 | udelay(1); |
| 468 | } |
| 469 | |
| 470 | dprintf(CRITICAL, "failed to update rcg config for reg = 0x%x\n", reg); |
| 471 | ASSERT(0); |
| 472 | } |
| 473 | |
| 474 | static void branch_clk_halt_check(uint32_t reg) |
| 475 | { |
| 476 | int i; |
| 477 | |
| 478 | for (i = 0; i < MAX_LOOPS; i++) { |
| 479 | if (!(readl(reg) & BIT(31))) |
| 480 | return; |
| 481 | udelay(1); |
| 482 | } |
| 483 | |
| 484 | dprintf(CRITICAL, "failed to enable branch for reg = 0x%x\n", reg); |
| 485 | ASSERT(0); |
| 486 | } |
| 487 | |
Padmanabhan Komanduru | 3ccc055 | 2015-04-27 16:46:33 -0700 | [diff] [blame] | 488 | void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags, |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 489 | uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d) |
| 490 | { |
| 491 | int ret; |
| 492 | |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 493 | if (flags & MMSS_DSI_CLKS_FLAG_DSI0) { |
| 494 | /* Enable DSI0 branch clocks */ |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 495 | |
| 496 | /* Set the source for DSI0 byte RCG */ |
Padmanabhan Komanduru | 3ccc055 | 2015-04-27 16:46:33 -0700 | [diff] [blame] | 497 | writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 498 | /* Set the update RCG bit */ |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 499 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 500 | rcg_update_config(DSI_BYTE0_CMD_RCGR); |
| 501 | /* Enable the branch clock */ |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 502 | writel(0x1, DSI_BYTE0_CBCR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 503 | branch_clk_halt_check(DSI_BYTE0_CBCR); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 504 | |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 505 | /* Set the source for DSI0 pixel RCG */ |
Padmanabhan Komanduru | 3ccc055 | 2015-04-27 16:46:33 -0700 | [diff] [blame] | 506 | writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 507 | /* Set the MND for DSI0 pixel clock */ |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 508 | writel(pclk0_m, DSI_PIXEL0_M); |
| 509 | writel(pclk0_n, DSI_PIXEL0_N); |
| 510 | writel(pclk0_d, DSI_PIXEL0_D); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 511 | /* Set the update RCG bit */ |
| 512 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 513 | rcg_update_config(DSI_PIXEL0_CMD_RCGR); |
| 514 | /* Enable the branch clock */ |
| 515 | writel(0x1, DSI_PIXEL0_CBCR); |
| 516 | branch_clk_halt_check(DSI_PIXEL0_CBCR); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 517 | |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 518 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 519 | if(ret) |
| 520 | { |
| 521 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 522 | ASSERT(0); |
| 523 | } |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 524 | } |
| 525 | |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 526 | if (flags & MMSS_DSI_CLKS_FLAG_DSI1) { |
| 527 | /* Enable DSI1 branch clocks */ |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 528 | |
| 529 | /* Set the source for DSI1 byte RCG */ |
Padmanabhan Komanduru | 3ccc055 | 2015-04-27 16:46:33 -0700 | [diff] [blame] | 530 | writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 531 | /* Set the update RCG bit */ |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 532 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 533 | rcg_update_config(DSI_BYTE1_CMD_RCGR); |
| 534 | /* Enable the branch clock */ |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 535 | writel(0x1, DSI_BYTE1_CBCR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 536 | branch_clk_halt_check(DSI_BYTE1_CBCR); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 537 | |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 538 | /* Set the source for DSI1 pixel RCG */ |
Padmanabhan Komanduru | 3ccc055 | 2015-04-27 16:46:33 -0700 | [diff] [blame] | 539 | writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 540 | /* Set the MND for DSI1 pixel clock */ |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 541 | writel(pclk0_m, DSI_PIXEL1_M); |
| 542 | writel(pclk0_n, DSI_PIXEL1_N); |
| 543 | writel(pclk0_d, DSI_PIXEL1_D); |
Padmanabhan Komanduru | 36e609f | 2015-05-04 12:52:26 -0700 | [diff] [blame] | 544 | /* Set the update RCG bit */ |
| 545 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 546 | rcg_update_config(DSI_PIXEL1_CMD_RCGR); |
| 547 | /* Enable the branch clock */ |
| 548 | writel(0x1, DSI_PIXEL1_CBCR); |
| 549 | branch_clk_halt_check(DSI_PIXEL1_CBCR); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 550 | |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 551 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 552 | if(ret) |
| 553 | { |
| 554 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 555 | ASSERT(0); |
| 556 | } |
| 557 | } |
| 558 | } |
| 559 | |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 560 | void mmss_dsi_clock_disable(uint32_t flags) |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 561 | { |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 562 | if (flags & MMSS_DSI_CLKS_FLAG_DSI0) { |
| 563 | clk_disable(clk_get("mdss_esc0_clk")); |
| 564 | writel(0x0, DSI_BYTE0_CBCR); |
| 565 | writel(0x0, DSI_PIXEL0_CBCR); |
| 566 | } |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 567 | |
Aravind Venkateswaran | f355432 | 2014-12-08 12:03:48 -0800 | [diff] [blame] | 568 | if (flags & MMSS_DSI_CLKS_FLAG_DSI1) { |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 569 | clk_disable(clk_get("mdss_esc1_clk")); |
| 570 | writel(0x0, DSI_BYTE1_CBCR); |
| 571 | writel(0x0, DSI_PIXEL1_CBCR); |
| 572 | } |
| 573 | } |
Ajay Singh Parmar | 6cf1629 | 2015-02-13 17:13:38 -0800 | [diff] [blame] | 574 | |
Casey Piper | 4b5cd7b | 2015-03-26 16:12:10 -0700 | [diff] [blame] | 575 | void hdmi_core_ahb_clk_enable(void) |
Ajay Singh Parmar | 6cf1629 | 2015-02-13 17:13:38 -0800 | [diff] [blame] | 576 | { |
| 577 | int ret; |
| 578 | |
| 579 | /* Configure hdmi ahb clock */ |
| 580 | ret = clk_get_set_enable("hdmi_ahb_clk", 0, 1); |
| 581 | if(ret) { |
| 582 | dprintf(CRITICAL, "failed to set hdmi_ahb_clk ret = %d\n", ret); |
| 583 | ASSERT(0); |
| 584 | } |
| 585 | |
| 586 | /* Configure hdmi core clock */ |
| 587 | ret = clk_get_set_enable("hdmi_core_clk", 19200000, 1); |
| 588 | if(ret) { |
| 589 | dprintf(CRITICAL, "failed to set hdmi_core_clk ret = %d\n", ret); |
| 590 | ASSERT(0); |
| 591 | } |
Casey Piper | 4b5cd7b | 2015-03-26 16:12:10 -0700 | [diff] [blame] | 592 | } |
| 593 | |
| 594 | void hdmi_pixel_clk_enable(uint32_t rate) |
| 595 | { |
| 596 | int ret; |
Ajay Singh Parmar | 6cf1629 | 2015-02-13 17:13:38 -0800 | [diff] [blame] | 597 | |
| 598 | /* Configure hdmi pixel clock */ |
Casey Piper | 4b5cd7b | 2015-03-26 16:12:10 -0700 | [diff] [blame] | 599 | ret = clk_get_set_enable("hdmi_extp_clk", rate, 1); |
Ajay Singh Parmar | 6cf1629 | 2015-02-13 17:13:38 -0800 | [diff] [blame] | 600 | if(ret) { |
| 601 | dprintf(CRITICAL, "failed to set hdmi_extp_clk ret = %d\n", ret); |
| 602 | ASSERT(0); |
| 603 | } |
| 604 | } |
| 605 | |
Casey Piper | 4b5cd7b | 2015-03-26 16:12:10 -0700 | [diff] [blame] | 606 | void hdmi_pixel_clk_disable(void) |
Ajay Singh Parmar | 6cf1629 | 2015-02-13 17:13:38 -0800 | [diff] [blame] | 607 | { |
| 608 | clk_disable(clk_get("hdmi_extp_clk")); |
Casey Piper | 4b5cd7b | 2015-03-26 16:12:10 -0700 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | void hdmi_core_ahb_clk_disable(void) |
| 612 | { |
Ajay Singh Parmar | 6cf1629 | 2015-02-13 17:13:38 -0800 | [diff] [blame] | 613 | clk_disable(clk_get("hdmi_core_clk")); |
| 614 | clk_disable(clk_get("hdmi_ahb_clk")); |
| 615 | } |