blob: 1b35bdbd5d74fca4bfe262bacd56c3bab03cdb83 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07007 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08008 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07009 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010010 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010011 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020012 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010013 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000014 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000015 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000016 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000017 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000018 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010019 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000020 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010021 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000022 select ARM_GIC_V3_ITS if PCI_MSI
Mark Rutlandbff60792015-07-31 15:46:16 +010023 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010024 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000025 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070026 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000027 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000028 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010029 select EDAC_SUPPORT
Laura Abbottd4932f92014-10-09 15:26:44 -070030 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010031 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010032 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000033 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070034 select GENERIC_EARLY_IOREMAP
Leo Yan2314ee42015-08-21 04:40:22 +010035 select GENERIC_IDLE_POLL_SETUP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010036 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010038 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010039 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070040 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010041 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000042 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010044 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010045 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010046 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010047 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010048 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010049 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080050 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000051 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000052 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010053 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070054 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010055 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010056 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010057 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010058 select HAVE_CMPXCHG_LOCAL
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070059 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070060 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_DMA_API_DEBUG
62 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000063 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010064 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000065 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010066 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090067 select HAVE_FUNCTION_TRACER
68 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000072 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010073 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010074 select HAVE_PERF_REGS
75 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070076 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010077 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020079 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010080 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010081 select NO_BOOTMEM
82 select OF
83 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010084 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010085 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000086 select POWER_RESET
87 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010088 select RTC_LIB
89 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070090 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070091 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010092 help
93 ARM 64-bit (AArch64) Linux support.
94
95config 64BIT
96 def_bool y
97
98config ARCH_PHYS_ADDR_T_64BIT
99 def_bool y
100
101config MMU
102 def_bool y
103
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700104config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100105 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100106
107config STACKTRACE_SUPPORT
108 def_bool y
109
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100110config ILLEGAL_POINTER_VALUE
111 hex
112 default 0xdead000000000000
113
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100114config LOCKDEP_SUPPORT
115 def_bool y
116
117config TRACE_IRQFLAGS_SUPPORT
118 def_bool y
119
Will Deaconc209f792014-03-14 17:47:05 +0000120config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100121 def_bool y
122
Dave P Martin9fb74102015-07-24 16:37:48 +0100123config GENERIC_BUG
124 def_bool y
125 depends on BUG
126
127config GENERIC_BUG_RELATIVE_POINTERS
128 def_bool y
129 depends on GENERIC_BUG
130
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100131config GENERIC_HWEIGHT
132 def_bool y
133
134config GENERIC_CSUM
135 def_bool y
136
137config GENERIC_CALIBRATE_DELAY
138 def_bool y
139
Catalin Marinas19e76402014-02-27 12:09:22 +0000140config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100141 def_bool y
142
Steve Capper29e56942014-10-09 15:29:25 -0700143config HAVE_GENERIC_RCU_GUP
144 def_bool y
145
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100146config ARCH_DMA_ADDR_T_64BIT
147 def_bool y
148
149config NEED_DMA_MAP_STATE
150 def_bool y
151
152config NEED_SG_DMA_LENGTH
153 def_bool y
154
Will Deacon4b3dc962015-05-29 18:28:44 +0100155config SMP
156 def_bool y
157
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100158config SWIOTLB
159 def_bool y
160
161config IOMMU_HELPER
162 def_bool SWIOTLB
163
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100164config KERNEL_MODE_NEON
165 def_bool y
166
Rob Herring92cc15f2014-04-18 17:19:59 -0500167config FIX_EARLYCON_MEM
168 def_bool y
169
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700170config PGTABLE_LEVELS
171 int
172 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
173 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
174 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
175 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
176
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100177source "init/Kconfig"
178
179source "kernel/Kconfig.freezer"
180
Olof Johansson6a377492015-07-20 12:09:16 -0700181source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100182
183menu "Bus support"
184
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100185config PCI
186 bool "PCI support"
187 help
188 This feature enables support for PCI bus system. If you say Y
189 here, the kernel will include drivers and infrastructure code
190 to support PCI bus devices.
191
192config PCI_DOMAINS
193 def_bool PCI
194
195config PCI_DOMAINS_GENERIC
196 def_bool PCI
197
198config PCI_SYSCALL
199 def_bool PCI
200
201source "drivers/pci/Kconfig"
202source "drivers/pci/pcie/Kconfig"
203source "drivers/pci/hotplug/Kconfig"
204
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100205endmenu
206
207menu "Kernel Features"
208
Andre Przywarac0a01b82014-11-14 15:54:12 +0000209menu "ARM errata workarounds via the alternatives framework"
210
211config ARM64_ERRATUM_826319
212 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
213 default y
214 help
215 This option adds an alternative code sequence to work around ARM
216 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
217 AXI master interface and an L2 cache.
218
219 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
220 and is unable to accept a certain write via this interface, it will
221 not progress on read data presented on the read data channel and the
222 system can deadlock.
223
224 The workaround promotes data cache clean instructions to
225 data cache clean-and-invalidate.
226 Please note that this does not necessarily enable the workaround,
227 as it depends on the alternative framework, which will only patch
228 the kernel if an affected CPU is detected.
229
230 If unsure, say Y.
231
232config ARM64_ERRATUM_827319
233 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
234 default y
235 help
236 This option adds an alternative code sequence to work around ARM
237 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
238 master interface and an L2 cache.
239
240 Under certain conditions this erratum can cause a clean line eviction
241 to occur at the same time as another transaction to the same address
242 on the AMBA 5 CHI interface, which can cause data corruption if the
243 interconnect reorders the two transactions.
244
245 The workaround promotes data cache clean instructions to
246 data cache clean-and-invalidate.
247 Please note that this does not necessarily enable the workaround,
248 as it depends on the alternative framework, which will only patch
249 the kernel if an affected CPU is detected.
250
251 If unsure, say Y.
252
253config ARM64_ERRATUM_824069
254 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
255 default y
256 help
257 This option adds an alternative code sequence to work around ARM
258 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
259 to a coherent interconnect.
260
261 If a Cortex-A53 processor is executing a store or prefetch for
262 write instruction at the same time as a processor in another
263 cluster is executing a cache maintenance operation to the same
264 address, then this erratum might cause a clean cache line to be
265 incorrectly marked as dirty.
266
267 The workaround promotes data cache clean instructions to
268 data cache clean-and-invalidate.
269 Please note that this option does not necessarily enable the
270 workaround, as it depends on the alternative framework, which will
271 only patch the kernel if an affected CPU is detected.
272
273 If unsure, say Y.
274
275config ARM64_ERRATUM_819472
276 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
277 default y
278 help
279 This option adds an alternative code sequence to work around ARM
280 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
281 present when it is connected to a coherent interconnect.
282
283 If the processor is executing a load and store exclusive sequence at
284 the same time as a processor in another cluster is executing a cache
285 maintenance operation to the same address, then this erratum might
286 cause data corruption.
287
288 The workaround promotes data cache clean instructions to
289 data cache clean-and-invalidate.
290 Please note that this does not necessarily enable the workaround,
291 as it depends on the alternative framework, which will only patch
292 the kernel if an affected CPU is detected.
293
294 If unsure, say Y.
295
296config ARM64_ERRATUM_832075
297 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
298 default y
299 help
300 This option adds an alternative code sequence to work around ARM
301 erratum 832075 on Cortex-A57 parts up to r1p2.
302
303 Affected Cortex-A57 parts might deadlock when exclusive load/store
304 instructions to Write-Back memory are mixed with Device loads.
305
306 The workaround is to promote device loads to use Load-Acquire
307 semantics.
308 Please note that this does not necessarily enable the workaround,
309 as it depends on the alternative framework, which will only patch
310 the kernel if an affected CPU is detected.
311
312 If unsure, say Y.
313
Will Deacon905e8c52015-03-23 19:07:02 +0000314config ARM64_ERRATUM_845719
315 bool "Cortex-A53: 845719: a load might read incorrect data"
316 depends on COMPAT
317 default y
318 help
319 This option adds an alternative code sequence to work around ARM
320 erratum 845719 on Cortex-A53 parts up to r0p4.
321
322 When running a compat (AArch32) userspace on an affected Cortex-A53
323 part, a load at EL0 from a virtual address that matches the bottom 32
324 bits of the virtual address used by a recent load at (AArch64) EL1
325 might return incorrect data.
326
327 The workaround is to write the contextidr_el1 register on exception
328 return to a 32-bit task.
329 Please note that this does not necessarily enable the workaround,
330 as it depends on the alternative framework, which will only patch
331 the kernel if an affected CPU is detected.
332
333 If unsure, say Y.
334
Will Deacondf057cc2015-03-17 12:15:02 +0000335config ARM64_ERRATUM_843419
336 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
337 depends on MODULES
338 default y
339 help
340 This option builds kernel modules using the large memory model in
341 order to avoid the use of the ADRP instruction, which can cause
342 a subsequent memory access to use an incorrect address on Cortex-A53
343 parts up to r0p4.
344
345 Note that the kernel itself must be linked with a version of ld
346 which fixes potentially affected ADRP instructions through the
347 use of veneers.
348
349 If unsure, say Y.
350
Andre Przywarac0a01b82014-11-14 15:54:12 +0000351endmenu
352
353
Jungseok Leee41ceed2014-05-12 10:40:38 +0100354choice
355 prompt "Page size"
356 default ARM64_4K_PAGES
357 help
358 Page size (translation granule) configuration.
359
360config ARM64_4K_PAGES
361 bool "4KB"
362 help
363 This feature enables 4KB pages support.
364
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100365config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100366 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100367 help
368 This feature enables 64KB pages support (4KB by default)
369 allowing only two levels of page tables and faster TLB
370 look-up. AArch32 emulation is not available when this feature
371 is enabled.
372
Jungseok Leee41ceed2014-05-12 10:40:38 +0100373endchoice
374
375choice
376 prompt "Virtual address space size"
377 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
378 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
379 help
380 Allows choosing one of multiple possible virtual address
381 space sizes. The level of translation table is determined by
382 a combination of page size and virtual address space size.
383
384config ARM64_VA_BITS_39
385 bool "39-bit"
386 depends on ARM64_4K_PAGES
387
388config ARM64_VA_BITS_42
389 bool "42-bit"
390 depends on ARM64_64K_PAGES
391
Jungseok Leec79b9542014-05-12 18:40:51 +0900392config ARM64_VA_BITS_48
393 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900394
Jungseok Leee41ceed2014-05-12 10:40:38 +0100395endchoice
396
397config ARM64_VA_BITS
398 int
399 default 39 if ARM64_VA_BITS_39
400 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900401 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100402
Will Deacona8720132013-10-11 14:52:19 +0100403config CPU_BIG_ENDIAN
404 bool "Build big-endian kernel"
405 help
406 Say Y if you plan on running a kernel in big-endian mode.
407
Mark Brownf6e763b2014-03-04 07:51:17 +0000408config SCHED_MC
409 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000410 help
411 Multi-core scheduler support improves the CPU scheduler's decision
412 making when dealing with multi-core CPU chips at a cost of slightly
413 increased overhead in some places. If unsure say N here.
414
415config SCHED_SMT
416 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000417 help
418 Improves the CPU scheduler's decision making when dealing with
419 MultiThreading at a cost of slightly increased overhead in some
420 places. If unsure say N here.
421
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100422config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000423 int "Maximum number of CPUs (2-4096)"
424 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100425 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100426 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100427
Mark Rutland9327e2c2013-10-24 20:30:18 +0100428config HOTPLUG_CPU
429 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +0800430 select GENERIC_IRQ_MIGRATION
Mark Rutland9327e2c2013-10-24 20:30:18 +0100431 help
432 Say Y here to experiment with turning CPUs off and on. CPUs
433 can be controlled through /sys/devices/system/cpu.
434
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100435source kernel/Kconfig.preempt
436
437config HZ
438 int
439 default 100
440
441config ARCH_HAS_HOLES_MEMORYMODEL
442 def_bool y if SPARSEMEM
443
444config ARCH_SPARSEMEM_ENABLE
445 def_bool y
446 select SPARSEMEM_VMEMMAP_ENABLE
447
448config ARCH_SPARSEMEM_DEFAULT
449 def_bool ARCH_SPARSEMEM_ENABLE
450
451config ARCH_SELECT_MEMORY_MODEL
452 def_bool ARCH_SPARSEMEM_ENABLE
453
454config HAVE_ARCH_PFN_VALID
455 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
456
457config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +0100458 def_bool y
459 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100460
Steve Capper084bd292013-04-10 13:48:00 +0100461config SYS_SUPPORTS_HUGETLBFS
462 def_bool y
463
464config ARCH_WANT_GENERAL_HUGETLB
465 def_bool y
466
467config ARCH_WANT_HUGE_PMD_SHARE
468 def_bool y if !ARM64_64K_PAGES
469
Steve Capperaf074842013-04-19 16:23:57 +0100470config HAVE_ARCH_TRANSPARENT_HUGEPAGE
471 def_bool y
472
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100473config ARCH_HAS_CACHE_LINE_SIZE
474 def_bool y
475
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100476source "mm/Kconfig"
477
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000478config SECCOMP
479 bool "Enable seccomp to safely compute untrusted bytecode"
480 ---help---
481 This kernel feature is useful for number crunching applications
482 that may need to compute untrusted bytecode during their
483 execution. By using pipes or other transports made available to
484 the process as file descriptors supporting the read/write
485 syscalls, it's possible to isolate those applications in
486 their own address space using seccomp. Once seccomp is
487 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
488 and the task is only allowed to execute a few safe syscalls
489 defined by each seccomp mode.
490
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000491config XEN_DOM0
492 def_bool y
493 depends on XEN
494
495config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700496 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000497 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000498 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000499 help
500 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
501
Steve Capperd03bb142013-04-25 15:19:21 +0100502config FORCE_MAX_ZONEORDER
503 int
504 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
505 default "11"
506
Will Deacon1b907f42014-11-20 16:51:10 +0000507menuconfig ARMV8_DEPRECATED
508 bool "Emulate deprecated/obsolete ARMv8 instructions"
509 depends on COMPAT
510 help
511 Legacy software support may require certain instructions
512 that have been deprecated or obsoleted in the architecture.
513
514 Enable this config to enable selective emulation of these
515 features.
516
517 If unsure, say Y
518
519if ARMV8_DEPRECATED
520
521config SWP_EMULATION
522 bool "Emulate SWP/SWPB instructions"
523 help
524 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
525 they are always undefined. Say Y here to enable software
526 emulation of these instructions for userspace using LDXR/STXR.
527
528 In some older versions of glibc [<=2.8] SWP is used during futex
529 trylock() operations with the assumption that the code will not
530 be preempted. This invalid assumption may be more likely to fail
531 with SWP emulation enabled, leading to deadlock of the user
532 application.
533
534 NOTE: when accessing uncached shared regions, LDXR/STXR rely
535 on an external transaction monitoring block called a global
536 monitor to maintain update atomicity. If your system does not
537 implement a global monitor, this option can cause programs that
538 perform SWP operations to uncached memory to deadlock.
539
540 If unsure, say Y
541
542config CP15_BARRIER_EMULATION
543 bool "Emulate CP15 Barrier instructions"
544 help
545 The CP15 barrier instructions - CP15ISB, CP15DSB, and
546 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
547 strongly recommended to use the ISB, DSB, and DMB
548 instructions instead.
549
550 Say Y here to enable software emulation of these
551 instructions for AArch32 userspace code. When this option is
552 enabled, CP15 barrier usage is traced which can help
553 identify software that needs updating.
554
555 If unsure, say Y
556
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000557config SETEND_EMULATION
558 bool "Emulate SETEND instruction"
559 help
560 The SETEND instruction alters the data-endianness of the
561 AArch32 EL0, and is deprecated in ARMv8.
562
563 Say Y here to enable software emulation of the instruction
564 for AArch32 userspace code.
565
566 Note: All the cpus on the system must have mixed endian support at EL0
567 for this feature to be enabled. If a new CPU - which doesn't support mixed
568 endian - is hotplugged in after this feature has been enabled, there could
569 be unexpected results in the applications.
570
571 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000572endif
573
Will Deacon0e4a0702015-07-27 15:54:13 +0100574menu "ARMv8.1 architectural features"
575
576config ARM64_HW_AFDBM
577 bool "Support for hardware updates of the Access and Dirty page flags"
578 default y
579 help
580 The ARMv8.1 architecture extensions introduce support for
581 hardware updates of the access and dirty information in page
582 table entries. When enabled in TCR_EL1 (HA and HD bits) on
583 capable processors, accesses to pages with PTE_AF cleared will
584 set this bit instead of raising an access flag fault.
585 Similarly, writes to read-only pages with the DBM bit set will
586 clear the read-only bit (AP[2]) instead of raising a
587 permission fault.
588
589 Kernels built with this configuration option enabled continue
590 to work on pre-ARMv8.1 hardware and the performance impact is
591 minimal. If unsure, say Y.
592
593config ARM64_PAN
594 bool "Enable support for Privileged Access Never (PAN)"
595 default y
596 help
597 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
598 prevents the kernel or hypervisor from accessing user-space (EL0)
599 memory directly.
600
601 Choosing this option will cause any unprotected (not using
602 copy_to_user et al) memory access to fail with a permission fault.
603
604 The feature is detected at runtime, and will remain as a 'nop'
605 instruction if the cpu does not implement the feature.
606
607config ARM64_LSE_ATOMICS
608 bool "Atomic instructions"
609 help
610 As part of the Large System Extensions, ARMv8.1 introduces new
611 atomic instructions that are designed specifically to scale in
612 very large systems.
613
614 Say Y here to make use of these instructions for the in-kernel
615 atomic routines. This incurs a small overhead on CPUs that do
616 not support these instructions and requires the kernel to be
617 built with binutils >= 2.25.
618
619endmenu
620
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100621endmenu
622
623menu "Boot options"
624
625config CMDLINE
626 string "Default kernel command string"
627 default ""
628 help
629 Provide a set of default command-line options at build time by
630 entering them here. As a minimum, you should specify the the
631 root device (e.g. root=/dev/nfs).
632
633config CMDLINE_FORCE
634 bool "Always use the default kernel command string"
635 help
636 Always use the default kernel command string, even if the boot
637 loader passes other arguments to the kernel.
638 This is useful if you cannot or don't want to change the
639 command-line options your boot loader passes to the kernel.
640
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200641config EFI_STUB
642 bool
643
Mark Salterf84d0272014-04-15 21:59:30 -0400644config EFI
645 bool "UEFI runtime support"
646 depends on OF && !CPU_BIG_ENDIAN
647 select LIBFDT
648 select UCS2_STRING
649 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200650 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200651 select EFI_STUB
652 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400653 default y
654 help
655 This option provides support for runtime services provided
656 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400657 clock, and platform reset). A UEFI stub is also provided to
658 allow the kernel to be booted as an EFI application. This
659 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400660
Yi Lid1ae8c02014-10-04 23:46:43 +0800661config DMI
662 bool "Enable support for SMBIOS (DMI) tables"
663 depends on EFI
664 default y
665 help
666 This enables SMBIOS/DMI feature for systems.
667
668 This option is only useful on systems that have UEFI firmware.
669 However, even with this option, the resultant kernel should
670 continue to boot on existing non-UEFI platforms.
671
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100672endmenu
673
674menu "Userspace binary formats"
675
676source "fs/Kconfig.binfmt"
677
678config COMPAT
679 bool "Kernel support for 32-bit EL0"
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000680 depends on !ARM64_64K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100681 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700682 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500683 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500684 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100685 help
686 This option enables support for a 32-bit EL0 running under a 64-bit
687 kernel at EL1. AArch32-specific components such as system calls,
688 the user helper functions, VFP support and the ptrace interface are
689 handled appropriately by the kernel.
690
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000691 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
692 will only be able to execute AArch32 binaries that were compiled with
693 64k aligned segments.
694
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100695 If you want to execute 32-bit userspace applications, say Y.
696
697config SYSVIPC_COMPAT
698 def_bool y
699 depends on COMPAT && SYSVIPC
700
701endmenu
702
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000703menu "Power management options"
704
705source "kernel/power/Kconfig"
706
707config ARCH_SUSPEND_POSSIBLE
708 def_bool y
709
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000710endmenu
711
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100712menu "CPU Power Management"
713
714source "drivers/cpuidle/Kconfig"
715
Rob Herring52e7e812014-02-24 11:27:57 +0900716source "drivers/cpufreq/Kconfig"
717
718endmenu
719
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100720source "net/Kconfig"
721
722source "drivers/Kconfig"
723
Mark Salterf84d0272014-04-15 21:59:30 -0400724source "drivers/firmware/Kconfig"
725
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000726source "drivers/acpi/Kconfig"
727
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100728source "fs/Kconfig"
729
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100730source "arch/arm64/kvm/Kconfig"
731
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100732source "arch/arm64/Kconfig.debug"
733
734source "security/Kconfig"
735
736source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800737if CRYPTO
738source "arch/arm64/crypto/Kconfig"
739endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100740
741source "lib/Kconfig"