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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070014#include <linux/pm.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/module.h>
17#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080018#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053019#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080020#include <linux/pci-aspm.h>
Stephen Rothwellc300bd2fb2008-07-10 02:16:44 +020021#include <linux/pm_wakeup.h>
Sheng Yang8dd7f802008-10-21 17:38:25 +080022#include <linux/interrupt.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090023#include <linux/device.h>
Rafael J. Wysockib67ea762010-02-17 23:44:09 +010024#include <linux/pm_runtime.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090025#include <asm/setup.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090026#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Alan Stern00240c32009-04-27 13:33:16 -040028const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30};
31EXPORT_SYMBOL_GPL(pci_power_names);
32
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010033int isa_dma_bridge_buggy;
34EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36int pci_pci_problems;
37EXPORT_SYMBOL(pci_pci_problems);
38
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +010039unsigned int pci_pm_d3_delay;
40
Matthew Garrettdf17e622010-10-04 14:22:29 -040041static void pci_pme_list_scan(struct work_struct *work);
42
43static LIST_HEAD(pci_pme_list);
44static DEFINE_MUTEX(pci_pme_list_mutex);
45static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
46
47struct pci_pme_device {
48 struct list_head list;
49 struct pci_dev *dev;
50};
51
52#define PME_TIMEOUT 1000 /* How long between PME checks */
53
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +010054static void pci_dev_d3_sleep(struct pci_dev *dev)
55{
56 unsigned int delay = dev->d3_delay;
57
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
60
61 msleep(delay);
62}
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Jeff Garzik32a2eea2007-10-11 16:57:27 -040064#ifdef CONFIG_PCI_DOMAINS
65int pci_domains_supported = 1;
66#endif
67
Atsushi Nemoto4516a612007-02-05 16:36:06 -080068#define DEFAULT_CARDBUS_IO_SIZE (256)
69#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70/* pci=cbmemsize=nnM,cbiosize=nn can override this */
71unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
73
Eric W. Biederman28760482009-09-09 14:09:24 -070074#define DEFAULT_HOTPLUG_IO_SIZE (256)
75#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76/* pci=hpmemsize=nnM,hpiosize=nn can override this */
77unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
79
Jesse Barnesac1aa472009-10-26 13:20:44 -070080/*
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
85 */
Tejun Heo98e724c2009-10-08 18:59:53 +090086u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
Jesse Barnesac1aa472009-10-26 13:20:44 -070087u8 pci_cache_line_size;
88
Linus Torvalds1da177e2005-04-16 15:20:36 -070089/**
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
92 *
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
95 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080096unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070097{
98 struct list_head *tmp;
99 unsigned char max, n;
100
Kristen Accardib82db5c2006-01-17 16:56:56 -0800101 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 list_for_each(tmp, &bus->children) {
103 n = pci_bus_max_busnr(pci_bus_b(tmp));
104 if(n > max)
105 max = n;
106 }
107 return max;
108}
Kristen Accardib82db5c2006-01-17 16:56:56 -0800109EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
Andrew Morton1684f5d2008-12-01 14:30:30 -0800111#ifdef CONFIG_HAS_IOMEM
112void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
113{
114 /*
115 * Make sure the BAR is actually a memory resource, not an IO resource
116 */
117 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
118 WARN_ON(1);
119 return NULL;
120 }
121 return ioremap_nocache(pci_resource_start(pdev, bar),
122 pci_resource_len(pdev, bar));
123}
124EXPORT_SYMBOL_GPL(pci_ioremap_bar);
125#endif
126
Kristen Accardib82db5c2006-01-17 16:56:56 -0800127#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128/**
129 * pci_max_busnr - returns maximum PCI bus number
130 *
131 * Returns the highest PCI bus number present in the system global list of
132 * PCI buses.
133 */
134unsigned char __devinit
135pci_max_busnr(void)
136{
137 struct pci_bus *bus = NULL;
138 unsigned char max, n;
139
140 max = 0;
141 while ((bus = pci_find_next_bus(bus)) != NULL) {
142 n = pci_bus_max_busnr(bus);
143 if(n > max)
144 max = n;
145 }
146 return max;
147}
148
Adrian Bunk54c762f2005-12-22 01:08:52 +0100149#endif /* 0 */
150
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100151#define PCI_FIND_CAP_TTL 48
152
153static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
154 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -0700155{
156 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -0700157
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100158 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -0700159 pci_bus_read_config_byte(bus, devfn, pos, &pos);
160 if (pos < 0x40)
161 break;
162 pos &= ~3;
163 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
164 &id);
165 if (id == 0xff)
166 break;
167 if (id == cap)
168 return pos;
169 pos += PCI_CAP_LIST_NEXT;
170 }
171 return 0;
172}
173
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100174static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
175 u8 pos, int cap)
176{
177 int ttl = PCI_FIND_CAP_TTL;
178
179 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
180}
181
Roland Dreier24a4e372005-10-28 17:35:34 -0700182int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
183{
184 return __pci_find_next_cap(dev->bus, dev->devfn,
185 pos + PCI_CAP_LIST_NEXT, cap);
186}
187EXPORT_SYMBOL_GPL(pci_find_next_capability);
188
Michael Ellermand3bac112006-11-22 18:26:16 +1100189static int __pci_bus_find_cap_start(struct pci_bus *bus,
190 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191{
192 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193
194 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
195 if (!(status & PCI_STATUS_CAP_LIST))
196 return 0;
197
198 switch (hdr_type) {
199 case PCI_HEADER_TYPE_NORMAL:
200 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100201 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100203 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 default:
205 return 0;
206 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100207
208 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209}
210
211/**
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
215 *
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
220 *
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
229 */
230int pci_find_capability(struct pci_dev *dev, int cap)
231{
Michael Ellermand3bac112006-11-22 18:26:16 +1100232 int pos;
233
234 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
235 if (pos)
236 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
237
238 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239}
240
241/**
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
246 *
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
249 *
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
252 * support it.
253 */
254int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
255{
Michael Ellermand3bac112006-11-22 18:26:16 +1100256 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 u8 hdr_type;
258
259 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
260
Michael Ellermand3bac112006-11-22 18:26:16 +1100261 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
262 if (pos)
263 pos = __pci_find_next_cap(bus, devfn, pos, cap);
264
265 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266}
267
268/**
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
272 *
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
276 *
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
281 */
282int pci_find_ext_capability(struct pci_dev *dev, int cap)
283{
284 u32 header;
Zhao, Yu557848c2008-10-13 19:18:07 +0800285 int ttl;
286 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
Zhao, Yu557848c2008-10-13 19:18:07 +0800288 /* minimum 8 bytes per capability */
289 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
290
291 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 return 0;
293
294 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
295 return 0;
296
297 /*
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
300 */
301 if (header == 0)
302 return 0;
303
304 while (ttl-- > 0) {
305 if (PCI_EXT_CAP_ID(header) == cap)
306 return pos;
307
308 pos = PCI_EXT_CAP_NEXT(header);
Zhao, Yu557848c2008-10-13 19:18:07 +0800309 if (pos < PCI_CFG_SPACE_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 break;
311
312 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
313 break;
314 }
315
316 return 0;
317}
Brice Goglin3a720d72006-05-23 06:10:01 -0400318EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319
Jesse Barnescf4c43d2009-07-15 13:13:00 -0700320/**
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
325 *
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
328 *
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
331 * support it.
332 */
333int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
334 int cap)
335{
336 u32 header;
337 int ttl;
338 int pos = PCI_CFG_SPACE_SIZE;
339
340 /* minimum 8 bytes per capability */
341 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
342
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
344 return 0;
345 if (header == 0xffffffff || header == 0)
346 return 0;
347
348 while (ttl-- > 0) {
349 if (PCI_EXT_CAP_ID(header) == cap)
350 return pos;
351
352 pos = PCI_EXT_CAP_NEXT(header);
353 if (pos < PCI_CFG_SPACE_SIZE)
354 break;
355
356 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
357 break;
358 }
359
360 return 0;
361}
362
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100363static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
364{
365 int rc, ttl = PCI_FIND_CAP_TTL;
366 u8 cap, mask;
367
368 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
369 mask = HT_3BIT_CAP_MASK;
370 else
371 mask = HT_5BIT_CAP_MASK;
372
373 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
374 PCI_CAP_ID_HT, &ttl);
375 while (pos) {
376 rc = pci_read_config_byte(dev, pos + 3, &cap);
377 if (rc != PCIBIOS_SUCCESSFUL)
378 return 0;
379
380 if ((cap & mask) == ht_cap)
381 return pos;
382
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
384 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100385 PCI_CAP_ID_HT, &ttl);
386 }
387
388 return 0;
389}
390/**
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
395 *
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
399 *
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
402 */
403int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
404{
405 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
406}
407EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
408
409/**
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
413 *
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
419 */
420int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
421{
422 int pos;
423
424 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
425 if (pos)
426 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
427
428 return pos;
429}
430EXPORT_SYMBOL_GPL(pci_find_ht_capability);
431
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432/**
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
436 *
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
440 */
441struct resource *
442pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
443{
444 const struct pci_bus *bus = dev->bus;
445 int i;
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700446 struct resource *best = NULL, *r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700448 pci_bus_for_each_resource(bus, r, i) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 if (!r)
450 continue;
451 if (res->start && !(res->start >= r->start && res->end <= r->end))
452 continue; /* Not contained */
453 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
454 continue; /* Wrong type */
455 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
456 return r; /* Exact match */
Linus Torvalds8c8def22009-11-09 12:04:32 -0800457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r->flags & IORESOURCE_PREFETCH)
459 continue;
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
461 if (!best)
462 best = r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 }
464 return best;
465}
466
467/**
John W. Linville064b53db2005-07-27 10:19:44 -0400468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
470 *
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
473 */
Adrian Bunkad6685992007-10-27 03:06:22 +0200474static void
John W. Linville064b53db2005-07-27 10:19:44 -0400475pci_restore_bars(struct pci_dev *dev)
476{
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800477 int i;
John W. Linville064b53db2005-07-27 10:19:44 -0400478
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800479 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
Yu Zhao14add802008-11-22 02:38:52 +0800480 pci_update_resource(dev, i);
John W. Linville064b53db2005-07-27 10:19:44 -0400481}
482
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200483static struct pci_platform_pm_ops *pci_platform_pm;
484
485int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
486{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200487 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
488 || !ops->sleep_wake || !ops->can_wakeup)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200489 return -EINVAL;
490 pci_platform_pm = ops;
491 return 0;
492}
493
494static inline bool platform_pci_power_manageable(struct pci_dev *dev)
495{
496 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
497}
498
499static inline int platform_pci_set_power_state(struct pci_dev *dev,
500 pci_power_t t)
501{
502 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
503}
504
505static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
506{
507 return pci_platform_pm ?
508 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
509}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700510
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200511static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
512{
513 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
514}
515
516static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
517{
518 return pci_platform_pm ?
519 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
520}
521
Rafael J. Wysockib67ea762010-02-17 23:44:09 +0100522static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
523{
524 return pci_platform_pm ?
525 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
526}
527
John W. Linville064b53db2005-07-27 10:19:44 -0400528/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
530 * given PCI device
531 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200534 * RETURN VALUE:
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 */
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100541static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200543 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200544 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100546 /* Check if we're already there */
547 if (dev->current_state == state)
548 return 0;
549
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200550 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700551 return -EIO;
552
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200553 if (state < PCI_D0 || state > PCI_D3hot)
554 return -EINVAL;
555
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
559 */
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100560 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200561 && dev->current_state > state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600562 dev_err(&dev->dev, "invalid power transition "
563 "(from state %d to %d)\n", dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200565 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200568 if ((state == PCI_D1 && !dev->d1_support)
569 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700570 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53db2005-07-27 10:19:44 -0400573
John W. Linville32a36582005-09-14 09:52:42 -0400574 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
577 */
John W. Linville32a36582005-09-14 09:52:42 -0400578 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400579 case PCI_D0:
580 case PCI_D1:
581 case PCI_D2:
582 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
583 pmcsr |= state;
584 break;
Rafael J. Wysockif62795f2009-05-18 22:51:12 +0200585 case PCI_D3hot:
586 case PCI_D3cold:
John W. Linville32a36582005-09-14 09:52:42 -0400587 case PCI_UNKNOWN: /* Boot-up */
588 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100589 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200590 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400591 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400592 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400593 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400594 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595 }
596
597 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200598 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +0100603 pci_dev_d3_sleep(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 else if (state == PCI_D2 || dev->current_state == PCI_D2)
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100605 udelay(PCI_PM_D2_DELAY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606
Rafael J. Wysockie13cdbd2009-10-05 00:48:40 +0200607 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
608 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
609 if (dev->current_state != state && printk_ratelimit())
610 dev_info(&dev->dev, "Refused to change power state, "
611 "currently in D%d\n", dev->current_state);
John W. Linville064b53db2005-07-27 10:19:44 -0400612
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
619 *
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
624 */
625 if (need_restore)
626 pci_restore_bars(dev);
627
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100628 if (dev->bus->self)
Shaohua Li7d715a62008-02-25 09:46:41 +0800629 pcie_aspm_pm_state_change(dev->bus->self);
630
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 return 0;
632}
633
634/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100638 * @state: State to cache in case the device doesn't have the PM capability
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200639 */
Rafael J. Wysocki734104292009-01-07 13:07:15 +0100640void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200641{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200642 if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200643 u16 pmcsr;
644
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200645 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200646 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100647 } else {
648 dev->current_state = state;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200649 }
650}
651
652/**
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
656 */
657static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
658{
659 int error;
660
661 if (platform_pci_power_manageable(dev)) {
662 error = platform_pci_set_power_state(dev, state);
663 if (!error)
664 pci_update_current_state(dev, state);
665 } else {
666 error = -ENODEV;
667 /* Fall back to PCI_D0 if native PM is not supported */
Rafael J. Wysockib3bad722009-05-17 20:17:06 +0200668 if (!dev->pm_cap)
669 dev->current_state = PCI_D0;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100670 }
671
672 return error;
673}
674
675/**
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
679 */
680static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
681{
682 if (state == PCI_D0)
683 pci_platform_power_transition(dev, PCI_D0);
684}
685
686/**
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
690 *
691 * This function should not be called directly by device drivers.
692 */
693int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
694{
Matthew Garrettcc2893b2010-04-22 09:30:51 -0400695 return state >= PCI_D0 ?
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100696 pci_platform_power_transition(dev, state) : -EINVAL;
697}
698EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
699
700/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
704 *
Nick Andrew877d0312009-01-26 11:06:57 +0100705 * Transition a device to a new power state, using the platform firmware and/or
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200706 * the device's PCI PM registers.
707 *
708 * RETURN VALUE:
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
714 */
715int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
716{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200717 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200718
719 /* bound the state we're entering */
720 if (state > PCI_D3hot)
721 state = PCI_D3hot;
722 else if (state < PCI_D0)
723 state = PCI_D0;
724 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
725 /*
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
729 */
730 return 0;
731
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100732 __pci_start_power_transition(dev, state);
733
Alan Cox979b1792008-07-24 17:18:38 +0100734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
737 return 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200738
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100739 error = pci_raw_set_power_state(dev, state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200740
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100741 if (!__pci_complete_power_transition(dev, state))
742 error = 0;
Naga Chumbalkar1a680b72011-03-21 03:29:08 +0000743 /*
744 * When aspm_policy is "powersave" this call ensures
745 * that ASPM is configured.
746 */
747 if (!error && dev->bus->self)
748 pcie_aspm_powersave_config_link(dev->bus->self);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200749
750 return error;
751}
752
753/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 * pci_choose_state - Choose the power state of a PCI device
755 * @dev: PCI device to be suspended
756 * @state: target sleep state for the whole system. This is the value
757 * that is passed to suspend() function.
758 *
759 * Returns PCI power state suitable for given device and given system
760 * message.
761 */
762
763pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
764{
Shaohua Liab826ca2007-07-20 10:03:22 +0800765 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500766
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
768 return PCI_D0;
769
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200770 ret = platform_pci_choose_state(dev);
771 if (ret != PCI_POWER_ERROR)
772 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700773
774 switch (state.event) {
775 case PM_EVENT_ON:
776 return PCI_D0;
777 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700778 case PM_EVENT_PRETHAW:
779 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700780 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100781 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700782 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600784 dev_info(&dev->dev, "unrecognized suspend event %d\n",
785 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 BUG();
787 }
788 return PCI_D0;
789}
790
791EXPORT_SYMBOL(pci_choose_state);
792
Yu Zhao89858512009-02-16 02:55:47 +0800793#define PCI_EXP_SAVE_REGS 7
794
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800795#define pcie_cap_has_devctl(type, flags) 1
796#define pcie_cap_has_lnkctl(type, flags) \
797 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
798 (type == PCI_EXP_TYPE_ROOT_PORT || \
799 type == PCI_EXP_TYPE_ENDPOINT || \
800 type == PCI_EXP_TYPE_LEG_END))
801#define pcie_cap_has_sltctl(type, flags) \
802 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
803 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
804 (type == PCI_EXP_TYPE_DOWNSTREAM && \
805 (flags & PCI_EXP_FLAGS_SLOT))))
806#define pcie_cap_has_rtctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_RC_EC))
810#define pcie_cap_has_devctl2(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1)
812#define pcie_cap_has_lnkctl2(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1)
814#define pcie_cap_has_sltctl2(type, flags) \
815 ((flags & PCI_EXP_FLAGS_VERS) > 1)
816
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300817static int pci_save_pcie_state(struct pci_dev *dev)
818{
819 int pos, i = 0;
820 struct pci_cap_saved_state *save_state;
821 u16 *cap;
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800822 u16 flags;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300823
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +0900824 pos = pci_pcie_cap(dev);
825 if (!pos)
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300826 return 0;
827
Eric W. Biederman9f355752007-03-08 13:06:13 -0700828 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300829 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800830 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300831 return -ENOMEM;
832 }
Alex Williamson24a4742f2011-05-10 10:02:11 -0600833 cap = (u16 *)&save_state->cap.data[0];
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300834
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800835 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
836
837 if (pcie_cap_has_devctl(dev->pcie_type, flags))
838 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
839 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
840 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
841 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
842 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
843 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
844 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
845 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
846 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
847 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
848 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
849 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
850 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100851
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300852 return 0;
853}
854
855static void pci_restore_pcie_state(struct pci_dev *dev)
856{
857 int i = 0, pos;
858 struct pci_cap_saved_state *save_state;
859 u16 *cap;
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800860 u16 flags;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300861
862 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
864 if (!save_state || pos <= 0)
865 return;
Alex Williamson24a4742f2011-05-10 10:02:11 -0600866 cap = (u16 *)&save_state->cap.data[0];
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300867
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800868 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
869
870 if (pcie_cap_has_devctl(dev->pcie_type, flags))
871 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
872 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
873 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
874 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
875 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
876 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
877 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
878 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
879 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
880 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
881 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
882 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
883 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300884}
885
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800886
887static int pci_save_pcix_state(struct pci_dev *dev)
888{
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100889 int pos;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800890 struct pci_cap_saved_state *save_state;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800891
892 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
893 if (pos <= 0)
894 return 0;
895
Shaohua Lif34303d2007-12-18 09:56:47 +0800896 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800897 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800898 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800899 return -ENOMEM;
900 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800901
Alex Williamson24a4742f2011-05-10 10:02:11 -0600902 pci_read_config_word(dev, pos + PCI_X_CMD,
903 (u16 *)save_state->cap.data);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100904
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800905 return 0;
906}
907
908static void pci_restore_pcix_state(struct pci_dev *dev)
909{
910 int i = 0, pos;
911 struct pci_cap_saved_state *save_state;
912 u16 *cap;
913
914 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
915 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
916 if (!save_state || pos <= 0)
917 return;
Alex Williamson24a4742f2011-05-10 10:02:11 -0600918 cap = (u16 *)&save_state->cap.data[0];
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800919
920 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800921}
922
923
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924/**
925 * pci_save_state - save the PCI configuration space of a device before suspending
926 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 */
928int
929pci_save_state(struct pci_dev *dev)
930{
931 int i;
932 /* XXX: 100% dword access ok here? */
933 for (i = 0; i < 16; i++)
Kleber Sacilotto de Souza9e0b5b22009-11-25 00:55:51 -0200934 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100935 dev->state_saved = true;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300936 if ((i = pci_save_pcie_state(dev)) != 0)
937 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800938 if ((i = pci_save_pcix_state(dev)) != 0)
939 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940 return 0;
941}
942
943/**
944 * pci_restore_state - Restore the saved state of a PCI device
945 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946 */
Jon Mason1d3c16a2010-11-30 17:43:26 -0600947void pci_restore_state(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948{
949 int i;
Al Virob4482a42007-10-14 19:35:40 +0100950 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951
Alek Duc82f63e2009-08-08 08:46:19 +0800952 if (!dev->state_saved)
Jon Mason1d3c16a2010-11-30 17:43:26 -0600953 return;
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +0200954
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300955 /* PCI Express register must be restored first */
956 pci_restore_pcie_state(dev);
957
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700958 /*
959 * The Base Address register should be programmed before the command
960 * register(s)
961 */
962 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700963 pci_read_config_dword(dev, i * 4, &val);
964 if (val != dev->saved_config_space[i]) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600965 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
966 "space at offset %#x (was %#x, writing %#x)\n",
967 i, val, (int)dev->saved_config_space[i]);
Dave Jones04d9c1a2006-04-18 21:06:51 -0700968 pci_write_config_dword(dev,i * 4,
969 dev->saved_config_space[i]);
970 }
971 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800972 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800973 pci_restore_msi_state(dev);
Yu Zhao8c5cdb62009-03-20 11:25:12 +0800974 pci_restore_iov_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100975
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +0200976 dev->state_saved = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977}
978
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900979static int do_pci_enable_device(struct pci_dev *dev, int bars)
980{
981 int err;
982
983 err = pci_set_power_state(dev, PCI_D0);
984 if (err < 0 && err != -EIO)
985 return err;
986 err = pcibios_enable_device(dev, bars);
987 if (err < 0)
988 return err;
989 pci_fixup_device(pci_fixup_enable, dev);
990
991 return 0;
992}
993
994/**
Tejun Heo0b62e132007-07-27 14:43:35 +0900995 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900996 * @dev: PCI device to be resumed
997 *
998 * Note this function is a backend of pci_default_resume and is not supposed
999 * to be called by normal code, write proper resume handler and use it instead.
1000 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001001int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001002{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001003 if (pci_is_enabled(dev))
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001004 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1005 return 0;
1006}
1007
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001008static int __pci_enable_device_flags(struct pci_dev *dev,
1009 resource_size_t flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010{
1011 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001012 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013
Jesse Barnes97c145f2010-11-05 15:16:36 -04001014 /*
1015 * Power state could be unknown at this point, either due to a fresh
1016 * boot or a device removal call. So get the current power state
1017 * so that things like MSI message writing will behave as expected
1018 * (e.g. if the device really is in D0 at enable time).
1019 */
1020 if (dev->pm_cap) {
1021 u16 pmcsr;
1022 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1023 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1024 }
1025
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +09001026 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1027 return 0; /* already enabled */
1028
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001029 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1030 if (dev->resource[i].flags & flags)
1031 bars |= (1 << i);
1032
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001033 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -07001034 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001035 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +09001036 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037}
1038
1039/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001040 * pci_enable_device_io - Initialize a device for use with IO space
1041 * @dev: PCI device to be initialized
1042 *
1043 * Initialize device before it's used by a driver. Ask low-level code
1044 * to enable I/O resources. Wake up the device if it was suspended.
1045 * Beware, this function can fail.
1046 */
1047int pci_enable_device_io(struct pci_dev *dev)
1048{
1049 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1050}
1051
1052/**
1053 * pci_enable_device_mem - Initialize a device for use with Memory space
1054 * @dev: PCI device to be initialized
1055 *
1056 * Initialize device before it's used by a driver. Ask low-level code
1057 * to enable Memory resources. Wake up the device if it was suspended.
1058 * Beware, this function can fail.
1059 */
1060int pci_enable_device_mem(struct pci_dev *dev)
1061{
1062 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1063}
1064
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065/**
1066 * pci_enable_device - Initialize device before it's used by a driver.
1067 * @dev: PCI device to be initialized
1068 *
1069 * Initialize device before it's used by a driver. Ask low-level code
1070 * to enable I/O and memory. Wake up the device if it was suspended.
1071 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001072 *
1073 * Note we don't actually enable the device many times if we call
1074 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001076int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077{
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001078 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079}
1080
Tejun Heo9ac78492007-01-20 16:00:26 +09001081/*
1082 * Managed PCI resources. This manages device on/off, intx/msi/msix
1083 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1084 * there's no need to track it separately. pci_devres is initialized
1085 * when a device is enabled using managed PCI device enable interface.
1086 */
1087struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -08001088 unsigned int enabled:1;
1089 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001090 unsigned int orig_intx:1;
1091 unsigned int restore_intx:1;
1092 u32 region_mask;
1093};
1094
1095static void pcim_release(struct device *gendev, void *res)
1096{
1097 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1098 struct pci_devres *this = res;
1099 int i;
1100
1101 if (dev->msi_enabled)
1102 pci_disable_msi(dev);
1103 if (dev->msix_enabled)
1104 pci_disable_msix(dev);
1105
1106 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1107 if (this->region_mask & (1 << i))
1108 pci_release_region(dev, i);
1109
1110 if (this->restore_intx)
1111 pci_intx(dev, this->orig_intx);
1112
Tejun Heo7f375f32007-02-25 04:36:01 -08001113 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +09001114 pci_disable_device(dev);
1115}
1116
1117static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1118{
1119 struct pci_devres *dr, *new_dr;
1120
1121 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1122 if (dr)
1123 return dr;
1124
1125 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1126 if (!new_dr)
1127 return NULL;
1128 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1129}
1130
1131static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1132{
1133 if (pci_is_managed(pdev))
1134 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1135 return NULL;
1136}
1137
1138/**
1139 * pcim_enable_device - Managed pci_enable_device()
1140 * @pdev: PCI device to be initialized
1141 *
1142 * Managed pci_enable_device().
1143 */
1144int pcim_enable_device(struct pci_dev *pdev)
1145{
1146 struct pci_devres *dr;
1147 int rc;
1148
1149 dr = get_pci_dr(pdev);
1150 if (unlikely(!dr))
1151 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +09001152 if (dr->enabled)
1153 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001154
1155 rc = pci_enable_device(pdev);
1156 if (!rc) {
1157 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -08001158 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001159 }
1160 return rc;
1161}
1162
1163/**
1164 * pcim_pin_device - Pin managed PCI device
1165 * @pdev: PCI device to pin
1166 *
1167 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1168 * driver detach. @pdev must have been enabled with
1169 * pcim_enable_device().
1170 */
1171void pcim_pin_device(struct pci_dev *pdev)
1172{
1173 struct pci_devres *dr;
1174
1175 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -08001176 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +09001177 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001178 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001179}
1180
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181/**
1182 * pcibios_disable_device - disable arch specific PCI resources for device dev
1183 * @dev: the PCI device to disable
1184 *
1185 * Disables architecture specific PCI resources for the device. This
1186 * is the default implementation. Architecture implementations can
1187 * override this.
1188 */
1189void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1190
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001191static void do_pci_disable_device(struct pci_dev *dev)
1192{
1193 u16 pci_command;
1194
1195 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1196 if (pci_command & PCI_COMMAND_MASTER) {
1197 pci_command &= ~PCI_COMMAND_MASTER;
1198 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1199 }
1200
1201 pcibios_disable_device(dev);
1202}
1203
1204/**
1205 * pci_disable_enabled_device - Disable device without updating enable_cnt
1206 * @dev: PCI device to disable
1207 *
1208 * NOTE: This function is a backend of PCI power management routines and is
1209 * not supposed to be called drivers.
1210 */
1211void pci_disable_enabled_device(struct pci_dev *dev)
1212{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001213 if (pci_is_enabled(dev))
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001214 do_pci_disable_device(dev);
1215}
1216
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217/**
1218 * pci_disable_device - Disable PCI device after use
1219 * @dev: PCI device to be disabled
1220 *
1221 * Signal to the system that the PCI device is not in use by the system
1222 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001223 *
1224 * Note we don't actually disable the device until all callers of
Roman Fietzeee6583f2010-05-18 14:45:47 +02001225 * pci_enable_device() have called pci_disable_device().
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 */
1227void
1228pci_disable_device(struct pci_dev *dev)
1229{
Tejun Heo9ac78492007-01-20 16:00:26 +09001230 struct pci_devres *dr;
Shaohua Li99dc8042006-05-26 10:58:27 +08001231
Tejun Heo9ac78492007-01-20 16:00:26 +09001232 dr = find_pci_dr(dev);
1233 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001234 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001235
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001236 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1237 return;
1238
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001239 do_pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001241 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242}
1243
1244/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001245 * pcibios_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001246 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001247 * @state: Reset state to enter into
1248 *
1249 *
Stefan Assmann45e829e2009-12-03 06:49:24 -05001250 * Sets the PCIe reset state for the device. This is the default
Brian Kingf7bdd122007-04-06 16:39:36 -05001251 * implementation. Architecture implementations can override this.
1252 */
1253int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1254 enum pcie_reset_state state)
1255{
1256 return -EINVAL;
1257}
1258
1259/**
1260 * pci_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001261 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001262 * @state: Reset state to enter into
1263 *
1264 *
1265 * Sets the PCI reset state for the device.
1266 */
1267int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1268{
1269 return pcibios_set_pcie_reset_state(dev, state);
1270}
1271
1272/**
Rafael J. Wysocki58ff4632010-02-17 23:36:58 +01001273 * pci_check_pme_status - Check if given device has generated PME.
1274 * @dev: Device to check.
1275 *
1276 * Check the PME status of the device and if set, clear it and clear PME enable
1277 * (if set). Return 'true' if PME status and PME enable were both set or
1278 * 'false' otherwise.
1279 */
1280bool pci_check_pme_status(struct pci_dev *dev)
1281{
1282 int pmcsr_pos;
1283 u16 pmcsr;
1284 bool ret = false;
1285
1286 if (!dev->pm_cap)
1287 return false;
1288
1289 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1290 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1291 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1292 return false;
1293
1294 /* Clear PME status. */
1295 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1296 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1297 /* Disable PME to avoid interrupt flood. */
1298 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1299 ret = true;
1300 }
1301
1302 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1303
1304 return ret;
1305}
1306
1307/**
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001308 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1309 * @dev: Device to handle.
1310 * @ign: Ignored.
1311 *
1312 * Check if @dev has generated PME and queue a resume request for it in that
1313 * case.
1314 */
1315static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1316{
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001317 if (pci_check_pme_status(dev)) {
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001318 pci_wakeup_event(dev);
Rafael J. Wysocki0f953bf2010-12-29 13:22:08 +01001319 pm_request_resume(&dev->dev);
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001320 }
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001321 return 0;
1322}
1323
1324/**
1325 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1326 * @bus: Top bus of the subtree to walk.
1327 */
1328void pci_pme_wakeup_bus(struct pci_bus *bus)
1329{
1330 if (bus)
1331 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1332}
1333
1334/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001335 * pci_pme_capable - check the capability of PCI device to generate PME#
1336 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001337 * @state: PCI state from which device will issue PME#.
1338 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001339bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001340{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001341 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001342 return false;
1343
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001344 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001345}
1346
Matthew Garrettdf17e622010-10-04 14:22:29 -04001347static void pci_pme_list_scan(struct work_struct *work)
1348{
1349 struct pci_pme_device *pme_dev;
1350
1351 mutex_lock(&pci_pme_list_mutex);
1352 if (!list_empty(&pci_pme_list)) {
1353 list_for_each_entry(pme_dev, &pci_pme_list, list)
1354 pci_pme_wakeup(pme_dev->dev, NULL);
1355 schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1356 }
1357 mutex_unlock(&pci_pme_list_mutex);
1358}
1359
1360/**
1361 * pci_external_pme - is a device an external PCI PME source?
1362 * @dev: PCI device to check
1363 *
1364 */
1365
1366static bool pci_external_pme(struct pci_dev *dev)
1367{
1368 if (pci_is_pcie(dev) || dev->bus->number == 0)
1369 return false;
1370 return true;
1371}
1372
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001373/**
1374 * pci_pme_active - enable or disable PCI device's PME# function
1375 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001376 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1377 *
1378 * The caller must verify that the device is capable of generating PME# before
1379 * calling this function with @enable equal to 'true'.
1380 */
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02001381void pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001382{
1383 u16 pmcsr;
1384
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001385 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001386 return;
1387
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001388 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001389 /* Clear PME_Status by writing 1 to it and enable PME# */
1390 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1391 if (!enable)
1392 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1393
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001394 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001395
Matthew Garrettdf17e622010-10-04 14:22:29 -04001396 /* PCI (as opposed to PCIe) PME requires that the device have
1397 its PME# line hooked up correctly. Not all hardware vendors
1398 do this, so the PME never gets delivered and the device
1399 remains asleep. The easiest way around this is to
1400 periodically walk the list of suspended devices and check
1401 whether any have their PME flag set. The assumption is that
1402 we'll wake up often enough anyway that this won't be a huge
1403 hit, and the power savings from the devices will still be a
1404 win. */
1405
1406 if (pci_external_pme(dev)) {
1407 struct pci_pme_device *pme_dev;
1408 if (enable) {
1409 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1410 GFP_KERNEL);
1411 if (!pme_dev)
1412 goto out;
1413 pme_dev->dev = dev;
1414 mutex_lock(&pci_pme_list_mutex);
1415 list_add(&pme_dev->list, &pci_pme_list);
1416 if (list_is_singular(&pci_pme_list))
1417 schedule_delayed_work(&pci_pme_work,
1418 msecs_to_jiffies(PME_TIMEOUT));
1419 mutex_unlock(&pci_pme_list_mutex);
1420 } else {
1421 mutex_lock(&pci_pme_list_mutex);
1422 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1423 if (pme_dev->dev == dev) {
1424 list_del(&pme_dev->list);
1425 kfree(pme_dev);
1426 break;
1427 }
1428 }
1429 mutex_unlock(&pci_pme_list_mutex);
1430 }
1431 }
1432
1433out:
Bjorn Helgaas10c3d712009-11-04 10:32:42 -07001434 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001435 enable ? "enabled" : "disabled");
1436}
1437
1438/**
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001439 * __pci_enable_wake - enable PCI device as wakeup event source
David Brownell075c1772007-04-26 00:12:06 -07001440 * @dev: PCI device affected
1441 * @state: PCI state from which device will issue wakeup events
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001442 * @runtime: True if the events are to be generated at run time
David Brownell075c1772007-04-26 00:12:06 -07001443 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 *
David Brownell075c1772007-04-26 00:12:06 -07001445 * This enables the device as a wakeup event source, or disables it.
1446 * When such events involves platform-specific hooks, those hooks are
1447 * called automatically by this routine.
1448 *
1449 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001450 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001451 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001452 * RETURN VALUE:
1453 * 0 is returned on success
1454 * -EINVAL is returned if device is not supposed to wake up the system
1455 * Error code depending on the platform is returned if both the platform and
1456 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 */
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001458int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1459 bool runtime, bool enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460{
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001461 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001463 if (enable && !runtime && !device_may_wakeup(&dev->dev))
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001464 return -EINVAL;
1465
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001466 /* Don't do the same thing twice in a row for one device. */
1467 if (!!enable == !!dev->wakeup_prepared)
1468 return 0;
1469
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001470 /*
1471 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1472 * Anderson we should be doing PME# wake enable followed by ACPI wake
1473 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001474 */
1475
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001476 if (enable) {
1477 int error;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001478
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001479 if (pci_pme_capable(dev, state))
1480 pci_pme_active(dev, true);
1481 else
1482 ret = 1;
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001483 error = runtime ? platform_pci_run_wake(dev, true) :
1484 platform_pci_sleep_wake(dev, true);
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001485 if (ret)
1486 ret = error;
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001487 if (!ret)
1488 dev->wakeup_prepared = true;
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001489 } else {
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001490 if (runtime)
1491 platform_pci_run_wake(dev, false);
1492 else
1493 platform_pci_sleep_wake(dev, false);
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001494 pci_pme_active(dev, false);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001495 dev->wakeup_prepared = false;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001496 }
1497
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001498 return ret;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001499}
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001500EXPORT_SYMBOL(__pci_enable_wake);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001501
1502/**
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02001503 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1504 * @dev: PCI device to prepare
1505 * @enable: True to enable wake-up event generation; false to disable
1506 *
1507 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1508 * and this function allows them to set that up cleanly - pci_enable_wake()
1509 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1510 * ordering constraints.
1511 *
1512 * This function only returns error code if the device is not capable of
1513 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1514 * enable wake-up power for it.
1515 */
1516int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1517{
1518 return pci_pme_capable(dev, PCI_D3cold) ?
1519 pci_enable_wake(dev, PCI_D3cold, enable) :
1520 pci_enable_wake(dev, PCI_D3hot, enable);
1521}
1522
1523/**
Jesse Barnes37139072008-07-28 11:49:26 -07001524 * pci_target_state - find an appropriate low power state for a given PCI dev
1525 * @dev: PCI device
1526 *
1527 * Use underlying platform code to find a supported low power state for @dev.
1528 * If the platform can't manage @dev, return the deepest state from which it
1529 * can generate wake events, based on any available PME info.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001530 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001531pci_power_t pci_target_state(struct pci_dev *dev)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001532{
1533 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001534
1535 if (platform_pci_power_manageable(dev)) {
1536 /*
1537 * Call the platform to choose the target state of the device
1538 * and enable wake-up from this state if supported.
1539 */
1540 pci_power_t state = platform_pci_choose_state(dev);
1541
1542 switch (state) {
1543 case PCI_POWER_ERROR:
1544 case PCI_UNKNOWN:
1545 break;
1546 case PCI_D1:
1547 case PCI_D2:
1548 if (pci_no_d1d2(dev))
1549 break;
1550 default:
1551 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001552 }
Rafael J. Wysockid2abdf62009-06-14 21:25:02 +02001553 } else if (!dev->pm_cap) {
1554 target_state = PCI_D0;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001555 } else if (device_may_wakeup(&dev->dev)) {
1556 /*
1557 * Find the deepest state from which the device can generate
1558 * wake-up events, make it the target state and enable device
1559 * to generate PME#.
1560 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001561 if (dev->pme_support) {
1562 while (target_state
1563 && !(dev->pme_support & (1 << target_state)))
1564 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001565 }
1566 }
1567
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001568 return target_state;
1569}
1570
1571/**
1572 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1573 * @dev: Device to handle.
1574 *
1575 * Choose the power state appropriate for the device depending on whether
1576 * it can wake up the system and/or is power manageable by the platform
1577 * (PCI_D3hot is the default) and put the device into that state.
1578 */
1579int pci_prepare_to_sleep(struct pci_dev *dev)
1580{
1581 pci_power_t target_state = pci_target_state(dev);
1582 int error;
1583
1584 if (target_state == PCI_POWER_ERROR)
1585 return -EIO;
1586
Rafael J. Wysocki8efb8c72009-03-30 21:46:27 +02001587 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02001588
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001589 error = pci_set_power_state(dev, target_state);
1590
1591 if (error)
1592 pci_enable_wake(dev, target_state, false);
1593
1594 return error;
1595}
1596
1597/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07001598 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001599 * @dev: Device to handle.
1600 *
Thomas Weber88393162010-03-16 11:47:56 +01001601 * Disable device's system wake-up capability and put it into D0.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001602 */
1603int pci_back_from_sleep(struct pci_dev *dev)
1604{
1605 pci_enable_wake(dev, PCI_D0, false);
1606 return pci_set_power_state(dev, PCI_D0);
1607}
1608
1609/**
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001610 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1611 * @dev: PCI device being suspended.
1612 *
1613 * Prepare @dev to generate wake-up events at run time and put it into a low
1614 * power state.
1615 */
1616int pci_finish_runtime_suspend(struct pci_dev *dev)
1617{
1618 pci_power_t target_state = pci_target_state(dev);
1619 int error;
1620
1621 if (target_state == PCI_POWER_ERROR)
1622 return -EIO;
1623
1624 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1625
1626 error = pci_set_power_state(dev, target_state);
1627
1628 if (error)
1629 __pci_enable_wake(dev, target_state, true, false);
1630
1631 return error;
1632}
1633
1634/**
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001635 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1636 * @dev: Device to check.
1637 *
1638 * Return true if the device itself is cabable of generating wake-up events
1639 * (through the platform or using the native PCIe PME) or if the device supports
1640 * PME and one of its upstream bridges can generate wake-up events.
1641 */
1642bool pci_dev_run_wake(struct pci_dev *dev)
1643{
1644 struct pci_bus *bus = dev->bus;
1645
1646 if (device_run_wake(&dev->dev))
1647 return true;
1648
1649 if (!dev->pme_support)
1650 return false;
1651
1652 while (bus->parent) {
1653 struct pci_dev *bridge = bus->self;
1654
1655 if (device_run_wake(&bridge->dev))
1656 return true;
1657
1658 bus = bus->parent;
1659 }
1660
1661 /* We have reached the root bus. */
1662 if (bus->bridge)
1663 return device_run_wake(bus->bridge);
1664
1665 return false;
1666}
1667EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1668
1669/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001670 * pci_pm_init - Initialize PM functions of given PCI device
1671 * @dev: PCI device to handle.
1672 */
1673void pci_pm_init(struct pci_dev *dev)
1674{
1675 int pm;
1676 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07001677
Rafael J. Wysockibb910a72010-02-27 21:37:37 +01001678 pm_runtime_forbid(&dev->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001679 device_enable_async_suspend(&dev->dev);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001680 dev->wakeup_prepared = false;
Rafael J. Wysockibb910a72010-02-27 21:37:37 +01001681
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001682 dev->pm_cap = 0;
1683
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684 /* find PCI PM capability in list */
1685 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07001686 if (!pm)
Linus Torvalds50246dd2009-01-16 08:14:51 -08001687 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001689 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001690
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001691 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1692 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1693 pmc & PCI_PM_CAP_VER_MASK);
Linus Torvalds50246dd2009-01-16 08:14:51 -08001694 return;
David Brownell075c1772007-04-26 00:12:06 -07001695 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001697 dev->pm_cap = pm;
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01001698 dev->d3_delay = PCI_PM_D3_WAIT;
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001699
1700 dev->d1_support = false;
1701 dev->d2_support = false;
1702 if (!pci_no_d1d2(dev)) {
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001703 if (pmc & PCI_PM_CAP_D1)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001704 dev->d1_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001705 if (pmc & PCI_PM_CAP_D2)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001706 dev->d2_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001707
1708 if (dev->d1_support || dev->d2_support)
1709 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
Jesse Barnesec84f122008-09-23 11:43:34 -07001710 dev->d1_support ? " D1" : "",
1711 dev->d2_support ? " D2" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001712 }
1713
1714 pmc &= PCI_PM_CAP_PME_MASK;
1715 if (pmc) {
Bjorn Helgaas10c3d712009-11-04 10:32:42 -07001716 dev_printk(KERN_DEBUG, &dev->dev,
1717 "PME# supported from%s%s%s%s%s\n",
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001718 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1719 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1720 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1721 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1722 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001723 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001724 /*
1725 * Make device's PM flags reflect the wake-up capability, but
1726 * let the user space enable it to wake up the system as needed.
1727 */
1728 device_set_wakeup_capable(&dev->dev, true);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001729 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001730 pci_pme_active(dev, false);
1731 } else {
1732 dev->pme_support = 0;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001733 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734}
1735
Yu Zhao58c3a722008-10-14 14:02:53 +08001736/**
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001737 * platform_pci_wakeup_init - init platform wakeup if present
1738 * @dev: PCI device
1739 *
1740 * Some devices don't have PCI PM caps but can still generate wakeup
1741 * events through platform methods (like ACPI events). If @dev supports
1742 * platform wakeup events, set the device flag to indicate as much. This
1743 * may be redundant if the device also supports PCI PM caps, but double
1744 * initialization should be safe in that case.
1745 */
1746void platform_pci_wakeup_init(struct pci_dev *dev)
1747{
1748 if (!platform_pci_can_wakeup(dev))
1749 return;
1750
1751 device_set_wakeup_capable(&dev->dev, true);
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001752 platform_pci_sleep_wake(dev, false);
1753}
1754
1755/**
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001756 * pci_add_save_buffer - allocate buffer for saving given capability registers
1757 * @dev: the PCI device
1758 * @cap: the capability to allocate the buffer for
1759 * @size: requested size of the buffer
1760 */
1761static int pci_add_cap_save_buffer(
1762 struct pci_dev *dev, char cap, unsigned int size)
1763{
1764 int pos;
1765 struct pci_cap_saved_state *save_state;
1766
1767 pos = pci_find_capability(dev, cap);
1768 if (pos <= 0)
1769 return 0;
1770
1771 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1772 if (!save_state)
1773 return -ENOMEM;
1774
Alex Williamson24a4742f2011-05-10 10:02:11 -06001775 save_state->cap.cap_nr = cap;
1776 save_state->cap.size = size;
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001777 pci_add_saved_cap(dev, save_state);
1778
1779 return 0;
1780}
1781
1782/**
1783 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1784 * @dev: the PCI device
1785 */
1786void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1787{
1788 int error;
1789
Yu Zhao89858512009-02-16 02:55:47 +08001790 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1791 PCI_EXP_SAVE_REGS * sizeof(u16));
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001792 if (error)
1793 dev_err(&dev->dev,
1794 "unable to preallocate PCI Express save buffer\n");
1795
1796 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1797 if (error)
1798 dev_err(&dev->dev,
1799 "unable to preallocate PCI-X save buffer\n");
1800}
1801
1802/**
Yu Zhao58c3a722008-10-14 14:02:53 +08001803 * pci_enable_ari - enable ARI forwarding if hardware support it
1804 * @dev: the PCI device
1805 */
1806void pci_enable_ari(struct pci_dev *dev)
1807{
1808 int pos;
1809 u32 cap;
1810 u16 ctrl;
Zhao, Yu81135872008-10-23 13:15:39 +08001811 struct pci_dev *bridge;
Yu Zhao58c3a722008-10-14 14:02:53 +08001812
Kenji Kaneshige5f4d91a2009-11-11 14:36:17 +09001813 if (!pci_is_pcie(dev) || dev->devfn)
Yu Zhao58c3a722008-10-14 14:02:53 +08001814 return;
1815
Zhao, Yu81135872008-10-23 13:15:39 +08001816 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
Yu Zhao58c3a722008-10-14 14:02:53 +08001817 if (!pos)
1818 return;
1819
Zhao, Yu81135872008-10-23 13:15:39 +08001820 bridge = dev->bus->self;
Kenji Kaneshige5f4d91a2009-11-11 14:36:17 +09001821 if (!bridge || !pci_is_pcie(bridge))
Zhao, Yu81135872008-10-23 13:15:39 +08001822 return;
1823
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09001824 pos = pci_pcie_cap(bridge);
Zhao, Yu81135872008-10-23 13:15:39 +08001825 if (!pos)
1826 return;
1827
1828 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
Yu Zhao58c3a722008-10-14 14:02:53 +08001829 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1830 return;
1831
Zhao, Yu81135872008-10-23 13:15:39 +08001832 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
Yu Zhao58c3a722008-10-14 14:02:53 +08001833 ctrl |= PCI_EXP_DEVCTL2_ARI;
Zhao, Yu81135872008-10-23 13:15:39 +08001834 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
Yu Zhao58c3a722008-10-14 14:02:53 +08001835
Zhao, Yu81135872008-10-23 13:15:39 +08001836 bridge->ari_enabled = 1;
Yu Zhao58c3a722008-10-14 14:02:53 +08001837}
1838
Jesse Barnesb48d4422010-10-19 13:07:57 -07001839/**
1840 * pci_enable_ido - enable ID-based ordering on a device
1841 * @dev: the PCI device
1842 * @type: which types of IDO to enable
1843 *
1844 * Enable ID-based ordering on @dev. @type can contain the bits
1845 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1846 * which types of transactions are allowed to be re-ordered.
1847 */
1848void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1849{
1850 int pos;
1851 u16 ctrl;
1852
1853 pos = pci_pcie_cap(dev);
1854 if (!pos)
1855 return;
1856
1857 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1858 if (type & PCI_EXP_IDO_REQUEST)
1859 ctrl |= PCI_EXP_IDO_REQ_EN;
1860 if (type & PCI_EXP_IDO_COMPLETION)
1861 ctrl |= PCI_EXP_IDO_CMP_EN;
1862 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1863}
1864EXPORT_SYMBOL(pci_enable_ido);
1865
1866/**
1867 * pci_disable_ido - disable ID-based ordering on a device
1868 * @dev: the PCI device
1869 * @type: which types of IDO to disable
1870 */
1871void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1872{
1873 int pos;
1874 u16 ctrl;
1875
1876 if (!pci_is_pcie(dev))
1877 return;
1878
1879 pos = pci_pcie_cap(dev);
1880 if (!pos)
1881 return;
1882
1883 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1884 if (type & PCI_EXP_IDO_REQUEST)
1885 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1886 if (type & PCI_EXP_IDO_COMPLETION)
1887 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1888 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1889}
1890EXPORT_SYMBOL(pci_disable_ido);
1891
Jesse Barnes48a92a82011-01-10 12:46:36 -08001892/**
1893 * pci_enable_obff - enable optimized buffer flush/fill
1894 * @dev: PCI device
1895 * @type: type of signaling to use
1896 *
1897 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
1898 * signaling if possible, falling back to message signaling only if
1899 * WAKE# isn't supported. @type should indicate whether the PCIe link
1900 * be brought out of L0s or L1 to send the message. It should be either
1901 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
1902 *
1903 * If your device can benefit from receiving all messages, even at the
1904 * power cost of bringing the link back up from a low power state, use
1905 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
1906 * preferred type).
1907 *
1908 * RETURNS:
1909 * Zero on success, appropriate error number on failure.
1910 */
1911int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
1912{
1913 int pos;
1914 u32 cap;
1915 u16 ctrl;
1916 int ret;
1917
1918 if (!pci_is_pcie(dev))
1919 return -ENOTSUPP;
1920
1921 pos = pci_pcie_cap(dev);
1922 if (!pos)
1923 return -ENOTSUPP;
1924
1925 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
1926 if (!(cap & PCI_EXP_OBFF_MASK))
1927 return -ENOTSUPP; /* no OBFF support at all */
1928
1929 /* Make sure the topology supports OBFF as well */
1930 if (dev->bus) {
1931 ret = pci_enable_obff(dev->bus->self, type);
1932 if (ret)
1933 return ret;
1934 }
1935
1936 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1937 if (cap & PCI_EXP_OBFF_WAKE)
1938 ctrl |= PCI_EXP_OBFF_WAKE_EN;
1939 else {
1940 switch (type) {
1941 case PCI_EXP_OBFF_SIGNAL_L0:
1942 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
1943 ctrl |= PCI_EXP_OBFF_MSGA_EN;
1944 break;
1945 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
1946 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
1947 ctrl |= PCI_EXP_OBFF_MSGB_EN;
1948 break;
1949 default:
1950 WARN(1, "bad OBFF signal type\n");
1951 return -ENOTSUPP;
1952 }
1953 }
1954 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1955
1956 return 0;
1957}
1958EXPORT_SYMBOL(pci_enable_obff);
1959
1960/**
1961 * pci_disable_obff - disable optimized buffer flush/fill
1962 * @dev: PCI device
1963 *
1964 * Disable OBFF on @dev.
1965 */
1966void pci_disable_obff(struct pci_dev *dev)
1967{
1968 int pos;
1969 u16 ctrl;
1970
1971 if (!pci_is_pcie(dev))
1972 return;
1973
1974 pos = pci_pcie_cap(dev);
1975 if (!pos)
1976 return;
1977
1978 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1979 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
1980 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1981}
1982EXPORT_SYMBOL(pci_disable_obff);
1983
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08001984/**
1985 * pci_ltr_supported - check whether a device supports LTR
1986 * @dev: PCI device
1987 *
1988 * RETURNS:
1989 * True if @dev supports latency tolerance reporting, false otherwise.
1990 */
1991bool pci_ltr_supported(struct pci_dev *dev)
1992{
1993 int pos;
1994 u32 cap;
1995
1996 if (!pci_is_pcie(dev))
1997 return false;
1998
1999 pos = pci_pcie_cap(dev);
2000 if (!pos)
2001 return false;
2002
2003 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2004
2005 return cap & PCI_EXP_DEVCAP2_LTR;
2006}
2007EXPORT_SYMBOL(pci_ltr_supported);
2008
2009/**
2010 * pci_enable_ltr - enable latency tolerance reporting
2011 * @dev: PCI device
2012 *
2013 * Enable LTR on @dev if possible, which means enabling it first on
2014 * upstream ports.
2015 *
2016 * RETURNS:
2017 * Zero on success, errno on failure.
2018 */
2019int pci_enable_ltr(struct pci_dev *dev)
2020{
2021 int pos;
2022 u16 ctrl;
2023 int ret;
2024
2025 if (!pci_ltr_supported(dev))
2026 return -ENOTSUPP;
2027
2028 pos = pci_pcie_cap(dev);
2029 if (!pos)
2030 return -ENOTSUPP;
2031
2032 /* Only primary function can enable/disable LTR */
2033 if (PCI_FUNC(dev->devfn) != 0)
2034 return -EINVAL;
2035
2036 /* Enable upstream ports first */
2037 if (dev->bus) {
2038 ret = pci_enable_ltr(dev->bus->self);
2039 if (ret)
2040 return ret;
2041 }
2042
2043 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2044 ctrl |= PCI_EXP_LTR_EN;
2045 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2046
2047 return 0;
2048}
2049EXPORT_SYMBOL(pci_enable_ltr);
2050
2051/**
2052 * pci_disable_ltr - disable latency tolerance reporting
2053 * @dev: PCI device
2054 */
2055void pci_disable_ltr(struct pci_dev *dev)
2056{
2057 int pos;
2058 u16 ctrl;
2059
2060 if (!pci_ltr_supported(dev))
2061 return;
2062
2063 pos = pci_pcie_cap(dev);
2064 if (!pos)
2065 return;
2066
2067 /* Only primary function can enable/disable LTR */
2068 if (PCI_FUNC(dev->devfn) != 0)
2069 return;
2070
2071 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2072 ctrl &= ~PCI_EXP_LTR_EN;
2073 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2074}
2075EXPORT_SYMBOL(pci_disable_ltr);
2076
2077static int __pci_ltr_scale(int *val)
2078{
2079 int scale = 0;
2080
2081 while (*val > 1023) {
2082 *val = (*val + 31) / 32;
2083 scale++;
2084 }
2085 return scale;
2086}
2087
2088/**
2089 * pci_set_ltr - set LTR latency values
2090 * @dev: PCI device
2091 * @snoop_lat_ns: snoop latency in nanoseconds
2092 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2093 *
2094 * Figure out the scale and set the LTR values accordingly.
2095 */
2096int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2097{
2098 int pos, ret, snoop_scale, nosnoop_scale;
2099 u16 val;
2100
2101 if (!pci_ltr_supported(dev))
2102 return -ENOTSUPP;
2103
2104 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2105 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2106
2107 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2108 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2109 return -EINVAL;
2110
2111 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2112 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2113 return -EINVAL;
2114
2115 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2116 if (!pos)
2117 return -ENOTSUPP;
2118
2119 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2120 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2121 if (ret != 4)
2122 return -EIO;
2123
2124 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2125 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2126 if (ret != 4)
2127 return -EIO;
2128
2129 return 0;
2130}
2131EXPORT_SYMBOL(pci_set_ltr);
2132
Chris Wright5d990b62009-12-04 12:15:21 -08002133static int pci_acs_enable;
2134
2135/**
2136 * pci_request_acs - ask for ACS to be enabled if supported
2137 */
2138void pci_request_acs(void)
2139{
2140 pci_acs_enable = 1;
2141}
2142
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002143/**
Allen Kayae21ee62009-10-07 10:27:17 -07002144 * pci_enable_acs - enable ACS if hardware support it
2145 * @dev: the PCI device
2146 */
2147void pci_enable_acs(struct pci_dev *dev)
2148{
2149 int pos;
2150 u16 cap;
2151 u16 ctrl;
2152
Chris Wright5d990b62009-12-04 12:15:21 -08002153 if (!pci_acs_enable)
2154 return;
2155
Kenji Kaneshige5f4d91a2009-11-11 14:36:17 +09002156 if (!pci_is_pcie(dev))
Allen Kayae21ee62009-10-07 10:27:17 -07002157 return;
2158
2159 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2160 if (!pos)
2161 return;
2162
2163 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2164 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2165
2166 /* Source Validation */
2167 ctrl |= (cap & PCI_ACS_SV);
2168
2169 /* P2P Request Redirect */
2170 ctrl |= (cap & PCI_ACS_RR);
2171
2172 /* P2P Completion Redirect */
2173 ctrl |= (cap & PCI_ACS_CR);
2174
2175 /* Upstream Forwarding */
2176 ctrl |= (cap & PCI_ACS_UF);
2177
2178 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2179}
2180
2181/**
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002182 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2183 * @dev: the PCI device
2184 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2185 *
2186 * Perform INTx swizzling for a device behind one level of bridge. This is
2187 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
Matthew Wilcox46b952a2009-07-01 14:24:30 -07002188 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2189 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2190 * the PCI Express Base Specification, Revision 2.1)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002191 */
2192u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2193{
Matthew Wilcox46b952a2009-07-01 14:24:30 -07002194 int slot;
2195
2196 if (pci_ari_enabled(dev->bus))
2197 slot = 0;
2198 else
2199 slot = PCI_SLOT(dev->devfn);
2200
2201 return (((pin - 1) + slot) % 4) + 1;
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002202}
2203
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204int
2205pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2206{
2207 u8 pin;
2208
Kristen Accardi514d2072005-11-02 16:24:39 -08002209 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002210 if (!pin)
2211 return -1;
Bjorn Helgaas878f2e52008-12-09 16:11:46 -07002212
Kenji Kaneshige8784fd42009-05-26 16:07:33 +09002213 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002214 pin = pci_swizzle_interrupt_pin(dev, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002215 dev = dev->bus->self;
2216 }
2217 *bridge = dev;
2218 return pin;
2219}
2220
2221/**
Bjorn Helgaas68feac82008-12-16 21:36:55 -07002222 * pci_common_swizzle - swizzle INTx all the way to root bridge
2223 * @dev: the PCI device
2224 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2225 *
2226 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2227 * bridges all the way up to a PCI root bus.
2228 */
2229u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2230{
2231 u8 pin = *pinp;
2232
Kenji Kaneshige1eb39482009-05-26 16:08:36 +09002233 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas68feac82008-12-16 21:36:55 -07002234 pin = pci_swizzle_interrupt_pin(dev, pin);
2235 dev = dev->bus->self;
2236 }
2237 *pinp = pin;
2238 return PCI_SLOT(dev->devfn);
2239}
2240
2241/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002242 * pci_release_region - Release a PCI bar
2243 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2244 * @bar: BAR to release
2245 *
2246 * Releases the PCI I/O and memory resources previously reserved by a
2247 * successful call to pci_request_region. Call this function only
2248 * after all use of the PCI regions has ceased.
2249 */
2250void pci_release_region(struct pci_dev *pdev, int bar)
2251{
Tejun Heo9ac78492007-01-20 16:00:26 +09002252 struct pci_devres *dr;
2253
Linus Torvalds1da177e2005-04-16 15:20:36 -07002254 if (pci_resource_len(pdev, bar) == 0)
2255 return;
2256 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2257 release_region(pci_resource_start(pdev, bar),
2258 pci_resource_len(pdev, bar));
2259 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2260 release_mem_region(pci_resource_start(pdev, bar),
2261 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09002262
2263 dr = find_pci_dr(pdev);
2264 if (dr)
2265 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266}
2267
2268/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002269 * __pci_request_region - Reserved PCI I/O and memory resource
Linus Torvalds1da177e2005-04-16 15:20:36 -07002270 * @pdev: PCI device whose resources are to be reserved
2271 * @bar: BAR to be reserved
2272 * @res_name: Name to be associated with resource.
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002273 * @exclusive: whether the region access is exclusive or not
Linus Torvalds1da177e2005-04-16 15:20:36 -07002274 *
2275 * Mark the PCI region associated with PCI device @pdev BR @bar as
2276 * being reserved by owner @res_name. Do not access any
2277 * address inside the PCI regions unless this call returns
2278 * successfully.
2279 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002280 * If @exclusive is set, then the region is marked so that userspace
2281 * is explicitly not allowed to map the resource via /dev/mem or
2282 * sysfs MMIO access.
2283 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284 * Returns 0 on success, or %EBUSY on error. A warning
2285 * message is also printed on failure.
2286 */
Arjan van de Vene8de1482008-10-22 19:55:31 -07002287static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2288 int exclusive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002289{
Tejun Heo9ac78492007-01-20 16:00:26 +09002290 struct pci_devres *dr;
2291
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292 if (pci_resource_len(pdev, bar) == 0)
2293 return 0;
2294
2295 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2296 if (!request_region(pci_resource_start(pdev, bar),
2297 pci_resource_len(pdev, bar), res_name))
2298 goto err_out;
2299 }
2300 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
Arjan van de Vene8de1482008-10-22 19:55:31 -07002301 if (!__request_mem_region(pci_resource_start(pdev, bar),
2302 pci_resource_len(pdev, bar), res_name,
2303 exclusive))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002304 goto err_out;
2305 }
Tejun Heo9ac78492007-01-20 16:00:26 +09002306
2307 dr = find_pci_dr(pdev);
2308 if (dr)
2309 dr->region_mask |= 1 << bar;
2310
Linus Torvalds1da177e2005-04-16 15:20:36 -07002311 return 0;
2312
2313err_out:
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -06002314 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +11002315 &pdev->resource[bar]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002316 return -EBUSY;
2317}
2318
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002319/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002320 * pci_request_region - Reserve PCI I/O and memory resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07002321 * @pdev: PCI device whose resources are to be reserved
2322 * @bar: BAR to be reserved
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002323 * @res_name: Name to be associated with resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07002324 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002325 * Mark the PCI region associated with PCI device @pdev BAR @bar as
Arjan van de Vene8de1482008-10-22 19:55:31 -07002326 * being reserved by owner @res_name. Do not access any
2327 * address inside the PCI regions unless this call returns
2328 * successfully.
2329 *
2330 * Returns 0 on success, or %EBUSY on error. A warning
2331 * message is also printed on failure.
2332 */
2333int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2334{
2335 return __pci_request_region(pdev, bar, res_name, 0);
2336}
2337
2338/**
2339 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2340 * @pdev: PCI device whose resources are to be reserved
2341 * @bar: BAR to be reserved
2342 * @res_name: Name to be associated with resource.
2343 *
2344 * Mark the PCI region associated with PCI device @pdev BR @bar as
2345 * being reserved by owner @res_name. Do not access any
2346 * address inside the PCI regions unless this call returns
2347 * successfully.
2348 *
2349 * Returns 0 on success, or %EBUSY on error. A warning
2350 * message is also printed on failure.
2351 *
2352 * The key difference that _exclusive makes it that userspace is
2353 * explicitly not allowed to map the resource via /dev/mem or
2354 * sysfs.
2355 */
2356int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2357{
2358 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2359}
2360/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002361 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2362 * @pdev: PCI device whose resources were previously reserved
2363 * @bars: Bitmask of BARs to be released
2364 *
2365 * Release selected PCI I/O and memory resources previously reserved.
2366 * Call this function only after all use of the PCI regions has ceased.
2367 */
2368void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2369{
2370 int i;
2371
2372 for (i = 0; i < 6; i++)
2373 if (bars & (1 << i))
2374 pci_release_region(pdev, i);
2375}
2376
Arjan van de Vene8de1482008-10-22 19:55:31 -07002377int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2378 const char *res_name, int excl)
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002379{
2380 int i;
2381
2382 for (i = 0; i < 6; i++)
2383 if (bars & (1 << i))
Arjan van de Vene8de1482008-10-22 19:55:31 -07002384 if (__pci_request_region(pdev, i, res_name, excl))
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002385 goto err_out;
2386 return 0;
2387
2388err_out:
2389 while(--i >= 0)
2390 if (bars & (1 << i))
2391 pci_release_region(pdev, i);
2392
2393 return -EBUSY;
2394}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002395
Arjan van de Vene8de1482008-10-22 19:55:31 -07002396
2397/**
2398 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2399 * @pdev: PCI device whose resources are to be reserved
2400 * @bars: Bitmask of BARs to be requested
2401 * @res_name: Name to be associated with resource
2402 */
2403int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2404 const char *res_name)
2405{
2406 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2407}
2408
2409int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2410 int bars, const char *res_name)
2411{
2412 return __pci_request_selected_regions(pdev, bars, res_name,
2413 IORESOURCE_EXCLUSIVE);
2414}
2415
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416/**
2417 * pci_release_regions - Release reserved PCI I/O and memory resources
2418 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2419 *
2420 * Releases all PCI I/O and memory resources previously reserved by a
2421 * successful call to pci_request_regions. Call this function only
2422 * after all use of the PCI regions has ceased.
2423 */
2424
2425void pci_release_regions(struct pci_dev *pdev)
2426{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002427 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002428}
2429
2430/**
2431 * pci_request_regions - Reserved PCI I/O and memory resources
2432 * @pdev: PCI device whose resources are to be reserved
2433 * @res_name: Name to be associated with resource.
2434 *
2435 * Mark all PCI regions associated with PCI device @pdev as
2436 * being reserved by owner @res_name. Do not access any
2437 * address inside the PCI regions unless this call returns
2438 * successfully.
2439 *
2440 * Returns 0 on success, or %EBUSY on error. A warning
2441 * message is also printed on failure.
2442 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05002443int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002444{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002445 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002446}
2447
2448/**
Arjan van de Vene8de1482008-10-22 19:55:31 -07002449 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2450 * @pdev: PCI device whose resources are to be reserved
2451 * @res_name: Name to be associated with resource.
2452 *
2453 * Mark all PCI regions associated with PCI device @pdev as
2454 * being reserved by owner @res_name. Do not access any
2455 * address inside the PCI regions unless this call returns
2456 * successfully.
2457 *
2458 * pci_request_regions_exclusive() will mark the region so that
2459 * /dev/mem and the sysfs MMIO access will not be allowed.
2460 *
2461 * Returns 0 on success, or %EBUSY on error. A warning
2462 * message is also printed on failure.
2463 */
2464int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2465{
2466 return pci_request_selected_regions_exclusive(pdev,
2467 ((1 << 6) - 1), res_name);
2468}
2469
Ben Hutchings6a479072008-12-23 03:08:29 +00002470static void __pci_set_master(struct pci_dev *dev, bool enable)
2471{
2472 u16 old_cmd, cmd;
2473
2474 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2475 if (enable)
2476 cmd = old_cmd | PCI_COMMAND_MASTER;
2477 else
2478 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2479 if (cmd != old_cmd) {
2480 dev_dbg(&dev->dev, "%s bus mastering\n",
2481 enable ? "enabling" : "disabling");
2482 pci_write_config_word(dev, PCI_COMMAND, cmd);
2483 }
2484 dev->is_busmaster = enable;
2485}
Arjan van de Vene8de1482008-10-22 19:55:31 -07002486
2487/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002488 * pci_set_master - enables bus-mastering for device dev
2489 * @dev: the PCI device to enable
2490 *
2491 * Enables bus-mastering on the device and calls pcibios_set_master()
2492 * to do the needed arch specific settings.
2493 */
Ben Hutchings6a479072008-12-23 03:08:29 +00002494void pci_set_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002495{
Ben Hutchings6a479072008-12-23 03:08:29 +00002496 __pci_set_master(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002497 pcibios_set_master(dev);
2498}
2499
Ben Hutchings6a479072008-12-23 03:08:29 +00002500/**
2501 * pci_clear_master - disables bus-mastering for device dev
2502 * @dev: the PCI device to disable
2503 */
2504void pci_clear_master(struct pci_dev *dev)
2505{
2506 __pci_set_master(dev, false);
2507}
2508
Linus Torvalds1da177e2005-04-16 15:20:36 -07002509/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002510 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2511 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07002512 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002513 * Helper function for pci_set_mwi.
2514 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002515 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2516 *
2517 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2518 */
Tejun Heo15ea76d2009-09-22 17:34:48 +09002519int pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002520{
2521 u8 cacheline_size;
2522
2523 if (!pci_cache_line_size)
Tejun Heo15ea76d2009-09-22 17:34:48 +09002524 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002525
2526 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2527 equal to or multiple of the right value. */
2528 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2529 if (cacheline_size >= pci_cache_line_size &&
2530 (cacheline_size % pci_cache_line_size) == 0)
2531 return 0;
2532
2533 /* Write the correct value. */
2534 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2535 /* Read it back. */
2536 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2537 if (cacheline_size == pci_cache_line_size)
2538 return 0;
2539
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06002540 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2541 "supported\n", pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542
2543 return -EINVAL;
2544}
Tejun Heo15ea76d2009-09-22 17:34:48 +09002545EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2546
2547#ifdef PCI_DISABLE_MWI
2548int pci_set_mwi(struct pci_dev *dev)
2549{
2550 return 0;
2551}
2552
2553int pci_try_set_mwi(struct pci_dev *dev)
2554{
2555 return 0;
2556}
2557
2558void pci_clear_mwi(struct pci_dev *dev)
2559{
2560}
2561
2562#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07002563
2564/**
2565 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2566 * @dev: the PCI device for which MWI is enabled
2567 *
Randy Dunlap694625c2007-07-09 11:55:54 -07002568 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002569 *
2570 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2571 */
2572int
2573pci_set_mwi(struct pci_dev *dev)
2574{
2575 int rc;
2576 u16 cmd;
2577
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002578 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002579 if (rc)
2580 return rc;
2581
2582 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2583 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06002584 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002585 cmd |= PCI_COMMAND_INVALIDATE;
2586 pci_write_config_word(dev, PCI_COMMAND, cmd);
2587 }
2588
2589 return 0;
2590}
2591
2592/**
Randy Dunlap694625c2007-07-09 11:55:54 -07002593 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2594 * @dev: the PCI device for which MWI is enabled
2595 *
2596 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2597 * Callers are not required to check the return value.
2598 *
2599 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2600 */
2601int pci_try_set_mwi(struct pci_dev *dev)
2602{
2603 int rc = pci_set_mwi(dev);
2604 return rc;
2605}
2606
2607/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002608 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2609 * @dev: the PCI device to disable
2610 *
2611 * Disables PCI Memory-Write-Invalidate transaction on the device
2612 */
2613void
2614pci_clear_mwi(struct pci_dev *dev)
2615{
2616 u16 cmd;
2617
2618 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2619 if (cmd & PCI_COMMAND_INVALIDATE) {
2620 cmd &= ~PCI_COMMAND_INVALIDATE;
2621 pci_write_config_word(dev, PCI_COMMAND, cmd);
2622 }
2623}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002624#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002625
Brett M Russa04ce0f2005-08-15 15:23:41 -04002626/**
2627 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07002628 * @pdev: the PCI device to operate on
2629 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04002630 *
2631 * Enables/disables PCI INTx for device dev
2632 */
2633void
2634pci_intx(struct pci_dev *pdev, int enable)
2635{
2636 u16 pci_command, new;
2637
2638 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2639
2640 if (enable) {
2641 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2642 } else {
2643 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2644 }
2645
2646 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09002647 struct pci_devres *dr;
2648
Brett M Russ2fd9d742005-09-09 10:02:22 -07002649 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09002650
2651 dr = find_pci_dr(pdev);
2652 if (dr && !dr->restore_intx) {
2653 dr->restore_intx = 1;
2654 dr->orig_intx = !enable;
2655 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04002656 }
2657}
2658
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08002659/**
2660 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07002661 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08002662 *
2663 * If you want to use msi see pci_enable_msi and friends.
2664 * This is a lower level primitive that allows us to disable
2665 * msi operation at the device level.
2666 */
2667void pci_msi_off(struct pci_dev *dev)
2668{
2669 int pos;
2670 u16 control;
2671
2672 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2673 if (pos) {
2674 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2675 control &= ~PCI_MSI_FLAGS_ENABLE;
2676 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2677 }
2678 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2679 if (pos) {
2680 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2681 control &= ~PCI_MSIX_FLAGS_ENABLE;
2682 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2683 }
2684}
Michael S. Tsirkinb03214d2010-06-23 22:49:06 -06002685EXPORT_SYMBOL_GPL(pci_msi_off);
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08002686
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08002687int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2688{
2689 return dma_set_max_seg_size(&dev->dev, size);
2690}
2691EXPORT_SYMBOL(pci_set_dma_max_seg_size);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08002692
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08002693int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2694{
2695 return dma_set_seg_boundary(&dev->dev, mask);
2696}
2697EXPORT_SYMBOL(pci_set_dma_seg_boundary);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08002698
Yu Zhao8c1c6992009-06-13 15:52:13 +08002699static int pcie_flr(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002700{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002701 int i;
2702 int pos;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002703 u32 cap;
Shmulik Ravid04b55c42009-12-03 22:27:51 +02002704 u16 status, control;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002705
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09002706 pos = pci_pcie_cap(dev);
Yu Zhao8c1c6992009-06-13 15:52:13 +08002707 if (!pos)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002708 return -ENOTTY;
Yu Zhao8c1c6992009-06-13 15:52:13 +08002709
2710 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002711 if (!(cap & PCI_EXP_DEVCAP_FLR))
2712 return -ENOTTY;
2713
Sheng Yangd91cdc72008-11-11 17:17:47 +08002714 if (probe)
2715 return 0;
2716
Sheng Yang8dd7f802008-10-21 17:38:25 +08002717 /* Wait for Transaction Pending bit clean */
Yu Zhao8c1c6992009-06-13 15:52:13 +08002718 for (i = 0; i < 4; i++) {
2719 if (i)
2720 msleep((1 << (i - 1)) * 100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002721
Yu Zhao8c1c6992009-06-13 15:52:13 +08002722 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2723 if (!(status & PCI_EXP_DEVSTA_TRPND))
2724 goto clear;
2725 }
Sheng Yang8dd7f802008-10-21 17:38:25 +08002726
Yu Zhao8c1c6992009-06-13 15:52:13 +08002727 dev_err(&dev->dev, "transaction is not cleared; "
2728 "proceeding with reset anyway\n");
Sheng Yang5fe5db02009-02-09 14:53:47 +08002729
Yu Zhao8c1c6992009-06-13 15:52:13 +08002730clear:
Shmulik Ravid04b55c42009-12-03 22:27:51 +02002731 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2732 control |= PCI_EXP_DEVCTL_BCR_FLR;
2733 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2734
Yu Zhao8c1c6992009-06-13 15:52:13 +08002735 msleep(100);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002736
Sheng Yang8dd7f802008-10-21 17:38:25 +08002737 return 0;
2738}
Sheng Yangd91cdc72008-11-11 17:17:47 +08002739
Yu Zhao8c1c6992009-06-13 15:52:13 +08002740static int pci_af_flr(struct pci_dev *dev, int probe)
Sheng Yang1ca88792008-11-11 17:17:48 +08002741{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002742 int i;
2743 int pos;
Sheng Yang1ca88792008-11-11 17:17:48 +08002744 u8 cap;
Yu Zhao8c1c6992009-06-13 15:52:13 +08002745 u8 status;
Sheng Yang1ca88792008-11-11 17:17:48 +08002746
Yu Zhao8c1c6992009-06-13 15:52:13 +08002747 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2748 if (!pos)
Sheng Yang1ca88792008-11-11 17:17:48 +08002749 return -ENOTTY;
Yu Zhao8c1c6992009-06-13 15:52:13 +08002750
2751 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
Sheng Yang1ca88792008-11-11 17:17:48 +08002752 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2753 return -ENOTTY;
2754
2755 if (probe)
2756 return 0;
2757
Sheng Yang1ca88792008-11-11 17:17:48 +08002758 /* Wait for Transaction Pending bit clean */
Yu Zhao8c1c6992009-06-13 15:52:13 +08002759 for (i = 0; i < 4; i++) {
2760 if (i)
2761 msleep((1 << (i - 1)) * 100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002762
Yu Zhao8c1c6992009-06-13 15:52:13 +08002763 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2764 if (!(status & PCI_AF_STATUS_TP))
2765 goto clear;
2766 }
2767
2768 dev_err(&dev->dev, "transaction is not cleared; "
2769 "proceeding with reset anyway\n");
2770
2771clear:
2772 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
Sheng Yang1ca88792008-11-11 17:17:48 +08002773 msleep(100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002774
Sheng Yang1ca88792008-11-11 17:17:48 +08002775 return 0;
2776}
2777
Rafael J. Wysocki83d74e02011-03-05 21:48:44 +01002778/**
2779 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2780 * @dev: Device to reset.
2781 * @probe: If set, only check if the device can be reset this way.
2782 *
2783 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2784 * unset, it will be reinitialized internally when going from PCI_D3hot to
2785 * PCI_D0. If that's the case and the device is not in a low-power state
2786 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2787 *
2788 * NOTE: This causes the caller to sleep for twice the device power transition
2789 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2790 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2791 * Moreover, only devices in D0 can be reset by this function.
2792 */
Yu Zhaof85876b2009-06-13 15:52:14 +08002793static int pci_pm_reset(struct pci_dev *dev, int probe)
Sheng Yangd91cdc72008-11-11 17:17:47 +08002794{
Yu Zhaof85876b2009-06-13 15:52:14 +08002795 u16 csr;
Sheng Yangd91cdc72008-11-11 17:17:47 +08002796
Yu Zhaof85876b2009-06-13 15:52:14 +08002797 if (!dev->pm_cap)
2798 return -ENOTTY;
Sheng Yangd91cdc72008-11-11 17:17:47 +08002799
Yu Zhaof85876b2009-06-13 15:52:14 +08002800 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2801 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2802 return -ENOTTY;
Sheng Yang1ca88792008-11-11 17:17:48 +08002803
Yu Zhaof85876b2009-06-13 15:52:14 +08002804 if (probe)
2805 return 0;
2806
2807 if (dev->current_state != PCI_D0)
2808 return -EINVAL;
2809
2810 csr &= ~PCI_PM_CTRL_STATE_MASK;
2811 csr |= PCI_D3hot;
2812 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01002813 pci_dev_d3_sleep(dev);
Yu Zhaof85876b2009-06-13 15:52:14 +08002814
2815 csr &= ~PCI_PM_CTRL_STATE_MASK;
2816 csr |= PCI_D0;
2817 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01002818 pci_dev_d3_sleep(dev);
Yu Zhaof85876b2009-06-13 15:52:14 +08002819
2820 return 0;
2821}
2822
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08002823static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2824{
2825 u16 ctrl;
2826 struct pci_dev *pdev;
2827
Yu Zhao654b75e2009-06-26 14:04:46 +08002828 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08002829 return -ENOTTY;
2830
2831 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2832 if (pdev != dev)
2833 return -ENOTTY;
2834
2835 if (probe)
2836 return 0;
2837
2838 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2839 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2840 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2841 msleep(100);
2842
2843 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2844 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2845 msleep(100);
2846
2847 return 0;
2848}
2849
Yu Zhao8c1c6992009-06-13 15:52:13 +08002850static int pci_dev_reset(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002851{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002852 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002853
Yu Zhao8c1c6992009-06-13 15:52:13 +08002854 might_sleep();
Sheng Yang8dd7f802008-10-21 17:38:25 +08002855
Yu Zhao8c1c6992009-06-13 15:52:13 +08002856 if (!probe) {
2857 pci_block_user_cfg_access(dev);
2858 /* block PM suspend, driver probe, etc. */
Greg Kroah-Hartman8e9394c2010-02-17 10:57:05 -08002859 device_lock(&dev->dev);
Yu Zhao8c1c6992009-06-13 15:52:13 +08002860 }
Sheng Yang8dd7f802008-10-21 17:38:25 +08002861
Dexuan Cuib9c3b262009-12-07 13:03:21 +08002862 rc = pci_dev_specific_reset(dev, probe);
2863 if (rc != -ENOTTY)
2864 goto done;
2865
Yu Zhao8c1c6992009-06-13 15:52:13 +08002866 rc = pcie_flr(dev, probe);
2867 if (rc != -ENOTTY)
2868 goto done;
2869
2870 rc = pci_af_flr(dev, probe);
Yu Zhaof85876b2009-06-13 15:52:14 +08002871 if (rc != -ENOTTY)
2872 goto done;
2873
2874 rc = pci_pm_reset(dev, probe);
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08002875 if (rc != -ENOTTY)
2876 goto done;
2877
2878 rc = pci_parent_bus_reset(dev, probe);
Yu Zhao8c1c6992009-06-13 15:52:13 +08002879done:
2880 if (!probe) {
Greg Kroah-Hartman8e9394c2010-02-17 10:57:05 -08002881 device_unlock(&dev->dev);
Yu Zhao8c1c6992009-06-13 15:52:13 +08002882 pci_unblock_user_cfg_access(dev);
2883 }
2884
2885 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002886}
2887
2888/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08002889 * __pci_reset_function - reset a PCI device function
2890 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08002891 *
2892 * Some devices allow an individual function to be reset without affecting
2893 * other functions in the same device. The PCI device must be responsive
2894 * to PCI config space in order to use this function.
2895 *
2896 * The device function is presumed to be unused when this function is called.
2897 * Resetting the device will make the contents of PCI configuration space
2898 * random, so any caller of this must be prepared to reinitialise the
2899 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2900 * etc.
2901 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08002902 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08002903 * device doesn't support resetting a single function.
2904 */
Yu Zhao8c1c6992009-06-13 15:52:13 +08002905int __pci_reset_function(struct pci_dev *dev)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002906{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002907 return pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002908}
Yu Zhao8c1c6992009-06-13 15:52:13 +08002909EXPORT_SYMBOL_GPL(__pci_reset_function);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002910
2911/**
Michael S. Tsirkin711d5772009-07-27 23:37:48 +03002912 * pci_probe_reset_function - check whether the device can be safely reset
2913 * @dev: PCI device to reset
2914 *
2915 * Some devices allow an individual function to be reset without affecting
2916 * other functions in the same device. The PCI device must be responsive
2917 * to PCI config space in order to use this function.
2918 *
2919 * Returns 0 if the device function can be reset or negative if the
2920 * device doesn't support resetting a single function.
2921 */
2922int pci_probe_reset_function(struct pci_dev *dev)
2923{
2924 return pci_dev_reset(dev, 1);
2925}
2926
2927/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08002928 * pci_reset_function - quiesce and reset a PCI device function
2929 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08002930 *
2931 * Some devices allow an individual function to be reset without affecting
2932 * other functions in the same device. The PCI device must be responsive
2933 * to PCI config space in order to use this function.
2934 *
2935 * This function does not just reset the PCI portion of a device, but
2936 * clears all the state associated with the device. This function differs
Yu Zhao8c1c6992009-06-13 15:52:13 +08002937 * from __pci_reset_function in that it saves and restores device state
Sheng Yang8dd7f802008-10-21 17:38:25 +08002938 * over the reset.
2939 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08002940 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08002941 * device doesn't support resetting a single function.
2942 */
2943int pci_reset_function(struct pci_dev *dev)
2944{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002945 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002946
Yu Zhao8c1c6992009-06-13 15:52:13 +08002947 rc = pci_dev_reset(dev, 1);
2948 if (rc)
2949 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002950
Sheng Yang8dd7f802008-10-21 17:38:25 +08002951 pci_save_state(dev);
2952
Yu Zhao8c1c6992009-06-13 15:52:13 +08002953 /*
2954 * both INTx and MSI are disabled after the Interrupt Disable bit
2955 * is set and the Bus Master bit is cleared.
2956 */
Sheng Yang8dd7f802008-10-21 17:38:25 +08002957 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2958
Yu Zhao8c1c6992009-06-13 15:52:13 +08002959 rc = pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002960
2961 pci_restore_state(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002962
Yu Zhao8c1c6992009-06-13 15:52:13 +08002963 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002964}
2965EXPORT_SYMBOL_GPL(pci_reset_function);
2966
2967/**
Peter Orubad556ad42007-05-15 13:59:13 +02002968 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2969 * @dev: PCI device to query
2970 *
2971 * Returns mmrbc: maximum designed memory read count in bytes
2972 * or appropriate error value.
2973 */
2974int pcix_get_max_mmrbc(struct pci_dev *dev)
2975{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05002976 int cap;
Peter Orubad556ad42007-05-15 13:59:13 +02002977 u32 stat;
2978
2979 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2980 if (!cap)
2981 return -EINVAL;
2982
Dean Nelson7c9e2b12010-03-09 22:26:55 -05002983 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
Peter Orubad556ad42007-05-15 13:59:13 +02002984 return -EINVAL;
2985
Dean Nelson25daeb52010-03-09 22:26:40 -05002986 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
Peter Orubad556ad42007-05-15 13:59:13 +02002987}
2988EXPORT_SYMBOL(pcix_get_max_mmrbc);
2989
2990/**
2991 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2992 * @dev: PCI device to query
2993 *
2994 * Returns mmrbc: maximum memory read count in bytes
2995 * or appropriate error value.
2996 */
2997int pcix_get_mmrbc(struct pci_dev *dev)
2998{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05002999 int cap;
Dean Nelsonbdc2bda2010-03-09 22:26:48 -05003000 u16 cmd;
Peter Orubad556ad42007-05-15 13:59:13 +02003001
3002 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3003 if (!cap)
3004 return -EINVAL;
3005
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003006 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3007 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003008
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003009 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
Peter Orubad556ad42007-05-15 13:59:13 +02003010}
3011EXPORT_SYMBOL(pcix_get_mmrbc);
3012
3013/**
3014 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3015 * @dev: PCI device to query
3016 * @mmrbc: maximum memory read count in bytes
3017 * valid values are 512, 1024, 2048, 4096
3018 *
3019 * If possible sets maximum memory read byte count, some bridges have erratas
3020 * that prevent this.
3021 */
3022int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3023{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003024 int cap;
Dean Nelsonbdc2bda2010-03-09 22:26:48 -05003025 u32 stat, v, o;
3026 u16 cmd;
Peter Orubad556ad42007-05-15 13:59:13 +02003027
vignesh babu229f5af2007-08-13 18:23:14 +05303028 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003029 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003030
3031 v = ffs(mmrbc) - 10;
3032
3033 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3034 if (!cap)
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003035 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003036
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003037 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3038 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003039
3040 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3041 return -E2BIG;
3042
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003043 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3044 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003045
3046 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3047 if (o != v) {
3048 if (v > o && dev->bus &&
3049 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3050 return -EIO;
3051
3052 cmd &= ~PCI_X_CMD_MAX_READ;
3053 cmd |= v << 2;
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003054 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3055 return -EIO;
Peter Orubad556ad42007-05-15 13:59:13 +02003056 }
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003057 return 0;
Peter Orubad556ad42007-05-15 13:59:13 +02003058}
3059EXPORT_SYMBOL(pcix_set_mmrbc);
3060
3061/**
3062 * pcie_get_readrq - get PCI Express read request size
3063 * @dev: PCI device to query
3064 *
3065 * Returns maximum memory read request in bytes
3066 * or appropriate error value.
3067 */
3068int pcie_get_readrq(struct pci_dev *dev)
3069{
3070 int ret, cap;
3071 u16 ctl;
3072
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09003073 cap = pci_pcie_cap(dev);
Peter Orubad556ad42007-05-15 13:59:13 +02003074 if (!cap)
3075 return -EINVAL;
3076
3077 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3078 if (!ret)
Julia Lawall93e75fa2010-08-05 22:23:16 +02003079 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
Peter Orubad556ad42007-05-15 13:59:13 +02003080
3081 return ret;
3082}
3083EXPORT_SYMBOL(pcie_get_readrq);
3084
3085/**
3086 * pcie_set_readrq - set PCI Express maximum memory read request
3087 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07003088 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02003089 * valid values are 128, 256, 512, 1024, 2048, 4096
3090 *
3091 * If possible sets maximum read byte count
3092 */
3093int pcie_set_readrq(struct pci_dev *dev, int rq)
3094{
3095 int cap, err = -EINVAL;
3096 u16 ctl, v;
3097
vignesh babu229f5af2007-08-13 18:23:14 +05303098 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Peter Orubad556ad42007-05-15 13:59:13 +02003099 goto out;
3100
3101 v = (ffs(rq) - 8) << 12;
3102
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09003103 cap = pci_pcie_cap(dev);
Peter Orubad556ad42007-05-15 13:59:13 +02003104 if (!cap)
3105 goto out;
3106
3107 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3108 if (err)
3109 goto out;
3110
3111 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3112 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3113 ctl |= v;
3114 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
3115 }
3116
3117out:
3118 return err;
3119}
3120EXPORT_SYMBOL(pcie_set_readrq);
3121
3122/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003123 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08003124 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003125 * @flags: resource type mask to be selected
3126 *
3127 * This helper routine makes bar mask from the type of resource.
3128 */
3129int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3130{
3131 int i, bars = 0;
3132 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3133 if (pci_resource_flags(dev, i) & flags)
3134 bars |= (1 << i);
3135 return bars;
3136}
3137
Yu Zhao613e7ed2008-11-22 02:41:27 +08003138/**
3139 * pci_resource_bar - get position of the BAR associated with a resource
3140 * @dev: the PCI device
3141 * @resno: the resource number
3142 * @type: the BAR type to be filled in
3143 *
3144 * Returns BAR position in config space, or 0 if the BAR is invalid.
3145 */
3146int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3147{
Yu Zhaod1b054d2009-03-20 11:25:11 +08003148 int reg;
3149
Yu Zhao613e7ed2008-11-22 02:41:27 +08003150 if (resno < PCI_ROM_RESOURCE) {
3151 *type = pci_bar_unknown;
3152 return PCI_BASE_ADDRESS_0 + 4 * resno;
3153 } else if (resno == PCI_ROM_RESOURCE) {
3154 *type = pci_bar_mem32;
3155 return dev->rom_base_reg;
Yu Zhaod1b054d2009-03-20 11:25:11 +08003156 } else if (resno < PCI_BRIDGE_RESOURCES) {
3157 /* device specific resource */
3158 reg = pci_iov_resource_bar(dev, resno, type);
3159 if (reg)
3160 return reg;
Yu Zhao613e7ed2008-11-22 02:41:27 +08003161 }
3162
Bjorn Helgaas865df572009-11-04 10:32:57 -07003163 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
Yu Zhao613e7ed2008-11-22 02:41:27 +08003164 return 0;
3165}
3166
Mike Travis95a8b6e2010-02-02 14:38:13 -08003167/* Some architectures require additional programming to enable VGA */
3168static arch_set_vga_state_t arch_set_vga_state;
3169
3170void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3171{
3172 arch_set_vga_state = func; /* NULL disables */
3173}
3174
3175static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3176 unsigned int command_bits, bool change_bridge)
3177{
3178 if (arch_set_vga_state)
3179 return arch_set_vga_state(dev, decode, command_bits,
3180 change_bridge);
3181 return 0;
3182}
3183
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10003184/**
3185 * pci_set_vga_state - set VGA decode state on device and parents if requested
Randy Dunlap19eea632009-09-17 15:28:22 -07003186 * @dev: the PCI device
3187 * @decode: true = enable decoding, false = disable decoding
3188 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3189 * @change_bridge: traverse ancestors and change bridges
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10003190 */
3191int pci_set_vga_state(struct pci_dev *dev, bool decode,
3192 unsigned int command_bits, bool change_bridge)
3193{
3194 struct pci_bus *bus;
3195 struct pci_dev *bridge;
3196 u16 cmd;
Mike Travis95a8b6e2010-02-02 14:38:13 -08003197 int rc;
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10003198
3199 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
3200
Mike Travis95a8b6e2010-02-02 14:38:13 -08003201 /* ARCH specific VGA enables */
3202 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
3203 if (rc)
3204 return rc;
3205
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10003206 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3207 if (decode == true)
3208 cmd |= command_bits;
3209 else
3210 cmd &= ~command_bits;
3211 pci_write_config_word(dev, PCI_COMMAND, cmd);
3212
3213 if (change_bridge == false)
3214 return 0;
3215
3216 bus = dev->bus;
3217 while (bus) {
3218 bridge = bus->self;
3219 if (bridge) {
3220 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3221 &cmd);
3222 if (decode == true)
3223 cmd |= PCI_BRIDGE_CTL_VGA;
3224 else
3225 cmd &= ~PCI_BRIDGE_CTL_VGA;
3226 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3227 cmd);
3228 }
3229 bus = bus->parent;
3230 }
3231 return 0;
3232}
3233
Yuji Shimada32a9a6822009-03-16 17:13:39 +09003234#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3235static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
Thomas Gleixnere9d1e492009-11-06 22:41:23 +00003236static DEFINE_SPINLOCK(resource_alignment_lock);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09003237
3238/**
3239 * pci_specified_resource_alignment - get resource alignment specified by user.
3240 * @dev: the PCI device to get
3241 *
3242 * RETURNS: Resource alignment if it is specified.
3243 * Zero if it is not specified.
3244 */
3245resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3246{
3247 int seg, bus, slot, func, align_order, count;
3248 resource_size_t align = 0;
3249 char *p;
3250
3251 spin_lock(&resource_alignment_lock);
3252 p = resource_alignment_param;
3253 while (*p) {
3254 count = 0;
3255 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3256 p[count] == '@') {
3257 p += count + 1;
3258 } else {
3259 align_order = -1;
3260 }
3261 if (sscanf(p, "%x:%x:%x.%x%n",
3262 &seg, &bus, &slot, &func, &count) != 4) {
3263 seg = 0;
3264 if (sscanf(p, "%x:%x.%x%n",
3265 &bus, &slot, &func, &count) != 3) {
3266 /* Invalid format */
3267 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3268 p);
3269 break;
3270 }
3271 }
3272 p += count;
3273 if (seg == pci_domain_nr(dev->bus) &&
3274 bus == dev->bus->number &&
3275 slot == PCI_SLOT(dev->devfn) &&
3276 func == PCI_FUNC(dev->devfn)) {
3277 if (align_order == -1) {
3278 align = PAGE_SIZE;
3279 } else {
3280 align = 1 << align_order;
3281 }
3282 /* Found */
3283 break;
3284 }
3285 if (*p != ';' && *p != ',') {
3286 /* End of param or invalid format */
3287 break;
3288 }
3289 p++;
3290 }
3291 spin_unlock(&resource_alignment_lock);
3292 return align;
3293}
3294
3295/**
3296 * pci_is_reassigndev - check if specified PCI is target device to reassign
3297 * @dev: the PCI device to check
3298 *
3299 * RETURNS: non-zero for PCI device is a target device to reassign,
3300 * or zero is not.
3301 */
3302int pci_is_reassigndev(struct pci_dev *dev)
3303{
3304 return (pci_specified_resource_alignment(dev) != 0);
3305}
3306
3307ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3308{
3309 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3310 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3311 spin_lock(&resource_alignment_lock);
3312 strncpy(resource_alignment_param, buf, count);
3313 resource_alignment_param[count] = '\0';
3314 spin_unlock(&resource_alignment_lock);
3315 return count;
3316}
3317
3318ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3319{
3320 size_t count;
3321 spin_lock(&resource_alignment_lock);
3322 count = snprintf(buf, size, "%s", resource_alignment_param);
3323 spin_unlock(&resource_alignment_lock);
3324 return count;
3325}
3326
3327static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3328{
3329 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3330}
3331
3332static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3333 const char *buf, size_t count)
3334{
3335 return pci_set_resource_alignment_param(buf, count);
3336}
3337
3338BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3339 pci_resource_alignment_store);
3340
3341static int __init pci_resource_alignment_sysfs_init(void)
3342{
3343 return bus_create_file(&pci_bus_type,
3344 &bus_attr_resource_alignment);
3345}
3346
3347late_initcall(pci_resource_alignment_sysfs_init);
3348
Jeff Garzik32a2eea2007-10-11 16:57:27 -04003349static void __devinit pci_no_domains(void)
3350{
3351#ifdef CONFIG_PCI_DOMAINS
3352 pci_domains_supported = 0;
3353#endif
3354}
3355
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07003356/**
3357 * pci_ext_cfg_enabled - can we access extended PCI config space?
3358 * @dev: The PCI device of the root bridge.
3359 *
3360 * Returns 1 if we can access PCI extended config space (offsets
3361 * greater than 0xff). This is the default implementation. Architecture
3362 * implementations can override this.
3363 */
3364int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3365{
3366 return 1;
3367}
3368
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11003369void __weak pci_fixup_cardbus(struct pci_bus *bus)
3370{
3371}
3372EXPORT_SYMBOL(pci_fixup_cardbus);
3373
Al Viroad04d312008-11-22 17:37:14 +00003374static int __init pci_setup(char *str)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003375{
3376 while (str) {
3377 char *k = strchr(str, ',');
3378 if (k)
3379 *k++ = 0;
3380 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07003381 if (!strcmp(str, "nomsi")) {
3382 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07003383 } else if (!strcmp(str, "noaer")) {
3384 pci_no_aer();
Jeff Garzik32a2eea2007-10-11 16:57:27 -04003385 } else if (!strcmp(str, "nodomains")) {
3386 pci_no_domains();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08003387 } else if (!strncmp(str, "cbiosize=", 9)) {
3388 pci_cardbus_io_size = memparse(str + 9, &str);
3389 } else if (!strncmp(str, "cbmemsize=", 10)) {
3390 pci_cardbus_mem_size = memparse(str + 10, &str);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09003391 } else if (!strncmp(str, "resource_alignment=", 19)) {
3392 pci_set_resource_alignment_param(str + 19,
3393 strlen(str + 19));
Andrew Patterson43c16402009-04-22 16:52:09 -06003394 } else if (!strncmp(str, "ecrc=", 5)) {
3395 pcie_ecrc_get_policy(str + 5);
Eric W. Biederman28760482009-09-09 14:09:24 -07003396 } else if (!strncmp(str, "hpiosize=", 9)) {
3397 pci_hotplug_io_size = memparse(str + 9, &str);
3398 } else if (!strncmp(str, "hpmemsize=", 10)) {
3399 pci_hotplug_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07003400 } else {
3401 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3402 str);
3403 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003404 }
3405 str = k;
3406 }
Andi Kleen0637a702006-09-26 10:52:41 +02003407 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003408}
Andi Kleen0637a702006-09-26 10:52:41 +02003409early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003410
Tejun Heo0b62e132007-07-27 14:43:35 +09003411EXPORT_SYMBOL(pci_reenable_device);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11003412EXPORT_SYMBOL(pci_enable_device_io);
3413EXPORT_SYMBOL(pci_enable_device_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003414EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09003415EXPORT_SYMBOL(pcim_enable_device);
3416EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003417EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003418EXPORT_SYMBOL(pci_find_capability);
3419EXPORT_SYMBOL(pci_bus_find_capability);
3420EXPORT_SYMBOL(pci_release_regions);
3421EXPORT_SYMBOL(pci_request_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003422EXPORT_SYMBOL(pci_request_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003423EXPORT_SYMBOL(pci_release_region);
3424EXPORT_SYMBOL(pci_request_region);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003425EXPORT_SYMBOL(pci_request_region_exclusive);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003426EXPORT_SYMBOL(pci_release_selected_regions);
3427EXPORT_SYMBOL(pci_request_selected_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003428EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003429EXPORT_SYMBOL(pci_set_master);
Ben Hutchings6a479072008-12-23 03:08:29 +00003430EXPORT_SYMBOL(pci_clear_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003431EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07003432EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003433EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04003434EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003435EXPORT_SYMBOL(pci_assign_resource);
3436EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003437EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003438
3439EXPORT_SYMBOL(pci_set_power_state);
3440EXPORT_SYMBOL(pci_save_state);
3441EXPORT_SYMBOL(pci_restore_state);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02003442EXPORT_SYMBOL(pci_pme_capable);
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02003443EXPORT_SYMBOL(pci_pme_active);
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02003444EXPORT_SYMBOL(pci_wake_from_d3);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02003445EXPORT_SYMBOL(pci_target_state);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02003446EXPORT_SYMBOL(pci_prepare_to_sleep);
3447EXPORT_SYMBOL(pci_back_from_sleep);
Brian Kingf7bdd122007-04-06 16:39:36 -05003448EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);