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gerrit-public.fairphone.software / kernel / msm-4.19 / 39ffbd917c6230ca503edcd90de6b373f34b6b1a / . / arch / arm / boot / dts / am33xx.dtsi
blob: d76ae24c97453ff94ee9bc7232ed8283c8dbc01c [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]29 usb0 = &usb0;
30 usb1 = &usb1;
31 phy0 = &usb0_phy;
32 phy1 = &usb1_phy;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]33 };
34
35 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]36 #address-cells = <1>;
37 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 cpu@0 {
39 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]40 device_type = "cpu";
41 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]42
43 /*
44 * To consider voltage drop between PMIC and SoC,
45 * tolerance value is reduced to 2% from 4% and
46 * voltage value is increased as a precaution.
47 */
48 operating-points = <
49 /* kHz uV */
50 720000 1285000
51 600000 1225000
52 500000 1125000
53 275000 1125000
54 >;
55 voltage-tolerance = <2>; /* 2 percentage */
56 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]57 };
58 };
59
60 /*
61 * The soc node represents the soc top level view. It is uses for IPs
62 * that are not memory mapped in the MPU view or for the MPU itself.
63 */
64 soc {
65 compatible = "ti,omap-infra";
66 mpu {
67 compatible = "ti,omap3-mpu";
68 ti,hwmods = "mpu";
69 };
70 };
71
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]72 am33xx_pinmux: pinmux@44e10800 {
73 compatible = "pinctrl-single";
74 reg = <0x44e10800 0x0238>;
75 #address-cells = <1>;
76 #size-cells = <0>;
77 pinctrl-single,register-width = <32>;
78 pinctrl-single,function-mask = <0x7f>;
79 };
80
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]81 /*
82 * XXX: Use a flat representation of the AM33XX interconnect.
83 * The real AM33XX interconnect network is quite complex.Since
84 * that will not bring real advantage to represent that in DT
85 * for the moment, just use a fake OCP bus entry to represent
86 * the whole bus hierarchy.
87 */
88 ocp {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93 ti,hwmods = "l3_main";
94
95 intc: interrupt-controller@48200000 {
96 compatible = "ti,omap2-intc";
97 interrupt-controller;
98 #interrupt-cells = <1>;
99 ti,intc-size = <128>;
100 reg = <0x48200000 0x1000>;
101 };
102
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]103 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]104 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio1";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]110 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]111 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]112 };
113
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]114 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]115 compatible = "ti,omap4-gpio";
116 ti,hwmods = "gpio2";
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]121 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]122 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]123 };
124
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]125 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]126 compatible = "ti,omap4-gpio";
127 ti,hwmods = "gpio3";
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]132 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]133 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]134 };
135
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]136 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]137 compatible = "ti,omap4-gpio";
138 ti,hwmods = "gpio4";
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]143 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]144 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]145 };
146
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]147 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]148 compatible = "ti,omap3-uart";
149 ti,hwmods = "uart1";
150 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]151 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]152 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]153 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]154 };
155
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]156 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]157 compatible = "ti,omap3-uart";
158 ti,hwmods = "uart2";
159 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]160 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]161 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]162 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]163 };
164
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]165 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]166 compatible = "ti,omap3-uart";
167 ti,hwmods = "uart3";
168 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]169 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]171 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]172 };
173
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]174 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]175 compatible = "ti,omap3-uart";
176 ti,hwmods = "uart4";
177 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]178 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]179 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]180 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]181 };
182
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]183 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]184 compatible = "ti,omap3-uart";
185 ti,hwmods = "uart5";
186 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]187 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]188 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]189 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]190 };
191
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]192 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]193 compatible = "ti,omap3-uart";
194 ti,hwmods = "uart6";
195 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]197 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]198 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]199 };
200
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]201 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]202 compatible = "ti,omap4-i2c";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]206 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]207 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]208 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]209 };
210
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]211 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]212 compatible = "ti,omap4-i2c";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]216 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]217 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]218 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]219 };
220
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]221 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]222 compatible = "ti,omap4-i2c";
223 #address-cells = <1>;
224 #size-cells = <0>;
225 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]228 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]229 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]230
231 wdt2: wdt@44e35000 {
232 compatible = "ti,omap3-wdt";
233 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]234 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]235 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]236 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]237
238 dcan0: d_can@481cc000 {
239 compatible = "bosch,d_can";
240 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]241 reg = <0x481cc000 0x2000
242 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]243 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]244 status = "disabled";
245 };
246
247 dcan1: d_can@481d0000 {
248 compatible = "bosch,d_can";
249 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]250 reg = <0x481d0000 0x2000
251 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]252 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]253 status = "disabled";
254 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]255
256 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]257 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]258 reg = <0x44e31000 0x400>;
259 interrupts = <67>;
260 ti,hwmods = "timer1";
261 ti,timer-alwon;
262 };
263
264 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]265 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]266 reg = <0x48040000 0x400>;
267 interrupts = <68>;
268 ti,hwmods = "timer2";
269 };
270
271 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]272 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]273 reg = <0x48042000 0x400>;
274 interrupts = <69>;
275 ti,hwmods = "timer3";
276 };
277
278 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]279 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]280 reg = <0x48044000 0x400>;
281 interrupts = <92>;
282 ti,hwmods = "timer4";
283 ti,timer-pwm;
284 };
285
286 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]287 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]288 reg = <0x48046000 0x400>;
289 interrupts = <93>;
290 ti,hwmods = "timer5";
291 ti,timer-pwm;
292 };
293
294 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]295 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]296 reg = <0x48048000 0x400>;
297 interrupts = <94>;
298 ti,hwmods = "timer6";
299 ti,timer-pwm;
300 };
301
302 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]303 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]304 reg = <0x4804a000 0x400>;
305 interrupts = <95>;
306 ti,hwmods = "timer7";
307 ti,timer-pwm;
308 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]309
310 rtc@44e3e000 {
311 compatible = "ti,da830-rtc";
312 reg = <0x44e3e000 0x1000>;
313 interrupts = <75
314 76>;
315 ti,hwmods = "rtc";
316 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]317
318 spi0: spi@48030000 {
319 compatible = "ti,omap4-mcspi";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]323 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]324 ti,spi-num-cs = <2>;
325 ti,hwmods = "spi0";
326 status = "disabled";
327 };
328
329 spi1: spi@481a0000 {
330 compatible = "ti,omap4-mcspi";
331 #address-cells = <1>;
332 #size-cells = <0>;
333 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]334 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]335 ti,spi-num-cs = <2>;
336 ti,hwmods = "spi1";
337 status = "disabled";
338 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]339
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]340 usb: usb@47400000 {
341 compatible = "ti,am33xx-usb";
342 reg = <0x47400000 0x1000>;
343 ranges;
344 #address-cells = <1>;
345 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]346 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]347 status = "disabled";
348
349 ctrl_mod: control@44e10000 {
350 compatible = "ti,am335x-usb-ctrl-module";
351 reg = <0x44e10620 0x10
352 0x44e10648 0x4>;
353 reg-names = "phy_ctrl", "wakeup";
354 status = "disabled";
355 };
356
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]357 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]358 compatible = "ti,am335x-usb-phy";
359 reg = <0x47401300 0x100>;
360 reg-names = "phy";
361 status = "disabled";
362 ti,ctrl_mod = <&ctrl_mod>;
363 };
364
365 usb0: usb@47401000 {
366 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]367 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]368 reg = <0x47401400 0x400
369 0x47401000 0x200>;
370 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]371
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]372 interrupts = <18>;
373 interrupt-names = "mc";
374 dr_mode = "otg";
375 mentor,multipoint = <1>;
376 mentor,num-eps = <16>;
377 mentor,ram-bits = <12>;
378 mentor,power = <500>;
379 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]380
381 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
382 &cppi41dma 2 0 &cppi41dma 3 0
383 &cppi41dma 4 0 &cppi41dma 5 0
384 &cppi41dma 6 0 &cppi41dma 7 0
385 &cppi41dma 8 0 &cppi41dma 9 0
386 &cppi41dma 10 0 &cppi41dma 11 0
387 &cppi41dma 12 0 &cppi41dma 13 0
388 &cppi41dma 14 0 &cppi41dma 0 1
389 &cppi41dma 1 1 &cppi41dma 2 1
390 &cppi41dma 3 1 &cppi41dma 4 1
391 &cppi41dma 5 1 &cppi41dma 6 1
392 &cppi41dma 7 1 &cppi41dma 8 1
393 &cppi41dma 9 1 &cppi41dma 10 1
394 &cppi41dma 11 1 &cppi41dma 12 1
395 &cppi41dma 13 1 &cppi41dma 14 1>;
396 dma-names =
397 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
398 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
399 "rx14", "rx15",
400 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
401 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
402 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]403 };
404
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]405 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]406 compatible = "ti,am335x-usb-phy";
407 reg = <0x47401b00 0x100>;
408 reg-names = "phy";
409 status = "disabled";
410 ti,ctrl_mod = <&ctrl_mod>;
411 };
412
413 usb1: usb@47401800 {
414 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]415 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]416 reg = <0x47401c00 0x400
417 0x47401800 0x200>;
418 reg-names = "mc", "control";
419 interrupts = <19>;
420 interrupt-names = "mc";
421 dr_mode = "otg";
422 mentor,multipoint = <1>;
423 mentor,num-eps = <16>;
424 mentor,ram-bits = <12>;
425 mentor,power = <500>;
426 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]427
428 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
429 &cppi41dma 17 0 &cppi41dma 18 0
430 &cppi41dma 19 0 &cppi41dma 20 0
431 &cppi41dma 21 0 &cppi41dma 22 0
432 &cppi41dma 23 0 &cppi41dma 24 0
433 &cppi41dma 25 0 &cppi41dma 26 0
434 &cppi41dma 27 0 &cppi41dma 28 0
435 &cppi41dma 29 0 &cppi41dma 15 1
436 &cppi41dma 16 1 &cppi41dma 17 1
437 &cppi41dma 18 1 &cppi41dma 19 1
438 &cppi41dma 20 1 &cppi41dma 21 1
439 &cppi41dma 22 1 &cppi41dma 23 1
440 &cppi41dma 24 1 &cppi41dma 25 1
441 &cppi41dma 26 1 &cppi41dma 27 1
442 &cppi41dma 28 1 &cppi41dma 29 1>;
443 dma-names =
444 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
445 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
446 "rx14", "rx15",
447 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
448 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
449 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]450 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]451
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]452 cppi41dma: dma-controller@07402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]453 compatible = "ti,am3359-cppi41";
454 reg = <0x47400000 0x1000
455 0x47402000 0x1000
456 0x47403000 0x1000
457 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]458 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]459 interrupts = <17>;
460 interrupt-names = "glue";
461 #dma-cells = <2>;
462 #dma-channels = <30>;
463 #dma-requests = <256>;
464 status = "disabled";
465 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]466 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]467
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]468 epwmss0: epwmss@48300000 {
469 compatible = "ti,am33xx-pwmss";
470 reg = <0x48300000 0x10>;
471 ti,hwmods = "epwmss0";
472 #address-cells = <1>;
473 #size-cells = <1>;
474 status = "disabled";
475 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
476 0x48300180 0x48300180 0x80 /* EQEP */
477 0x48300200 0x48300200 0x80>; /* EHRPWM */
478
479 ecap0: ecap@48300100 {
480 compatible = "ti,am33xx-ecap";
481 #pwm-cells = <3>;
482 reg = <0x48300100 0x80>;
483 ti,hwmods = "ecap0";
484 status = "disabled";
485 };
486
487 ehrpwm0: ehrpwm@48300200 {
488 compatible = "ti,am33xx-ehrpwm";
489 #pwm-cells = <3>;
490 reg = <0x48300200 0x80>;
491 ti,hwmods = "ehrpwm0";
492 status = "disabled";
493 };
494 };
495
496 epwmss1: epwmss@48302000 {
497 compatible = "ti,am33xx-pwmss";
498 reg = <0x48302000 0x10>;
499 ti,hwmods = "epwmss1";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 status = "disabled";
503 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
504 0x48302180 0x48302180 0x80 /* EQEP */
505 0x48302200 0x48302200 0x80>; /* EHRPWM */
506
507 ecap1: ecap@48302100 {
508 compatible = "ti,am33xx-ecap";
509 #pwm-cells = <3>;
510 reg = <0x48302100 0x80>;
511 ti,hwmods = "ecap1";
512 status = "disabled";
513 };
514
515 ehrpwm1: ehrpwm@48302200 {
516 compatible = "ti,am33xx-ehrpwm";
517 #pwm-cells = <3>;
518 reg = <0x48302200 0x80>;
519 ti,hwmods = "ehrpwm1";
520 status = "disabled";
521 };
522 };
523
524 epwmss2: epwmss@48304000 {
525 compatible = "ti,am33xx-pwmss";
526 reg = <0x48304000 0x10>;
527 ti,hwmods = "epwmss2";
528 #address-cells = <1>;
529 #size-cells = <1>;
530 status = "disabled";
531 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
532 0x48304180 0x48304180 0x80 /* EQEP */
533 0x48304200 0x48304200 0x80>; /* EHRPWM */
534
535 ecap2: ecap@48304100 {
536 compatible = "ti,am33xx-ecap";
537 #pwm-cells = <3>;
538 reg = <0x48304100 0x80>;
539 ti,hwmods = "ecap2";
540 status = "disabled";
541 };
542
543 ehrpwm2: ehrpwm@48304200 {
544 compatible = "ti,am33xx-ehrpwm";
545 #pwm-cells = <3>;
546 reg = <0x48304200 0x80>;
547 ti,hwmods = "ehrpwm2";
548 status = "disabled";
549 };
550 };
551
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]552 mac: ethernet@4a100000 {
553 compatible = "ti,cpsw";
554 ti,hwmods = "cpgmac0";
555 cpdma_channels = <8>;
556 ale_entries = <1024>;
557 bd_ram_size = <0x2000>;
558 no_bd_ram = <0>;
559 rx_descs = <64>;
560 mac_control = <0x20>;
561 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]562 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]563 cpts_clock_mult = <0x80000000>;
564 cpts_clock_shift = <29>;
565 reg = <0x4a100000 0x800
566 0x4a101200 0x100>;
567 #address-cells = <1>;
568 #size-cells = <1>;
569 interrupt-parent = <&intc>;
570 /*
571 * c0_rx_thresh_pend
572 * c0_rx_pend
573 * c0_tx_pend
574 * c0_misc_pend
575 */
576 interrupts = <40 41 42 43>;
577 ranges;
578
579 davinci_mdio: mdio@4a101000 {
580 compatible = "ti,davinci_mdio";
581 #address-cells = <1>;
582 #size-cells = <0>;
583 ti,hwmods = "davinci_mdio";
584 bus_freq = <1000000>;
585 reg = <0x4a101000 0x100>;
586 };
587
588 cpsw_emac0: slave@4a100200 {
589 /* Filled in by U-Boot */
590 mac-address = [ 00 00 00 00 00 00 ];
591 };
592
593 cpsw_emac1: slave@4a100300 {
594 /* Filled in by U-Boot */
595 mac-address = [ 00 00 00 00 00 00 ];
596 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame^]597
598 phy_sel: cpsw-phy-sel@44e10650 {
599 compatible = "ti,am3352-cpsw-phy-sel";
600 reg= <0x44e10650 0x4>;
601 reg-names = "gmii-sel";
602 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]603 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]604
605 ocmcram: ocmcram@40300000 {
606 compatible = "ti,am3352-ocmcram";
607 reg = <0x40300000 0x10000>;
608 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]609 };
610
611 wkup_m3: wkup_m3@44d00000 {
612 compatible = "ti,am3353-wkup-m3";
613 reg = <0x44d00000 0x4000 /* M3 UMEM */
614 0x44d80000 0x2000>; /* M3 DMEM */
615 ti,hwmods = "wkup_m3";
616 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]617
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]618 elm: elm@48080000 {
619 compatible = "ti,am3352-elm";
620 reg = <0x48080000 0x2000>;
621 interrupts = <4>;
622 ti,hwmods = "elm";
623 status = "disabled";
624 };
625
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]626 tscadc: tscadc@44e0d000 {
627 compatible = "ti,am3359-tscadc";
628 reg = <0x44e0d000 0x1000>;
629 interrupt-parent = <&intc>;
630 interrupts = <16>;
631 ti,hwmods = "adc_tsc";
632 status = "disabled";
633
634 tsc {
635 compatible = "ti,am3359-tsc";
636 };
637 am335x_adc: adc {
638 #io-channel-cells = <1>;
639 compatible = "ti,am3359-adc";
640 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]641 };
642
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]643 gpmc: gpmc@50000000 {
644 compatible = "ti,am3352-gpmc";
645 ti,hwmods = "gpmc";
646 reg = <0x50000000 0x2000>;
647 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]648 gpmc,num-cs = <7>;
649 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]650 #address-cells = <2>;
651 #size-cells = <1>;
652 status = "disabled";
653 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]654 };
655};