Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * probe.c - PCI detection and setup code |
| 3 | */ |
| 4 | |
| 5 | #include <linux/kernel.h> |
| 6 | #include <linux/delay.h> |
| 7 | #include <linux/init.h> |
| 8 | #include <linux/pci.h> |
Suthikulpanit, Suravee | 5023071 | 2015-10-28 15:50:53 -0700 | [diff] [blame] | 9 | #include <linux/of_device.h> |
Murali Karicheri | de335bb4 | 2015-03-03 12:52:13 -0500 | [diff] [blame] | 10 | #include <linux/of_pci.h> |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 11 | #include <linux/pci_hotplug.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/slab.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/cpumask.h> |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 15 | #include <linux/pci-aspm.h> |
Taku Izumi | b07461a | 2015-09-17 10:09:37 -0500 | [diff] [blame] | 16 | #include <linux/aer.h> |
Suthikulpanit, Suravee | 29dbe1f | 2015-10-28 15:50:54 -0700 | [diff] [blame] | 17 | #include <linux/acpi.h> |
Jake Oshins | 788858e | 2016-02-16 21:56:22 +0000 | [diff] [blame] | 18 | #include <linux/irqdomain.h> |
Mika Westerberg | d963f65 | 2016-06-02 11:17:13 +0300 | [diff] [blame] | 19 | #include <linux/pm_runtime.h> |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 20 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | |
| 22 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ |
| 23 | #define CARDBUS_RESERVE_BUSNR 3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 25 | static struct resource busn_resource = { |
Yinghai Lu | 67cdc82 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 26 | .name = "PCI busn", |
| 27 | .start = 0, |
| 28 | .end = 255, |
| 29 | .flags = IORESOURCE_BUS, |
| 30 | }; |
| 31 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | /* Ugh. Need to stop exporting this to modules. */ |
| 33 | LIST_HEAD(pci_root_buses); |
| 34 | EXPORT_SYMBOL(pci_root_buses); |
| 35 | |
Yinghai Lu | 5cc62c2 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 36 | static LIST_HEAD(pci_domain_busn_res_list); |
| 37 | |
| 38 | struct pci_domain_busn_res { |
| 39 | struct list_head list; |
| 40 | struct resource res; |
| 41 | int domain_nr; |
| 42 | }; |
| 43 | |
| 44 | static struct resource *get_pci_domain_busn_res(int domain_nr) |
| 45 | { |
| 46 | struct pci_domain_busn_res *r; |
| 47 | |
| 48 | list_for_each_entry(r, &pci_domain_busn_res_list, list) |
| 49 | if (r->domain_nr == domain_nr) |
| 50 | return &r->res; |
| 51 | |
| 52 | r = kzalloc(sizeof(*r), GFP_KERNEL); |
| 53 | if (!r) |
| 54 | return NULL; |
| 55 | |
| 56 | r->domain_nr = domain_nr; |
| 57 | r->res.start = 0; |
| 58 | r->res.end = 0xff; |
| 59 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; |
| 60 | |
| 61 | list_add_tail(&r->list, &pci_domain_busn_res_list); |
| 62 | |
| 63 | return &r->res; |
| 64 | } |
| 65 | |
Greg Kroah-Hartman | 7030892 | 2008-02-13 22:30:39 -0800 | [diff] [blame] | 66 | static int find_anything(struct device *dev, void *data) |
| 67 | { |
| 68 | return 1; |
| 69 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | |
Zhang, Yanmin | ed4aaad | 2007-07-15 23:39:39 -0700 | [diff] [blame] | 71 | /* |
| 72 | * Some device drivers need know if pci is initiated. |
| 73 | * Basically, we think pci is not initiated when there |
Greg Kroah-Hartman | 7030892 | 2008-02-13 22:30:39 -0800 | [diff] [blame] | 74 | * is no device to be found on the pci_bus_type. |
Zhang, Yanmin | ed4aaad | 2007-07-15 23:39:39 -0700 | [diff] [blame] | 75 | */ |
| 76 | int no_pci_devices(void) |
| 77 | { |
Greg Kroah-Hartman | 7030892 | 2008-02-13 22:30:39 -0800 | [diff] [blame] | 78 | struct device *dev; |
| 79 | int no_devices; |
Zhang, Yanmin | ed4aaad | 2007-07-15 23:39:39 -0700 | [diff] [blame] | 80 | |
Greg Kroah-Hartman | 7030892 | 2008-02-13 22:30:39 -0800 | [diff] [blame] | 81 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
| 82 | no_devices = (dev == NULL); |
| 83 | put_device(dev); |
| 84 | return no_devices; |
| 85 | } |
Zhang, Yanmin | ed4aaad | 2007-07-15 23:39:39 -0700 | [diff] [blame] | 86 | EXPORT_SYMBOL(no_pci_devices); |
| 87 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | * PCI Bus Class |
| 90 | */ |
Greg Kroah-Hartman | fd7d1ce | 2007-05-22 22:47:54 -0400 | [diff] [blame] | 91 | static void release_pcibus_dev(struct device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | { |
Greg Kroah-Hartman | fd7d1ce | 2007-05-22 22:47:54 -0400 | [diff] [blame] | 93 | struct pci_bus *pci_bus = to_pci_bus(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | |
Markus Elfring | ff0387c | 2014-11-10 21:02:17 -0700 | [diff] [blame] | 95 | put_device(pci_bus->bridge); |
Bjorn Helgaas | 2fe2abf | 2010-02-23 10:24:36 -0700 | [diff] [blame] | 96 | pci_bus_remove_resources(pci_bus); |
Benjamin Herrenschmidt | 98d9f30c8 | 2011-04-11 11:37:07 +1000 | [diff] [blame] | 97 | pci_release_bus_of_node(pci_bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | kfree(pci_bus); |
| 99 | } |
| 100 | |
| 101 | static struct class pcibus_class = { |
| 102 | .name = "pci_bus", |
Greg Kroah-Hartman | fd7d1ce | 2007-05-22 22:47:54 -0400 | [diff] [blame] | 103 | .dev_release = &release_pcibus_dev, |
Greg Kroah-Hartman | 56039e6 | 2013-07-24 15:05:17 -0700 | [diff] [blame] | 104 | .dev_groups = pcibus_groups, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | }; |
| 106 | |
| 107 | static int __init pcibus_class_init(void) |
| 108 | { |
| 109 | return class_register(&pcibus_class); |
| 110 | } |
| 111 | postcore_initcall(pcibus_class_init); |
| 112 | |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 113 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
Yinghai Lu | 07eddf3 | 2006-11-29 13:53:10 -0800 | [diff] [blame] | 114 | { |
| 115 | u64 size = mask & maxbase; /* Find the significant bits */ |
| 116 | if (!size) |
| 117 | return 0; |
| 118 | |
| 119 | /* Get the lowest of them to find the decode size, and |
| 120 | from that the extent. */ |
| 121 | size = (size & ~(size-1)) - 1; |
| 122 | |
| 123 | /* base == maxbase can be valid only if the BAR has |
| 124 | already been programmed with all 1s. */ |
| 125 | if (base == maxbase && ((base | size) & mask) != mask) |
| 126 | return 0; |
| 127 | |
| 128 | return size; |
| 129 | } |
| 130 | |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 131 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
Yinghai Lu | 07eddf3 | 2006-11-29 13:53:10 -0800 | [diff] [blame] | 132 | { |
Bjorn Helgaas | 8d6a6a4 | 2011-06-14 13:04:29 -0600 | [diff] [blame] | 133 | u32 mem_type; |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 134 | unsigned long flags; |
Bjorn Helgaas | 8d6a6a4 | 2011-06-14 13:04:29 -0600 | [diff] [blame] | 135 | |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 136 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 137 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
| 138 | flags |= IORESOURCE_IO; |
| 139 | return flags; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 140 | } |
| 141 | |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 142 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
| 143 | flags |= IORESOURCE_MEM; |
| 144 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
| 145 | flags |= IORESOURCE_PREFETCH; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 146 | |
Bjorn Helgaas | 8d6a6a4 | 2011-06-14 13:04:29 -0600 | [diff] [blame] | 147 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
| 148 | switch (mem_type) { |
| 149 | case PCI_BASE_ADDRESS_MEM_TYPE_32: |
| 150 | break; |
| 151 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: |
Bjorn Helgaas | 0ff9514 | 2012-08-23 10:53:08 -0600 | [diff] [blame] | 152 | /* 1M mem BAR treated as 32-bit BAR */ |
Bjorn Helgaas | 8d6a6a4 | 2011-06-14 13:04:29 -0600 | [diff] [blame] | 153 | break; |
| 154 | case PCI_BASE_ADDRESS_MEM_TYPE_64: |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 155 | flags |= IORESOURCE_MEM_64; |
| 156 | break; |
Bjorn Helgaas | 8d6a6a4 | 2011-06-14 13:04:29 -0600 | [diff] [blame] | 157 | default: |
Bjorn Helgaas | 0ff9514 | 2012-08-23 10:53:08 -0600 | [diff] [blame] | 158 | /* mem unknown type treated as 32-bit BAR */ |
Bjorn Helgaas | 8d6a6a4 | 2011-06-14 13:04:29 -0600 | [diff] [blame] | 159 | break; |
| 160 | } |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 161 | return flags; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 162 | } |
| 163 | |
Zoltan Kiss | 808e34e | 2013-08-22 23:19:18 +0100 | [diff] [blame] | 164 | #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
| 165 | |
Yu Zhao | 0b400c7 | 2008-11-22 02:40:40 +0800 | [diff] [blame] | 166 | /** |
| 167 | * pci_read_base - read a PCI BAR |
| 168 | * @dev: the PCI device |
| 169 | * @type: type of the BAR |
| 170 | * @res: resource buffer to be filled in |
| 171 | * @pos: BAR position in the config space |
| 172 | * |
| 173 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 174 | */ |
Yu Zhao | 0b400c7 | 2008-11-22 02:40:40 +0800 | [diff] [blame] | 175 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 176 | struct resource *res, unsigned int pos) |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 177 | { |
| 178 | u32 l, sz, mask; |
Bjorn Helgaas | 23b13bc | 2014-04-14 15:25:54 -0600 | [diff] [blame] | 179 | u64 l64, sz64, mask64; |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 180 | u16 orig_cmd; |
Kevin Hao | cf4d1cf | 2013-05-25 19:36:27 +0800 | [diff] [blame] | 181 | struct pci_bus_region region, inverted_region; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 182 | |
Michael S. Tsirkin | 1ed6743 | 2009-10-29 17:24:59 +0200 | [diff] [blame] | 183 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 184 | |
Bjorn Helgaas | 0ff9514 | 2012-08-23 10:53:08 -0600 | [diff] [blame] | 185 | /* No printks while decoding is disabled! */ |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 186 | if (!dev->mmio_always_on) { |
| 187 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); |
Zoltan Kiss | 808e34e | 2013-08-22 23:19:18 +0100 | [diff] [blame] | 188 | if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { |
| 189 | pci_write_config_word(dev, PCI_COMMAND, |
| 190 | orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); |
| 191 | } |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 192 | } |
| 193 | |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 194 | res->name = pci_name(dev); |
| 195 | |
| 196 | pci_read_config_dword(dev, pos, &l); |
Michael S. Tsirkin | 1ed6743 | 2009-10-29 17:24:59 +0200 | [diff] [blame] | 197 | pci_write_config_dword(dev, pos, l | mask); |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 198 | pci_read_config_dword(dev, pos, &sz); |
| 199 | pci_write_config_dword(dev, pos, l); |
| 200 | |
| 201 | /* |
| 202 | * All bits set in sz means the device isn't working properly. |
Bjorn Helgaas | 45aa23b | 2010-04-22 09:02:43 -0600 | [diff] [blame] | 203 | * If the BAR isn't implemented, all bits must be 0. If it's a |
| 204 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit |
| 205 | * 1 must be clear. |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 206 | */ |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 207 | if (sz == 0xffffffff) |
| 208 | sz = 0; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 209 | |
| 210 | /* |
| 211 | * I don't know how l can have all bits set. Copied from old code. |
| 212 | * Maybe it fixes a bug on some ancient platform. |
| 213 | */ |
| 214 | if (l == 0xffffffff) |
| 215 | l = 0; |
| 216 | |
| 217 | if (type == pci_bar_unknown) { |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 218 | res->flags = decode_bar(dev, l); |
| 219 | res->flags |= IORESOURCE_SIZEALIGN; |
| 220 | if (res->flags & IORESOURCE_IO) { |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 221 | l64 = l & PCI_BASE_ADDRESS_IO_MASK; |
| 222 | sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; |
| 223 | mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 224 | } else { |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 225 | l64 = l & PCI_BASE_ADDRESS_MEM_MASK; |
| 226 | sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; |
| 227 | mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 228 | } |
| 229 | } else { |
Bjorn Helgaas | 7a6d312 | 2016-11-28 17:21:02 -0600 | [diff] [blame] | 230 | if (l & PCI_ROM_ADDRESS_ENABLE) |
| 231 | res->flags |= IORESOURCE_ROM_ENABLE; |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 232 | l64 = l & PCI_ROM_ADDRESS_MASK; |
| 233 | sz64 = sz & PCI_ROM_ADDRESS_MASK; |
| 234 | mask64 = (u32)PCI_ROM_ADDRESS_MASK; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 235 | } |
| 236 | |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 237 | if (res->flags & IORESOURCE_MEM_64) { |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 238 | pci_read_config_dword(dev, pos + 4, &l); |
| 239 | pci_write_config_dword(dev, pos + 4, ~0); |
| 240 | pci_read_config_dword(dev, pos + 4, &sz); |
| 241 | pci_write_config_dword(dev, pos + 4, l); |
| 242 | |
| 243 | l64 |= ((u64)l << 32); |
| 244 | sz64 |= ((u64)sz << 32); |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 245 | mask64 |= ((u64)~0 << 32); |
| 246 | } |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 247 | |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 248 | if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
| 249 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 250 | |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 251 | if (!sz64) |
| 252 | goto fail; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 253 | |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 254 | sz64 = pci_size(l64, sz64, mask64); |
Myron Stowe | 7e79c5f | 2014-10-30 11:54:50 -0600 | [diff] [blame] | 255 | if (!sz64) { |
| 256 | dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", |
| 257 | pos); |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 258 | goto fail; |
Myron Stowe | 7e79c5f | 2014-10-30 11:54:50 -0600 | [diff] [blame] | 259 | } |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 260 | |
| 261 | if (res->flags & IORESOURCE_MEM_64) { |
Yinghai Lu | 3a9ad0b | 2015-05-27 17:23:51 -0700 | [diff] [blame] | 262 | if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) |
| 263 | && sz64 > 0x100000000ULL) { |
Bjorn Helgaas | 23b13bc | 2014-04-14 15:25:54 -0600 | [diff] [blame] | 264 | res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; |
| 265 | res->start = 0; |
| 266 | res->end = 0; |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 267 | dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
| 268 | pos, (unsigned long long)sz64); |
Bjorn Helgaas | 23b13bc | 2014-04-14 15:25:54 -0600 | [diff] [blame] | 269 | goto out; |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 270 | } |
| 271 | |
Yinghai Lu | 3a9ad0b | 2015-05-27 17:23:51 -0700 | [diff] [blame] | 272 | if ((sizeof(pci_bus_addr_t) < 8) && l) { |
Bjorn Helgaas | 31e9dd2 | 2014-04-29 18:37:47 -0600 | [diff] [blame] | 273 | /* Above 32-bit boundary; try to reallocate */ |
Bjorn Helgaas | c83bd90 | 2014-02-26 11:26:00 -0700 | [diff] [blame] | 274 | res->flags |= IORESOURCE_UNSET; |
Bjorn Helgaas | 72dc560 | 2014-04-29 18:42:49 -0600 | [diff] [blame] | 275 | res->start = 0; |
| 276 | res->end = sz64; |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 277 | dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", |
| 278 | pos, (unsigned long long)l64); |
Bjorn Helgaas | 72dc560 | 2014-04-29 18:42:49 -0600 | [diff] [blame] | 279 | goto out; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 280 | } |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 281 | } |
| 282 | |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 283 | region.start = l64; |
| 284 | region.end = l64 + sz64; |
| 285 | |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 286 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
| 287 | pcibios_resource_to_bus(dev->bus, &inverted_region, res); |
Kevin Hao | cf4d1cf | 2013-05-25 19:36:27 +0800 | [diff] [blame] | 288 | |
| 289 | /* |
| 290 | * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is |
| 291 | * the corresponding resource address (the physical address used by |
| 292 | * the CPU. Converting that resource address back to a bus address |
| 293 | * should yield the original BAR value: |
| 294 | * |
| 295 | * resource_to_bus(bus_to_resource(A)) == A |
| 296 | * |
| 297 | * If it doesn't, CPU accesses to "bus_to_resource(A)" will not |
| 298 | * be claimed by the device. |
| 299 | */ |
| 300 | if (inverted_region.start != region.start) { |
Kevin Hao | cf4d1cf | 2013-05-25 19:36:27 +0800 | [diff] [blame] | 301 | res->flags |= IORESOURCE_UNSET; |
Kevin Hao | cf4d1cf | 2013-05-25 19:36:27 +0800 | [diff] [blame] | 302 | res->start = 0; |
Bjorn Helgaas | 26370fc | 2014-04-14 15:26:50 -0600 | [diff] [blame] | 303 | res->end = region.end - region.start; |
Myron Stowe | f795d86 | 2014-10-30 11:54:43 -0600 | [diff] [blame] | 304 | dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", |
| 305 | pos, (unsigned long long)region.start); |
Kevin Hao | cf4d1cf | 2013-05-25 19:36:27 +0800 | [diff] [blame] | 306 | } |
Kevin Hao | 96ddef2 | 2013-05-25 19:36:26 +0800 | [diff] [blame] | 307 | |
Bjorn Helgaas | 0ff9514 | 2012-08-23 10:53:08 -0600 | [diff] [blame] | 308 | goto out; |
| 309 | |
| 310 | |
| 311 | fail: |
| 312 | res->flags = 0; |
| 313 | out: |
Bjorn Helgaas | 31e9dd2 | 2014-04-29 18:37:47 -0600 | [diff] [blame] | 314 | if (res->flags) |
Kevin Hao | 33963e30 | 2013-05-25 19:36:25 +0800 | [diff] [blame] | 315 | dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); |
Bjorn Helgaas | 0ff9514 | 2012-08-23 10:53:08 -0600 | [diff] [blame] | 316 | |
Bjorn Helgaas | 28c6821 | 2011-06-14 13:04:35 -0600 | [diff] [blame] | 317 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
Yinghai Lu | 07eddf3 | 2006-11-29 13:53:10 -0800 | [diff] [blame] | 318 | } |
| 319 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
| 321 | { |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 322 | unsigned int pos, reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | |
Prarit Bhargava | ad67b43 | 2016-05-11 12:27:16 -0400 | [diff] [blame] | 324 | if (dev->non_compliant_bars) |
| 325 | return; |
| 326 | |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 327 | for (pos = 0; pos < howmany; pos++) { |
| 328 | struct resource *res = &dev->resource[pos]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 330 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | } |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | if (rom) { |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 334 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | dev->rom_base_reg = rom; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 336 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
Dan Williams | 92b19ff | 2015-08-10 23:07:06 -0400 | [diff] [blame] | 337 | IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; |
Matthew Wilcox | 6ac665c | 2008-07-28 13:38:59 -0400 | [diff] [blame] | 338 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | } |
| 340 | } |
| 341 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 342 | static void pci_read_bridge_io(struct pci_bus *child) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | { |
| 344 | struct pci_dev *dev = child->self; |
| 345 | u8 io_base_lo, io_limit_lo; |
Bjorn Helgaas | 2b28ae1 | 2012-07-09 13:38:57 -0600 | [diff] [blame] | 346 | unsigned long io_mask, io_granularity, base, limit; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 347 | struct pci_bus_region region; |
Bjorn Helgaas | 2b28ae1 | 2012-07-09 13:38:57 -0600 | [diff] [blame] | 348 | struct resource *res; |
| 349 | |
| 350 | io_mask = PCI_IO_RANGE_MASK; |
| 351 | io_granularity = 0x1000; |
| 352 | if (dev->io_window_1k) { |
| 353 | /* Support 1K I/O space granularity */ |
| 354 | io_mask = PCI_IO_1K_RANGE_MASK; |
| 355 | io_granularity = 0x400; |
| 356 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | res = child->resource[0]; |
| 359 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
| 360 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
Bjorn Helgaas | 2b28ae1 | 2012-07-09 13:38:57 -0600 | [diff] [blame] | 361 | base = (io_base_lo & io_mask) << 8; |
| 362 | limit = (io_limit_lo & io_mask) << 8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | |
| 364 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { |
| 365 | u16 io_base_hi, io_limit_hi; |
Bjorn Helgaas | 8f38eac | 2012-06-19 07:45:44 -0600 | [diff] [blame] | 366 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
| 368 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); |
Bjorn Helgaas | 8f38eac | 2012-06-19 07:45:44 -0600 | [diff] [blame] | 369 | base |= ((unsigned long) io_base_hi << 16); |
| 370 | limit |= ((unsigned long) io_limit_hi << 16); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | } |
| 372 | |
Bjorn Helgaas | 5dde383 | 2012-07-09 13:38:41 -0600 | [diff] [blame] | 373 | if (base <= limit) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 375 | region.start = base; |
Bjorn Helgaas | 2b28ae1 | 2012-07-09 13:38:57 -0600 | [diff] [blame] | 376 | region.end = limit + io_granularity - 1; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 377 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 378 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | } |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 380 | } |
| 381 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 382 | static void pci_read_bridge_mmio(struct pci_bus *child) |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 383 | { |
| 384 | struct pci_dev *dev = child->self; |
| 385 | u16 mem_base_lo, mem_limit_lo; |
| 386 | unsigned long base, limit; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 387 | struct pci_bus_region region; |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 388 | struct resource *res; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | |
| 390 | res = child->resource[1]; |
| 391 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); |
| 392 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); |
Bjorn Helgaas | 8f38eac | 2012-06-19 07:45:44 -0600 | [diff] [blame] | 393 | base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
| 394 | limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; |
Bjorn Helgaas | 5dde383 | 2012-07-09 13:38:41 -0600 | [diff] [blame] | 395 | if (base <= limit) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 397 | region.start = base; |
| 398 | region.end = limit + 0xfffff; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 399 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 400 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | } |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 402 | } |
| 403 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 404 | static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 405 | { |
| 406 | struct pci_dev *dev = child->self; |
| 407 | u16 mem_base_lo, mem_limit_lo; |
Yinghai Lu | 7fc986d | 2014-11-19 14:30:32 -0700 | [diff] [blame] | 408 | u64 base64, limit64; |
Yinghai Lu | 3a9ad0b | 2015-05-27 17:23:51 -0700 | [diff] [blame] | 409 | pci_bus_addr_t base, limit; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 410 | struct pci_bus_region region; |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 411 | struct resource *res; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | |
| 413 | res = child->resource[2]; |
| 414 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); |
| 415 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); |
Yinghai Lu | 7fc986d | 2014-11-19 14:30:32 -0700 | [diff] [blame] | 416 | base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
| 417 | limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 418 | |
| 419 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { |
| 420 | u32 mem_base_hi, mem_limit_hi; |
Bjorn Helgaas | 8f38eac | 2012-06-19 07:45:44 -0600 | [diff] [blame] | 421 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
| 423 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); |
| 424 | |
| 425 | /* |
| 426 | * Some bridges set the base > limit by default, and some |
| 427 | * (broken) BIOSes do not initialize them. If we find |
| 428 | * this, just assume they are not being used. |
| 429 | */ |
| 430 | if (mem_base_hi <= mem_limit_hi) { |
Yinghai Lu | 7fc986d | 2014-11-19 14:30:32 -0700 | [diff] [blame] | 431 | base64 |= (u64) mem_base_hi << 32; |
| 432 | limit64 |= (u64) mem_limit_hi << 32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | } |
| 434 | } |
Yinghai Lu | 7fc986d | 2014-11-19 14:30:32 -0700 | [diff] [blame] | 435 | |
Yinghai Lu | 3a9ad0b | 2015-05-27 17:23:51 -0700 | [diff] [blame] | 436 | base = (pci_bus_addr_t) base64; |
| 437 | limit = (pci_bus_addr_t) limit64; |
Yinghai Lu | 7fc986d | 2014-11-19 14:30:32 -0700 | [diff] [blame] | 438 | |
| 439 | if (base != base64) { |
| 440 | dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", |
| 441 | (unsigned long long) base64); |
| 442 | return; |
| 443 | } |
| 444 | |
Bjorn Helgaas | 5dde383 | 2012-07-09 13:38:41 -0600 | [diff] [blame] | 445 | if (base <= limit) { |
Yinghai Lu | 1f82de1 | 2009-04-23 20:48:32 -0700 | [diff] [blame] | 446 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
| 447 | IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 448 | if (res->flags & PCI_PREF_RANGE_TYPE_64) |
| 449 | res->flags |= IORESOURCE_MEM_64; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 450 | region.start = base; |
| 451 | region.end = limit + 0xfffff; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 452 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 453 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 457 | void pci_read_bridge_bases(struct pci_bus *child) |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 458 | { |
| 459 | struct pci_dev *dev = child->self; |
Bjorn Helgaas | 2fe2abf | 2010-02-23 10:24:36 -0700 | [diff] [blame] | 460 | struct resource *res; |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 461 | int i; |
| 462 | |
| 463 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ |
| 464 | return; |
| 465 | |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 466 | dev_info(&dev->dev, "PCI bridge to %pR%s\n", |
| 467 | &child->busn_res, |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 468 | dev->transparent ? " (subtractive decode)" : ""); |
| 469 | |
Bjorn Helgaas | 2fe2abf | 2010-02-23 10:24:36 -0700 | [diff] [blame] | 470 | pci_bus_remove_resources(child); |
| 471 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) |
| 472 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
| 473 | |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 474 | pci_read_bridge_io(child); |
| 475 | pci_read_bridge_mmio(child); |
| 476 | pci_read_bridge_mmio_pref(child); |
Bjorn Helgaas | 2adf751 | 2010-02-23 10:24:26 -0700 | [diff] [blame] | 477 | |
| 478 | if (dev->transparent) { |
Bjorn Helgaas | 2fe2abf | 2010-02-23 10:24:36 -0700 | [diff] [blame] | 479 | pci_bus_for_each_resource(child->parent, res, i) { |
Bjorn Helgaas | d739a09 | 2014-04-14 16:10:54 -0600 | [diff] [blame] | 480 | if (res && res->flags) { |
Bjorn Helgaas | 2fe2abf | 2010-02-23 10:24:36 -0700 | [diff] [blame] | 481 | pci_bus_add_resource(child, res, |
| 482 | PCI_SUBTRACTIVE_DECODE); |
Bjorn Helgaas | 2adf751 | 2010-02-23 10:24:26 -0700 | [diff] [blame] | 483 | dev_printk(KERN_DEBUG, &dev->dev, |
| 484 | " bridge window %pR (subtractive decode)\n", |
Bjorn Helgaas | 2fe2abf | 2010-02-23 10:24:36 -0700 | [diff] [blame] | 485 | res); |
| 486 | } |
Bjorn Helgaas | 2adf751 | 2010-02-23 10:24:26 -0700 | [diff] [blame] | 487 | } |
| 488 | } |
Bjorn Helgaas | fa27b2d | 2010-02-23 10:24:21 -0700 | [diff] [blame] | 489 | } |
| 490 | |
Catalin Marinas | 670ba0c | 2014-09-29 15:29:26 +0100 | [diff] [blame] | 491 | static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 492 | { |
| 493 | struct pci_bus *b; |
| 494 | |
Eric Sesterhenn | f5afe80 | 2006-02-28 15:34:49 +0100 | [diff] [blame] | 495 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
Bjorn Helgaas | 0501348 | 2013-06-05 14:22:11 -0600 | [diff] [blame] | 496 | if (!b) |
| 497 | return NULL; |
| 498 | |
| 499 | INIT_LIST_HEAD(&b->node); |
| 500 | INIT_LIST_HEAD(&b->children); |
| 501 | INIT_LIST_HEAD(&b->devices); |
| 502 | INIT_LIST_HEAD(&b->slots); |
| 503 | INIT_LIST_HEAD(&b->resources); |
| 504 | b->max_bus_speed = PCI_SPEED_UNKNOWN; |
| 505 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; |
Catalin Marinas | 670ba0c | 2014-09-29 15:29:26 +0100 | [diff] [blame] | 506 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
| 507 | if (parent) |
| 508 | b->domain_nr = parent->domain_nr; |
| 509 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | return b; |
| 511 | } |
| 512 | |
Jiang Liu | 70efde2 | 2013-06-07 16:16:51 -0600 | [diff] [blame] | 513 | static void pci_release_host_bridge_dev(struct device *dev) |
| 514 | { |
| 515 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); |
| 516 | |
| 517 | if (bridge->release_fn) |
| 518 | bridge->release_fn(bridge); |
| 519 | |
| 520 | pci_free_resource_list(&bridge->windows); |
| 521 | |
| 522 | kfree(bridge); |
| 523 | } |
| 524 | |
Thierry Reding | a52d144 | 2016-11-25 11:57:11 +0100 | [diff] [blame] | 525 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 526 | { |
| 527 | struct pci_host_bridge *bridge; |
| 528 | |
Thierry Reding | 5909406 | 2016-11-25 11:57:10 +0100 | [diff] [blame] | 529 | bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); |
Bjorn Helgaas | 0501348 | 2013-06-05 14:22:11 -0600 | [diff] [blame] | 530 | if (!bridge) |
| 531 | return NULL; |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 532 | |
Bjorn Helgaas | 0501348 | 2013-06-05 14:22:11 -0600 | [diff] [blame] | 533 | INIT_LIST_HEAD(&bridge->windows); |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 534 | |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 535 | return bridge; |
| 536 | } |
Thierry Reding | a52d144 | 2016-11-25 11:57:11 +0100 | [diff] [blame] | 537 | EXPORT_SYMBOL(pci_alloc_host_bridge); |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 538 | |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 539 | static const unsigned char pcix_bus_speed[] = { |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 540 | PCI_SPEED_UNKNOWN, /* 0 */ |
| 541 | PCI_SPEED_66MHz_PCIX, /* 1 */ |
| 542 | PCI_SPEED_100MHz_PCIX, /* 2 */ |
| 543 | PCI_SPEED_133MHz_PCIX, /* 3 */ |
| 544 | PCI_SPEED_UNKNOWN, /* 4 */ |
| 545 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ |
| 546 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ |
| 547 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ |
| 548 | PCI_SPEED_UNKNOWN, /* 8 */ |
| 549 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ |
| 550 | PCI_SPEED_100MHz_PCIX_266, /* A */ |
| 551 | PCI_SPEED_133MHz_PCIX_266, /* B */ |
| 552 | PCI_SPEED_UNKNOWN, /* C */ |
| 553 | PCI_SPEED_66MHz_PCIX_533, /* D */ |
| 554 | PCI_SPEED_100MHz_PCIX_533, /* E */ |
| 555 | PCI_SPEED_133MHz_PCIX_533 /* F */ |
| 556 | }; |
| 557 | |
Jacob Keller | 343e51a | 2013-07-31 06:53:16 +0000 | [diff] [blame] | 558 | const unsigned char pcie_link_speed[] = { |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 559 | PCI_SPEED_UNKNOWN, /* 0 */ |
| 560 | PCIE_SPEED_2_5GT, /* 1 */ |
| 561 | PCIE_SPEED_5_0GT, /* 2 */ |
Matthew Wilcox | 9dfd97f | 2009-12-13 08:11:35 -0500 | [diff] [blame] | 562 | PCIE_SPEED_8_0GT, /* 3 */ |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 563 | PCI_SPEED_UNKNOWN, /* 4 */ |
| 564 | PCI_SPEED_UNKNOWN, /* 5 */ |
| 565 | PCI_SPEED_UNKNOWN, /* 6 */ |
| 566 | PCI_SPEED_UNKNOWN, /* 7 */ |
| 567 | PCI_SPEED_UNKNOWN, /* 8 */ |
| 568 | PCI_SPEED_UNKNOWN, /* 9 */ |
| 569 | PCI_SPEED_UNKNOWN, /* A */ |
| 570 | PCI_SPEED_UNKNOWN, /* B */ |
| 571 | PCI_SPEED_UNKNOWN, /* C */ |
| 572 | PCI_SPEED_UNKNOWN, /* D */ |
| 573 | PCI_SPEED_UNKNOWN, /* E */ |
| 574 | PCI_SPEED_UNKNOWN /* F */ |
| 575 | }; |
| 576 | |
| 577 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) |
| 578 | { |
Bjorn Helgaas | 231afea | 2012-12-05 13:51:18 -0700 | [diff] [blame] | 579 | bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 580 | } |
| 581 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); |
| 582 | |
Matthew Wilcox | 45b4cdd5 | 2009-12-13 08:11:34 -0500 | [diff] [blame] | 583 | static unsigned char agp_speeds[] = { |
| 584 | AGP_UNKNOWN, |
| 585 | AGP_1X, |
| 586 | AGP_2X, |
| 587 | AGP_4X, |
| 588 | AGP_8X |
| 589 | }; |
| 590 | |
| 591 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) |
| 592 | { |
| 593 | int index = 0; |
| 594 | |
| 595 | if (agpstat & 4) |
| 596 | index = 3; |
| 597 | else if (agpstat & 2) |
| 598 | index = 2; |
| 599 | else if (agpstat & 1) |
| 600 | index = 1; |
| 601 | else |
| 602 | goto out; |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 603 | |
Matthew Wilcox | 45b4cdd5 | 2009-12-13 08:11:34 -0500 | [diff] [blame] | 604 | if (agp3) { |
| 605 | index += 2; |
| 606 | if (index == 5) |
| 607 | index = 0; |
| 608 | } |
| 609 | |
| 610 | out: |
| 611 | return agp_speeds[index]; |
| 612 | } |
| 613 | |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 614 | static void pci_set_bus_speed(struct pci_bus *bus) |
| 615 | { |
| 616 | struct pci_dev *bridge = bus->self; |
| 617 | int pos; |
| 618 | |
Matthew Wilcox | 45b4cdd5 | 2009-12-13 08:11:34 -0500 | [diff] [blame] | 619 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
| 620 | if (!pos) |
| 621 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); |
| 622 | if (pos) { |
| 623 | u32 agpstat, agpcmd; |
| 624 | |
| 625 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); |
| 626 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); |
| 627 | |
| 628 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); |
| 629 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); |
| 630 | } |
| 631 | |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 632 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
| 633 | if (pos) { |
| 634 | u16 status; |
| 635 | enum pci_bus_speed max; |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 636 | |
Bjorn Helgaas | 7793eea | 2012-12-05 13:51:17 -0700 | [diff] [blame] | 637 | pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, |
| 638 | &status); |
| 639 | |
| 640 | if (status & PCI_X_SSTATUS_533MHZ) { |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 641 | max = PCI_SPEED_133MHz_PCIX_533; |
Bjorn Helgaas | 7793eea | 2012-12-05 13:51:17 -0700 | [diff] [blame] | 642 | } else if (status & PCI_X_SSTATUS_266MHZ) { |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 643 | max = PCI_SPEED_133MHz_PCIX_266; |
Bjorn Helgaas | 7793eea | 2012-12-05 13:51:17 -0700 | [diff] [blame] | 644 | } else if (status & PCI_X_SSTATUS_133MHZ) { |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 645 | if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 646 | max = PCI_SPEED_133MHz_PCIX_ECC; |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 647 | else |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 648 | max = PCI_SPEED_133MHz_PCIX; |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 649 | } else { |
| 650 | max = PCI_SPEED_66MHz_PCIX; |
| 651 | } |
| 652 | |
| 653 | bus->max_bus_speed = max; |
Bjorn Helgaas | 7793eea | 2012-12-05 13:51:17 -0700 | [diff] [blame] | 654 | bus->cur_bus_speed = pcix_bus_speed[ |
| 655 | (status & PCI_X_SSTATUS_FREQ) >> 6]; |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 656 | |
| 657 | return; |
| 658 | } |
| 659 | |
Yijing Wang | fdfe151 | 2013-09-05 15:55:29 +0800 | [diff] [blame] | 660 | if (pci_is_pcie(bridge)) { |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 661 | u32 linkcap; |
| 662 | u16 linksta; |
| 663 | |
Jiang Liu | 59875ae | 2012-07-24 17:20:06 +0800 | [diff] [blame] | 664 | pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
Bjorn Helgaas | 231afea | 2012-12-05 13:51:18 -0700 | [diff] [blame] | 665 | bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 666 | |
Jiang Liu | 59875ae | 2012-07-24 17:20:06 +0800 | [diff] [blame] | 667 | pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 668 | pcie_update_link_speed(bus, linksta); |
| 669 | } |
| 670 | } |
| 671 | |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 672 | static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) |
| 673 | { |
Marc Zyngier | b165e2b | 2015-07-28 14:46:12 +0100 | [diff] [blame] | 674 | struct irq_domain *d; |
| 675 | |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 676 | /* |
| 677 | * Any firmware interface that can resolve the msi_domain |
| 678 | * should be called from here. |
| 679 | */ |
Marc Zyngier | b165e2b | 2015-07-28 14:46:12 +0100 | [diff] [blame] | 680 | d = pci_host_bridge_of_msi_domain(bus); |
Suravee Suthikulpanit | 471036b | 2015-12-10 08:55:27 -0800 | [diff] [blame] | 681 | if (!d) |
| 682 | d = pci_host_bridge_acpi_msi_domain(bus); |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 683 | |
Jake Oshins | 788858e | 2016-02-16 21:56:22 +0000 | [diff] [blame] | 684 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
| 685 | /* |
| 686 | * If no IRQ domain was found via the OF tree, try looking it up |
| 687 | * directly through the fwnode_handle. |
| 688 | */ |
| 689 | if (!d) { |
| 690 | struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); |
| 691 | |
| 692 | if (fwnode) |
| 693 | d = irq_find_matching_fwnode(fwnode, |
| 694 | DOMAIN_BUS_PCI_MSI); |
| 695 | } |
| 696 | #endif |
| 697 | |
Marc Zyngier | b165e2b | 2015-07-28 14:46:12 +0100 | [diff] [blame] | 698 | return d; |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | static void pci_set_bus_msi_domain(struct pci_bus *bus) |
| 702 | { |
| 703 | struct irq_domain *d; |
Alex Williamson | 38ea72b | 2015-09-18 15:08:54 -0600 | [diff] [blame] | 704 | struct pci_bus *b; |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 705 | |
| 706 | /* |
Alex Williamson | 38ea72b | 2015-09-18 15:08:54 -0600 | [diff] [blame] | 707 | * The bus can be a root bus, a subordinate bus, or a virtual bus |
| 708 | * created by an SR-IOV device. Walk up to the first bridge device |
| 709 | * found or derive the domain from the host bridge. |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 710 | */ |
Alex Williamson | 38ea72b | 2015-09-18 15:08:54 -0600 | [diff] [blame] | 711 | for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { |
| 712 | if (b->self) |
| 713 | d = dev_get_msi_domain(&b->self->dev); |
| 714 | } |
| 715 | |
| 716 | if (!d) |
| 717 | d = pci_host_bridge_msi_domain(b); |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 718 | |
| 719 | dev_set_msi_domain(&bus->dev, d); |
| 720 | } |
| 721 | |
Thierry Reding | a52d144 | 2016-11-25 11:57:11 +0100 | [diff] [blame] | 722 | int pci_register_host_bridge(struct pci_host_bridge *bridge) |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 723 | { |
| 724 | struct device *parent = bridge->dev.parent; |
| 725 | struct resource_entry *window, *n; |
| 726 | struct pci_bus *bus, *b; |
| 727 | resource_size_t offset; |
| 728 | LIST_HEAD(resources); |
| 729 | struct resource *res; |
| 730 | char addr[64], *fmt; |
| 731 | const char *name; |
| 732 | int err; |
| 733 | |
| 734 | bus = pci_alloc_bus(NULL); |
| 735 | if (!bus) |
| 736 | return -ENOMEM; |
| 737 | |
| 738 | bridge->bus = bus; |
| 739 | |
| 740 | /* temporarily move resources off the list */ |
| 741 | list_splice_init(&bridge->windows, &resources); |
| 742 | bus->sysdata = bridge->sysdata; |
| 743 | bus->msi = bridge->msi; |
| 744 | bus->ops = bridge->ops; |
| 745 | bus->number = bus->busn_res.start = bridge->busnr; |
| 746 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
| 747 | bus->domain_nr = pci_bus_find_domain_nr(bus, parent); |
| 748 | #endif |
| 749 | |
| 750 | b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); |
| 751 | if (b) { |
| 752 | /* If we already got to this bus through a different bridge, ignore it */ |
| 753 | dev_dbg(&b->dev, "bus already known\n"); |
| 754 | err = -EEXIST; |
| 755 | goto free; |
| 756 | } |
| 757 | |
| 758 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), |
| 759 | bridge->busnr); |
| 760 | |
| 761 | err = pcibios_root_bridge_prepare(bridge); |
| 762 | if (err) |
| 763 | goto free; |
| 764 | |
| 765 | err = device_register(&bridge->dev); |
| 766 | if (err) |
| 767 | put_device(&bridge->dev); |
| 768 | |
| 769 | bus->bridge = get_device(&bridge->dev); |
| 770 | device_enable_async_suspend(bus->bridge); |
| 771 | pci_set_bus_of_node(bus); |
| 772 | pci_set_bus_msi_domain(bus); |
| 773 | |
| 774 | if (!parent) |
| 775 | set_dev_node(bus->bridge, pcibus_to_node(bus)); |
| 776 | |
| 777 | bus->dev.class = &pcibus_class; |
| 778 | bus->dev.parent = bus->bridge; |
| 779 | |
| 780 | dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); |
| 781 | name = dev_name(&bus->dev); |
| 782 | |
| 783 | err = device_register(&bus->dev); |
| 784 | if (err) |
| 785 | goto unregister; |
| 786 | |
| 787 | pcibios_add_bus(bus); |
| 788 | |
| 789 | /* Create legacy_io and legacy_mem files for this bus */ |
| 790 | pci_create_legacy_files(bus); |
| 791 | |
| 792 | if (parent) |
| 793 | dev_info(parent, "PCI host bridge to bus %s\n", name); |
| 794 | else |
| 795 | pr_info("PCI host bridge to bus %s\n", name); |
| 796 | |
| 797 | /* Add initial resources to the bus */ |
| 798 | resource_list_for_each_entry_safe(window, n, &resources) { |
| 799 | list_move_tail(&window->node, &bridge->windows); |
| 800 | offset = window->offset; |
| 801 | res = window->res; |
| 802 | |
| 803 | if (res->flags & IORESOURCE_BUS) |
| 804 | pci_bus_insert_busn_res(bus, bus->number, res->end); |
| 805 | else |
| 806 | pci_bus_add_resource(bus, res, 0); |
| 807 | |
| 808 | if (offset) { |
| 809 | if (resource_type(res) == IORESOURCE_IO) |
| 810 | fmt = " (bus address [%#06llx-%#06llx])"; |
| 811 | else |
| 812 | fmt = " (bus address [%#010llx-%#010llx])"; |
| 813 | |
| 814 | snprintf(addr, sizeof(addr), fmt, |
| 815 | (unsigned long long)(res->start - offset), |
| 816 | (unsigned long long)(res->end - offset)); |
| 817 | } else |
| 818 | addr[0] = '\0'; |
| 819 | |
| 820 | dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); |
| 821 | } |
| 822 | |
| 823 | down_write(&pci_bus_sem); |
| 824 | list_add_tail(&bus->node, &pci_root_buses); |
| 825 | up_write(&pci_bus_sem); |
| 826 | |
| 827 | return 0; |
| 828 | |
| 829 | unregister: |
| 830 | put_device(&bridge->dev); |
| 831 | device_unregister(&bridge->dev); |
| 832 | |
| 833 | free: |
| 834 | kfree(bus); |
| 835 | return err; |
| 836 | } |
Thierry Reding | a52d144 | 2016-11-25 11:57:11 +0100 | [diff] [blame] | 837 | EXPORT_SYMBOL(pci_register_host_bridge); |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 838 | |
Adrian Bunk | cbd4e05 | 2008-04-18 13:53:55 -0700 | [diff] [blame] | 839 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
| 840 | struct pci_dev *bridge, int busnr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 841 | { |
| 842 | struct pci_bus *child; |
| 843 | int i; |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 844 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 845 | |
| 846 | /* |
| 847 | * Allocate a new bus, and inherit stuff from the parent.. |
| 848 | */ |
Catalin Marinas | 670ba0c | 2014-09-29 15:29:26 +0100 | [diff] [blame] | 849 | child = pci_alloc_bus(parent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 850 | if (!child) |
| 851 | return NULL; |
| 852 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 853 | child->parent = parent; |
| 854 | child->ops = parent->ops; |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 855 | child->msi = parent->msi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 856 | child->sysdata = parent->sysdata; |
Michael S. Tsirkin | 6e325a6 | 2006-02-14 18:52:22 +0200 | [diff] [blame] | 857 | child->bus_flags = parent->bus_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | |
Greg Kroah-Hartman | fd7d1ce | 2007-05-22 22:47:54 -0400 | [diff] [blame] | 859 | /* initialize some portions of the bus device, but don't register it |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 860 | * now as the parent is not properly set up yet. |
Greg Kroah-Hartman | fd7d1ce | 2007-05-22 22:47:54 -0400 | [diff] [blame] | 861 | */ |
| 862 | child->dev.class = &pcibus_class; |
Kay Sievers | 1a92713 | 2008-10-30 02:17:49 +0100 | [diff] [blame] | 863 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | |
| 865 | /* |
| 866 | * Set up the primary, secondary and subordinate |
| 867 | * bus numbers. |
| 868 | */ |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 869 | child->number = child->busn_res.start = busnr; |
| 870 | child->primary = parent->busn_res.start; |
| 871 | child->busn_res.end = 0xff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 872 | |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 873 | if (!bridge) { |
| 874 | child->dev.parent = parent->bridge; |
| 875 | goto add_dev; |
| 876 | } |
Yu Zhao | 3789fa8 | 2008-11-22 02:41:07 +0800 | [diff] [blame] | 877 | |
| 878 | child->self = bridge; |
| 879 | child->bridge = get_device(&bridge->dev); |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 880 | child->dev.parent = child->bridge; |
Benjamin Herrenschmidt | 98d9f30c8 | 2011-04-11 11:37:07 +1000 | [diff] [blame] | 881 | pci_set_bus_of_node(child); |
Matthew Wilcox | 9be60ca | 2009-12-13 08:11:33 -0500 | [diff] [blame] | 882 | pci_set_bus_speed(child); |
| 883 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | /* Set up default resource pointers and names.. */ |
Yu Zhao | fde09c6 | 2008-11-22 02:39:32 +0800 | [diff] [blame] | 885 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
| 887 | child->resource[i]->name = child->name; |
| 888 | } |
| 889 | bridge->subordinate = child; |
| 890 | |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 891 | add_dev: |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 892 | pci_set_bus_msi_domain(child); |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 893 | ret = device_register(&child->dev); |
| 894 | WARN_ON(ret < 0); |
| 895 | |
Jiang Liu | 10a9574 | 2013-04-12 05:44:20 +0000 | [diff] [blame] | 896 | pcibios_add_bus(child); |
| 897 | |
Thierry Reding | 057bd2e | 2016-02-09 15:30:47 +0100 | [diff] [blame] | 898 | if (child->ops->add_bus) { |
| 899 | ret = child->ops->add_bus(child); |
| 900 | if (WARN_ON(ret < 0)) |
| 901 | dev_err(&child->dev, "failed to add bus: %d\n", ret); |
| 902 | } |
| 903 | |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 904 | /* Create legacy_io and legacy_mem files for this bus */ |
| 905 | pci_create_legacy_files(child); |
| 906 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 907 | return child; |
| 908 | } |
| 909 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 910 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
| 911 | int busnr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 912 | { |
| 913 | struct pci_bus *child; |
| 914 | |
| 915 | child = pci_alloc_child_bus(parent, dev, busnr); |
Rajesh Shah | e4ea9bb | 2005-04-28 00:25:48 -0700 | [diff] [blame] | 916 | if (child) { |
Zhang Yanmin | d71374d | 2006-06-02 12:35:43 +0800 | [diff] [blame] | 917 | down_write(&pci_bus_sem); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 918 | list_add_tail(&child->node, &parent->children); |
Zhang Yanmin | d71374d | 2006-06-02 12:35:43 +0800 | [diff] [blame] | 919 | up_write(&pci_bus_sem); |
Rajesh Shah | e4ea9bb | 2005-04-28 00:25:48 -0700 | [diff] [blame] | 920 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | return child; |
| 922 | } |
Ryan Desfosses | b7fe943 | 2014-04-25 14:32:25 -0600 | [diff] [blame] | 923 | EXPORT_SYMBOL(pci_add_new_bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | |
Rajat Jain | f3dbd80 | 2014-09-02 16:26:00 -0700 | [diff] [blame] | 925 | static void pci_enable_crs(struct pci_dev *pdev) |
| 926 | { |
| 927 | u16 root_cap = 0; |
| 928 | |
| 929 | /* Enable CRS Software Visibility if supported */ |
| 930 | pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); |
| 931 | if (root_cap & PCI_EXP_RTCAP_CRSVIS) |
| 932 | pcie_capability_set_word(pdev, PCI_EXP_RTCTL, |
| 933 | PCI_EXP_RTCTL_CRSSVE); |
| 934 | } |
| 935 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 936 | /* |
| 937 | * If it's a bridge, configure it and scan the bus behind it. |
| 938 | * For CardBus bridges, we don't scan behind as the devices will |
| 939 | * be handled by the bridge driver itself. |
| 940 | * |
| 941 | * We need to process bridges in two passes -- first we scan those |
| 942 | * already configured by the BIOS and after we are done with all of |
| 943 | * them, we proceed to assigning numbers to the remaining buses in |
| 944 | * order to avoid overlaps between old and new bus numbers. |
| 945 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 946 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 947 | { |
| 948 | struct pci_bus *child; |
| 949 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 950 | u32 buses, i, j = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | u16 bctl; |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 952 | u8 primary, secondary, subordinate; |
Benjamin Herrenschmidt | a1c1989 | 2008-10-21 10:06:29 +1100 | [diff] [blame] | 953 | int broken = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 954 | |
Mika Westerberg | d963f65 | 2016-06-02 11:17:13 +0300 | [diff] [blame] | 955 | /* |
| 956 | * Make sure the bridge is powered on to be able to access config |
| 957 | * space of devices below it. |
| 958 | */ |
| 959 | pm_runtime_get_sync(&dev->dev); |
| 960 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 962 | primary = buses & 0xFF; |
| 963 | secondary = (buses >> 8) & 0xFF; |
| 964 | subordinate = (buses >> 16) & 0xFF; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 966 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
| 967 | secondary, subordinate, pass); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | |
Yinghai Lu | 71f6bd4 | 2012-01-30 12:25:24 +0100 | [diff] [blame] | 969 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
| 970 | dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); |
| 971 | primary = bus->number; |
| 972 | } |
| 973 | |
Benjamin Herrenschmidt | a1c1989 | 2008-10-21 10:06:29 +1100 | [diff] [blame] | 974 | /* Check if setup is sensible at all */ |
| 975 | if (!pass && |
Yinghai Lu | 1965f66 | 2012-09-10 17:19:33 -0700 | [diff] [blame] | 976 | (primary != bus->number || secondary <= bus->number || |
Bjorn Helgaas | 12d8706 | 2014-09-19 11:08:40 -0600 | [diff] [blame] | 977 | secondary > subordinate)) { |
Yinghai Lu | 1965f66 | 2012-09-10 17:19:33 -0700 | [diff] [blame] | 978 | dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", |
| 979 | secondary, subordinate); |
Benjamin Herrenschmidt | a1c1989 | 2008-10-21 10:06:29 +1100 | [diff] [blame] | 980 | broken = 1; |
| 981 | } |
| 982 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | /* Disable MasterAbortMode during probing to avoid reporting |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 984 | of bus errors (in some architectures) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
| 986 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, |
| 987 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
| 988 | |
Rajat Jain | f3dbd80 | 2014-09-02 16:26:00 -0700 | [diff] [blame] | 989 | pci_enable_crs(dev); |
| 990 | |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 991 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
| 992 | !is_cardbus && !broken) { |
| 993 | unsigned int cmax; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | /* |
| 995 | * Bus already configured by firmware, process it in the first |
| 996 | * pass and just note the configuration. |
| 997 | */ |
| 998 | if (pass) |
Ralf Baechle | bbe8f9a | 2006-02-14 16:23:57 +0000 | [diff] [blame] | 999 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1000 | |
| 1001 | /* |
Andreas Noever | 2ed8582 | 2014-01-23 21:59:22 +0100 | [diff] [blame] | 1002 | * The bus might already exist for two reasons: Either we are |
| 1003 | * rescanning the bus or the bus is reachable through more than |
| 1004 | * one bridge. The second case can happen with the i450NX |
| 1005 | * chipset. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1006 | */ |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 1007 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
Alex Chiang | 74710de | 2009-03-20 14:56:10 -0600 | [diff] [blame] | 1008 | if (!child) { |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 1009 | child = pci_add_new_bus(bus, dev, secondary); |
Alex Chiang | 74710de | 2009-03-20 14:56:10 -0600 | [diff] [blame] | 1010 | if (!child) |
| 1011 | goto out; |
Bjorn Helgaas | 99ddd55 | 2010-03-16 15:52:58 -0600 | [diff] [blame] | 1012 | child->primary = primary; |
Yinghai Lu | bc76b73 | 2012-05-17 18:51:13 -0700 | [diff] [blame] | 1013 | pci_bus_insert_busn_res(child, secondary, subordinate); |
Alex Chiang | 74710de | 2009-03-20 14:56:10 -0600 | [diff] [blame] | 1014 | child->bridge_ctl = bctl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1015 | } |
| 1016 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | cmax = pci_scan_child_bus(child); |
Andreas Noever | c95b0bd | 2014-01-23 21:59:27 +0100 | [diff] [blame] | 1018 | if (cmax > subordinate) |
| 1019 | dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", |
| 1020 | subordinate, cmax); |
| 1021 | /* subordinate should equal child->busn_res.end */ |
| 1022 | if (subordinate > max) |
| 1023 | max = subordinate; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1024 | } else { |
| 1025 | /* |
| 1026 | * We need to assign a number to this bus which we always |
| 1027 | * do in the second pass. |
| 1028 | */ |
Ivan Kokshaysky | 12f44f4 | 2005-09-22 21:06:31 -0700 | [diff] [blame] | 1029 | if (!pass) { |
Andreas Noever | 619c8c3 | 2014-01-23 21:59:23 +0100 | [diff] [blame] | 1030 | if (pcibios_assign_all_busses() || broken || is_cardbus) |
Ivan Kokshaysky | 12f44f4 | 2005-09-22 21:06:31 -0700 | [diff] [blame] | 1031 | /* Temporarily disable forwarding of the |
| 1032 | configuration cycles on all bridges in |
| 1033 | this bus segment to avoid possible |
| 1034 | conflicts in the second pass between two |
| 1035 | bridges programmed with overlapping |
| 1036 | bus ranges. */ |
| 1037 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, |
| 1038 | buses & ~0xffffff); |
Ralf Baechle | bbe8f9a | 2006-02-14 16:23:57 +0000 | [diff] [blame] | 1039 | goto out; |
Ivan Kokshaysky | 12f44f4 | 2005-09-22 21:06:31 -0700 | [diff] [blame] | 1040 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1041 | |
| 1042 | /* Clear errors */ |
| 1043 | pci_write_config_word(dev, PCI_STATUS, 0xffff); |
| 1044 | |
Bjorn Helgaas | 7a0b33d | 2014-09-19 10:56:06 -0600 | [diff] [blame] | 1045 | /* Prevent assigning a bus number that already exists. |
| 1046 | * This can happen when a bridge is hot-plugged, so in |
| 1047 | * this case we only re-scan this bus. */ |
Tiejun Chen | b1a98b6 | 2011-06-02 11:02:50 +0800 | [diff] [blame] | 1048 | child = pci_find_bus(pci_domain_nr(bus), max+1); |
| 1049 | if (!child) { |
Andreas Noever | 9a4d7d8 | 2014-01-23 21:59:21 +0100 | [diff] [blame] | 1050 | child = pci_add_new_bus(bus, dev, max+1); |
Tiejun Chen | b1a98b6 | 2011-06-02 11:02:50 +0800 | [diff] [blame] | 1051 | if (!child) |
| 1052 | goto out; |
Bjorn Helgaas | 12d8706 | 2014-09-19 11:08:40 -0600 | [diff] [blame] | 1053 | pci_bus_insert_busn_res(child, max+1, 0xff); |
Tiejun Chen | b1a98b6 | 2011-06-02 11:02:50 +0800 | [diff] [blame] | 1054 | } |
Andreas Noever | 9a4d7d8 | 2014-01-23 21:59:21 +0100 | [diff] [blame] | 1055 | max++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | buses = (buses & 0xff000000) |
| 1057 | | ((unsigned int)(child->primary) << 0) |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1058 | | ((unsigned int)(child->busn_res.start) << 8) |
| 1059 | | ((unsigned int)(child->busn_res.end) << 16); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1060 | |
| 1061 | /* |
| 1062 | * yenta.c forces a secondary latency timer of 176. |
| 1063 | * Copy that behaviour here. |
| 1064 | */ |
| 1065 | if (is_cardbus) { |
| 1066 | buses &= ~0xff000000; |
| 1067 | buses |= CARDBUS_LATENCY_TIMER << 24; |
| 1068 | } |
Jesper Juhl | 7c867c8 | 2011-01-24 21:14:33 +0100 | [diff] [blame] | 1069 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | /* |
| 1071 | * We need to blast all three values with a single write. |
| 1072 | */ |
| 1073 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
| 1074 | |
| 1075 | if (!is_cardbus) { |
Gary Hade | 1194925 | 2007-10-08 16:24:16 -0700 | [diff] [blame] | 1076 | child->bridge_ctl = bctl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1077 | max = pci_scan_child_bus(child); |
| 1078 | } else { |
| 1079 | /* |
| 1080 | * For CardBus bridges, we leave 4 bus numbers |
| 1081 | * as cards with a PCI-to-PCI bridge can be |
| 1082 | * inserted later. |
| 1083 | */ |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 1084 | for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 1085 | struct pci_bus *parent = bus; |
Rajesh Shah | cc57450 | 2005-04-28 00:25:47 -0700 | [diff] [blame] | 1086 | if (pci_find_bus(pci_domain_nr(bus), |
| 1087 | max+i+1)) |
| 1088 | break; |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 1089 | while (parent->parent) { |
| 1090 | if ((!pcibios_assign_all_busses()) && |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1091 | (parent->busn_res.end > max) && |
| 1092 | (parent->busn_res.end <= max+i)) { |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 1093 | j = 1; |
| 1094 | } |
| 1095 | parent = parent->parent; |
| 1096 | } |
| 1097 | if (j) { |
| 1098 | /* |
| 1099 | * Often, there are two cardbus bridges |
| 1100 | * -- try to leave one valid bus number |
| 1101 | * for each one. |
| 1102 | */ |
| 1103 | i /= 2; |
| 1104 | break; |
| 1105 | } |
| 1106 | } |
Rajesh Shah | cc57450 | 2005-04-28 00:25:47 -0700 | [diff] [blame] | 1107 | max += i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1108 | } |
| 1109 | /* |
| 1110 | * Set the subordinate bus number to its real value. |
| 1111 | */ |
Yinghai Lu | bc76b73 | 2012-05-17 18:51:13 -0700 | [diff] [blame] | 1112 | pci_bus_update_busn_res_end(child, max); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1113 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
| 1114 | } |
| 1115 | |
Gary Hade | cb3576f | 2008-02-08 14:00:52 -0800 | [diff] [blame] | 1116 | sprintf(child->name, |
| 1117 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), |
| 1118 | pci_domain_nr(bus), child->number); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | |
Bernhard Kaindl | d55bef51 | 2007-07-30 20:35:13 +0200 | [diff] [blame] | 1120 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 1121 | while (bus->parent) { |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1122 | if ((child->busn_res.end > bus->busn_res.end) || |
| 1123 | (child->number > bus->busn_res.end) || |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 1124 | (child->number < bus->number) || |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1125 | (child->busn_res.end < bus->number)) { |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 1126 | dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n", |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1127 | &child->busn_res, |
| 1128 | (bus->number > child->busn_res.end && |
| 1129 | bus->busn_res.end < child->number) ? |
Joe Perches | a6f29a9 | 2007-11-19 17:48:29 -0800 | [diff] [blame] | 1130 | "wholly" : "partially", |
| 1131 | bus->self->transparent ? " transparent" : "", |
Bjorn Helgaas | 865df57 | 2009-11-04 10:32:57 -0700 | [diff] [blame] | 1132 | dev_name(&bus->dev), |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1133 | &bus->busn_res); |
Dominik Brodowski | 4988794 | 2005-12-08 16:53:12 +0100 | [diff] [blame] | 1134 | } |
| 1135 | bus = bus->parent; |
| 1136 | } |
| 1137 | |
Ralf Baechle | bbe8f9a | 2006-02-14 16:23:57 +0000 | [diff] [blame] | 1138 | out: |
| 1139 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); |
| 1140 | |
Mika Westerberg | d963f65 | 2016-06-02 11:17:13 +0300 | [diff] [blame] | 1141 | pm_runtime_put(&dev->dev); |
| 1142 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | return max; |
| 1144 | } |
Ryan Desfosses | b7fe943 | 2014-04-25 14:32:25 -0600 | [diff] [blame] | 1145 | EXPORT_SYMBOL(pci_scan_bridge); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | |
| 1147 | /* |
| 1148 | * Read interrupt line and base address registers. |
| 1149 | * The architecture-dependent code can tweak these, of course. |
| 1150 | */ |
| 1151 | static void pci_read_irq(struct pci_dev *dev) |
| 1152 | { |
| 1153 | unsigned char irq; |
| 1154 | |
| 1155 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
Kristen Accardi | ffeff78 | 2005-11-02 16:24:32 -0800 | [diff] [blame] | 1156 | dev->pin = irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1157 | if (irq) |
| 1158 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
| 1159 | dev->irq = irq; |
| 1160 | } |
| 1161 | |
Benjamin Herrenschmidt | bb209c8 | 2010-01-26 17:10:03 +0000 | [diff] [blame] | 1162 | void set_pcie_port_type(struct pci_dev *pdev) |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1163 | { |
| 1164 | int pos; |
| 1165 | u16 reg16; |
Yijing Wang | d0751b9 | 2015-05-21 15:05:02 +0800 | [diff] [blame] | 1166 | int type; |
| 1167 | struct pci_dev *parent; |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1168 | |
| 1169 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
| 1170 | if (!pos) |
| 1171 | return; |
Bjorn Helgaas | 51ebfc9 | 2017-01-11 09:11:53 -0600 | [diff] [blame] | 1172 | |
Kenji Kaneshige | 0efea00 | 2009-11-05 12:05:11 +0900 | [diff] [blame] | 1173 | pdev->pcie_cap = pos; |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1174 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
Yijing Wang | 786e228 | 2012-07-24 17:20:02 +0800 | [diff] [blame] | 1175 | pdev->pcie_flags_reg = reg16; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 1176 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); |
| 1177 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; |
Yijing Wang | d0751b9 | 2015-05-21 15:05:02 +0800 | [diff] [blame] | 1178 | |
| 1179 | /* |
Bjorn Helgaas | 51ebfc9 | 2017-01-11 09:11:53 -0600 | [diff] [blame] | 1180 | * A Root Port or a PCI-to-PCIe bridge is always the upstream end |
| 1181 | * of a Link. No PCIe component has two Links. Two Links are |
| 1182 | * connected by a Switch that has a Port on each Link and internal |
| 1183 | * logic to connect the two Ports. |
Yijing Wang | d0751b9 | 2015-05-21 15:05:02 +0800 | [diff] [blame] | 1184 | */ |
| 1185 | type = pci_pcie_type(pdev); |
Bjorn Helgaas | 51ebfc9 | 2017-01-11 09:11:53 -0600 | [diff] [blame] | 1186 | if (type == PCI_EXP_TYPE_ROOT_PORT || |
| 1187 | type == PCI_EXP_TYPE_PCIE_BRIDGE) |
Yijing Wang | d0751b9 | 2015-05-21 15:05:02 +0800 | [diff] [blame] | 1188 | pdev->has_secondary_link = 1; |
| 1189 | else if (type == PCI_EXP_TYPE_UPSTREAM || |
| 1190 | type == PCI_EXP_TYPE_DOWNSTREAM) { |
| 1191 | parent = pci_upstream_bridge(pdev); |
Yijing Wang | b35b1df | 2015-08-17 18:47:58 +0800 | [diff] [blame] | 1192 | |
| 1193 | /* |
| 1194 | * Usually there's an upstream device (Root Port or Switch |
| 1195 | * Downstream Port), but we can't assume one exists. |
| 1196 | */ |
| 1197 | if (parent && !parent->has_secondary_link) |
Yijing Wang | d0751b9 | 2015-05-21 15:05:02 +0800 | [diff] [blame] | 1198 | pdev->has_secondary_link = 1; |
| 1199 | } |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1200 | } |
| 1201 | |
Benjamin Herrenschmidt | bb209c8 | 2010-01-26 17:10:03 +0000 | [diff] [blame] | 1202 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 1203 | { |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 1204 | u32 reg32; |
| 1205 | |
Jiang Liu | 59875ae | 2012-07-24 17:20:06 +0800 | [diff] [blame] | 1206 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 1207 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
| 1208 | pdev->is_hotplug_bridge = 1; |
| 1209 | } |
| 1210 | |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1211 | /** |
Alex Williamson | 78916b0 | 2014-05-05 14:20:51 -0600 | [diff] [blame] | 1212 | * pci_ext_cfg_is_aliased - is ext config space just an alias of std config? |
| 1213 | * @dev: PCI device |
| 1214 | * |
| 1215 | * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that |
| 1216 | * when forwarding a type1 configuration request the bridge must check that |
| 1217 | * the extended register address field is zero. The bridge is not permitted |
| 1218 | * to forward the transactions and must handle it as an Unsupported Request. |
| 1219 | * Some bridges do not follow this rule and simply drop the extended register |
| 1220 | * bits, resulting in the standard config space being aliased, every 256 |
| 1221 | * bytes across the entire configuration space. Test for this condition by |
| 1222 | * comparing the first dword of each potential alias to the vendor/device ID. |
| 1223 | * Known offenders: |
| 1224 | * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) |
| 1225 | * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) |
| 1226 | */ |
| 1227 | static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) |
| 1228 | { |
| 1229 | #ifdef CONFIG_PCI_QUIRKS |
| 1230 | int pos; |
| 1231 | u32 header, tmp; |
| 1232 | |
| 1233 | pci_read_config_dword(dev, PCI_VENDOR_ID, &header); |
| 1234 | |
| 1235 | for (pos = PCI_CFG_SPACE_SIZE; |
| 1236 | pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { |
| 1237 | if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL |
| 1238 | || header != tmp) |
| 1239 | return false; |
| 1240 | } |
| 1241 | |
| 1242 | return true; |
| 1243 | #else |
| 1244 | return false; |
| 1245 | #endif |
| 1246 | } |
| 1247 | |
| 1248 | /** |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1249 | * pci_cfg_space_size - get the configuration space size of the PCI device. |
| 1250 | * @dev: PCI device |
| 1251 | * |
| 1252 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices |
| 1253 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can |
| 1254 | * access it. Maybe we don't have a way to generate extended config space |
| 1255 | * accesses, or the device is behind a reverse Express bridge. So we try |
| 1256 | * reading the dword at 0x100 which must either be 0 or a valid extended |
| 1257 | * capability header. |
| 1258 | */ |
| 1259 | static int pci_cfg_space_size_ext(struct pci_dev *dev) |
| 1260 | { |
| 1261 | u32 status; |
| 1262 | int pos = PCI_CFG_SPACE_SIZE; |
| 1263 | |
| 1264 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
Bjorn Helgaas | 8e5a395 | 2015-12-07 18:21:10 -0600 | [diff] [blame] | 1265 | return PCI_CFG_SPACE_SIZE; |
Alex Williamson | 78916b0 | 2014-05-05 14:20:51 -0600 | [diff] [blame] | 1266 | if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) |
Bjorn Helgaas | 8e5a395 | 2015-12-07 18:21:10 -0600 | [diff] [blame] | 1267 | return PCI_CFG_SPACE_SIZE; |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1268 | |
| 1269 | return PCI_CFG_SPACE_EXP_SIZE; |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1270 | } |
| 1271 | |
| 1272 | int pci_cfg_space_size(struct pci_dev *dev) |
| 1273 | { |
| 1274 | int pos; |
| 1275 | u32 status; |
| 1276 | u16 class; |
| 1277 | |
| 1278 | class = dev->class >> 8; |
| 1279 | if (class == PCI_CLASS_BRIDGE_HOST) |
| 1280 | return pci_cfg_space_size_ext(dev); |
| 1281 | |
Bjorn Helgaas | 8e5a395 | 2015-12-07 18:21:10 -0600 | [diff] [blame] | 1282 | if (pci_is_pcie(dev)) |
| 1283 | return pci_cfg_space_size_ext(dev); |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1284 | |
Bjorn Helgaas | 8e5a395 | 2015-12-07 18:21:10 -0600 | [diff] [blame] | 1285 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 1286 | if (!pos) |
| 1287 | return PCI_CFG_SPACE_SIZE; |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1288 | |
Bjorn Helgaas | 8e5a395 | 2015-12-07 18:21:10 -0600 | [diff] [blame] | 1289 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); |
| 1290 | if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) |
| 1291 | return pci_cfg_space_size_ext(dev); |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1292 | |
Stephen Hemminger | 0b950f0 | 2014-01-10 17:14:48 -0700 | [diff] [blame] | 1293 | return PCI_CFG_SPACE_SIZE; |
| 1294 | } |
| 1295 | |
Bartlomiej Zolnierkiewicz | 01abc2a | 2007-04-23 23:19:36 +0200 | [diff] [blame] | 1296 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
Randy Dunlap | 76e6a1d | 2006-12-29 16:47:29 -0800 | [diff] [blame] | 1297 | |
Guilherme G. Piccoli | e80e7ed | 2015-10-21 12:17:35 -0200 | [diff] [blame] | 1298 | static void pci_msi_setup_pci_dev(struct pci_dev *dev) |
Michael S. Tsirkin | 1851617 | 2015-05-07 09:52:21 -0500 | [diff] [blame] | 1299 | { |
| 1300 | /* |
| 1301 | * Disable the MSI hardware to avoid screaming interrupts |
| 1302 | * during boot. This is the power on reset default so |
| 1303 | * usually this should be a noop. |
| 1304 | */ |
| 1305 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
| 1306 | if (dev->msi_cap) |
| 1307 | pci_msi_set_enable(dev, 0); |
| 1308 | |
| 1309 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
| 1310 | if (dev->msix_cap) |
| 1311 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
| 1312 | } |
| 1313 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1314 | /** |
| 1315 | * pci_setup_device - fill in class and map information of a device |
| 1316 | * @dev: the device structure to fill |
| 1317 | * |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 1318 | * Initialize the device structure with information about the device's |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
| 1320 | * Called at initialisation of the PCI subsystem and by CardBus services. |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1321 | * Returns 0 on success and negative if unknown type of device (not normal, |
| 1322 | * bridge or CardBus). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1323 | */ |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1324 | int pci_setup_device(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | { |
| 1326 | u32 class; |
Bjorn Helgaas | b84106b | 2016-02-25 14:35:57 -0600 | [diff] [blame] | 1327 | u16 cmd; |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1328 | u8 hdr_type; |
Gabe Black | bc577d2 | 2009-10-06 10:45:19 -0500 | [diff] [blame] | 1329 | int pos = 0; |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 1330 | struct pci_bus_region region; |
| 1331 | struct resource *res; |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1332 | |
| 1333 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) |
| 1334 | return -EIO; |
| 1335 | |
| 1336 | dev->sysdata = dev->bus->sysdata; |
| 1337 | dev->dev.parent = dev->bus->bridge; |
| 1338 | dev->dev.bus = &pci_bus_type; |
| 1339 | dev->hdr_type = hdr_type & 0x7f; |
| 1340 | dev->multifunction = !!(hdr_type & 0x80); |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1341 | dev->error_state = pci_channel_io_normal; |
| 1342 | set_pcie_port_type(dev); |
| 1343 | |
Yijing Wang | 017ffe6 | 2015-07-17 17:16:32 +0800 | [diff] [blame] | 1344 | pci_dev_assign_slot(dev); |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1345 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) |
| 1346 | set this higher, assuming the system even supports it. */ |
| 1347 | dev->dma_mask = 0xffffffff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1348 | |
Greg Kroah-Hartman | eebfcfb | 2008-07-02 13:24:49 -0700 | [diff] [blame] | 1349 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
| 1350 | dev->bus->number, PCI_SLOT(dev->devfn), |
| 1351 | PCI_FUNC(dev->devfn)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | |
| 1353 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); |
Auke Kok | b8a3a52 | 2007-06-08 15:46:30 -0700 | [diff] [blame] | 1354 | dev->revision = class & 0xff; |
Yinghai Lu | 2dd8ba9 | 2012-02-19 14:50:12 -0800 | [diff] [blame] | 1355 | dev->class = class >> 8; /* upper 3 bytes */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | |
Yinghai Lu | 2dd8ba9 | 2012-02-19 14:50:12 -0800 | [diff] [blame] | 1357 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", |
| 1358 | dev->vendor, dev->device, dev->hdr_type, dev->class); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1359 | |
Yu Zhao | 853346e | 2009-03-21 22:05:11 +0800 | [diff] [blame] | 1360 | /* need to have dev->class ready */ |
| 1361 | dev->cfg_size = pci_cfg_space_size(dev); |
| 1362 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | /* "Unknown power state" */ |
Daniel Ritz | 3fe9d19 | 2005-08-17 15:32:19 -0700 | [diff] [blame] | 1364 | dev->current_state = PCI_UNKNOWN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1365 | |
| 1366 | /* Early fixups, before probing the BARs */ |
| 1367 | pci_fixup_device(pci_fixup_early, dev); |
Yu Zhao | f79b1b1 | 2009-05-28 00:25:05 +0800 | [diff] [blame] | 1368 | /* device class may be changed after fixup */ |
| 1369 | class = dev->class >> 8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1370 | |
Bjorn Helgaas | b84106b | 2016-02-25 14:35:57 -0600 | [diff] [blame] | 1371 | if (dev->non_compliant_bars) { |
| 1372 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1373 | if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { |
| 1374 | dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); |
| 1375 | cmd &= ~PCI_COMMAND_IO; |
| 1376 | cmd &= ~PCI_COMMAND_MEMORY; |
| 1377 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1378 | } |
| 1379 | } |
| 1380 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1381 | switch (dev->hdr_type) { /* header type */ |
| 1382 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
| 1383 | if (class == PCI_CLASS_BRIDGE_PCI) |
| 1384 | goto bad; |
| 1385 | pci_read_irq(dev); |
| 1386 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
| 1387 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
| 1388 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 1389 | |
| 1390 | /* |
Bjorn Helgaas | 075eb9e | 2014-03-05 14:07:03 -0700 | [diff] [blame] | 1391 | * Do the ugly legacy mode stuff here rather than broken chip |
| 1392 | * quirk code. Legacy mode ATA controllers have fixed |
| 1393 | * addresses. These are not always echoed in BAR0-3, and |
| 1394 | * BAR0-3 in a few cases contain junk! |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 1395 | */ |
| 1396 | if (class == PCI_CLASS_STORAGE_IDE) { |
| 1397 | u8 progif; |
| 1398 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); |
| 1399 | if ((progif & 1) == 0) { |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 1400 | region.start = 0x1F0; |
| 1401 | region.end = 0x1F7; |
| 1402 | res = &dev->resource[0]; |
| 1403 | res->flags = LEGACY_IO_RESOURCE; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 1404 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | 075eb9e | 2014-03-05 14:07:03 -0700 | [diff] [blame] | 1405 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", |
| 1406 | res); |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 1407 | region.start = 0x3F6; |
| 1408 | region.end = 0x3F6; |
| 1409 | res = &dev->resource[1]; |
| 1410 | res->flags = LEGACY_IO_RESOURCE; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 1411 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | 075eb9e | 2014-03-05 14:07:03 -0700 | [diff] [blame] | 1412 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", |
| 1413 | res); |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 1414 | } |
| 1415 | if ((progif & 4) == 0) { |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 1416 | region.start = 0x170; |
| 1417 | region.end = 0x177; |
| 1418 | res = &dev->resource[2]; |
| 1419 | res->flags = LEGACY_IO_RESOURCE; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 1420 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | 075eb9e | 2014-03-05 14:07:03 -0700 | [diff] [blame] | 1421 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", |
| 1422 | res); |
Bjorn Helgaas | 5bfa14e | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 1423 | region.start = 0x376; |
| 1424 | region.end = 0x376; |
| 1425 | res = &dev->resource[3]; |
| 1426 | res->flags = LEGACY_IO_RESOURCE; |
Yinghai Lu | fc27985 | 2013-12-09 22:54:40 -0800 | [diff] [blame] | 1427 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
Bjorn Helgaas | 075eb9e | 2014-03-05 14:07:03 -0700 | [diff] [blame] | 1428 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", |
| 1429 | res); |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 1430 | } |
| 1431 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1432 | break; |
| 1433 | |
| 1434 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
| 1435 | if (class != PCI_CLASS_BRIDGE_PCI) |
| 1436 | goto bad; |
| 1437 | /* The PCI-to-PCI bridge spec requires that subtractive |
| 1438 | decoding (i.e. transparent) bridge must have programming |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 1439 | interface code of 0x01. */ |
Kristen Accardi | 3efd273 | 2005-11-02 16:55:49 -0800 | [diff] [blame] | 1440 | pci_read_irq(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1441 | dev->transparent = ((dev->class & 0xff) == 1); |
| 1442 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 1443 | set_pcie_hotplug_bridge(dev); |
Gabe Black | bc577d2 | 2009-10-06 10:45:19 -0500 | [diff] [blame] | 1444 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
| 1445 | if (pos) { |
| 1446 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); |
| 1447 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); |
| 1448 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1449 | break; |
| 1450 | |
| 1451 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
| 1452 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
| 1453 | goto bad; |
| 1454 | pci_read_irq(dev); |
| 1455 | pci_read_bases(dev, 1, 0); |
| 1456 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
| 1457 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); |
| 1458 | break; |
| 1459 | |
| 1460 | default: /* unknown header */ |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 1461 | dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", |
| 1462 | dev->hdr_type); |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1463 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1464 | |
| 1465 | bad: |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 1466 | dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", |
| 1467 | dev->class, dev->hdr_type); |
Bjorn Helgaas | 2b4aed1 | 2015-06-19 16:20:58 -0500 | [diff] [blame] | 1468 | dev->class = PCI_CLASS_NOT_DEFINED << 8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1469 | } |
| 1470 | |
| 1471 | /* We found a fine healthy device, go go go... */ |
| 1472 | return 0; |
| 1473 | } |
| 1474 | |
Bjorn Helgaas | 9dae3a9 | 2015-08-20 16:08:27 -0500 | [diff] [blame] | 1475 | static void pci_configure_mps(struct pci_dev *dev) |
| 1476 | { |
| 1477 | struct pci_dev *bridge = pci_upstream_bridge(dev); |
Keith Busch | 27d868b | 2015-08-24 08:48:16 -0500 | [diff] [blame] | 1478 | int mps, p_mps, rc; |
Bjorn Helgaas | 9dae3a9 | 2015-08-20 16:08:27 -0500 | [diff] [blame] | 1479 | |
| 1480 | if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) |
| 1481 | return; |
| 1482 | |
| 1483 | mps = pcie_get_mps(dev); |
| 1484 | p_mps = pcie_get_mps(bridge); |
| 1485 | |
| 1486 | if (mps == p_mps) |
| 1487 | return; |
| 1488 | |
| 1489 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { |
| 1490 | dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", |
| 1491 | mps, pci_name(bridge), p_mps); |
| 1492 | return; |
| 1493 | } |
Keith Busch | 27d868b | 2015-08-24 08:48:16 -0500 | [diff] [blame] | 1494 | |
| 1495 | /* |
| 1496 | * Fancier MPS configuration is done later by |
| 1497 | * pcie_bus_configure_settings() |
| 1498 | */ |
| 1499 | if (pcie_bus_config != PCIE_BUS_DEFAULT) |
| 1500 | return; |
| 1501 | |
| 1502 | rc = pcie_set_mps(dev, p_mps); |
| 1503 | if (rc) { |
| 1504 | dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", |
| 1505 | p_mps); |
| 1506 | return; |
| 1507 | } |
| 1508 | |
| 1509 | dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n", |
| 1510 | p_mps, mps, 128 << dev->pcie_mpss); |
Bjorn Helgaas | 9dae3a9 | 2015-08-20 16:08:27 -0500 | [diff] [blame] | 1511 | } |
| 1512 | |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1513 | static struct hpp_type0 pci_default_type0 = { |
| 1514 | .revision = 1, |
| 1515 | .cache_line_size = 8, |
| 1516 | .latency_timer = 0x40, |
| 1517 | .enable_serr = 0, |
| 1518 | .enable_perr = 0, |
| 1519 | }; |
| 1520 | |
| 1521 | static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) |
| 1522 | { |
| 1523 | u16 pci_cmd, pci_bctl; |
| 1524 | |
Bjorn Helgaas | c6285fc | 2014-08-29 18:10:19 -0600 | [diff] [blame] | 1525 | if (!hpp) |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1526 | hpp = &pci_default_type0; |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1527 | |
| 1528 | if (hpp->revision > 1) { |
| 1529 | dev_warn(&dev->dev, |
| 1530 | "PCI settings rev %d not supported; using defaults\n", |
| 1531 | hpp->revision); |
| 1532 | hpp = &pci_default_type0; |
| 1533 | } |
| 1534 | |
| 1535 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); |
| 1536 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); |
| 1537 | pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); |
| 1538 | if (hpp->enable_serr) |
| 1539 | pci_cmd |= PCI_COMMAND_SERR; |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1540 | if (hpp->enable_perr) |
| 1541 | pci_cmd |= PCI_COMMAND_PARITY; |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1542 | pci_write_config_word(dev, PCI_COMMAND, pci_cmd); |
| 1543 | |
| 1544 | /* Program bridge control value */ |
| 1545 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
| 1546 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, |
| 1547 | hpp->latency_timer); |
| 1548 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); |
| 1549 | if (hpp->enable_serr) |
| 1550 | pci_bctl |= PCI_BRIDGE_CTL_SERR; |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1551 | if (hpp->enable_perr) |
| 1552 | pci_bctl |= PCI_BRIDGE_CTL_PARITY; |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1553 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); |
| 1554 | } |
| 1555 | } |
| 1556 | |
| 1557 | static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) |
| 1558 | { |
| 1559 | if (hpp) |
| 1560 | dev_warn(&dev->dev, "PCI-X settings not supported\n"); |
| 1561 | } |
| 1562 | |
Johannes Thumshirn | e42010d | 2016-11-23 10:56:28 -0600 | [diff] [blame] | 1563 | static bool pcie_root_rcb_set(struct pci_dev *dev) |
| 1564 | { |
| 1565 | struct pci_dev *rp = pcie_find_root_port(dev); |
| 1566 | u16 lnkctl; |
| 1567 | |
| 1568 | if (!rp) |
| 1569 | return false; |
| 1570 | |
| 1571 | pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); |
| 1572 | if (lnkctl & PCI_EXP_LNKCTL_RCB) |
| 1573 | return true; |
| 1574 | |
| 1575 | return false; |
| 1576 | } |
| 1577 | |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1578 | static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) |
| 1579 | { |
| 1580 | int pos; |
| 1581 | u32 reg32; |
| 1582 | |
| 1583 | if (!hpp) |
| 1584 | return; |
| 1585 | |
| 1586 | if (hpp->revision > 1) { |
| 1587 | dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", |
| 1588 | hpp->revision); |
| 1589 | return; |
| 1590 | } |
| 1591 | |
Bjorn Helgaas | 302328c | 2014-09-03 13:26:29 -0600 | [diff] [blame] | 1592 | /* |
| 1593 | * Don't allow _HPX to change MPS or MRRS settings. We manage |
| 1594 | * those to make sure they're consistent with the rest of the |
| 1595 | * platform. |
| 1596 | */ |
| 1597 | hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | |
| 1598 | PCI_EXP_DEVCTL_READRQ; |
| 1599 | hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | |
| 1600 | PCI_EXP_DEVCTL_READRQ); |
| 1601 | |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1602 | /* Initialize Device Control Register */ |
| 1603 | pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
| 1604 | ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); |
| 1605 | |
| 1606 | /* Initialize Link Control Register */ |
Johannes Thumshirn | e42010d | 2016-11-23 10:56:28 -0600 | [diff] [blame] | 1607 | if (pcie_cap_has_lnkctl(dev)) { |
| 1608 | |
| 1609 | /* |
| 1610 | * If the Root Port supports Read Completion Boundary of |
| 1611 | * 128, set RCB to 128. Otherwise, clear it. |
| 1612 | */ |
| 1613 | hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB; |
| 1614 | hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB; |
| 1615 | if (pcie_root_rcb_set(dev)) |
| 1616 | hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB; |
| 1617 | |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1618 | pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, |
| 1619 | ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); |
Johannes Thumshirn | e42010d | 2016-11-23 10:56:28 -0600 | [diff] [blame] | 1620 | } |
Bjorn Helgaas | 589fcc2 | 2014-09-12 20:02:00 -0600 | [diff] [blame] | 1621 | |
| 1622 | /* Find Advanced Error Reporting Enhanced Capability */ |
| 1623 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
| 1624 | if (!pos) |
| 1625 | return; |
| 1626 | |
| 1627 | /* Initialize Uncorrectable Error Mask Register */ |
| 1628 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); |
| 1629 | reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; |
| 1630 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); |
| 1631 | |
| 1632 | /* Initialize Uncorrectable Error Severity Register */ |
| 1633 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); |
| 1634 | reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; |
| 1635 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); |
| 1636 | |
| 1637 | /* Initialize Correctable Error Mask Register */ |
| 1638 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); |
| 1639 | reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; |
| 1640 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); |
| 1641 | |
| 1642 | /* Initialize Advanced Error Capabilities and Control Register */ |
| 1643 | pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); |
| 1644 | reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; |
| 1645 | pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); |
| 1646 | |
| 1647 | /* |
| 1648 | * FIXME: The following two registers are not supported yet. |
| 1649 | * |
| 1650 | * o Secondary Uncorrectable Error Severity Register |
| 1651 | * o Secondary Uncorrectable Error Mask Register |
| 1652 | */ |
| 1653 | } |
| 1654 | |
Bjorn Helgaas | 6cd3364 | 2014-08-27 14:29:47 -0600 | [diff] [blame] | 1655 | static void pci_configure_device(struct pci_dev *dev) |
| 1656 | { |
| 1657 | struct hotplug_params hpp; |
| 1658 | int ret; |
| 1659 | |
Bjorn Helgaas | 9dae3a9 | 2015-08-20 16:08:27 -0500 | [diff] [blame] | 1660 | pci_configure_mps(dev); |
| 1661 | |
Bjorn Helgaas | 6cd3364 | 2014-08-27 14:29:47 -0600 | [diff] [blame] | 1662 | memset(&hpp, 0, sizeof(hpp)); |
| 1663 | ret = pci_get_hp_params(dev, &hpp); |
| 1664 | if (ret) |
| 1665 | return; |
| 1666 | |
| 1667 | program_hpp_type2(dev, hpp.t2); |
| 1668 | program_hpp_type1(dev, hpp.t1); |
| 1669 | program_hpp_type0(dev, hpp.t0); |
| 1670 | } |
| 1671 | |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1672 | static void pci_release_capabilities(struct pci_dev *dev) |
| 1673 | { |
| 1674 | pci_vpd_release(dev); |
Yu Zhao | d1b054d | 2009-03-20 11:25:11 +0800 | [diff] [blame] | 1675 | pci_iov_release(dev); |
Yinghai Lu | f796841 | 2012-02-11 00:18:30 -0800 | [diff] [blame] | 1676 | pci_free_cap_save_buffers(dev); |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1677 | } |
| 1678 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1679 | /** |
| 1680 | * pci_release_dev - free a pci device structure when all users of it are finished. |
| 1681 | * @dev: device that's been disconnected |
| 1682 | * |
| 1683 | * Will be called only by the device core when all users of this pci device are |
| 1684 | * done. |
| 1685 | */ |
| 1686 | static void pci_release_dev(struct device *dev) |
| 1687 | { |
Rafael J. Wysocki | 0448009 | 2014-02-01 15:38:29 +0100 | [diff] [blame] | 1688 | struct pci_dev *pci_dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1689 | |
Rafael J. Wysocki | 0448009 | 2014-02-01 15:38:29 +0100 | [diff] [blame] | 1690 | pci_dev = to_pci_dev(dev); |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1691 | pci_release_capabilities(pci_dev); |
Benjamin Herrenschmidt | 98d9f30c8 | 2011-04-11 11:37:07 +1000 | [diff] [blame] | 1692 | pci_release_of_node(pci_dev); |
Sebastian Ott | 6ae32c5 | 2013-06-04 19:18:14 +0200 | [diff] [blame] | 1693 | pcibios_release_device(pci_dev); |
Gu Zheng | 8b1fce0 | 2013-05-25 21:48:31 +0800 | [diff] [blame] | 1694 | pci_bus_put(pci_dev->bus); |
Alex Williamson | 782a985 | 2014-05-20 08:53:21 -0600 | [diff] [blame] | 1695 | kfree(pci_dev->driver_override); |
Jacek Lawrynowicz | 338c314 | 2016-03-03 15:38:02 +0100 | [diff] [blame] | 1696 | kfree(pci_dev->dma_alias_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1697 | kfree(pci_dev); |
| 1698 | } |
| 1699 | |
Gu Zheng | 3c6e6ae | 2013-05-25 21:48:30 +0800 | [diff] [blame] | 1700 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
Michael Ellerman | 6589121 | 2007-04-05 17:19:08 +1000 | [diff] [blame] | 1701 | { |
| 1702 | struct pci_dev *dev; |
| 1703 | |
| 1704 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); |
| 1705 | if (!dev) |
| 1706 | return NULL; |
| 1707 | |
Michael Ellerman | 6589121 | 2007-04-05 17:19:08 +1000 | [diff] [blame] | 1708 | INIT_LIST_HEAD(&dev->bus_list); |
Brian King | 88e7b16 | 2013-04-08 03:05:07 +0000 | [diff] [blame] | 1709 | dev->dev.type = &pci_dev_type; |
Gu Zheng | 3c6e6ae | 2013-05-25 21:48:30 +0800 | [diff] [blame] | 1710 | dev->bus = pci_bus_get(bus); |
Michael Ellerman | 6589121 | 2007-04-05 17:19:08 +1000 | [diff] [blame] | 1711 | |
| 1712 | return dev; |
| 1713 | } |
Gu Zheng | 3c6e6ae | 2013-05-25 21:48:30 +0800 | [diff] [blame] | 1714 | EXPORT_SYMBOL(pci_alloc_dev); |
| 1715 | |
Yinghai Lu | efdc87d | 2012-01-27 10:55:10 -0800 | [diff] [blame] | 1716 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 1717 | int crs_timeout) |
Yinghai Lu | efdc87d | 2012-01-27 10:55:10 -0800 | [diff] [blame] | 1718 | { |
| 1719 | int delay = 1; |
| 1720 | |
| 1721 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
| 1722 | return false; |
| 1723 | |
| 1724 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
| 1725 | if (*l == 0xffffffff || *l == 0x00000000 || |
| 1726 | *l == 0x0000ffff || *l == 0xffff0000) |
| 1727 | return false; |
| 1728 | |
Rajat Jain | 89665a6 | 2014-09-08 14:19:49 -0700 | [diff] [blame] | 1729 | /* |
| 1730 | * Configuration Request Retry Status. Some root ports return the |
| 1731 | * actual device ID instead of the synthetic ID (0xFFFF) required |
| 1732 | * by the PCIe spec. Ignore the device ID and only check for |
| 1733 | * (vendor id == 1). |
| 1734 | */ |
| 1735 | while ((*l & 0xffff) == 0x0001) { |
Yinghai Lu | efdc87d | 2012-01-27 10:55:10 -0800 | [diff] [blame] | 1736 | if (!crs_timeout) |
| 1737 | return false; |
| 1738 | |
| 1739 | msleep(delay); |
| 1740 | delay *= 2; |
| 1741 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
| 1742 | return false; |
| 1743 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
| 1744 | if (delay > crs_timeout) { |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 1745 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n", |
| 1746 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), |
| 1747 | PCI_FUNC(devfn)); |
Yinghai Lu | efdc87d | 2012-01-27 10:55:10 -0800 | [diff] [blame] | 1748 | return false; |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | return true; |
| 1753 | } |
| 1754 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); |
| 1755 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1756 | /* |
| 1757 | * Read the config data for a PCI device, sanity-check it |
| 1758 | * and fill in the dev structure... |
| 1759 | */ |
Adrian Bunk | 7f7b5de | 2008-04-18 13:53:55 -0700 | [diff] [blame] | 1760 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1761 | { |
| 1762 | struct pci_dev *dev; |
| 1763 | u32 l; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1764 | |
Yinghai Lu | efdc87d | 2012-01-27 10:55:10 -0800 | [diff] [blame] | 1765 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1766 | return NULL; |
| 1767 | |
Gu Zheng | 8b1fce0 | 2013-05-25 21:48:31 +0800 | [diff] [blame] | 1768 | dev = pci_alloc_dev(bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1769 | if (!dev) |
| 1770 | return NULL; |
| 1771 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | dev->devfn = devfn; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1773 | dev->vendor = l & 0xffff; |
| 1774 | dev->device = (l >> 16) & 0xffff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1775 | |
Benjamin Herrenschmidt | 98d9f30c8 | 2011-04-11 11:37:07 +1000 | [diff] [blame] | 1776 | pci_set_of_node(dev); |
| 1777 | |
Yu Zhao | 480b93b | 2009-03-20 11:25:14 +0800 | [diff] [blame] | 1778 | if (pci_setup_device(dev)) { |
Gu Zheng | 8b1fce0 | 2013-05-25 21:48:31 +0800 | [diff] [blame] | 1779 | pci_bus_put(dev->bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1780 | kfree(dev); |
| 1781 | return NULL; |
| 1782 | } |
Paul Mackerras | cdb9b9f | 2005-09-06 09:31:03 +1000 | [diff] [blame] | 1783 | |
| 1784 | return dev; |
| 1785 | } |
| 1786 | |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1787 | static void pci_init_capabilities(struct pci_dev *dev) |
| 1788 | { |
Sean O. Stalley | 938174e | 2015-10-29 17:35:39 -0500 | [diff] [blame] | 1789 | /* Enhanced Allocation */ |
| 1790 | pci_ea_init(dev); |
| 1791 | |
Guilherme G. Piccoli | e80e7ed | 2015-10-21 12:17:35 -0200 | [diff] [blame] | 1792 | /* Setup MSI caps & disable MSI/MSI-X interrupts */ |
| 1793 | pci_msi_setup_pci_dev(dev); |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1794 | |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 1795 | /* Buffers for saving PCIe and PCI-X capabilities */ |
| 1796 | pci_allocate_cap_save_buffers(dev); |
| 1797 | |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1798 | /* Power Management */ |
| 1799 | pci_pm_init(dev); |
| 1800 | |
| 1801 | /* Vital Product Data */ |
Bjorn Helgaas | f1cd93f | 2016-02-22 13:58:37 -0600 | [diff] [blame] | 1802 | pci_vpd_init(dev); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1803 | |
| 1804 | /* Alternative Routing-ID Forwarding */ |
Yijing Wang | 31ab247 | 2013-01-15 11:12:17 +0800 | [diff] [blame] | 1805 | pci_configure_ari(dev); |
Yu Zhao | d1b054d | 2009-03-20 11:25:11 +0800 | [diff] [blame] | 1806 | |
| 1807 | /* Single Root I/O Virtualization */ |
| 1808 | pci_iov_init(dev); |
Allen Kay | ae21ee6 | 2009-10-07 10:27:17 -0700 | [diff] [blame] | 1809 | |
Bjorn Helgaas | edc90fe | 2015-07-17 15:05:46 -0500 | [diff] [blame] | 1810 | /* Address Translation Services */ |
| 1811 | pci_ats_init(dev); |
| 1812 | |
Allen Kay | ae21ee6 | 2009-10-07 10:27:17 -0700 | [diff] [blame] | 1813 | /* Enable ACS P2P upstream forwarding */ |
Chris Wright | 5d990b6 | 2009-12-04 12:15:21 -0800 | [diff] [blame] | 1814 | pci_enable_acs(dev); |
Taku Izumi | b07461a | 2015-09-17 10:09:37 -0500 | [diff] [blame] | 1815 | |
Jonathan Yong | 9bb04a0 | 2016-06-11 14:13:38 -0500 | [diff] [blame] | 1816 | /* Precision Time Measurement */ |
| 1817 | pci_ptm_init(dev); |
Bjorn Helgaas | 4dc2db0 | 2016-10-03 09:42:57 -0500 | [diff] [blame] | 1818 | |
Keith Busch | 66b8080 | 2016-09-27 16:23:34 -0400 | [diff] [blame] | 1819 | /* Advanced Error Reporting */ |
| 1820 | pci_aer_init(dev); |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1821 | } |
| 1822 | |
Marc Zyngier | 098259e | 2015-10-02 10:19:32 +0100 | [diff] [blame] | 1823 | /* |
| 1824 | * This is the equivalent of pci_host_bridge_msi_domain that acts on |
| 1825 | * devices. Firmware interfaces that can select the MSI domain on a |
| 1826 | * per-device basis should be called from here. |
| 1827 | */ |
| 1828 | static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) |
| 1829 | { |
| 1830 | struct irq_domain *d; |
| 1831 | |
| 1832 | /* |
| 1833 | * If a domain has been set through the pcibios_add_device |
| 1834 | * callback, then this is the one (platform code knows best). |
| 1835 | */ |
| 1836 | d = dev_get_msi_domain(&dev->dev); |
| 1837 | if (d) |
| 1838 | return d; |
| 1839 | |
Marc Zyngier | 54fa97e | 2015-10-02 14:43:06 +0100 | [diff] [blame] | 1840 | /* |
| 1841 | * Let's see if we have a firmware interface able to provide |
| 1842 | * the domain. |
| 1843 | */ |
| 1844 | d = pci_msi_get_device_domain(dev); |
| 1845 | if (d) |
| 1846 | return d; |
| 1847 | |
Marc Zyngier | 098259e | 2015-10-02 10:19:32 +0100 | [diff] [blame] | 1848 | return NULL; |
| 1849 | } |
| 1850 | |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 1851 | static void pci_set_msi_domain(struct pci_dev *dev) |
| 1852 | { |
Marc Zyngier | 098259e | 2015-10-02 10:19:32 +0100 | [diff] [blame] | 1853 | struct irq_domain *d; |
| 1854 | |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 1855 | /* |
Marc Zyngier | 098259e | 2015-10-02 10:19:32 +0100 | [diff] [blame] | 1856 | * If the platform or firmware interfaces cannot supply a |
| 1857 | * device-specific MSI domain, then inherit the default domain |
| 1858 | * from the host bridge itself. |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 1859 | */ |
Marc Zyngier | 098259e | 2015-10-02 10:19:32 +0100 | [diff] [blame] | 1860 | d = pci_dev_msi_domain(dev); |
| 1861 | if (!d) |
| 1862 | d = dev_get_msi_domain(&dev->bus->dev); |
| 1863 | |
| 1864 | dev_set_msi_domain(&dev->dev, d); |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 1865 | } |
| 1866 | |
Suthikulpanit, Suravee | 5023071 | 2015-10-28 15:50:53 -0700 | [diff] [blame] | 1867 | /** |
| 1868 | * pci_dma_configure - Setup DMA configuration |
| 1869 | * @dev: ptr to pci_dev struct of the PCI device |
| 1870 | * |
| 1871 | * Function to update PCI devices's DMA configuration using the same |
Suthikulpanit, Suravee | 29dbe1f | 2015-10-28 15:50:54 -0700 | [diff] [blame] | 1872 | * info from the OF node or ACPI node of host bridge's parent (if any). |
Suthikulpanit, Suravee | 5023071 | 2015-10-28 15:50:53 -0700 | [diff] [blame] | 1873 | */ |
| 1874 | static void pci_dma_configure(struct pci_dev *dev) |
| 1875 | { |
| 1876 | struct device *bridge = pci_get_host_bridge_device(dev); |
| 1877 | |
Suravee Suthikulpanit | 768acd6 | 2015-11-18 16:49:52 -0800 | [diff] [blame] | 1878 | if (IS_ENABLED(CONFIG_OF) && |
| 1879 | bridge->parent && bridge->parent->of_node) { |
Suthikulpanit, Suravee | 5023071 | 2015-10-28 15:50:53 -0700 | [diff] [blame] | 1880 | of_dma_configure(&dev->dev, bridge->parent->of_node); |
Suthikulpanit, Suravee | 29dbe1f | 2015-10-28 15:50:54 -0700 | [diff] [blame] | 1881 | } else if (has_acpi_companion(bridge)) { |
| 1882 | struct acpi_device *adev = to_acpi_device_node(bridge->fwnode); |
| 1883 | enum dev_dma_attr attr = acpi_get_dma_attr(adev); |
| 1884 | |
| 1885 | if (attr == DEV_DMA_NOT_SUPPORTED) |
| 1886 | dev_warn(&dev->dev, "DMA not supported.\n"); |
| 1887 | else |
Lorenzo Pieralisi | d760a1b | 2016-11-21 10:01:39 +0000 | [diff] [blame] | 1888 | acpi_dma_configure(&dev->dev, attr); |
Suthikulpanit, Suravee | 5023071 | 2015-10-28 15:50:53 -0700 | [diff] [blame] | 1889 | } |
| 1890 | |
| 1891 | pci_put_host_bridge_device(bridge); |
| 1892 | } |
| 1893 | |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 1894 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
Paul Mackerras | cdb9b9f | 2005-09-06 09:31:03 +1000 | [diff] [blame] | 1895 | { |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 1896 | int ret; |
| 1897 | |
Bjorn Helgaas | 6cd3364 | 2014-08-27 14:29:47 -0600 | [diff] [blame] | 1898 | pci_configure_device(dev); |
| 1899 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1900 | device_initialize(&dev->dev); |
| 1901 | dev->dev.release = pci_release_dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1902 | |
Yinghai Lu | 7629d19 | 2013-01-21 13:20:44 -0800 | [diff] [blame] | 1903 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1904 | dev->dev.dma_mask = &dev->dma_mask; |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 1905 | dev->dev.dma_parms = &dev->dma_parms; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1906 | dev->dev.coherent_dma_mask = 0xffffffffull; |
Suthikulpanit, Suravee | 5023071 | 2015-10-28 15:50:53 -0700 | [diff] [blame] | 1907 | pci_dma_configure(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1908 | |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 1909 | pci_set_dma_max_seg_size(dev, 65536); |
FUJITA Tomonori | 59fc67d | 2008-02-04 22:28:14 -0800 | [diff] [blame] | 1910 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 1911 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1912 | /* Fix up broken headers */ |
| 1913 | pci_fixup_device(pci_fixup_header, dev); |
| 1914 | |
Yinghai Lu | 2069ecf | 2012-02-15 21:40:31 -0800 | [diff] [blame] | 1915 | /* moved out from quirk header fixup code */ |
| 1916 | pci_reassigndev_resource_alignment(dev); |
| 1917 | |
Rafael J. Wysocki | 4b77b0a | 2009-09-09 23:49:59 +0200 | [diff] [blame] | 1918 | /* Clear the state_saved flag. */ |
| 1919 | dev->state_saved = false; |
| 1920 | |
Zhao, Yu | 201de56 | 2008-10-13 19:49:55 +0800 | [diff] [blame] | 1921 | /* Initialize various capabilities */ |
| 1922 | pci_init_capabilities(dev); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1923 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1924 | /* |
| 1925 | * Add the device to our list of discovered devices |
| 1926 | * and the bus list for fixup functions, etc. |
| 1927 | */ |
Zhang Yanmin | d71374d | 2006-06-02 12:35:43 +0800 | [diff] [blame] | 1928 | down_write(&pci_bus_sem); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1929 | list_add_tail(&dev->bus_list, &bus->devices); |
Zhang Yanmin | d71374d | 2006-06-02 12:35:43 +0800 | [diff] [blame] | 1930 | up_write(&pci_bus_sem); |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 1931 | |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 1932 | ret = pcibios_add_device(dev); |
| 1933 | WARN_ON(ret < 0); |
| 1934 | |
Marc Zyngier | 44aa0c6 | 2015-07-28 14:46:11 +0100 | [diff] [blame] | 1935 | /* Setup MSI irq domain */ |
| 1936 | pci_set_msi_domain(dev); |
| 1937 | |
Yinghai Lu | 4f53509 | 2013-01-21 13:20:52 -0800 | [diff] [blame] | 1938 | /* Notifier could use PCI capabilities */ |
| 1939 | dev->match_driver = false; |
| 1940 | ret = device_add(&dev->dev); |
| 1941 | WARN_ON(ret < 0); |
Paul Mackerras | cdb9b9f | 2005-09-06 09:31:03 +1000 | [diff] [blame] | 1942 | } |
| 1943 | |
Bjorn Helgaas | 10874f5 | 2014-04-14 16:11:40 -0600 | [diff] [blame] | 1944 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
Paul Mackerras | cdb9b9f | 2005-09-06 09:31:03 +1000 | [diff] [blame] | 1945 | { |
| 1946 | struct pci_dev *dev; |
| 1947 | |
Trent Piepho | 90bdb31 | 2009-03-20 14:56:00 -0600 | [diff] [blame] | 1948 | dev = pci_get_slot(bus, devfn); |
| 1949 | if (dev) { |
| 1950 | pci_dev_put(dev); |
| 1951 | return dev; |
| 1952 | } |
| 1953 | |
Paul Mackerras | cdb9b9f | 2005-09-06 09:31:03 +1000 | [diff] [blame] | 1954 | dev = pci_scan_device(bus, devfn); |
| 1955 | if (!dev) |
| 1956 | return NULL; |
| 1957 | |
| 1958 | pci_device_add(dev, bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1959 | |
| 1960 | return dev; |
| 1961 | } |
Adrian Bunk | b73e968 | 2007-11-21 15:07:11 -0800 | [diff] [blame] | 1962 | EXPORT_SYMBOL(pci_scan_single_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1963 | |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 1964 | static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 1965 | { |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 1966 | int pos; |
| 1967 | u16 cap = 0; |
| 1968 | unsigned next_fn; |
Matthew Wilcox | 4fb88c1 | 2010-01-17 14:01:41 -0700 | [diff] [blame] | 1969 | |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 1970 | if (pci_ari_enabled(bus)) { |
| 1971 | if (!dev) |
| 1972 | return 0; |
| 1973 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
| 1974 | if (!pos) |
| 1975 | return 0; |
Matthew Wilcox | 4fb88c1 | 2010-01-17 14:01:41 -0700 | [diff] [blame] | 1976 | |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 1977 | pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); |
| 1978 | next_fn = PCI_ARI_CAP_NFN(cap); |
| 1979 | if (next_fn <= fn) |
| 1980 | return 0; /* protect against malformed list */ |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 1981 | |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 1982 | return next_fn; |
| 1983 | } |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 1984 | |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 1985 | /* dev may be NULL for non-contiguous multifunction devices */ |
| 1986 | if (!dev || dev->multifunction) |
| 1987 | return (fn + 1) % 8; |
| 1988 | |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 1989 | return 0; |
| 1990 | } |
| 1991 | |
| 1992 | static int only_one_child(struct pci_bus *bus) |
| 1993 | { |
| 1994 | struct pci_dev *parent = bus->self; |
Bjorn Helgaas | 284f5f9 | 2012-04-30 15:21:02 -0600 | [diff] [blame] | 1995 | |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 1996 | if (!parent || !pci_is_pcie(parent)) |
| 1997 | return 0; |
Yijing Wang | 62f87c0 | 2012-07-24 17:20:03 +0800 | [diff] [blame] | 1998 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) |
Bjorn Helgaas | 284f5f9 | 2012-04-30 15:21:02 -0600 | [diff] [blame] | 1999 | return 1; |
Bjorn Helgaas | 5bbe029 | 2016-02-05 14:57:47 -0600 | [diff] [blame] | 2000 | |
| 2001 | /* |
| 2002 | * PCIe downstream ports are bridges that normally lead to only a |
| 2003 | * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all |
| 2004 | * possible devices, not just device 0. See PCIe spec r3.0, |
| 2005 | * sec 7.3.1. |
| 2006 | */ |
Yijing Wang | 777e61e | 2015-05-21 15:05:04 +0800 | [diff] [blame] | 2007 | if (parent->has_secondary_link && |
Bjorn Helgaas | 284f5f9 | 2012-04-30 15:21:02 -0600 | [diff] [blame] | 2008 | !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 2009 | return 1; |
| 2010 | return 0; |
| 2011 | } |
| 2012 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2013 | /** |
| 2014 | * pci_scan_slot - scan a PCI slot on a bus for devices. |
| 2015 | * @bus: PCI bus to scan |
| 2016 | * @devfn: slot number to scan (must have zero function.) |
| 2017 | * |
| 2018 | * Scan a PCI slot on the specified PCI bus for devices, adding |
| 2019 | * discovered devices to the @bus->devices list. New devices |
Greg Kroah-Hartman | 8a1bc90 | 2008-02-14 14:56:56 -0800 | [diff] [blame] | 2020 | * will not have is_added set. |
Trent Piepho | 1b69dfc | 2009-03-20 14:56:05 -0600 | [diff] [blame] | 2021 | * |
| 2022 | * Returns the number of new devices found. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2023 | */ |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 2024 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2025 | { |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 2026 | unsigned fn, nr = 0; |
Trent Piepho | 1b69dfc | 2009-03-20 14:56:05 -0600 | [diff] [blame] | 2027 | struct pci_dev *dev; |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 2028 | |
| 2029 | if (only_one_child(bus) && (devfn > 0)) |
| 2030 | return 0; /* Already scanned the entire slot */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2031 | |
Trent Piepho | 1b69dfc | 2009-03-20 14:56:05 -0600 | [diff] [blame] | 2032 | dev = pci_scan_single_device(bus, devfn); |
Matthew Wilcox | 4fb88c1 | 2010-01-17 14:01:41 -0700 | [diff] [blame] | 2033 | if (!dev) |
| 2034 | return 0; |
| 2035 | if (!dev->is_added) |
Trent Piepho | 1b69dfc | 2009-03-20 14:56:05 -0600 | [diff] [blame] | 2036 | nr++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2037 | |
Yijing Wang | b1bd58e | 2013-01-25 09:12:31 -0700 | [diff] [blame] | 2038 | for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
Matthew Wilcox | f07852d | 2009-12-13 08:10:02 -0500 | [diff] [blame] | 2039 | dev = pci_scan_single_device(bus, devfn + fn); |
| 2040 | if (dev) { |
| 2041 | if (!dev->is_added) |
| 2042 | nr++; |
| 2043 | dev->multifunction = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2044 | } |
| 2045 | } |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 2046 | |
Shaohua Li | 149e163 | 2008-07-23 10:32:31 +0800 | [diff] [blame] | 2047 | /* only one slot has pcie device */ |
| 2048 | if (bus->self && nr) |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 2049 | pcie_aspm_init_link_state(bus->self); |
| 2050 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2051 | return nr; |
| 2052 | } |
Ryan Desfosses | b7fe943 | 2014-04-25 14:32:25 -0600 | [diff] [blame] | 2053 | EXPORT_SYMBOL(pci_scan_slot); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2054 | |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2055 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
| 2056 | { |
| 2057 | u8 *smpss = data; |
| 2058 | |
| 2059 | if (!pci_is_pcie(dev)) |
| 2060 | return 0; |
| 2061 | |
Yijing Wang | d4aa68f | 2013-08-22 11:24:47 +0800 | [diff] [blame] | 2062 | /* |
| 2063 | * We don't have a way to change MPS settings on devices that have |
| 2064 | * drivers attached. A hot-added device might support only the minimum |
| 2065 | * MPS setting (MPS=128). Therefore, if the fabric contains a bridge |
| 2066 | * where devices may be hot-added, we limit the fabric MPS to 128 so |
| 2067 | * hot-added devices will work correctly. |
| 2068 | * |
| 2069 | * However, if we hot-add a device to a slot directly below a Root |
| 2070 | * Port, it's impossible for there to be other existing devices below |
| 2071 | * the port. We don't limit the MPS in this case because we can |
| 2072 | * reconfigure MPS on both the Root Port and the hot-added device, |
| 2073 | * and there are no other devices involved. |
| 2074 | * |
| 2075 | * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2076 | */ |
Yijing Wang | d4aa68f | 2013-08-22 11:24:47 +0800 | [diff] [blame] | 2077 | if (dev->is_hotplug_bridge && |
| 2078 | pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2079 | *smpss = 0; |
| 2080 | |
| 2081 | if (*smpss > dev->pcie_mpss) |
| 2082 | *smpss = dev->pcie_mpss; |
| 2083 | |
| 2084 | return 0; |
| 2085 | } |
| 2086 | |
| 2087 | static void pcie_write_mps(struct pci_dev *dev, int mps) |
| 2088 | { |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2089 | int rc; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2090 | |
| 2091 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2092 | mps = 128 << dev->pcie_mpss; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2093 | |
Yijing Wang | 62f87c0 | 2012-07-24 17:20:03 +0800 | [diff] [blame] | 2094 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && |
| 2095 | dev->bus->self) |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2096 | /* For "Performance", the assumption is made that |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2097 | * downstream communication will never be larger than |
| 2098 | * the MRRS. So, the MPS only needs to be configured |
| 2099 | * for the upstream communication. This being the case, |
| 2100 | * walk from the top down and set the MPS of the child |
| 2101 | * to that of the parent bus. |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2102 | * |
| 2103 | * Configure the device MPS with the smaller of the |
| 2104 | * device MPSS or the bridge MPS (which is assumed to be |
| 2105 | * properly configured at this point to the largest |
| 2106 | * allowable MPS based on its parent bus). |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2107 | */ |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2108 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2109 | } |
| 2110 | |
| 2111 | rc = pcie_set_mps(dev, mps); |
| 2112 | if (rc) |
| 2113 | dev_err(&dev->dev, "Failed attempting to set the MPS\n"); |
| 2114 | } |
| 2115 | |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2116 | static void pcie_write_mrrs(struct pci_dev *dev) |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2117 | { |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2118 | int rc, mrrs; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2119 | |
Jon Mason | ed2888e | 2011-09-08 16:41:18 -0500 | [diff] [blame] | 2120 | /* In the "safe" case, do not configure the MRRS. There appear to be |
| 2121 | * issues with setting MRRS to 0 on a number of devices. |
| 2122 | */ |
Jon Mason | ed2888e | 2011-09-08 16:41:18 -0500 | [diff] [blame] | 2123 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
| 2124 | return; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2125 | |
Jon Mason | ed2888e | 2011-09-08 16:41:18 -0500 | [diff] [blame] | 2126 | /* For Max performance, the MRRS must be set to the largest supported |
| 2127 | * value. However, it cannot be configured larger than the MPS the |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2128 | * device or the bus can support. This should already be properly |
| 2129 | * configured by a prior call to pcie_write_mps. |
Jon Mason | ed2888e | 2011-09-08 16:41:18 -0500 | [diff] [blame] | 2130 | */ |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2131 | mrrs = pcie_get_mps(dev); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2132 | |
| 2133 | /* MRRS is a R/W register. Invalid values can be written, but a |
Jon Mason | ed2888e | 2011-09-08 16:41:18 -0500 | [diff] [blame] | 2134 | * subsequent read will verify if the value is acceptable or not. |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2135 | * If the MRRS value provided is not acceptable (e.g., too large), |
| 2136 | * shrink the value until it is acceptable to the HW. |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 2137 | */ |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2138 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
| 2139 | rc = pcie_set_readrq(dev, mrrs); |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2140 | if (!rc) |
| 2141 | break; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2142 | |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2143 | dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2144 | mrrs /= 2; |
| 2145 | } |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2146 | |
| 2147 | if (mrrs < 128) |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 2148 | dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2149 | } |
| 2150 | |
| 2151 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) |
| 2152 | { |
Jon Mason | a513a99 | 2011-10-14 14:56:16 -0500 | [diff] [blame] | 2153 | int mps, orig_mps; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2154 | |
| 2155 | if (!pci_is_pcie(dev)) |
| 2156 | return 0; |
| 2157 | |
Keith Busch | 27d868b | 2015-08-24 08:48:16 -0500 | [diff] [blame] | 2158 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
| 2159 | pcie_bus_config == PCIE_BUS_DEFAULT) |
Yijing Wang | 5895af7 | 2013-08-26 16:33:06 +0800 | [diff] [blame] | 2160 | return 0; |
Yijing Wang | 5895af7 | 2013-08-26 16:33:06 +0800 | [diff] [blame] | 2161 | |
Jon Mason | a513a99 | 2011-10-14 14:56:16 -0500 | [diff] [blame] | 2162 | mps = 128 << *(u8 *)data; |
| 2163 | orig_mps = pcie_get_mps(dev); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2164 | |
| 2165 | pcie_write_mps(dev, mps); |
Jon Mason | 62f392e | 2011-10-14 14:56:14 -0500 | [diff] [blame] | 2166 | pcie_write_mrrs(dev); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2167 | |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 2168 | dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", |
| 2169 | pcie_get_mps(dev), 128 << dev->pcie_mpss, |
Jon Mason | a513a99 | 2011-10-14 14:56:16 -0500 | [diff] [blame] | 2170 | orig_mps, pcie_get_readrq(dev)); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2171 | |
| 2172 | return 0; |
| 2173 | } |
| 2174 | |
Jon Mason | a513a99 | 2011-10-14 14:56:16 -0500 | [diff] [blame] | 2175 | /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2176 | * parents then children fashion. If this changes, then this code will not |
| 2177 | * work as designed. |
| 2178 | */ |
Bjorn Helgaas | a58674f | 2013-08-22 11:24:44 +0800 | [diff] [blame] | 2179 | void pcie_bus_configure_settings(struct pci_bus *bus) |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2180 | { |
Bjorn Helgaas | 1e358f9 | 2014-04-29 12:51:55 -0600 | [diff] [blame] | 2181 | u8 smpss = 0; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2182 | |
Bjorn Helgaas | a58674f | 2013-08-22 11:24:44 +0800 | [diff] [blame] | 2183 | if (!bus->self) |
| 2184 | return; |
| 2185 | |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2186 | if (!pci_is_pcie(bus->self)) |
| 2187 | return; |
| 2188 | |
Jon Mason | 5f39e67 | 2011-10-03 09:50:20 -0500 | [diff] [blame] | 2189 | /* FIXME - Peer to peer DMA is possible, though the endpoint would need |
Jon Mason | 3315472 | 2013-08-26 16:33:05 +0800 | [diff] [blame] | 2190 | * to be aware of the MPS of the destination. To work around this, |
Jon Mason | 5f39e67 | 2011-10-03 09:50:20 -0500 | [diff] [blame] | 2191 | * simply force the MPS of the entire system to the smallest possible. |
| 2192 | */ |
| 2193 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) |
| 2194 | smpss = 0; |
| 2195 | |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2196 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
Bjorn Helgaas | a58674f | 2013-08-22 11:24:44 +0800 | [diff] [blame] | 2197 | smpss = bus->self->pcie_mpss; |
Jon Mason | 5f39e67 | 2011-10-03 09:50:20 -0500 | [diff] [blame] | 2198 | |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2199 | pcie_find_smpss(bus->self, &smpss); |
| 2200 | pci_walk_bus(bus, pcie_find_smpss, &smpss); |
| 2201 | } |
| 2202 | |
| 2203 | pcie_bus_configure_set(bus->self, &smpss); |
| 2204 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); |
| 2205 | } |
Jon Mason | debc3b7 | 2011-08-02 00:01:18 -0500 | [diff] [blame] | 2206 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 2207 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2208 | unsigned int pci_scan_child_bus(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2209 | { |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 2210 | unsigned int devfn, pass, max = bus->busn_res.start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2211 | struct pci_dev *dev; |
| 2212 | |
Bjorn Helgaas | 0207c35 | 2009-11-04 10:32:52 -0700 | [diff] [blame] | 2213 | dev_dbg(&bus->dev, "scanning bus\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2214 | |
| 2215 | /* Go find them, Rover! */ |
| 2216 | for (devfn = 0; devfn < 0x100; devfn += 8) |
| 2217 | pci_scan_slot(bus, devfn); |
| 2218 | |
Yu Zhao | a28724b | 2009-03-20 11:25:13 +0800 | [diff] [blame] | 2219 | /* Reserve buses for SR-IOV capability. */ |
| 2220 | max += pci_iov_bus_range(bus); |
| 2221 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2222 | /* |
| 2223 | * After performing arch-dependent fixup of the bus, look behind |
| 2224 | * all PCI-to-PCI bridges on this bus. |
| 2225 | */ |
Alex Chiang | 74710de | 2009-03-20 14:56:10 -0600 | [diff] [blame] | 2226 | if (!bus->is_added) { |
Bjorn Helgaas | 0207c35 | 2009-11-04 10:32:52 -0700 | [diff] [blame] | 2227 | dev_dbg(&bus->dev, "fixups for bus\n"); |
Alex Chiang | 74710de | 2009-03-20 14:56:10 -0600 | [diff] [blame] | 2228 | pcibios_fixup_bus(bus); |
Jiang Liu | 981cf9e | 2013-04-12 05:44:16 +0000 | [diff] [blame] | 2229 | bus->is_added = 1; |
Alex Chiang | 74710de | 2009-03-20 14:56:10 -0600 | [diff] [blame] | 2230 | } |
| 2231 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 2232 | for (pass = 0; pass < 2; pass++) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2233 | list_for_each_entry(dev, &bus->devices, bus_list) { |
Yijing Wang | 6788a51 | 2014-05-04 12:23:38 +0800 | [diff] [blame] | 2234 | if (pci_is_bridge(dev)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2235 | max = pci_scan_bridge(bus, dev, max, pass); |
| 2236 | } |
| 2237 | |
| 2238 | /* |
Keith Busch | e16b466 | 2016-07-21 21:40:28 -0600 | [diff] [blame] | 2239 | * Make sure a hotplug bridge has at least the minimum requested |
| 2240 | * number of buses. |
| 2241 | */ |
| 2242 | if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) { |
| 2243 | if (max - bus->busn_res.start < pci_hotplug_bus_size - 1) |
| 2244 | max = bus->busn_res.start + pci_hotplug_bus_size - 1; |
| 2245 | } |
| 2246 | |
| 2247 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2248 | * We've scanned the bus and so we know all about what's on |
| 2249 | * the other side of any bridges that may be on this bus plus |
| 2250 | * any devices. |
| 2251 | * |
| 2252 | * Return how far we've got finding sub-buses. |
| 2253 | */ |
Bjorn Helgaas | 0207c35 | 2009-11-04 10:32:52 -0700 | [diff] [blame] | 2254 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2255 | return max; |
| 2256 | } |
Ryan Desfosses | b7fe943 | 2014-04-25 14:32:25 -0600 | [diff] [blame] | 2257 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2258 | |
Rafael J. Wysocki | 6c0cc95 | 2013-01-09 22:33:37 +0100 | [diff] [blame] | 2259 | /** |
| 2260 | * pcibios_root_bridge_prepare - Platform-specific host bridge setup. |
| 2261 | * @bridge: Host bridge to set up. |
| 2262 | * |
| 2263 | * Default empty implementation. Replace with an architecture-specific setup |
| 2264 | * routine, if necessary. |
| 2265 | */ |
| 2266 | int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
| 2267 | { |
| 2268 | return 0; |
| 2269 | } |
| 2270 | |
Jiang Liu | 10a9574 | 2013-04-12 05:44:20 +0000 | [diff] [blame] | 2271 | void __weak pcibios_add_bus(struct pci_bus *bus) |
| 2272 | { |
| 2273 | } |
| 2274 | |
| 2275 | void __weak pcibios_remove_bus(struct pci_bus *bus) |
| 2276 | { |
| 2277 | } |
| 2278 | |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2279 | static struct pci_bus *pci_create_root_bus_msi(struct device *parent, |
| 2280 | int bus, struct pci_ops *ops, void *sysdata, |
| 2281 | struct list_head *resources, struct msi_controller *msi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2282 | { |
Bjorn Helgaas | 0efd5aa | 2012-02-23 20:19:00 -0700 | [diff] [blame] | 2283 | int error; |
Bjorn Helgaas | 5a21d70 | 2012-02-23 20:18:59 -0700 | [diff] [blame] | 2284 | struct pci_host_bridge *bridge; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2285 | |
Thierry Reding | 5909406 | 2016-11-25 11:57:10 +0100 | [diff] [blame] | 2286 | bridge = pci_alloc_host_bridge(0); |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 2287 | if (!bridge) |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2288 | return NULL; |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 2289 | |
| 2290 | bridge->dev.parent = parent; |
Jiang Liu | 70efde2 | 2013-06-07 16:16:51 -0600 | [diff] [blame] | 2291 | bridge->dev.release = pci_release_host_bridge_dev; |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2292 | |
| 2293 | list_splice_init(resources, &bridge->windows); |
| 2294 | bridge->sysdata = sysdata; |
| 2295 | bridge->busnr = bus; |
| 2296 | bridge->ops = ops; |
| 2297 | bridge->msi = msi; |
| 2298 | |
| 2299 | error = pci_register_host_bridge(bridge); |
| 2300 | if (error < 0) |
Jiang Liu | 343df77 | 2013-06-07 01:10:08 +0800 | [diff] [blame] | 2301 | goto err_out; |
Rafael J. Wysocki | 6c0cc95 | 2013-01-09 22:33:37 +0100 | [diff] [blame] | 2302 | |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2303 | return bridge->bus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2304 | |
Yinghai Lu | 7b54366 | 2012-04-02 18:31:53 -0700 | [diff] [blame] | 2305 | err_out: |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2306 | kfree(bridge); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2307 | return NULL; |
| 2308 | } |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2309 | |
| 2310 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
| 2311 | struct pci_ops *ops, void *sysdata, struct list_head *resources) |
| 2312 | { |
| 2313 | return pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, |
| 2314 | NULL); |
| 2315 | } |
Ray Jui | e6b29de | 2015-04-08 11:21:33 -0700 | [diff] [blame] | 2316 | EXPORT_SYMBOL_GPL(pci_create_root_bus); |
Paul Mackerras | cdb9b9f | 2005-09-06 09:31:03 +1000 | [diff] [blame] | 2317 | |
Yinghai Lu | 98a3583 | 2012-05-18 11:35:50 -0600 | [diff] [blame] | 2318 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
| 2319 | { |
| 2320 | struct resource *res = &b->busn_res; |
| 2321 | struct resource *parent_res, *conflict; |
| 2322 | |
| 2323 | res->start = bus; |
| 2324 | res->end = bus_max; |
| 2325 | res->flags = IORESOURCE_BUS; |
| 2326 | |
| 2327 | if (!pci_is_root_bus(b)) |
| 2328 | parent_res = &b->parent->busn_res; |
| 2329 | else { |
| 2330 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); |
| 2331 | res->flags |= IORESOURCE_PCI_FIXED; |
| 2332 | } |
| 2333 | |
Andreas Noever | ced04d1 | 2014-01-23 21:59:24 +0100 | [diff] [blame] | 2334 | conflict = request_resource_conflict(parent_res, res); |
Yinghai Lu | 98a3583 | 2012-05-18 11:35:50 -0600 | [diff] [blame] | 2335 | |
| 2336 | if (conflict) |
| 2337 | dev_printk(KERN_DEBUG, &b->dev, |
| 2338 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", |
| 2339 | res, pci_is_root_bus(b) ? "domain " : "", |
| 2340 | parent_res, conflict->name, conflict); |
Yinghai Lu | 98a3583 | 2012-05-18 11:35:50 -0600 | [diff] [blame] | 2341 | |
| 2342 | return conflict == NULL; |
| 2343 | } |
| 2344 | |
| 2345 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) |
| 2346 | { |
| 2347 | struct resource *res = &b->busn_res; |
| 2348 | struct resource old_res = *res; |
| 2349 | resource_size_t size; |
| 2350 | int ret; |
| 2351 | |
| 2352 | if (res->start > bus_max) |
| 2353 | return -EINVAL; |
| 2354 | |
| 2355 | size = bus_max - res->start + 1; |
| 2356 | ret = adjust_resource(res, res->start, size); |
| 2357 | dev_printk(KERN_DEBUG, &b->dev, |
| 2358 | "busn_res: %pR end %s updated to %02x\n", |
| 2359 | &old_res, ret ? "can not be" : "is", bus_max); |
| 2360 | |
| 2361 | if (!ret && !res->parent) |
| 2362 | pci_bus_insert_busn_res(b, res->start, res->end); |
| 2363 | |
| 2364 | return ret; |
| 2365 | } |
| 2366 | |
| 2367 | void pci_bus_release_busn_res(struct pci_bus *b) |
| 2368 | { |
| 2369 | struct resource *res = &b->busn_res; |
| 2370 | int ret; |
| 2371 | |
| 2372 | if (!res->flags || !res->parent) |
| 2373 | return; |
| 2374 | |
| 2375 | ret = release_resource(res); |
| 2376 | dev_printk(KERN_DEBUG, &b->dev, |
| 2377 | "busn_res: %pR %s released\n", |
| 2378 | res, ret ? "can not be" : "is"); |
| 2379 | } |
| 2380 | |
Lorenzo Pieralisi | d2a7926 | 2015-08-03 21:27:10 -0500 | [diff] [blame] | 2381 | struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, |
| 2382 | struct pci_ops *ops, void *sysdata, |
| 2383 | struct list_head *resources, struct msi_controller *msi) |
Bjorn Helgaas | a2ebb82 | 2011-10-28 16:25:50 -0600 | [diff] [blame] | 2384 | { |
Jiang Liu | 14d76b6 | 2015-02-05 13:44:44 +0800 | [diff] [blame] | 2385 | struct resource_entry *window; |
Yinghai Lu | 4d99f52 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 2386 | bool found = false; |
Bjorn Helgaas | a2ebb82 | 2011-10-28 16:25:50 -0600 | [diff] [blame] | 2387 | struct pci_bus *b; |
Yinghai Lu | 4d99f52 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 2388 | int max; |
| 2389 | |
Jiang Liu | 14d76b6 | 2015-02-05 13:44:44 +0800 | [diff] [blame] | 2390 | resource_list_for_each_entry(window, resources) |
Yinghai Lu | 4d99f52 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 2391 | if (window->res->flags & IORESOURCE_BUS) { |
| 2392 | found = true; |
| 2393 | break; |
| 2394 | } |
Bjorn Helgaas | a2ebb82 | 2011-10-28 16:25:50 -0600 | [diff] [blame] | 2395 | |
Arnd Bergmann | 37d6a0a | 2016-11-25 11:57:09 +0100 | [diff] [blame] | 2396 | b = pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, msi); |
Bjorn Helgaas | a2ebb82 | 2011-10-28 16:25:50 -0600 | [diff] [blame] | 2397 | if (!b) |
| 2398 | return NULL; |
| 2399 | |
Yinghai Lu | 4d99f52 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 2400 | if (!found) { |
| 2401 | dev_info(&b->dev, |
| 2402 | "No busn resource found for root bus, will use [bus %02x-ff]\n", |
| 2403 | bus); |
| 2404 | pci_bus_insert_busn_res(b, bus, 255); |
| 2405 | } |
| 2406 | |
| 2407 | max = pci_scan_child_bus(b); |
| 2408 | |
| 2409 | if (!found) |
| 2410 | pci_bus_update_busn_res_end(b, max); |
| 2411 | |
Bjorn Helgaas | a2ebb82 | 2011-10-28 16:25:50 -0600 | [diff] [blame] | 2412 | return b; |
| 2413 | } |
Lorenzo Pieralisi | d2a7926 | 2015-08-03 21:27:10 -0500 | [diff] [blame] | 2414 | |
| 2415 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
| 2416 | struct pci_ops *ops, void *sysdata, struct list_head *resources) |
| 2417 | { |
| 2418 | return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources, |
| 2419 | NULL); |
| 2420 | } |
Bjorn Helgaas | a2ebb82 | 2011-10-28 16:25:50 -0600 | [diff] [blame] | 2421 | EXPORT_SYMBOL(pci_scan_root_bus); |
| 2422 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2423 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
Bjorn Helgaas | de4b2f7 | 2011-10-28 16:25:55 -0600 | [diff] [blame] | 2424 | void *sysdata) |
| 2425 | { |
| 2426 | LIST_HEAD(resources); |
| 2427 | struct pci_bus *b; |
| 2428 | |
| 2429 | pci_add_resource(&resources, &ioport_resource); |
| 2430 | pci_add_resource(&resources, &iomem_resource); |
Yinghai Lu | 857c3b6 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 2431 | pci_add_resource(&resources, &busn_resource); |
Bjorn Helgaas | de4b2f7 | 2011-10-28 16:25:55 -0600 | [diff] [blame] | 2432 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); |
| 2433 | if (b) { |
Yinghai Lu | 857c3b6 | 2012-05-17 18:51:12 -0700 | [diff] [blame] | 2434 | pci_scan_child_bus(b); |
Bjorn Helgaas | de4b2f7 | 2011-10-28 16:25:55 -0600 | [diff] [blame] | 2435 | } else { |
| 2436 | pci_free_resource_list(&resources); |
| 2437 | } |
| 2438 | return b; |
| 2439 | } |
| 2440 | EXPORT_SYMBOL(pci_scan_bus); |
| 2441 | |
Alex Chiang | 3ed4fd9 | 2009-03-20 14:56:25 -0600 | [diff] [blame] | 2442 | /** |
Yinghai Lu | 2f32052 | 2012-01-21 02:08:22 -0800 | [diff] [blame] | 2443 | * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. |
| 2444 | * @bridge: PCI bridge for the bus to scan |
| 2445 | * |
| 2446 | * Scan a PCI bus and child buses for new devices, add them, |
| 2447 | * and enable them, resizing bridge mmio/io resource if necessary |
| 2448 | * and possible. The caller must ensure the child devices are already |
| 2449 | * removed for resizing to occur. |
| 2450 | * |
| 2451 | * Returns the max number of subordinate bus discovered. |
| 2452 | */ |
Bjorn Helgaas | 10874f5 | 2014-04-14 16:11:40 -0600 | [diff] [blame] | 2453 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
Yinghai Lu | 2f32052 | 2012-01-21 02:08:22 -0800 | [diff] [blame] | 2454 | { |
| 2455 | unsigned int max; |
| 2456 | struct pci_bus *bus = bridge->subordinate; |
| 2457 | |
| 2458 | max = pci_scan_child_bus(bus); |
| 2459 | |
| 2460 | pci_assign_unassigned_bridge_resources(bridge); |
| 2461 | |
| 2462 | pci_bus_add_devices(bus); |
| 2463 | |
| 2464 | return max; |
| 2465 | } |
| 2466 | |
Yinghai Lu | a5213a3 | 2012-10-30 14:31:21 -0600 | [diff] [blame] | 2467 | /** |
| 2468 | * pci_rescan_bus - scan a PCI bus for devices. |
| 2469 | * @bus: PCI bus to scan |
| 2470 | * |
| 2471 | * Scan a PCI bus and child buses for new devices, adds them, |
| 2472 | * and enables them. |
| 2473 | * |
| 2474 | * Returns the max number of subordinate bus discovered. |
| 2475 | */ |
Bjorn Helgaas | 10874f5 | 2014-04-14 16:11:40 -0600 | [diff] [blame] | 2476 | unsigned int pci_rescan_bus(struct pci_bus *bus) |
Yinghai Lu | a5213a3 | 2012-10-30 14:31:21 -0600 | [diff] [blame] | 2477 | { |
| 2478 | unsigned int max; |
| 2479 | |
| 2480 | max = pci_scan_child_bus(bus); |
| 2481 | pci_assign_unassigned_bus_resources(bus); |
| 2482 | pci_bus_add_devices(bus); |
| 2483 | |
| 2484 | return max; |
| 2485 | } |
| 2486 | EXPORT_SYMBOL_GPL(pci_rescan_bus); |
| 2487 | |
Rafael J. Wysocki | 9d16947 | 2014-01-10 15:22:18 +0100 | [diff] [blame] | 2488 | /* |
| 2489 | * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal |
| 2490 | * routines should always be executed under this mutex. |
| 2491 | */ |
| 2492 | static DEFINE_MUTEX(pci_rescan_remove_lock); |
| 2493 | |
| 2494 | void pci_lock_rescan_remove(void) |
| 2495 | { |
| 2496 | mutex_lock(&pci_rescan_remove_lock); |
| 2497 | } |
| 2498 | EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); |
| 2499 | |
| 2500 | void pci_unlock_rescan_remove(void) |
| 2501 | { |
| 2502 | mutex_unlock(&pci_rescan_remove_lock); |
| 2503 | } |
| 2504 | EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); |
| 2505 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 2506 | static int __init pci_sort_bf_cmp(const struct device *d_a, |
| 2507 | const struct device *d_b) |
Matt Domsch | 6b4b78f | 2006-09-29 15:23:23 -0500 | [diff] [blame] | 2508 | { |
Greg Kroah-Hartman | 99178b0 | 2008-08-26 11:00:57 -0500 | [diff] [blame] | 2509 | const struct pci_dev *a = to_pci_dev(d_a); |
| 2510 | const struct pci_dev *b = to_pci_dev(d_b); |
| 2511 | |
Matt Domsch | 6b4b78f | 2006-09-29 15:23:23 -0500 | [diff] [blame] | 2512 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
| 2513 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; |
| 2514 | |
| 2515 | if (a->bus->number < b->bus->number) return -1; |
| 2516 | else if (a->bus->number > b->bus->number) return 1; |
| 2517 | |
| 2518 | if (a->devfn < b->devfn) return -1; |
| 2519 | else if (a->devfn > b->devfn) return 1; |
| 2520 | |
| 2521 | return 0; |
| 2522 | } |
| 2523 | |
Greg Kroah-Hartman | 5ff580c | 2008-02-14 14:56:56 -0800 | [diff] [blame] | 2524 | void __init pci_sort_breadthfirst(void) |
Matt Domsch | 6b4b78f | 2006-09-29 15:23:23 -0500 | [diff] [blame] | 2525 | { |
Greg Kroah-Hartman | 99178b0 | 2008-08-26 11:00:57 -0500 | [diff] [blame] | 2526 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
Matt Domsch | 6b4b78f | 2006-09-29 15:23:23 -0500 | [diff] [blame] | 2527 | } |