blob: 204960e70333f1dbe49d03ffffac7393f06a37c4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07009#include <linux/of_device.h>
Murali Karicheride335bb42015-03-03 12:52:13 -050010#include <linux/of_pci.h>
Bjorn Helgaas589fcc22014-09-12 20:02:00 -060011#include <linux/pci_hotplug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080015#include <linux/pci-aspm.h>
Taku Izumib07461a2015-09-17 10:09:37 -050016#include <linux/aer.h>
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -070017#include <linux/acpi.h>
Jake Oshins788858e2016-02-16 21:56:22 +000018#include <linux/irqdomain.h>
Mika Westerbergd963f652016-06-02 11:17:13 +030019#include <linux/pm_runtime.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090020#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
Stephen Hemminger0b950f02014-01-10 17:14:48 -070025static struct resource busn_resource = {
Yinghai Lu67cdc822012-05-17 18:51:12 -070026 .name = "PCI busn",
27 .start = 0,
28 .end = 255,
29 .flags = IORESOURCE_BUS,
30};
31
Linus Torvalds1da177e2005-04-16 15:20:36 -070032/* Ugh. Need to stop exporting this to modules. */
33LIST_HEAD(pci_root_buses);
34EXPORT_SYMBOL(pci_root_buses);
35
Yinghai Lu5cc62c22012-05-17 18:51:11 -070036static LIST_HEAD(pci_domain_busn_res_list);
37
38struct pci_domain_busn_res {
39 struct list_head list;
40 struct resource res;
41 int domain_nr;
42};
43
44static struct resource *get_pci_domain_busn_res(int domain_nr)
45{
46 struct pci_domain_busn_res *r;
47
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
50 return &r->res;
51
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
53 if (!r)
54 return NULL;
55
56 r->domain_nr = domain_nr;
57 r->res.start = 0;
58 r->res.end = 0xff;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
60
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
62
63 return &r->res;
64}
65
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080066static int find_anything(struct device *dev, void *data)
67{
68 return 1;
69}
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070071/*
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080074 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070075 */
76int no_pci_devices(void)
77{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080078 struct device *dev;
79 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070080
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080081 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
83 put_device(dev);
84 return no_devices;
85}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070086EXPORT_SYMBOL(no_pci_devices);
87
Linus Torvalds1da177e2005-04-16 15:20:36 -070088/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 * PCI Bus Class
90 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040091static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070092{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040093 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
Markus Elfringff0387c2014-11-10 21:02:17 -070095 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070096 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100097 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098 kfree(pci_bus);
99}
100
101static struct class pcibus_class = {
102 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400103 .dev_release = &release_pcibus_dev,
Greg Kroah-Hartman56039e62013-07-24 15:05:17 -0700104 .dev_groups = pcibus_groups,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105};
106
107static int __init pcibus_class_init(void)
108{
109 return class_register(&pcibus_class);
110}
111postcore_initcall(pcibus_class_init);
112
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400113static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800114{
115 u64 size = mask & maxbase; /* Find the significant bits */
116 if (!size)
117 return 0;
118
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
122
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
126 return 0;
127
128 return size;
129}
130
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600131static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800132{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600133 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600134 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600135
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
139 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400140 }
141
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400146
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 switch (mem_type) {
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600152 /* 1M mem BAR treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600153 break;
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600155 flags |= IORESOURCE_MEM_64;
156 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600157 default:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600158 /* mem unknown type treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600159 break;
160 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600161 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400162}
163
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100164#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165
Yu Zhao0b400c72008-11-22 02:40:40 +0800166/**
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
172 *
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400174 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800175int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400176 struct resource *res, unsigned int pos)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400177{
178 u32 l, sz, mask;
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600179 u64 l64, sz64, mask64;
Jacob Pan253d2e52010-07-16 10:19:22 -0700180 u16 orig_cmd;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800181 struct pci_bus_region region, inverted_region;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400182
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400184
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600185 /* No printks while decoding is disabled! */
Jacob Pan253d2e52010-07-16 10:19:22 -0700186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 }
Jacob Pan253d2e52010-07-16 10:19:22 -0700192 }
193
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400194 res->name = pci_name(dev);
195
196 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200197 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
200
201 /*
202 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400206 */
Myron Stowef795d862014-10-30 11:54:43 -0600207 if (sz == 0xffffffff)
208 sz = 0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400209
210 /*
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
213 */
214 if (l == 0xffffffff)
215 l = 0;
216
217 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
Myron Stowef795d862014-10-30 11:54:43 -0600221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400224 } else {
Myron Stowef795d862014-10-30 11:54:43 -0600225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400228 }
229 } else {
Bjorn Helgaas7a6d3122016-11-28 17:21:02 -0600230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
Myron Stowef795d862014-10-30 11:54:43 -0600232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400235 }
236
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600237 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
242
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
Myron Stowef795d862014-10-30 11:54:43 -0600245 mask64 |= ((u64)~0 << 32);
246 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400247
Myron Stowef795d862014-10-30 11:54:43 -0600248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400250
Myron Stowef795d862014-10-30 11:54:43 -0600251 if (!sz64)
252 goto fail;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400253
Myron Stowef795d862014-10-30 11:54:43 -0600254 sz64 = pci_size(l64, sz64, mask64);
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600255 if (!sz64) {
256 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
257 pos);
Myron Stowef795d862014-10-30 11:54:43 -0600258 goto fail;
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600259 }
Myron Stowef795d862014-10-30 11:54:43 -0600260
261 if (res->flags & IORESOURCE_MEM_64) {
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 res->start = 0;
266 res->end = 0;
Myron Stowef795d862014-10-30 11:54:43 -0600267 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600269 goto out;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600270 }
271
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600273 /* Above 32-bit boundary; try to reallocate */
Bjorn Helgaasc83bd902014-02-26 11:26:00 -0700274 res->flags |= IORESOURCE_UNSET;
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600275 res->start = 0;
276 res->end = sz64;
Myron Stowef795d862014-10-30 11:54:43 -0600277 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600279 goto out;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400280 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400281 }
282
Myron Stowef795d862014-10-30 11:54:43 -0600283 region.start = l64;
284 region.end = l64 + sz64;
285
Yinghai Lufc279852013-12-09 22:54:40 -0800286 pcibios_bus_to_resource(dev->bus, res, &region);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800288
289 /*
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
294 *
295 * resource_to_bus(bus_to_resource(A)) == A
296 *
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
299 */
300 if (inverted_region.start != region.start) {
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800301 res->flags |= IORESOURCE_UNSET;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800302 res->start = 0;
Bjorn Helgaas26370fc2014-04-14 15:26:50 -0600303 res->end = region.end - region.start;
Myron Stowef795d862014-10-30 11:54:43 -0600304 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800306 }
Kevin Hao96ddef22013-05-25 19:36:26 +0800307
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600308 goto out;
309
310
311fail:
312 res->flags = 0;
313out:
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600314 if (res->flags)
Kevin Hao33963e302013-05-25 19:36:25 +0800315 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600316
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800318}
319
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400322 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323
Prarit Bhargavaad67b432016-05-11 12:27:16 -0400324 if (dev->non_compliant_bars)
325 return;
326
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400327 for (pos = 0; pos < howmany; pos++) {
328 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400330 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400332
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400334 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400336 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
Dan Williams92b19ff2015-08-10 23:07:06 -0400337 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400338 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 }
340}
341
Bill Pemberton15856ad2012-11-21 15:35:00 -0500342static void pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343{
344 struct pci_dev *dev = child->self;
345 u8 io_base_lo, io_limit_lo;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600346 unsigned long io_mask, io_granularity, base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700347 struct pci_bus_region region;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600348 struct resource *res;
349
350 io_mask = PCI_IO_RANGE_MASK;
351 io_granularity = 0x1000;
352 if (dev->io_window_1k) {
353 /* Support 1K I/O space granularity */
354 io_mask = PCI_IO_1K_RANGE_MASK;
355 io_granularity = 0x400;
356 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 res = child->resource[0];
359 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
360 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600361 base = (io_base_lo & io_mask) << 8;
362 limit = (io_limit_lo & io_mask) << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363
364 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
365 u16 io_base_hi, io_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600366
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
368 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600369 base |= ((unsigned long) io_base_hi << 16);
370 limit |= ((unsigned long) io_limit_hi << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371 }
372
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600373 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700375 region.start = base;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600376 region.end = limit + io_granularity - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800377 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700380}
381
Bill Pemberton15856ad2012-11-21 15:35:00 -0500382static void pci_read_bridge_mmio(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700383{
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700387 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700388 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600393 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600395 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700397 region.start = base;
398 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800399 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700402}
403
Bill Pemberton15856ad2012-11-21 15:35:00 -0500404static void pci_read_bridge_mmio_pref(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700405{
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700408 u64 base64, limit64;
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700409 pci_bus_addr_t base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700410 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700411 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413 res = child->resource[2];
414 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
415 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700416 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
417 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418
419 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
420 u32 mem_base_hi, mem_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600421
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
423 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
424
425 /*
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
429 */
430 if (mem_base_hi <= mem_limit_hi) {
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700431 base64 |= (u64) mem_base_hi << 32;
432 limit64 |= (u64) mem_limit_hi << 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 }
434 }
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700435
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700436 base = (pci_bus_addr_t) base64;
437 limit = (pci_bus_addr_t) limit64;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700438
439 if (base != base64) {
440 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64);
442 return;
443 }
444
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600445 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700446 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
447 IORESOURCE_MEM | IORESOURCE_PREFETCH;
448 if (res->flags & PCI_PREF_RANGE_TYPE_64)
449 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700450 region.start = base;
451 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800452 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600453 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 }
455}
456
Bill Pemberton15856ad2012-11-21 15:35:00 -0500457void pci_read_bridge_bases(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700458{
459 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700460 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700461 int i;
462
463 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 return;
465
Yinghai Lub918c622012-05-17 18:51:11 -0700466 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
467 &child->busn_res,
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700468 dev->transparent ? " (subtractive decode)" : "");
469
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700470 pci_bus_remove_resources(child);
471 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
472 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
473
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700474 pci_read_bridge_io(child);
475 pci_read_bridge_mmio(child);
476 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700477
478 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700479 pci_bus_for_each_resource(child->parent, res, i) {
Bjorn Helgaasd739a092014-04-14 16:10:54 -0600480 if (res && res->flags) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700481 pci_bus_add_resource(child, res,
482 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700483 dev_printk(KERN_DEBUG, &dev->dev,
484 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700485 res);
486 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700487 }
488 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700489}
490
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100491static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492{
493 struct pci_bus *b;
494
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100495 b = kzalloc(sizeof(*b), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600496 if (!b)
497 return NULL;
498
499 INIT_LIST_HEAD(&b->node);
500 INIT_LIST_HEAD(&b->children);
501 INIT_LIST_HEAD(&b->devices);
502 INIT_LIST_HEAD(&b->slots);
503 INIT_LIST_HEAD(&b->resources);
504 b->max_bus_speed = PCI_SPEED_UNKNOWN;
505 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100506#ifdef CONFIG_PCI_DOMAINS_GENERIC
507 if (parent)
508 b->domain_nr = parent->domain_nr;
509#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510 return b;
511}
512
Jiang Liu70efde22013-06-07 16:16:51 -0600513static void pci_release_host_bridge_dev(struct device *dev)
514{
515 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
516
517 if (bridge->release_fn)
518 bridge->release_fn(bridge);
519
520 pci_free_resource_list(&bridge->windows);
521
522 kfree(bridge);
523}
524
Thierry Redinga52d1442016-11-25 11:57:11 +0100525struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
Yinghai Lu7b543662012-04-02 18:31:53 -0700526{
527 struct pci_host_bridge *bridge;
528
Thierry Reding59094062016-11-25 11:57:10 +0100529 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600530 if (!bridge)
531 return NULL;
Yinghai Lu7b543662012-04-02 18:31:53 -0700532
Bjorn Helgaas05013482013-06-05 14:22:11 -0600533 INIT_LIST_HEAD(&bridge->windows);
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100534
Yinghai Lu7b543662012-04-02 18:31:53 -0700535 return bridge;
536}
Thierry Redinga52d1442016-11-25 11:57:11 +0100537EXPORT_SYMBOL(pci_alloc_host_bridge);
Yinghai Lu7b543662012-04-02 18:31:53 -0700538
Stephen Hemminger0b950f02014-01-10 17:14:48 -0700539static const unsigned char pcix_bus_speed[] = {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500540 PCI_SPEED_UNKNOWN, /* 0 */
541 PCI_SPEED_66MHz_PCIX, /* 1 */
542 PCI_SPEED_100MHz_PCIX, /* 2 */
543 PCI_SPEED_133MHz_PCIX, /* 3 */
544 PCI_SPEED_UNKNOWN, /* 4 */
545 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
546 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
547 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
548 PCI_SPEED_UNKNOWN, /* 8 */
549 PCI_SPEED_66MHz_PCIX_266, /* 9 */
550 PCI_SPEED_100MHz_PCIX_266, /* A */
551 PCI_SPEED_133MHz_PCIX_266, /* B */
552 PCI_SPEED_UNKNOWN, /* C */
553 PCI_SPEED_66MHz_PCIX_533, /* D */
554 PCI_SPEED_100MHz_PCIX_533, /* E */
555 PCI_SPEED_133MHz_PCIX_533 /* F */
556};
557
Jacob Keller343e51a2013-07-31 06:53:16 +0000558const unsigned char pcie_link_speed[] = {
Matthew Wilcox3749c512009-12-13 08:11:32 -0500559 PCI_SPEED_UNKNOWN, /* 0 */
560 PCIE_SPEED_2_5GT, /* 1 */
561 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500562 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500563 PCI_SPEED_UNKNOWN, /* 4 */
564 PCI_SPEED_UNKNOWN, /* 5 */
565 PCI_SPEED_UNKNOWN, /* 6 */
566 PCI_SPEED_UNKNOWN, /* 7 */
567 PCI_SPEED_UNKNOWN, /* 8 */
568 PCI_SPEED_UNKNOWN, /* 9 */
569 PCI_SPEED_UNKNOWN, /* A */
570 PCI_SPEED_UNKNOWN, /* B */
571 PCI_SPEED_UNKNOWN, /* C */
572 PCI_SPEED_UNKNOWN, /* D */
573 PCI_SPEED_UNKNOWN, /* E */
574 PCI_SPEED_UNKNOWN /* F */
575};
576
577void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
578{
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700579 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
Matthew Wilcox3749c512009-12-13 08:11:32 -0500580}
581EXPORT_SYMBOL_GPL(pcie_update_link_speed);
582
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500583static unsigned char agp_speeds[] = {
584 AGP_UNKNOWN,
585 AGP_1X,
586 AGP_2X,
587 AGP_4X,
588 AGP_8X
589};
590
591static enum pci_bus_speed agp_speed(int agp3, int agpstat)
592{
593 int index = 0;
594
595 if (agpstat & 4)
596 index = 3;
597 else if (agpstat & 2)
598 index = 2;
599 else if (agpstat & 1)
600 index = 1;
601 else
602 goto out;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700603
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500604 if (agp3) {
605 index += 2;
606 if (index == 5)
607 index = 0;
608 }
609
610 out:
611 return agp_speeds[index];
612}
613
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500614static void pci_set_bus_speed(struct pci_bus *bus)
615{
616 struct pci_dev *bridge = bus->self;
617 int pos;
618
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
620 if (!pos)
621 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
622 if (pos) {
623 u32 agpstat, agpcmd;
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
626 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
627
628 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
629 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
630 }
631
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500632 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
633 if (pos) {
634 u16 status;
635 enum pci_bus_speed max;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500636
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700637 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
638 &status);
639
640 if (status & PCI_X_SSTATUS_533MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500641 max = PCI_SPEED_133MHz_PCIX_533;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700642 } else if (status & PCI_X_SSTATUS_266MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500643 max = PCI_SPEED_133MHz_PCIX_266;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700644 } else if (status & PCI_X_SSTATUS_133MHZ) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400645 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500646 max = PCI_SPEED_133MHz_PCIX_ECC;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400647 else
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500648 max = PCI_SPEED_133MHz_PCIX;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500649 } else {
650 max = PCI_SPEED_66MHz_PCIX;
651 }
652
653 bus->max_bus_speed = max;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700654 bus->cur_bus_speed = pcix_bus_speed[
655 (status & PCI_X_SSTATUS_FREQ) >> 6];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500656
657 return;
658 }
659
Yijing Wangfdfe1512013-09-05 15:55:29 +0800660 if (pci_is_pcie(bridge)) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500661 u32 linkcap;
662 u16 linksta;
663
Jiang Liu59875ae2012-07-24 17:20:06 +0800664 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700665 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500666
Jiang Liu59875ae2012-07-24 17:20:06 +0800667 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500668 pcie_update_link_speed(bus, linksta);
669 }
670}
671
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100672static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
673{
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100674 struct irq_domain *d;
675
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100676 /*
677 * Any firmware interface that can resolve the msi_domain
678 * should be called from here.
679 */
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100680 d = pci_host_bridge_of_msi_domain(bus);
Suravee Suthikulpanit471036b2015-12-10 08:55:27 -0800681 if (!d)
682 d = pci_host_bridge_acpi_msi_domain(bus);
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100683
Jake Oshins788858e2016-02-16 21:56:22 +0000684#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
685 /*
686 * If no IRQ domain was found via the OF tree, try looking it up
687 * directly through the fwnode_handle.
688 */
689 if (!d) {
690 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
691
692 if (fwnode)
693 d = irq_find_matching_fwnode(fwnode,
694 DOMAIN_BUS_PCI_MSI);
695 }
696#endif
697
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100698 return d;
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100699}
700
701static void pci_set_bus_msi_domain(struct pci_bus *bus)
702{
703 struct irq_domain *d;
Alex Williamson38ea72b2015-09-18 15:08:54 -0600704 struct pci_bus *b;
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100705
706 /*
Alex Williamson38ea72b2015-09-18 15:08:54 -0600707 * The bus can be a root bus, a subordinate bus, or a virtual bus
708 * created by an SR-IOV device. Walk up to the first bridge device
709 * found or derive the domain from the host bridge.
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100710 */
Alex Williamson38ea72b2015-09-18 15:08:54 -0600711 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
712 if (b->self)
713 d = dev_get_msi_domain(&b->self->dev);
714 }
715
716 if (!d)
717 d = pci_host_bridge_msi_domain(b);
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100718
719 dev_set_msi_domain(&bus->dev, d);
720}
721
Thierry Redinga52d1442016-11-25 11:57:11 +0100722int pci_register_host_bridge(struct pci_host_bridge *bridge)
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100723{
724 struct device *parent = bridge->dev.parent;
725 struct resource_entry *window, *n;
726 struct pci_bus *bus, *b;
727 resource_size_t offset;
728 LIST_HEAD(resources);
729 struct resource *res;
730 char addr[64], *fmt;
731 const char *name;
732 int err;
733
734 bus = pci_alloc_bus(NULL);
735 if (!bus)
736 return -ENOMEM;
737
738 bridge->bus = bus;
739
740 /* temporarily move resources off the list */
741 list_splice_init(&bridge->windows, &resources);
742 bus->sysdata = bridge->sysdata;
743 bus->msi = bridge->msi;
744 bus->ops = bridge->ops;
745 bus->number = bus->busn_res.start = bridge->busnr;
746#ifdef CONFIG_PCI_DOMAINS_GENERIC
747 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
748#endif
749
750 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
751 if (b) {
752 /* If we already got to this bus through a different bridge, ignore it */
753 dev_dbg(&b->dev, "bus already known\n");
754 err = -EEXIST;
755 goto free;
756 }
757
758 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
759 bridge->busnr);
760
761 err = pcibios_root_bridge_prepare(bridge);
762 if (err)
763 goto free;
764
765 err = device_register(&bridge->dev);
766 if (err)
767 put_device(&bridge->dev);
768
769 bus->bridge = get_device(&bridge->dev);
770 device_enable_async_suspend(bus->bridge);
771 pci_set_bus_of_node(bus);
772 pci_set_bus_msi_domain(bus);
773
774 if (!parent)
775 set_dev_node(bus->bridge, pcibus_to_node(bus));
776
777 bus->dev.class = &pcibus_class;
778 bus->dev.parent = bus->bridge;
779
780 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
781 name = dev_name(&bus->dev);
782
783 err = device_register(&bus->dev);
784 if (err)
785 goto unregister;
786
787 pcibios_add_bus(bus);
788
789 /* Create legacy_io and legacy_mem files for this bus */
790 pci_create_legacy_files(bus);
791
792 if (parent)
793 dev_info(parent, "PCI host bridge to bus %s\n", name);
794 else
795 pr_info("PCI host bridge to bus %s\n", name);
796
797 /* Add initial resources to the bus */
798 resource_list_for_each_entry_safe(window, n, &resources) {
799 list_move_tail(&window->node, &bridge->windows);
800 offset = window->offset;
801 res = window->res;
802
803 if (res->flags & IORESOURCE_BUS)
804 pci_bus_insert_busn_res(bus, bus->number, res->end);
805 else
806 pci_bus_add_resource(bus, res, 0);
807
808 if (offset) {
809 if (resource_type(res) == IORESOURCE_IO)
810 fmt = " (bus address [%#06llx-%#06llx])";
811 else
812 fmt = " (bus address [%#010llx-%#010llx])";
813
814 snprintf(addr, sizeof(addr), fmt,
815 (unsigned long long)(res->start - offset),
816 (unsigned long long)(res->end - offset));
817 } else
818 addr[0] = '\0';
819
820 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
821 }
822
823 down_write(&pci_bus_sem);
824 list_add_tail(&bus->node, &pci_root_buses);
825 up_write(&pci_bus_sem);
826
827 return 0;
828
829unregister:
830 put_device(&bridge->dev);
831 device_unregister(&bridge->dev);
832
833free:
834 kfree(bus);
835 return err;
836}
Thierry Redinga52d1442016-11-25 11:57:11 +0100837EXPORT_SYMBOL(pci_register_host_bridge);
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100838
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700839static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
840 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841{
842 struct pci_bus *child;
843 int i;
Yinghai Lu4f535092013-01-21 13:20:52 -0800844 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845
846 /*
847 * Allocate a new bus, and inherit stuff from the parent..
848 */
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100849 child = pci_alloc_bus(parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 if (!child)
851 return NULL;
852
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 child->parent = parent;
854 child->ops = parent->ops;
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200855 child->msi = parent->msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200857 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400859 /* initialize some portions of the bus device, but don't register it
Yinghai Lu4f535092013-01-21 13:20:52 -0800860 * now as the parent is not properly set up yet.
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400861 */
862 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100863 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864
865 /*
866 * Set up the primary, secondary and subordinate
867 * bus numbers.
868 */
Yinghai Lub918c622012-05-17 18:51:11 -0700869 child->number = child->busn_res.start = busnr;
870 child->primary = parent->busn_res.start;
871 child->busn_res.end = 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872
Yinghai Lu4f535092013-01-21 13:20:52 -0800873 if (!bridge) {
874 child->dev.parent = parent->bridge;
875 goto add_dev;
876 }
Yu Zhao3789fa82008-11-22 02:41:07 +0800877
878 child->self = bridge;
879 child->bridge = get_device(&bridge->dev);
Yinghai Lu4f535092013-01-21 13:20:52 -0800880 child->dev.parent = child->bridge;
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +1000881 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500882 pci_set_bus_speed(child);
883
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800885 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
887 child->resource[i]->name = child->name;
888 }
889 bridge->subordinate = child;
890
Yinghai Lu4f535092013-01-21 13:20:52 -0800891add_dev:
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100892 pci_set_bus_msi_domain(child);
Yinghai Lu4f535092013-01-21 13:20:52 -0800893 ret = device_register(&child->dev);
894 WARN_ON(ret < 0);
895
Jiang Liu10a95742013-04-12 05:44:20 +0000896 pcibios_add_bus(child);
897
Thierry Reding057bd2e2016-02-09 15:30:47 +0100898 if (child->ops->add_bus) {
899 ret = child->ops->add_bus(child);
900 if (WARN_ON(ret < 0))
901 dev_err(&child->dev, "failed to add bus: %d\n", ret);
902 }
903
Yinghai Lu4f535092013-01-21 13:20:52 -0800904 /* Create legacy_io and legacy_mem files for this bus */
905 pci_create_legacy_files(child);
906
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 return child;
908}
909
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400910struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
911 int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912{
913 struct pci_bus *child;
914
915 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700916 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800917 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800919 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700920 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921 return child;
922}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600923EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
Rajat Jainf3dbd802014-09-02 16:26:00 -0700925static void pci_enable_crs(struct pci_dev *pdev)
926{
927 u16 root_cap = 0;
928
929 /* Enable CRS Software Visibility if supported */
930 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
931 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
932 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
933 PCI_EXP_RTCTL_CRSSVE);
934}
935
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936/*
937 * If it's a bridge, configure it and scan the bus behind it.
938 * For CardBus bridges, we don't scan behind as the devices will
939 * be handled by the bridge driver itself.
940 *
941 * We need to process bridges in two passes -- first we scan those
942 * already configured by the BIOS and after we are done with all of
943 * them, we proceed to assigning numbers to the remaining buses in
944 * order to avoid overlaps between old and new bus numbers.
945 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500946int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947{
948 struct pci_bus *child;
949 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100950 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600952 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100953 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954
Mika Westerbergd963f652016-06-02 11:17:13 +0300955 /*
956 * Make sure the bridge is powered on to be able to access config
957 * space of devices below it.
958 */
959 pm_runtime_get_sync(&dev->dev);
960
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600962 primary = buses & 0xFF;
963 secondary = (buses >> 8) & 0xFF;
964 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600966 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
967 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968
Yinghai Lu71f6bd42012-01-30 12:25:24 +0100969 if (!primary && (primary != bus->number) && secondary && subordinate) {
970 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
971 primary = bus->number;
972 }
973
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100974 /* Check if setup is sensible at all */
975 if (!pass &&
Yinghai Lu1965f662012-09-10 17:19:33 -0700976 (primary != bus->number || secondary <= bus->number ||
Bjorn Helgaas12d87062014-09-19 11:08:40 -0600977 secondary > subordinate)) {
Yinghai Lu1965f662012-09-10 17:19:33 -0700978 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
979 secondary, subordinate);
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100980 broken = 1;
981 }
982
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983 /* Disable MasterAbortMode during probing to avoid reporting
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700984 of bus errors (in some architectures) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
986 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
987 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
988
Rajat Jainf3dbd802014-09-02 16:26:00 -0700989 pci_enable_crs(dev);
990
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600991 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
992 !is_cardbus && !broken) {
993 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994 /*
995 * Bus already configured by firmware, process it in the first
996 * pass and just note the configuration.
997 */
998 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000999 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000
1001 /*
Andreas Noever2ed85822014-01-23 21:59:22 +01001002 * The bus might already exist for two reasons: Either we are
1003 * rescanning the bus or the bus is reachable through more than
1004 * one bridge. The second case can happen with the i450NX
1005 * chipset.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001007 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -06001008 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001009 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -06001010 if (!child)
1011 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001012 child->primary = primary;
Yinghai Lubc76b732012-05-17 18:51:13 -07001013 pci_bus_insert_busn_res(child, secondary, subordinate);
Alex Chiang74710de2009-03-20 14:56:10 -06001014 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 }
1016
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017 cmax = pci_scan_child_bus(child);
Andreas Noeverc95b0bd2014-01-23 21:59:27 +01001018 if (cmax > subordinate)
1019 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1020 subordinate, cmax);
1021 /* subordinate should equal child->busn_res.end */
1022 if (subordinate > max)
1023 max = subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 } else {
1025 /*
1026 * We need to assign a number to this bus which we always
1027 * do in the second pass.
1028 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -07001029 if (!pass) {
Andreas Noever619c8c32014-01-23 21:59:23 +01001030 if (pcibios_assign_all_busses() || broken || is_cardbus)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -07001031 /* Temporarily disable forwarding of the
1032 configuration cycles on all bridges in
1033 this bus segment to avoid possible
1034 conflicts in the second pass between two
1035 bridges programmed with overlapping
1036 bus ranges. */
1037 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1038 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +00001039 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -07001040 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041
1042 /* Clear errors */
1043 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1044
Bjorn Helgaas7a0b33d2014-09-19 10:56:06 -06001045 /* Prevent assigning a bus number that already exists.
1046 * This can happen when a bridge is hot-plugged, so in
1047 * this case we only re-scan this bus. */
Tiejun Chenb1a98b62011-06-02 11:02:50 +08001048 child = pci_find_bus(pci_domain_nr(bus), max+1);
1049 if (!child) {
Andreas Noever9a4d7d82014-01-23 21:59:21 +01001050 child = pci_add_new_bus(bus, dev, max+1);
Tiejun Chenb1a98b62011-06-02 11:02:50 +08001051 if (!child)
1052 goto out;
Bjorn Helgaas12d87062014-09-19 11:08:40 -06001053 pci_bus_insert_busn_res(child, max+1, 0xff);
Tiejun Chenb1a98b62011-06-02 11:02:50 +08001054 }
Andreas Noever9a4d7d82014-01-23 21:59:21 +01001055 max++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 buses = (buses & 0xff000000)
1057 | ((unsigned int)(child->primary) << 0)
Yinghai Lub918c622012-05-17 18:51:11 -07001058 | ((unsigned int)(child->busn_res.start) << 8)
1059 | ((unsigned int)(child->busn_res.end) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060
1061 /*
1062 * yenta.c forces a secondary latency timer of 176.
1063 * Copy that behaviour here.
1064 */
1065 if (is_cardbus) {
1066 buses &= ~0xff000000;
1067 buses |= CARDBUS_LATENCY_TIMER << 24;
1068 }
Jesper Juhl7c867c82011-01-24 21:14:33 +01001069
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 /*
1071 * We need to blast all three values with a single write.
1072 */
1073 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1074
1075 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -07001076 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 max = pci_scan_child_bus(child);
1078 } else {
1079 /*
1080 * For CardBus bridges, we leave 4 bus numbers
1081 * as cards with a PCI-to-PCI bridge can be
1082 * inserted later.
1083 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001084 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
Dominik Brodowski49887942005-12-08 16:53:12 +01001085 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -07001086 if (pci_find_bus(pci_domain_nr(bus),
1087 max+i+1))
1088 break;
Dominik Brodowski49887942005-12-08 16:53:12 +01001089 while (parent->parent) {
1090 if ((!pcibios_assign_all_busses()) &&
Yinghai Lub918c622012-05-17 18:51:11 -07001091 (parent->busn_res.end > max) &&
1092 (parent->busn_res.end <= max+i)) {
Dominik Brodowski49887942005-12-08 16:53:12 +01001093 j = 1;
1094 }
1095 parent = parent->parent;
1096 }
1097 if (j) {
1098 /*
1099 * Often, there are two cardbus bridges
1100 * -- try to leave one valid bus number
1101 * for each one.
1102 */
1103 i /= 2;
1104 break;
1105 }
1106 }
Rajesh Shahcc574502005-04-28 00:25:47 -07001107 max += i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108 }
1109 /*
1110 * Set the subordinate bus number to its real value.
1111 */
Yinghai Lubc76b732012-05-17 18:51:13 -07001112 pci_bus_update_busn_res_end(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1114 }
1115
Gary Hadecb3576f2008-02-08 14:00:52 -08001116 sprintf(child->name,
1117 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1118 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119
Bernhard Kaindld55bef512007-07-30 20:35:13 +02001120 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +01001121 while (bus->parent) {
Yinghai Lub918c622012-05-17 18:51:11 -07001122 if ((child->busn_res.end > bus->busn_res.end) ||
1123 (child->number > bus->busn_res.end) ||
Dominik Brodowski49887942005-12-08 16:53:12 +01001124 (child->number < bus->number) ||
Yinghai Lub918c622012-05-17 18:51:11 -07001125 (child->busn_res.end < bus->number)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001126 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
Yinghai Lub918c622012-05-17 18:51:11 -07001127 &child->busn_res,
1128 (bus->number > child->busn_res.end &&
1129 bus->busn_res.end < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -08001130 "wholly" : "partially",
1131 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -07001132 dev_name(&bus->dev),
Yinghai Lub918c622012-05-17 18:51:11 -07001133 &bus->busn_res);
Dominik Brodowski49887942005-12-08 16:53:12 +01001134 }
1135 bus = bus->parent;
1136 }
1137
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +00001138out:
1139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1140
Mika Westerbergd963f652016-06-02 11:17:13 +03001141 pm_runtime_put(&dev->dev);
1142
Linus Torvalds1da177e2005-04-16 15:20:36 -07001143 return max;
1144}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001145EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146
1147/*
1148 * Read interrupt line and base address registers.
1149 * The architecture-dependent code can tweak these, of course.
1150 */
1151static void pci_read_irq(struct pci_dev *dev)
1152{
1153 unsigned char irq;
1154
1155 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -08001156 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 if (irq)
1158 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1159 dev->irq = irq;
1160}
1161
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +00001162void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +08001163{
1164 int pos;
1165 u16 reg16;
Yijing Wangd0751b92015-05-21 15:05:02 +08001166 int type;
1167 struct pci_dev *parent;
Yu Zhao480b93b2009-03-20 11:25:14 +08001168
1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1170 if (!pos)
1171 return;
Bjorn Helgaas51ebfc92017-01-11 09:11:53 -06001172
Kenji Kaneshige0efea002009-11-05 12:05:11 +09001173 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +08001174 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
Yijing Wang786e2282012-07-24 17:20:02 +08001175 pdev->pcie_flags_reg = reg16;
Jon Masonb03e7492011-07-20 15:20:54 -05001176 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1177 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yijing Wangd0751b92015-05-21 15:05:02 +08001178
1179 /*
Bjorn Helgaas51ebfc92017-01-11 09:11:53 -06001180 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1181 * of a Link. No PCIe component has two Links. Two Links are
1182 * connected by a Switch that has a Port on each Link and internal
1183 * logic to connect the two Ports.
Yijing Wangd0751b92015-05-21 15:05:02 +08001184 */
1185 type = pci_pcie_type(pdev);
Bjorn Helgaas51ebfc92017-01-11 09:11:53 -06001186 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1187 type == PCI_EXP_TYPE_PCIE_BRIDGE)
Yijing Wangd0751b92015-05-21 15:05:02 +08001188 pdev->has_secondary_link = 1;
1189 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1190 type == PCI_EXP_TYPE_DOWNSTREAM) {
1191 parent = pci_upstream_bridge(pdev);
Yijing Wangb35b1df2015-08-17 18:47:58 +08001192
1193 /*
1194 * Usually there's an upstream device (Root Port or Switch
1195 * Downstream Port), but we can't assume one exists.
1196 */
1197 if (parent && !parent->has_secondary_link)
Yijing Wangd0751b92015-05-21 15:05:02 +08001198 pdev->has_secondary_link = 1;
1199 }
Yu Zhao480b93b2009-03-20 11:25:14 +08001200}
1201
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +00001202void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -07001203{
Eric W. Biederman28760482009-09-09 14:09:24 -07001204 u32 reg32;
1205
Jiang Liu59875ae2012-07-24 17:20:06 +08001206 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
Eric W. Biederman28760482009-09-09 14:09:24 -07001207 if (reg32 & PCI_EXP_SLTCAP_HPC)
1208 pdev->is_hotplug_bridge = 1;
1209}
1210
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001211/**
Alex Williamson78916b02014-05-05 14:20:51 -06001212 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1213 * @dev: PCI device
1214 *
1215 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1216 * when forwarding a type1 configuration request the bridge must check that
1217 * the extended register address field is zero. The bridge is not permitted
1218 * to forward the transactions and must handle it as an Unsupported Request.
1219 * Some bridges do not follow this rule and simply drop the extended register
1220 * bits, resulting in the standard config space being aliased, every 256
1221 * bytes across the entire configuration space. Test for this condition by
1222 * comparing the first dword of each potential alias to the vendor/device ID.
1223 * Known offenders:
1224 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1225 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1226 */
1227static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1228{
1229#ifdef CONFIG_PCI_QUIRKS
1230 int pos;
1231 u32 header, tmp;
1232
1233 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1234
1235 for (pos = PCI_CFG_SPACE_SIZE;
1236 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1237 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1238 || header != tmp)
1239 return false;
1240 }
1241
1242 return true;
1243#else
1244 return false;
1245#endif
1246}
1247
1248/**
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001249 * pci_cfg_space_size - get the configuration space size of the PCI device.
1250 * @dev: PCI device
1251 *
1252 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1253 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1254 * access it. Maybe we don't have a way to generate extended config space
1255 * accesses, or the device is behind a reverse Express bridge. So we try
1256 * reading the dword at 0x100 which must either be 0 or a valid extended
1257 * capability header.
1258 */
1259static int pci_cfg_space_size_ext(struct pci_dev *dev)
1260{
1261 u32 status;
1262 int pos = PCI_CFG_SPACE_SIZE;
1263
1264 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001265 return PCI_CFG_SPACE_SIZE;
Alex Williamson78916b02014-05-05 14:20:51 -06001266 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001267 return PCI_CFG_SPACE_SIZE;
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001268
1269 return PCI_CFG_SPACE_EXP_SIZE;
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001270}
1271
1272int pci_cfg_space_size(struct pci_dev *dev)
1273{
1274 int pos;
1275 u32 status;
1276 u16 class;
1277
1278 class = dev->class >> 8;
1279 if (class == PCI_CLASS_BRIDGE_HOST)
1280 return pci_cfg_space_size_ext(dev);
1281
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001282 if (pci_is_pcie(dev))
1283 return pci_cfg_space_size_ext(dev);
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001284
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001285 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1286 if (!pos)
1287 return PCI_CFG_SPACE_SIZE;
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001288
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001289 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1290 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1291 return pci_cfg_space_size_ext(dev);
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001292
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001293 return PCI_CFG_SPACE_SIZE;
1294}
1295
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +02001296#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -08001297
Guilherme G. Piccolie80e7ed2015-10-21 12:17:35 -02001298static void pci_msi_setup_pci_dev(struct pci_dev *dev)
Michael S. Tsirkin18516172015-05-07 09:52:21 -05001299{
1300 /*
1301 * Disable the MSI hardware to avoid screaming interrupts
1302 * during boot. This is the power on reset default so
1303 * usually this should be a noop.
1304 */
1305 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1306 if (dev->msi_cap)
1307 pci_msi_set_enable(dev, 0);
1308
1309 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1310 if (dev->msix_cap)
1311 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1312}
1313
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314/**
1315 * pci_setup_device - fill in class and map information of a device
1316 * @dev: the device structure to fill
1317 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001318 * Initialize the device structure with information about the device's
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1320 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +08001321 * Returns 0 on success and negative if unknown type of device (not normal,
1322 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001323 */
Yu Zhao480b93b2009-03-20 11:25:14 +08001324int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325{
1326 u32 class;
Bjorn Helgaasb84106b2016-02-25 14:35:57 -06001327 u16 cmd;
Yu Zhao480b93b2009-03-20 11:25:14 +08001328 u8 hdr_type;
Gabe Blackbc577d22009-10-06 10:45:19 -05001329 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001330 struct pci_bus_region region;
1331 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +08001332
1333 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1334 return -EIO;
1335
1336 dev->sysdata = dev->bus->sysdata;
1337 dev->dev.parent = dev->bus->bridge;
1338 dev->dev.bus = &pci_bus_type;
1339 dev->hdr_type = hdr_type & 0x7f;
1340 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +08001341 dev->error_state = pci_channel_io_normal;
1342 set_pcie_port_type(dev);
1343
Yijing Wang017ffe62015-07-17 17:16:32 +08001344 pci_dev_assign_slot(dev);
Yu Zhao480b93b2009-03-20 11:25:14 +08001345 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1346 set this higher, assuming the system even supports it. */
1347 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -07001349 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1350 dev->bus->number, PCI_SLOT(dev->devfn),
1351 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352
1353 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -07001354 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001355 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001357 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1358 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359
Yu Zhao853346e2009-03-21 22:05:11 +08001360 /* need to have dev->class ready */
1361 dev->cfg_size = pci_cfg_space_size(dev);
1362
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -07001364 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365
1366 /* Early fixups, before probing the BARs */
1367 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +08001368 /* device class may be changed after fixup */
1369 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370
Bjorn Helgaasb84106b2016-02-25 14:35:57 -06001371 if (dev->non_compliant_bars) {
1372 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1373 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1374 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1375 cmd &= ~PCI_COMMAND_IO;
1376 cmd &= ~PCI_COMMAND_MEMORY;
1377 pci_write_config_word(dev, PCI_COMMAND, cmd);
1378 }
1379 }
1380
Linus Torvalds1da177e2005-04-16 15:20:36 -07001381 switch (dev->hdr_type) { /* header type */
1382 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1383 if (class == PCI_CLASS_BRIDGE_PCI)
1384 goto bad;
1385 pci_read_irq(dev);
1386 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1387 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1388 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +01001389
1390 /*
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001391 * Do the ugly legacy mode stuff here rather than broken chip
1392 * quirk code. Legacy mode ATA controllers have fixed
1393 * addresses. These are not always echoed in BAR0-3, and
1394 * BAR0-3 in a few cases contain junk!
Alan Cox368c73d2006-10-04 00:41:26 +01001395 */
1396 if (class == PCI_CLASS_STORAGE_IDE) {
1397 u8 progif;
1398 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1399 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001400 region.start = 0x1F0;
1401 region.end = 0x1F7;
1402 res = &dev->resource[0];
1403 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001404 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001405 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1406 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001407 region.start = 0x3F6;
1408 region.end = 0x3F6;
1409 res = &dev->resource[1];
1410 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001411 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001412 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1413 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001414 }
1415 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001416 region.start = 0x170;
1417 region.end = 0x177;
1418 res = &dev->resource[2];
1419 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001420 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001421 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1422 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001423 region.start = 0x376;
1424 region.end = 0x376;
1425 res = &dev->resource[3];
1426 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001427 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001428 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1429 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001430 }
1431 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 break;
1433
1434 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1435 if (class != PCI_CLASS_BRIDGE_PCI)
1436 goto bad;
1437 /* The PCI-to-PCI bridge spec requires that subtractive
1438 decoding (i.e. transparent) bridge must have programming
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001439 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001440 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441 dev->transparent = ((dev->class & 0xff) == 1);
1442 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -07001443 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001444 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1445 if (pos) {
1446 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1447 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1448 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 break;
1450
1451 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1452 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1453 goto bad;
1454 pci_read_irq(dev);
1455 pci_read_bases(dev, 1, 0);
1456 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1457 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1458 break;
1459
1460 default: /* unknown header */
Ryan Desfosses227f0642014-04-18 20:13:50 -04001461 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1462 dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001463 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464
1465 bad:
Ryan Desfosses227f0642014-04-18 20:13:50 -04001466 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1467 dev->class, dev->hdr_type);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05001468 dev->class = PCI_CLASS_NOT_DEFINED << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469 }
1470
1471 /* We found a fine healthy device, go go go... */
1472 return 0;
1473}
1474
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001475static void pci_configure_mps(struct pci_dev *dev)
1476{
1477 struct pci_dev *bridge = pci_upstream_bridge(dev);
Keith Busch27d868b2015-08-24 08:48:16 -05001478 int mps, p_mps, rc;
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001479
1480 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1481 return;
1482
1483 mps = pcie_get_mps(dev);
1484 p_mps = pcie_get_mps(bridge);
1485
1486 if (mps == p_mps)
1487 return;
1488
1489 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1490 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1491 mps, pci_name(bridge), p_mps);
1492 return;
1493 }
Keith Busch27d868b2015-08-24 08:48:16 -05001494
1495 /*
1496 * Fancier MPS configuration is done later by
1497 * pcie_bus_configure_settings()
1498 */
1499 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1500 return;
1501
1502 rc = pcie_set_mps(dev, p_mps);
1503 if (rc) {
1504 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1505 p_mps);
1506 return;
1507 }
1508
1509 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1510 p_mps, mps, 128 << dev->pcie_mpss);
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001511}
1512
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001513static struct hpp_type0 pci_default_type0 = {
1514 .revision = 1,
1515 .cache_line_size = 8,
1516 .latency_timer = 0x40,
1517 .enable_serr = 0,
1518 .enable_perr = 0,
1519};
1520
1521static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1522{
1523 u16 pci_cmd, pci_bctl;
1524
Bjorn Helgaasc6285fc2014-08-29 18:10:19 -06001525 if (!hpp)
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001526 hpp = &pci_default_type0;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001527
1528 if (hpp->revision > 1) {
1529 dev_warn(&dev->dev,
1530 "PCI settings rev %d not supported; using defaults\n",
1531 hpp->revision);
1532 hpp = &pci_default_type0;
1533 }
1534
1535 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1536 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1537 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1538 if (hpp->enable_serr)
1539 pci_cmd |= PCI_COMMAND_SERR;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001540 if (hpp->enable_perr)
1541 pci_cmd |= PCI_COMMAND_PARITY;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001542 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1543
1544 /* Program bridge control value */
1545 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1546 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1547 hpp->latency_timer);
1548 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1549 if (hpp->enable_serr)
1550 pci_bctl |= PCI_BRIDGE_CTL_SERR;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001551 if (hpp->enable_perr)
1552 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001553 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1554 }
1555}
1556
1557static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1558{
1559 if (hpp)
1560 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1561}
1562
Johannes Thumshirne42010d2016-11-23 10:56:28 -06001563static bool pcie_root_rcb_set(struct pci_dev *dev)
1564{
1565 struct pci_dev *rp = pcie_find_root_port(dev);
1566 u16 lnkctl;
1567
1568 if (!rp)
1569 return false;
1570
1571 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1572 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1573 return true;
1574
1575 return false;
1576}
1577
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001578static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1579{
1580 int pos;
1581 u32 reg32;
1582
1583 if (!hpp)
1584 return;
1585
1586 if (hpp->revision > 1) {
1587 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1588 hpp->revision);
1589 return;
1590 }
1591
Bjorn Helgaas302328c2014-09-03 13:26:29 -06001592 /*
1593 * Don't allow _HPX to change MPS or MRRS settings. We manage
1594 * those to make sure they're consistent with the rest of the
1595 * platform.
1596 */
1597 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1598 PCI_EXP_DEVCTL_READRQ;
1599 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1600 PCI_EXP_DEVCTL_READRQ);
1601
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001602 /* Initialize Device Control Register */
1603 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1604 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1605
1606 /* Initialize Link Control Register */
Johannes Thumshirne42010d2016-11-23 10:56:28 -06001607 if (pcie_cap_has_lnkctl(dev)) {
1608
1609 /*
1610 * If the Root Port supports Read Completion Boundary of
1611 * 128, set RCB to 128. Otherwise, clear it.
1612 */
1613 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1614 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1615 if (pcie_root_rcb_set(dev))
1616 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1617
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001618 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1619 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
Johannes Thumshirne42010d2016-11-23 10:56:28 -06001620 }
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001621
1622 /* Find Advanced Error Reporting Enhanced Capability */
1623 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1624 if (!pos)
1625 return;
1626
1627 /* Initialize Uncorrectable Error Mask Register */
1628 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1629 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1630 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1631
1632 /* Initialize Uncorrectable Error Severity Register */
1633 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1634 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1635 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1636
1637 /* Initialize Correctable Error Mask Register */
1638 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1639 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1640 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1641
1642 /* Initialize Advanced Error Capabilities and Control Register */
1643 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1644 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1645 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1646
1647 /*
1648 * FIXME: The following two registers are not supported yet.
1649 *
1650 * o Secondary Uncorrectable Error Severity Register
1651 * o Secondary Uncorrectable Error Mask Register
1652 */
1653}
1654
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001655static void pci_configure_device(struct pci_dev *dev)
1656{
1657 struct hotplug_params hpp;
1658 int ret;
1659
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001660 pci_configure_mps(dev);
1661
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001662 memset(&hpp, 0, sizeof(hpp));
1663 ret = pci_get_hp_params(dev, &hpp);
1664 if (ret)
1665 return;
1666
1667 program_hpp_type2(dev, hpp.t2);
1668 program_hpp_type1(dev, hpp.t1);
1669 program_hpp_type0(dev, hpp.t0);
1670}
1671
Zhao, Yu201de562008-10-13 19:49:55 +08001672static void pci_release_capabilities(struct pci_dev *dev)
1673{
1674 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001675 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08001676 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001677}
1678
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679/**
1680 * pci_release_dev - free a pci device structure when all users of it are finished.
1681 * @dev: device that's been disconnected
1682 *
1683 * Will be called only by the device core when all users of this pci device are
1684 * done.
1685 */
1686static void pci_release_dev(struct device *dev)
1687{
Rafael J. Wysocki04480092014-02-01 15:38:29 +01001688 struct pci_dev *pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689
Rafael J. Wysocki04480092014-02-01 15:38:29 +01001690 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001691 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001692 pci_release_of_node(pci_dev);
Sebastian Ott6ae32c52013-06-04 19:18:14 +02001693 pcibios_release_device(pci_dev);
Gu Zheng8b1fce02013-05-25 21:48:31 +08001694 pci_bus_put(pci_dev->bus);
Alex Williamson782a9852014-05-20 08:53:21 -06001695 kfree(pci_dev->driver_override);
Jacek Lawrynowicz338c3142016-03-03 15:38:02 +01001696 kfree(pci_dev->dma_alias_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697 kfree(pci_dev);
1698}
1699
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001700struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
Michael Ellerman65891212007-04-05 17:19:08 +10001701{
1702 struct pci_dev *dev;
1703
1704 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1705 if (!dev)
1706 return NULL;
1707
Michael Ellerman65891212007-04-05 17:19:08 +10001708 INIT_LIST_HEAD(&dev->bus_list);
Brian King88e7b162013-04-08 03:05:07 +00001709 dev->dev.type = &pci_dev_type;
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001710 dev->bus = pci_bus_get(bus);
Michael Ellerman65891212007-04-05 17:19:08 +10001711
1712 return dev;
1713}
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001714EXPORT_SYMBOL(pci_alloc_dev);
1715
Yinghai Luefdc87d2012-01-27 10:55:10 -08001716bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001717 int crs_timeout)
Yinghai Luefdc87d2012-01-27 10:55:10 -08001718{
1719 int delay = 1;
1720
1721 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1722 return false;
1723
1724 /* some broken boards return 0 or ~0 if a slot is empty: */
1725 if (*l == 0xffffffff || *l == 0x00000000 ||
1726 *l == 0x0000ffff || *l == 0xffff0000)
1727 return false;
1728
Rajat Jain89665a62014-09-08 14:19:49 -07001729 /*
1730 * Configuration Request Retry Status. Some root ports return the
1731 * actual device ID instead of the synthetic ID (0xFFFF) required
1732 * by the PCIe spec. Ignore the device ID and only check for
1733 * (vendor id == 1).
1734 */
1735 while ((*l & 0xffff) == 0x0001) {
Yinghai Luefdc87d2012-01-27 10:55:10 -08001736 if (!crs_timeout)
1737 return false;
1738
1739 msleep(delay);
1740 delay *= 2;
1741 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1742 return false;
1743 /* Card hasn't responded in 60 seconds? Must be stuck. */
1744 if (delay > crs_timeout) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001745 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1746 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1747 PCI_FUNC(devfn));
Yinghai Luefdc87d2012-01-27 10:55:10 -08001748 return false;
1749 }
1750 }
1751
1752 return true;
1753}
1754EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1755
Linus Torvalds1da177e2005-04-16 15:20:36 -07001756/*
1757 * Read the config data for a PCI device, sanity-check it
1758 * and fill in the dev structure...
1759 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001760static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761{
1762 struct pci_dev *dev;
1763 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764
Yinghai Luefdc87d2012-01-27 10:55:10 -08001765 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 return NULL;
1767
Gu Zheng8b1fce02013-05-25 21:48:31 +08001768 dev = pci_alloc_dev(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769 if (!dev)
1770 return NULL;
1771
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773 dev->vendor = l & 0xffff;
1774 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001776 pci_set_of_node(dev);
1777
Yu Zhao480b93b2009-03-20 11:25:14 +08001778 if (pci_setup_device(dev)) {
Gu Zheng8b1fce02013-05-25 21:48:31 +08001779 pci_bus_put(dev->bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001780 kfree(dev);
1781 return NULL;
1782 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001783
1784 return dev;
1785}
1786
Zhao, Yu201de562008-10-13 19:49:55 +08001787static void pci_init_capabilities(struct pci_dev *dev)
1788{
Sean O. Stalley938174e2015-10-29 17:35:39 -05001789 /* Enhanced Allocation */
1790 pci_ea_init(dev);
1791
Guilherme G. Piccolie80e7ed2015-10-21 12:17:35 -02001792 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1793 pci_msi_setup_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001794
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001795 /* Buffers for saving PCIe and PCI-X capabilities */
1796 pci_allocate_cap_save_buffers(dev);
1797
Zhao, Yu201de562008-10-13 19:49:55 +08001798 /* Power Management */
1799 pci_pm_init(dev);
1800
1801 /* Vital Product Data */
Bjorn Helgaasf1cd93f2016-02-22 13:58:37 -06001802 pci_vpd_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001803
1804 /* Alternative Routing-ID Forwarding */
Yijing Wang31ab2472013-01-15 11:12:17 +08001805 pci_configure_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001806
1807 /* Single Root I/O Virtualization */
1808 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001809
Bjorn Helgaasedc90fe2015-07-17 15:05:46 -05001810 /* Address Translation Services */
1811 pci_ats_init(dev);
1812
Allen Kayae21ee62009-10-07 10:27:17 -07001813 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001814 pci_enable_acs(dev);
Taku Izumib07461a2015-09-17 10:09:37 -05001815
Jonathan Yong9bb04a02016-06-11 14:13:38 -05001816 /* Precision Time Measurement */
1817 pci_ptm_init(dev);
Bjorn Helgaas4dc2db02016-10-03 09:42:57 -05001818
Keith Busch66b80802016-09-27 16:23:34 -04001819 /* Advanced Error Reporting */
1820 pci_aer_init(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001821}
1822
Marc Zyngier098259e2015-10-02 10:19:32 +01001823/*
1824 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1825 * devices. Firmware interfaces that can select the MSI domain on a
1826 * per-device basis should be called from here.
1827 */
1828static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1829{
1830 struct irq_domain *d;
1831
1832 /*
1833 * If a domain has been set through the pcibios_add_device
1834 * callback, then this is the one (platform code knows best).
1835 */
1836 d = dev_get_msi_domain(&dev->dev);
1837 if (d)
1838 return d;
1839
Marc Zyngier54fa97e2015-10-02 14:43:06 +01001840 /*
1841 * Let's see if we have a firmware interface able to provide
1842 * the domain.
1843 */
1844 d = pci_msi_get_device_domain(dev);
1845 if (d)
1846 return d;
1847
Marc Zyngier098259e2015-10-02 10:19:32 +01001848 return NULL;
1849}
1850
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001851static void pci_set_msi_domain(struct pci_dev *dev)
1852{
Marc Zyngier098259e2015-10-02 10:19:32 +01001853 struct irq_domain *d;
1854
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001855 /*
Marc Zyngier098259e2015-10-02 10:19:32 +01001856 * If the platform or firmware interfaces cannot supply a
1857 * device-specific MSI domain, then inherit the default domain
1858 * from the host bridge itself.
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001859 */
Marc Zyngier098259e2015-10-02 10:19:32 +01001860 d = pci_dev_msi_domain(dev);
1861 if (!d)
1862 d = dev_get_msi_domain(&dev->bus->dev);
1863
1864 dev_set_msi_domain(&dev->dev, d);
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001865}
1866
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001867/**
1868 * pci_dma_configure - Setup DMA configuration
1869 * @dev: ptr to pci_dev struct of the PCI device
1870 *
1871 * Function to update PCI devices's DMA configuration using the same
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -07001872 * info from the OF node or ACPI node of host bridge's parent (if any).
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001873 */
1874static void pci_dma_configure(struct pci_dev *dev)
1875{
1876 struct device *bridge = pci_get_host_bridge_device(dev);
1877
Suravee Suthikulpanit768acd62015-11-18 16:49:52 -08001878 if (IS_ENABLED(CONFIG_OF) &&
1879 bridge->parent && bridge->parent->of_node) {
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001880 of_dma_configure(&dev->dev, bridge->parent->of_node);
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -07001881 } else if (has_acpi_companion(bridge)) {
1882 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1883 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1884
1885 if (attr == DEV_DMA_NOT_SUPPORTED)
1886 dev_warn(&dev->dev, "DMA not supported.\n");
1887 else
Lorenzo Pieralisid760a1b2016-11-21 10:01:39 +00001888 acpi_dma_configure(&dev->dev, attr);
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001889 }
1890
1891 pci_put_host_bridge_device(bridge);
1892}
1893
Sam Ravnborg96bde062007-03-26 21:53:30 -08001894void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001895{
Yinghai Lu4f535092013-01-21 13:20:52 -08001896 int ret;
1897
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001898 pci_configure_device(dev);
1899
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900 device_initialize(&dev->dev);
1901 dev->dev.release = pci_release_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902
Yinghai Lu7629d192013-01-21 13:20:44 -08001903 set_dev_node(&dev->dev, pcibus_to_node(bus));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001905 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 dev->dev.coherent_dma_mask = 0xffffffffull;
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -07001907 pci_dma_configure(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001909 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001910 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001911
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912 /* Fix up broken headers */
1913 pci_fixup_device(pci_fixup_header, dev);
1914
Yinghai Lu2069ecf2012-02-15 21:40:31 -08001915 /* moved out from quirk header fixup code */
1916 pci_reassigndev_resource_alignment(dev);
1917
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001918 /* Clear the state_saved flag. */
1919 dev->state_saved = false;
1920
Zhao, Yu201de562008-10-13 19:49:55 +08001921 /* Initialize various capabilities */
1922 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001923
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924 /*
1925 * Add the device to our list of discovered devices
1926 * and the bus list for fixup functions, etc.
1927 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001928 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001930 up_write(&pci_bus_sem);
Yinghai Lu4f535092013-01-21 13:20:52 -08001931
Yinghai Lu4f535092013-01-21 13:20:52 -08001932 ret = pcibios_add_device(dev);
1933 WARN_ON(ret < 0);
1934
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001935 /* Setup MSI irq domain */
1936 pci_set_msi_domain(dev);
1937
Yinghai Lu4f535092013-01-21 13:20:52 -08001938 /* Notifier could use PCI capabilities */
1939 dev->match_driver = false;
1940 ret = device_add(&dev->dev);
1941 WARN_ON(ret < 0);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001942}
1943
Bjorn Helgaas10874f52014-04-14 16:11:40 -06001944struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001945{
1946 struct pci_dev *dev;
1947
Trent Piepho90bdb312009-03-20 14:56:00 -06001948 dev = pci_get_slot(bus, devfn);
1949 if (dev) {
1950 pci_dev_put(dev);
1951 return dev;
1952 }
1953
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001954 dev = pci_scan_device(bus, devfn);
1955 if (!dev)
1956 return NULL;
1957
1958 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959
1960 return dev;
1961}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001962EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001963
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001964static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001965{
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001966 int pos;
1967 u16 cap = 0;
1968 unsigned next_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001969
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001970 if (pci_ari_enabled(bus)) {
1971 if (!dev)
1972 return 0;
1973 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1974 if (!pos)
1975 return 0;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001976
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001977 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1978 next_fn = PCI_ARI_CAP_NFN(cap);
1979 if (next_fn <= fn)
1980 return 0; /* protect against malformed list */
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001981
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001982 return next_fn;
1983 }
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001984
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001985 /* dev may be NULL for non-contiguous multifunction devices */
1986 if (!dev || dev->multifunction)
1987 return (fn + 1) % 8;
1988
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001989 return 0;
1990}
1991
1992static int only_one_child(struct pci_bus *bus)
1993{
1994 struct pci_dev *parent = bus->self;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001995
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001996 if (!parent || !pci_is_pcie(parent))
1997 return 0;
Yijing Wang62f87c02012-07-24 17:20:03 +08001998 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001999 return 1;
Bjorn Helgaas5bbe0292016-02-05 14:57:47 -06002000
2001 /*
2002 * PCIe downstream ports are bridges that normally lead to only a
2003 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
2004 * possible devices, not just device 0. See PCIe spec r3.0,
2005 * sec 7.3.1.
2006 */
Yijing Wang777e61e2015-05-21 15:05:04 +08002007 if (parent->has_secondary_link &&
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06002008 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002009 return 1;
2010 return 0;
2011}
2012
Linus Torvalds1da177e2005-04-16 15:20:36 -07002013/**
2014 * pci_scan_slot - scan a PCI slot on a bus for devices.
2015 * @bus: PCI bus to scan
2016 * @devfn: slot number to scan (must have zero function.)
2017 *
2018 * Scan a PCI slot on the specified PCI bus for devices, adding
2019 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08002020 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002021 *
2022 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08002024int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002026 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002027 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002028
2029 if (only_one_child(bus) && (devfn > 0))
2030 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002032 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07002033 if (!dev)
2034 return 0;
2035 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002036 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002037
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002038 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002039 dev = pci_scan_single_device(bus, devfn + fn);
2040 if (dev) {
2041 if (!dev->is_added)
2042 nr++;
2043 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002044 }
2045 }
Shaohua Li7d715a62008-02-25 09:46:41 +08002046
Shaohua Li149e1632008-07-23 10:32:31 +08002047 /* only one slot has pcie device */
2048 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08002049 pcie_aspm_init_link_state(bus->self);
2050
Linus Torvalds1da177e2005-04-16 15:20:36 -07002051 return nr;
2052}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002053EXPORT_SYMBOL(pci_scan_slot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002054
Jon Masonb03e7492011-07-20 15:20:54 -05002055static int pcie_find_smpss(struct pci_dev *dev, void *data)
2056{
2057 u8 *smpss = data;
2058
2059 if (!pci_is_pcie(dev))
2060 return 0;
2061
Yijing Wangd4aa68f2013-08-22 11:24:47 +08002062 /*
2063 * We don't have a way to change MPS settings on devices that have
2064 * drivers attached. A hot-added device might support only the minimum
2065 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2066 * where devices may be hot-added, we limit the fabric MPS to 128 so
2067 * hot-added devices will work correctly.
2068 *
2069 * However, if we hot-add a device to a slot directly below a Root
2070 * Port, it's impossible for there to be other existing devices below
2071 * the port. We don't limit the MPS in this case because we can
2072 * reconfigure MPS on both the Root Port and the hot-added device,
2073 * and there are no other devices involved.
2074 *
2075 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
Jon Masonb03e7492011-07-20 15:20:54 -05002076 */
Yijing Wangd4aa68f2013-08-22 11:24:47 +08002077 if (dev->is_hotplug_bridge &&
2078 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
Jon Masonb03e7492011-07-20 15:20:54 -05002079 *smpss = 0;
2080
2081 if (*smpss > dev->pcie_mpss)
2082 *smpss = dev->pcie_mpss;
2083
2084 return 0;
2085}
2086
2087static void pcie_write_mps(struct pci_dev *dev, int mps)
2088{
Jon Mason62f392e2011-10-14 14:56:14 -05002089 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05002090
2091 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05002092 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05002093
Yijing Wang62f87c02012-07-24 17:20:03 +08002094 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2095 dev->bus->self)
Jon Mason62f392e2011-10-14 14:56:14 -05002096 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05002097 * downstream communication will never be larger than
2098 * the MRRS. So, the MPS only needs to be configured
2099 * for the upstream communication. This being the case,
2100 * walk from the top down and set the MPS of the child
2101 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05002102 *
2103 * Configure the device MPS with the smaller of the
2104 * device MPSS or the bridge MPS (which is assumed to be
2105 * properly configured at this point to the largest
2106 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05002107 */
Jon Mason62f392e2011-10-14 14:56:14 -05002108 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05002109 }
2110
2111 rc = pcie_set_mps(dev, mps);
2112 if (rc)
2113 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2114}
2115
Jon Mason62f392e2011-10-14 14:56:14 -05002116static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05002117{
Jon Mason62f392e2011-10-14 14:56:14 -05002118 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05002119
Jon Masoned2888e2011-09-08 16:41:18 -05002120 /* In the "safe" case, do not configure the MRRS. There appear to be
2121 * issues with setting MRRS to 0 on a number of devices.
2122 */
Jon Masoned2888e2011-09-08 16:41:18 -05002123 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2124 return;
Jon Masonb03e7492011-07-20 15:20:54 -05002125
Jon Masoned2888e2011-09-08 16:41:18 -05002126 /* For Max performance, the MRRS must be set to the largest supported
2127 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05002128 * device or the bus can support. This should already be properly
2129 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05002130 */
Jon Mason62f392e2011-10-14 14:56:14 -05002131 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002132
2133 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05002134 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05002135 * If the MRRS value provided is not acceptable (e.g., too large),
2136 * shrink the value until it is acceptable to the HW.
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002137 */
Jon Masonb03e7492011-07-20 15:20:54 -05002138 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2139 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05002140 if (!rc)
2141 break;
Jon Masonb03e7492011-07-20 15:20:54 -05002142
Jon Mason62f392e2011-10-14 14:56:14 -05002143 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05002144 mrrs /= 2;
2145 }
Jon Mason62f392e2011-10-14 14:56:14 -05002146
2147 if (mrrs < 128)
Ryan Desfosses227f0642014-04-18 20:13:50 -04002148 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
Jon Masonb03e7492011-07-20 15:20:54 -05002149}
2150
2151static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2152{
Jon Masona513a992011-10-14 14:56:16 -05002153 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05002154
2155 if (!pci_is_pcie(dev))
2156 return 0;
2157
Keith Busch27d868b2015-08-24 08:48:16 -05002158 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2159 pcie_bus_config == PCIE_BUS_DEFAULT)
Yijing Wang5895af72013-08-26 16:33:06 +08002160 return 0;
Yijing Wang5895af72013-08-26 16:33:06 +08002161
Jon Masona513a992011-10-14 14:56:16 -05002162 mps = 128 << *(u8 *)data;
2163 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002164
2165 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05002166 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002167
Ryan Desfosses227f0642014-04-18 20:13:50 -04002168 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2169 pcie_get_mps(dev), 128 << dev->pcie_mpss,
Jon Masona513a992011-10-14 14:56:16 -05002170 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05002171
2172 return 0;
2173}
2174
Jon Masona513a992011-10-14 14:56:16 -05002175/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05002176 * parents then children fashion. If this changes, then this code will not
2177 * work as designed.
2178 */
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002179void pcie_bus_configure_settings(struct pci_bus *bus)
Jon Masonb03e7492011-07-20 15:20:54 -05002180{
Bjorn Helgaas1e358f92014-04-29 12:51:55 -06002181 u8 smpss = 0;
Jon Masonb03e7492011-07-20 15:20:54 -05002182
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002183 if (!bus->self)
2184 return;
2185
Jon Masonb03e7492011-07-20 15:20:54 -05002186 if (!pci_is_pcie(bus->self))
2187 return;
2188
Jon Mason5f39e672011-10-03 09:50:20 -05002189 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
Jon Mason33154722013-08-26 16:33:05 +08002190 * to be aware of the MPS of the destination. To work around this,
Jon Mason5f39e672011-10-03 09:50:20 -05002191 * simply force the MPS of the entire system to the smallest possible.
2192 */
2193 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2194 smpss = 0;
2195
Jon Masonb03e7492011-07-20 15:20:54 -05002196 if (pcie_bus_config == PCIE_BUS_SAFE) {
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002197 smpss = bus->self->pcie_mpss;
Jon Mason5f39e672011-10-03 09:50:20 -05002198
Jon Masonb03e7492011-07-20 15:20:54 -05002199 pcie_find_smpss(bus->self, &smpss);
2200 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2201 }
2202
2203 pcie_bus_configure_set(bus->self, &smpss);
2204 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2205}
Jon Masondebc3b72011-08-02 00:01:18 -05002206EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05002207
Bill Pemberton15856ad2012-11-21 15:35:00 -05002208unsigned int pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002209{
Yinghai Lub918c622012-05-17 18:51:11 -07002210 unsigned int devfn, pass, max = bus->busn_res.start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002211 struct pci_dev *dev;
2212
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002213 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214
2215 /* Go find them, Rover! */
2216 for (devfn = 0; devfn < 0x100; devfn += 8)
2217 pci_scan_slot(bus, devfn);
2218
Yu Zhaoa28724b2009-03-20 11:25:13 +08002219 /* Reserve buses for SR-IOV capability. */
2220 max += pci_iov_bus_range(bus);
2221
Linus Torvalds1da177e2005-04-16 15:20:36 -07002222 /*
2223 * After performing arch-dependent fixup of the bus, look behind
2224 * all PCI-to-PCI bridges on this bus.
2225 */
Alex Chiang74710de2009-03-20 14:56:10 -06002226 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002227 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06002228 pcibios_fixup_bus(bus);
Jiang Liu981cf9e2013-04-12 05:44:16 +00002229 bus->is_added = 1;
Alex Chiang74710de2009-03-20 14:56:10 -06002230 }
2231
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002232 for (pass = 0; pass < 2; pass++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233 list_for_each_entry(dev, &bus->devices, bus_list) {
Yijing Wang6788a512014-05-04 12:23:38 +08002234 if (pci_is_bridge(dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002235 max = pci_scan_bridge(bus, dev, max, pass);
2236 }
2237
2238 /*
Keith Busche16b4662016-07-21 21:40:28 -06002239 * Make sure a hotplug bridge has at least the minimum requested
2240 * number of buses.
2241 */
2242 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2243 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2244 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2245 }
2246
2247 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002248 * We've scanned the bus and so we know all about what's on
2249 * the other side of any bridges that may be on this bus plus
2250 * any devices.
2251 *
2252 * Return how far we've got finding sub-buses.
2253 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002254 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002255 return max;
2256}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002257EXPORT_SYMBOL_GPL(pci_scan_child_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002258
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002259/**
2260 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2261 * @bridge: Host bridge to set up.
2262 *
2263 * Default empty implementation. Replace with an architecture-specific setup
2264 * routine, if necessary.
2265 */
2266int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2267{
2268 return 0;
2269}
2270
Jiang Liu10a95742013-04-12 05:44:20 +00002271void __weak pcibios_add_bus(struct pci_bus *bus)
2272{
2273}
2274
2275void __weak pcibios_remove_bus(struct pci_bus *bus)
2276{
2277}
2278
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002279static struct pci_bus *pci_create_root_bus_msi(struct device *parent,
2280 int bus, struct pci_ops *ops, void *sysdata,
2281 struct list_head *resources, struct msi_controller *msi)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002283 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07002284 struct pci_host_bridge *bridge;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002285
Thierry Reding59094062016-11-25 11:57:10 +01002286 bridge = pci_alloc_host_bridge(0);
Yinghai Lu7b543662012-04-02 18:31:53 -07002287 if (!bridge)
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002288 return NULL;
Yinghai Lu7b543662012-04-02 18:31:53 -07002289
2290 bridge->dev.parent = parent;
Jiang Liu70efde22013-06-07 16:16:51 -06002291 bridge->dev.release = pci_release_host_bridge_dev;
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002292
2293 list_splice_init(resources, &bridge->windows);
2294 bridge->sysdata = sysdata;
2295 bridge->busnr = bus;
2296 bridge->ops = ops;
2297 bridge->msi = msi;
2298
2299 error = pci_register_host_bridge(bridge);
2300 if (error < 0)
Jiang Liu343df772013-06-07 01:10:08 +08002301 goto err_out;
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002302
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002303 return bridge->bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002304
Yinghai Lu7b543662012-04-02 18:31:53 -07002305err_out:
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002306 kfree(bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002307 return NULL;
2308}
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002309
2310struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2311 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2312{
2313 return pci_create_root_bus_msi(parent, bus, ops, sysdata, resources,
2314 NULL);
2315}
Ray Juie6b29de2015-04-08 11:21:33 -07002316EXPORT_SYMBOL_GPL(pci_create_root_bus);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002317
Yinghai Lu98a35832012-05-18 11:35:50 -06002318int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2319{
2320 struct resource *res = &b->busn_res;
2321 struct resource *parent_res, *conflict;
2322
2323 res->start = bus;
2324 res->end = bus_max;
2325 res->flags = IORESOURCE_BUS;
2326
2327 if (!pci_is_root_bus(b))
2328 parent_res = &b->parent->busn_res;
2329 else {
2330 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2331 res->flags |= IORESOURCE_PCI_FIXED;
2332 }
2333
Andreas Noeverced04d12014-01-23 21:59:24 +01002334 conflict = request_resource_conflict(parent_res, res);
Yinghai Lu98a35832012-05-18 11:35:50 -06002335
2336 if (conflict)
2337 dev_printk(KERN_DEBUG, &b->dev,
2338 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2339 res, pci_is_root_bus(b) ? "domain " : "",
2340 parent_res, conflict->name, conflict);
Yinghai Lu98a35832012-05-18 11:35:50 -06002341
2342 return conflict == NULL;
2343}
2344
2345int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2346{
2347 struct resource *res = &b->busn_res;
2348 struct resource old_res = *res;
2349 resource_size_t size;
2350 int ret;
2351
2352 if (res->start > bus_max)
2353 return -EINVAL;
2354
2355 size = bus_max - res->start + 1;
2356 ret = adjust_resource(res, res->start, size);
2357 dev_printk(KERN_DEBUG, &b->dev,
2358 "busn_res: %pR end %s updated to %02x\n",
2359 &old_res, ret ? "can not be" : "is", bus_max);
2360
2361 if (!ret && !res->parent)
2362 pci_bus_insert_busn_res(b, res->start, res->end);
2363
2364 return ret;
2365}
2366
2367void pci_bus_release_busn_res(struct pci_bus *b)
2368{
2369 struct resource *res = &b->busn_res;
2370 int ret;
2371
2372 if (!res->flags || !res->parent)
2373 return;
2374
2375 ret = release_resource(res);
2376 dev_printk(KERN_DEBUG, &b->dev,
2377 "busn_res: %pR %s released\n",
2378 res, ret ? "can not be" : "is");
2379}
2380
Lorenzo Pieralisid2a79262015-08-03 21:27:10 -05002381struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2382 struct pci_ops *ops, void *sysdata,
2383 struct list_head *resources, struct msi_controller *msi)
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002384{
Jiang Liu14d76b62015-02-05 13:44:44 +08002385 struct resource_entry *window;
Yinghai Lu4d99f522012-05-17 18:51:12 -07002386 bool found = false;
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002387 struct pci_bus *b;
Yinghai Lu4d99f522012-05-17 18:51:12 -07002388 int max;
2389
Jiang Liu14d76b62015-02-05 13:44:44 +08002390 resource_list_for_each_entry(window, resources)
Yinghai Lu4d99f522012-05-17 18:51:12 -07002391 if (window->res->flags & IORESOURCE_BUS) {
2392 found = true;
2393 break;
2394 }
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002395
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002396 b = pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, msi);
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002397 if (!b)
2398 return NULL;
2399
Yinghai Lu4d99f522012-05-17 18:51:12 -07002400 if (!found) {
2401 dev_info(&b->dev,
2402 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2403 bus);
2404 pci_bus_insert_busn_res(b, bus, 255);
2405 }
2406
2407 max = pci_scan_child_bus(b);
2408
2409 if (!found)
2410 pci_bus_update_busn_res_end(b, max);
2411
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002412 return b;
2413}
Lorenzo Pieralisid2a79262015-08-03 21:27:10 -05002414
2415struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2416 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2417{
2418 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2419 NULL);
2420}
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002421EXPORT_SYMBOL(pci_scan_root_bus);
2422
Bill Pemberton15856ad2012-11-21 15:35:00 -05002423struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002424 void *sysdata)
2425{
2426 LIST_HEAD(resources);
2427 struct pci_bus *b;
2428
2429 pci_add_resource(&resources, &ioport_resource);
2430 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07002431 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002432 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2433 if (b) {
Yinghai Lu857c3b62012-05-17 18:51:12 -07002434 pci_scan_child_bus(b);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002435 } else {
2436 pci_free_resource_list(&resources);
2437 }
2438 return b;
2439}
2440EXPORT_SYMBOL(pci_scan_bus);
2441
Alex Chiang3ed4fd92009-03-20 14:56:25 -06002442/**
Yinghai Lu2f320522012-01-21 02:08:22 -08002443 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2444 * @bridge: PCI bridge for the bus to scan
2445 *
2446 * Scan a PCI bus and child buses for new devices, add them,
2447 * and enable them, resizing bridge mmio/io resource if necessary
2448 * and possible. The caller must ensure the child devices are already
2449 * removed for resizing to occur.
2450 *
2451 * Returns the max number of subordinate bus discovered.
2452 */
Bjorn Helgaas10874f52014-04-14 16:11:40 -06002453unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
Yinghai Lu2f320522012-01-21 02:08:22 -08002454{
2455 unsigned int max;
2456 struct pci_bus *bus = bridge->subordinate;
2457
2458 max = pci_scan_child_bus(bus);
2459
2460 pci_assign_unassigned_bridge_resources(bridge);
2461
2462 pci_bus_add_devices(bus);
2463
2464 return max;
2465}
2466
Yinghai Lua5213a32012-10-30 14:31:21 -06002467/**
2468 * pci_rescan_bus - scan a PCI bus for devices.
2469 * @bus: PCI bus to scan
2470 *
2471 * Scan a PCI bus and child buses for new devices, adds them,
2472 * and enables them.
2473 *
2474 * Returns the max number of subordinate bus discovered.
2475 */
Bjorn Helgaas10874f52014-04-14 16:11:40 -06002476unsigned int pci_rescan_bus(struct pci_bus *bus)
Yinghai Lua5213a32012-10-30 14:31:21 -06002477{
2478 unsigned int max;
2479
2480 max = pci_scan_child_bus(bus);
2481 pci_assign_unassigned_bus_resources(bus);
2482 pci_bus_add_devices(bus);
2483
2484 return max;
2485}
2486EXPORT_SYMBOL_GPL(pci_rescan_bus);
2487
Rafael J. Wysocki9d169472014-01-10 15:22:18 +01002488/*
2489 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2490 * routines should always be executed under this mutex.
2491 */
2492static DEFINE_MUTEX(pci_rescan_remove_lock);
2493
2494void pci_lock_rescan_remove(void)
2495{
2496 mutex_lock(&pci_rescan_remove_lock);
2497}
2498EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2499
2500void pci_unlock_rescan_remove(void)
2501{
2502 mutex_unlock(&pci_rescan_remove_lock);
2503}
2504EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2505
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002506static int __init pci_sort_bf_cmp(const struct device *d_a,
2507 const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002508{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002509 const struct pci_dev *a = to_pci_dev(d_a);
2510 const struct pci_dev *b = to_pci_dev(d_b);
2511
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002512 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2513 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2514
2515 if (a->bus->number < b->bus->number) return -1;
2516 else if (a->bus->number > b->bus->number) return 1;
2517
2518 if (a->devfn < b->devfn) return -1;
2519 else if (a->devfn > b->devfn) return 1;
2520
2521 return 0;
2522}
2523
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08002524void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002525{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002526 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002527}