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gerrit-public.fairphone.software / kernel / msm-4.19 / 5612ac83b9d7a32a7f2967d9f6f97e7f3428dfd2 / . / arch / arm / boot / dts / omap3.dtsi
blob: a3ff4933dbc173936bbec5a222aba6642e70564d [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +0200[diff] [blame]12#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]13#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]14
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]15/ {
16 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]17 interrupt-parent = <&intc>;
Javier Martinez Canillas008a2eb2016-08-31 12:35:18 +0200[diff] [blame]18 #address-cells = <1>;
19 #size-cells = <1>;
Javier Martinez Canillas23ab4c62016-12-19 11:44:34 -0300[diff] [blame]20 chosen { };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]21
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]22 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]29 };
30
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]31 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]32 #address-cells = <1>;
33 #size-cells = <0>;
34
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]35 cpu@0 {
36 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]37 device_type = "cpu";
38 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]39
40 clocks = <&dpll1_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]44 };
45 };
46
Javier Martinez Canillas2995a9e2016-04-01 16:20:20 -0400[diff] [blame]47 pmu@54000000 {
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]48 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]49 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]50 interrupts = <3>;
51 ti,hwmods = "debugss";
52 };
53
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]54 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]55 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]56 * that are not memory mapped in the MPU view or for the MPU itself.
57 */
58 soc {
59 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]60 mpu {
61 compatible = "ti,omap3-mpu";
62 ti,hwmods = "mpu";
63 };
64
Suman Anna4c051602014-04-22 17:23:37 -0500[diff] [blame]65 iva: iva {
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]66 compatible = "ti,iva2.2";
67 ti,hwmods = "iva";
68
69 dsp {
70 compatible = "ti,omap3-c64";
71 };
72 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]73 };
74
75 /*
76 * XXX: Use a flat representation of the OMAP3 interconnect.
77 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]78 * Since it will not bring real advantage to represent that in DT for
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]79 * the moment, just use a fake OCP bus entry to represent the whole bus
80 * hierarchy.
81 */
Javier Martinez Canillasf515f812016-08-01 12:46:55 -0400[diff] [blame]82 ocp@68000000 {
Tony Lindgrenaa25729c2014-11-05 09:21:23 -0800[diff] [blame]83 compatible = "ti,omap3-l3-smx", "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]84 reg = <0x68000000 0x10000>;
85 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 ti,hwmods = "l3_main";
90
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]91 l4_core: l4@48000000 {
92 compatible = "ti,omap3-l4-core", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x48000000 0x1000000>;
96
97 scm: scm@2000 {
98 compatible = "ti,omap3-scm", "simple-bus";
99 reg = <0x2000 0x2000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0x2000 0x2000>;
103
104 omap3_pmx_core: pinmux@30 {
105 compatible = "ti,omap3-padconf",
106 "pinctrl-single";
107 reg = <0x30 0x238>;
108 #address-cells = <1>;
109 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]110 #pinctrl-cells = <1>;
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]111 #interrupt-cells = <1>;
112 interrupt-controller;
113 pinctrl-single,register-width = <16>;
114 pinctrl-single,function-mask = <0xff1f>;
115 };
116
117 scm_conf: scm_conf@270 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]118 compatible = "syscon", "simple-bus";
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]119 reg = <0x270 0x330>;
120 #address-cells = <1>;
121 #size-cells = <1>;
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]122 ranges = <0 0x270 0x330>;
123
Javier Martinez Canillas308cfda2016-04-01 16:20:18 -0400[diff] [blame]124 pbias_regulator: pbias_regulator@2b0 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]125 compatible = "ti,pbias-omap3", "ti,pbias-omap";
126 reg = <0x2b0 0x4>;
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap2430 {
129 regulator-name = "pbias_mmc_omap2430";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
132 };
133 };
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]134
135 scm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139 };
140
141 scm_clockdomains: clockdomains {
142 };
143
144 omap3_pmx_wkup: pinmux@a00 {
145 compatible = "ti,omap3-padconf",
146 "pinctrl-single";
147 reg = <0xa00 0x5c>;
148 #address-cells = <1>;
149 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]150 #pinctrl-cells = <1>;
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]151 #interrupt-cells = <1>;
152 interrupt-controller;
153 pinctrl-single,register-width = <16>;
154 pinctrl-single,function-mask = <0xff1f>;
155 };
156 };
157 };
158
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]159 aes: aes@480c5000 {
160 compatible = "ti,omap3-aes";
161 ti,hwmods = "aes";
162 reg = <0x480c5000 0x50>;
163 interrupts = <0>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]164 dmas = <&sdma 65 &sdma 66>;
165 dma-names = "tx", "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]166 };
167
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]168 prm: prm@48306000 {
169 compatible = "ti,omap3-prm";
170 reg = <0x48306000 0x4000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500[diff] [blame]171 interrupts = <11>;
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]172
173 prm_clocks: clocks {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 };
177
178 prm_clockdomains: clockdomains {
179 };
180 };
181
182 cm: cm@48004000 {
183 compatible = "ti,omap3-cm";
184 reg = <0x48004000 0x4000>;
185
186 cm_clocks: clocks {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 };
190
191 cm_clockdomains: clockdomains {
192 };
193 };
194
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]195 counter32k: counter@48320000 {
196 compatible = "ti,omap-counter32k";
197 reg = <0x48320000 0x20>;
198 ti,hwmods = "counter_32k";
199 };
200
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]201 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]202 compatible = "ti,omap3-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]203 interrupt-controller;
204 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]205 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]206 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]207
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]208 sdma: dma-controller@48056000 {
209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
210 reg = <0x48056000 0x1000>;
211 interrupts = <12>,
212 <13>,
213 <14>,
214 <15>;
215 #dma-cells = <1>;
Peter Ujfalusi7e8d25d2015-02-20 15:42:03 +0200[diff] [blame]216 dma-channels = <32>;
217 dma-requests = <96>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]218 };
219
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]220 gpio1: gpio@48310000 {
221 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]222 reg = <0x48310000 0x200>;
223 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]224 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]225 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]229 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]230 };
231
232 gpio2: gpio@49050000 {
233 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]234 reg = <0x49050000 0x200>;
235 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]236 ti,hwmods = "gpio2";
237 gpio-controller;
238 #gpio-cells = <2>;
239 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]240 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]241 };
242
243 gpio3: gpio@49052000 {
244 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]245 reg = <0x49052000 0x200>;
246 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]247 ti,hwmods = "gpio3";
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]251 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]252 };
253
254 gpio4: gpio@49054000 {
255 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]256 reg = <0x49054000 0x200>;
257 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]258 ti,hwmods = "gpio4";
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]262 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]263 };
264
265 gpio5: gpio@49056000 {
266 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]267 reg = <0x49056000 0x200>;
268 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]269 ti,hwmods = "gpio5";
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]273 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]274 };
275
276 gpio6: gpio@49058000 {
277 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]278 reg = <0x49058000 0x200>;
279 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]280 ti,hwmods = "gpio6";
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]284 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]285 };
286
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]287 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]288 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]289 reg = <0x4806a000 0x2000>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]290 interrupts-extended = <&intc 72>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]291 dmas = <&sdma 49 &sdma 50>;
292 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]293 ti,hwmods = "uart1";
294 clock-frequency = <48000000>;
295 };
296
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]297 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]298 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]299 reg = <0x4806c000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]300 interrupts-extended = <&intc 73>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]301 dmas = <&sdma 51 &sdma 52>;
302 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]303 ti,hwmods = "uart2";
304 clock-frequency = <48000000>;
305 };
306
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]307 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]308 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]309 reg = <0x49020000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]310 interrupts-extended = <&intc 74>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]311 dmas = <&sdma 53 &sdma 54>;
312 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]313 ti,hwmods = "uart3";
314 clock-frequency = <48000000>;
315 };
316
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]317 i2c1: i2c@48070000 {
318 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]319 reg = <0x48070000 0x80>;
320 interrupts = <56>;
321 dmas = <&sdma 27 &sdma 28>;
322 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]323 #address-cells = <1>;
324 #size-cells = <0>;
325 ti,hwmods = "i2c1";
326 };
327
328 i2c2: i2c@48072000 {
329 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]330 reg = <0x48072000 0x80>;
331 interrupts = <57>;
332 dmas = <&sdma 29 &sdma 30>;
333 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]334 #address-cells = <1>;
335 #size-cells = <0>;
336 ti,hwmods = "i2c2";
337 };
338
339 i2c3: i2c@48060000 {
340 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]341 reg = <0x48060000 0x80>;
342 interrupts = <61>;
343 dmas = <&sdma 25 &sdma 26>;
344 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]345 #address-cells = <1>;
346 #size-cells = <0>;
347 ti,hwmods = "i2c3";
348 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]349
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]350 mailbox: mailbox@48094000 {
351 compatible = "ti,omap3-mailbox";
352 ti,hwmods = "mailbox";
353 reg = <0x48094000 0x200>;
354 interrupts = <26>;
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]355 #mbox-cells = <1>;
Suman Anna41ffada2014-07-11 16:44:34 -0500[diff] [blame]356 ti,mbox-num-users = <2>;
357 ti,mbox-num-fifos = <2>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]358 mbox_dsp: dsp {
359 ti,mbox-tx = <0 0 0>;
360 ti,mbox-rx = <1 0 0>;
361 };
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]362 };
363
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]364 mcspi1: spi@48098000 {
365 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]366 reg = <0x48098000 0x100>;
367 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]368 #address-cells = <1>;
369 #size-cells = <0>;
370 ti,hwmods = "mcspi1";
371 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]372 dmas = <&sdma 35>,
373 <&sdma 36>,
374 <&sdma 37>,
375 <&sdma 38>,
376 <&sdma 39>,
377 <&sdma 40>,
378 <&sdma 41>,
379 <&sdma 42>;
380 dma-names = "tx0", "rx0", "tx1", "rx1",
381 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]382 };
383
384 mcspi2: spi@4809a000 {
385 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]386 reg = <0x4809a000 0x100>;
387 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]388 #address-cells = <1>;
389 #size-cells = <0>;
390 ti,hwmods = "mcspi2";
391 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]392 dmas = <&sdma 43>,
393 <&sdma 44>,
394 <&sdma 45>,
395 <&sdma 46>;
396 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]397 };
398
399 mcspi3: spi@480b8000 {
400 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]401 reg = <0x480b8000 0x100>;
402 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]403 #address-cells = <1>;
404 #size-cells = <0>;
405 ti,hwmods = "mcspi3";
406 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]407 dmas = <&sdma 15>,
408 <&sdma 16>,
409 <&sdma 23>,
410 <&sdma 24>;
411 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]412 };
413
414 mcspi4: spi@480ba000 {
415 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]416 reg = <0x480ba000 0x100>;
417 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]418 #address-cells = <1>;
419 #size-cells = <0>;
420 ti,hwmods = "mcspi4";
421 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]422 dmas = <&sdma 70>, <&sdma 71>;
423 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]424 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]425
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]426 hdqw1w: 1w@480b2000 {
427 compatible = "ti,omap3-1w";
428 reg = <0x480b2000 0x1000>;
429 interrupts = <58>;
430 ti,hwmods = "hdq1w";
431 };
432
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]433 mmc1: mmc@4809c000 {
434 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]435 reg = <0x4809c000 0x200>;
436 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]437 ti,hwmods = "mmc1";
438 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]439 dmas = <&sdma 61>, <&sdma 62>;
440 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]441 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]442 };
443
444 mmc2: mmc@480b4000 {
445 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]446 reg = <0x480b4000 0x200>;
447 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]448 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]449 dmas = <&sdma 47>, <&sdma 48>;
450 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]451 };
452
453 mmc3: mmc@480ad000 {
454 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]455 reg = <0x480ad000 0x200>;
456 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]457 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]458 dmas = <&sdma 77>, <&sdma 78>;
459 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]460 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]461
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]462 mmu_isp: mmu@480bd400 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]463 #iommu-cells = <0>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]464 compatible = "ti,omap2-iommu";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]465 reg = <0x480bd400 0x80>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]466 interrupts = <24>;
467 ti,hwmods = "mmu_isp";
468 ti,#tlb-entries = <8>;
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]469 };
470
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]471 mmu_iva: mmu@5d000000 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]472 #iommu-cells = <0>;
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]473 compatible = "ti,omap2-iommu";
474 reg = <0x5d000000 0x80>;
475 interrupts = <28>;
476 ti,hwmods = "mmu_iva";
477 status = "disabled";
478 };
479
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]480 wdt2: wdt@48314000 {
481 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]482 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]483 ti,hwmods = "wd_timer2";
484 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]485
486 mcbsp1: mcbsp@48074000 {
487 compatible = "ti,omap3-mcbsp";
488 reg = <0x48074000 0xff>;
489 reg-names = "mpu";
490 interrupts = <16>, /* OCP compliant interrupt */
491 <59>, /* TX interrupt */
492 <60>; /* RX interrupt */
493 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]494 ti,buffer-size = <128>;
495 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]496 dmas = <&sdma 31>,
497 <&sdma 32>;
498 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]499 clocks = <&mcbsp1_fck>;
500 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]501 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]502 };
503
504 mcbsp2: mcbsp@49022000 {
505 compatible = "ti,omap3-mcbsp";
506 reg = <0x49022000 0xff>,
507 <0x49028000 0xff>;
508 reg-names = "mpu", "sidetone";
509 interrupts = <17>, /* OCP compliant interrupt */
510 <62>, /* TX interrupt */
511 <63>, /* RX interrupt */
512 <4>; /* Sidetone */
513 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]514 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]515 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]516 dmas = <&sdma 33>,
517 <&sdma 34>;
518 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]519 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
520 clock-names = "fck", "ick";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]521 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]522 };
523
524 mcbsp3: mcbsp@49024000 {
525 compatible = "ti,omap3-mcbsp";
526 reg = <0x49024000 0xff>,
527 <0x4902a000 0xff>;
528 reg-names = "mpu", "sidetone";
529 interrupts = <22>, /* OCP compliant interrupt */
530 <89>, /* TX interrupt */
531 <90>, /* RX interrupt */
532 <5>; /* Sidetone */
533 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]534 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]535 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]536 dmas = <&sdma 17>,
537 <&sdma 18>;
538 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]539 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
540 clock-names = "fck", "ick";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]541 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]542 };
543
544 mcbsp4: mcbsp@49026000 {
545 compatible = "ti,omap3-mcbsp";
546 reg = <0x49026000 0xff>;
547 reg-names = "mpu";
548 interrupts = <23>, /* OCP compliant interrupt */
549 <54>, /* TX interrupt */
550 <55>; /* RX interrupt */
551 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]552 ti,buffer-size = <128>;
553 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]554 dmas = <&sdma 19>,
555 <&sdma 20>;
556 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]557 clocks = <&mcbsp4_fck>;
558 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]559 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]560 };
561
562 mcbsp5: mcbsp@48096000 {
563 compatible = "ti,omap3-mcbsp";
564 reg = <0x48096000 0xff>;
565 reg-names = "mpu";
566 interrupts = <27>, /* OCP compliant interrupt */
567 <81>, /* TX interrupt */
568 <82>; /* RX interrupt */
569 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]570 ti,buffer-size = <128>;
571 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]572 dmas = <&sdma 21>,
573 <&sdma 22>;
574 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]575 clocks = <&mcbsp5_fck>;
576 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]577 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]578 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]579
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]580 sham: sham@480c3000 {
581 compatible = "ti,omap3-sham";
582 ti,hwmods = "sham";
583 reg = <0x480c3000 0x64>;
584 interrupts = <49>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]585 dmas = <&sdma 69>;
586 dma-names = "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]587 };
588
589 smartreflex_core: smartreflex@480cb000 {
590 compatible = "ti,omap3-smartreflex-core";
591 ti,hwmods = "smartreflex_core";
592 reg = <0x480cb000 0x400>;
593 interrupts = <19>;
594 };
595
596 smartreflex_mpu_iva: smartreflex@480c9000 {
597 compatible = "ti,omap3-smartreflex-iva";
598 ti,hwmods = "smartreflex_mpu_iva";
599 reg = <0x480c9000 0x400>;
600 interrupts = <18>;
601 };
602
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]603 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]604 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]605 reg = <0x48318000 0x400>;
606 interrupts = <37>;
607 ti,hwmods = "timer1";
608 ti,timer-alwon;
609 };
610
611 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]612 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]613 reg = <0x49032000 0x400>;
614 interrupts = <38>;
615 ti,hwmods = "timer2";
616 };
617
618 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]619 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]620 reg = <0x49034000 0x400>;
621 interrupts = <39>;
622 ti,hwmods = "timer3";
623 };
624
625 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]626 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]627 reg = <0x49036000 0x400>;
628 interrupts = <40>;
629 ti,hwmods = "timer4";
630 };
631
632 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]633 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]634 reg = <0x49038000 0x400>;
635 interrupts = <41>;
636 ti,hwmods = "timer5";
637 ti,timer-dsp;
638 };
639
640 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]641 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]642 reg = <0x4903a000 0x400>;
643 interrupts = <42>;
644 ti,hwmods = "timer6";
645 ti,timer-dsp;
646 };
647
648 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]649 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]650 reg = <0x4903c000 0x400>;
651 interrupts = <43>;
652 ti,hwmods = "timer7";
653 ti,timer-dsp;
654 };
655
656 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]657 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]658 reg = <0x4903e000 0x400>;
659 interrupts = <44>;
660 ti,hwmods = "timer8";
661 ti,timer-pwm;
662 ti,timer-dsp;
663 };
664
665 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]666 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]667 reg = <0x49040000 0x400>;
668 interrupts = <45>;
669 ti,hwmods = "timer9";
670 ti,timer-pwm;
671 };
672
673 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]674 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]675 reg = <0x48086000 0x400>;
676 interrupts = <46>;
677 ti,hwmods = "timer10";
678 ti,timer-pwm;
679 };
680
681 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]682 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]683 reg = <0x48088000 0x400>;
684 interrupts = <47>;
685 ti,hwmods = "timer11";
686 ti,timer-pwm;
687 };
688
689 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]690 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]691 reg = <0x48304000 0x400>;
692 interrupts = <95>;
693 ti,hwmods = "timer12";
694 ti,timer-alwon;
695 ti,timer-secure;
696 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]697
698 usbhstll: usbhstll@48062000 {
699 compatible = "ti,usbhs-tll";
700 reg = <0x48062000 0x1000>;
701 interrupts = <78>;
702 ti,hwmods = "usb_tll_hs";
703 };
704
705 usbhshost: usbhshost@48064000 {
706 compatible = "ti,usbhs-host";
707 reg = <0x48064000 0x400>;
708 ti,hwmods = "usb_host_hs";
709 #address-cells = <1>;
710 #size-cells = <1>;
711 ranges;
712
713 usbhsohci: ohci@48064400 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]714 compatible = "ti,ohci-omap3";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]715 reg = <0x48064400 0x400>;
716 interrupt-parent = <&intc>;
717 interrupts = <76>;
718 };
719
720 usbhsehci: ehci@48064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]721 compatible = "ti,ehci-omap";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]722 reg = <0x48064800 0x400>;
723 interrupt-parent = <&intc>;
724 interrupts = <77>;
725 };
726 };
727
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]728 gpmc: gpmc@6e000000 {
729 compatible = "ti,omap3430-gpmc";
730 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100[diff] [blame]731 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]732 interrupts = <20>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]733 dmas = <&sdma 4>;
734 dma-names = "rxtx";
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]735 gpmc,num-cs = <8>;
736 gpmc,num-waitpins = <4>;
737 #address-cells = <2>;
738 #size-cells = <1>;
Roger Quadros44e47162016-02-23 18:37:25 +0200[diff] [blame]739 interrupt-controller;
740 #interrupt-cells = <2>;
Roger Quadros94f56c82016-04-07 13:25:34 +0300[diff] [blame]741 gpio-controller;
742 #gpio-cells = <2>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]743 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]744
745 usb_otg_hs: usb_otg_hs@480ab000 {
746 compatible = "ti,omap3-musb";
747 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700[diff] [blame]748 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]749 interrupt-names = "mc", "dma";
750 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]751 multipoint = <1>;
752 num-eps = <16>;
753 ram-bits = <12>;
754 };
Tomi Valkeinenb8a7e422013-03-19 11:38:13 +0200[diff] [blame]755
756 dss: dss@48050000 {
757 compatible = "ti,omap3-dss";
758 reg = <0x48050000 0x200>;
759 status = "disabled";
760 ti,hwmods = "dss_core";
761 clocks = <&dss1_alwon_fck>;
762 clock-names = "fck";
763 #address-cells = <1>;
764 #size-cells = <1>;
765 ranges;
766
767 dispc@48050400 {
768 compatible = "ti,omap3-dispc";
769 reg = <0x48050400 0x400>;
770 interrupts = <25>;
771 ti,hwmods = "dss_dispc";
772 clocks = <&dss1_alwon_fck>;
773 clock-names = "fck";
774 };
775
776 dsi: encoder@4804fc00 {
777 compatible = "ti,omap3-dsi";
778 reg = <0x4804fc00 0x200>,
779 <0x4804fe00 0x40>,
780 <0x4804ff00 0x20>;
781 reg-names = "proto", "phy", "pll";
782 interrupts = <25>;
783 status = "disabled";
784 ti,hwmods = "dss_dsi1";
785 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
786 clock-names = "fck", "sys_clk";
787 };
788
789 rfbi: encoder@48050800 {
790 compatible = "ti,omap3-rfbi";
791 reg = <0x48050800 0x100>;
792 status = "disabled";
793 ti,hwmods = "dss_rfbi";
794 clocks = <&dss1_alwon_fck>, <&dss_ick>;
795 clock-names = "fck", "ick";
796 };
797
798 venc: encoder@48050c00 {
799 compatible = "ti,omap3-venc";
800 reg = <0x48050c00 0x100>;
801 status = "disabled";
802 ti,hwmods = "dss_venc";
803 clocks = <&dss_tv_fck>;
804 clock-names = "fck";
805 };
806 };
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200[diff] [blame]807
808 ssi: ssi-controller@48058000 {
809 compatible = "ti,omap3-ssi";
810 ti,hwmods = "ssi";
811
812 status = "disabled";
813
814 reg = <0x48058000 0x1000>,
815 <0x48059000 0x1000>;
816 reg-names = "sys",
817 "gdd";
818
819 interrupts = <71>;
820 interrupt-names = "gdd_mpu";
821
822 #address-cells = <1>;
823 #size-cells = <1>;
824 ranges;
825
826 ssi_port1: ssi-port@4805a000 {
827 compatible = "ti,omap3-ssi-port";
828
829 reg = <0x4805a000 0x800>,
830 <0x4805a800 0x800>;
831 reg-names = "tx",
832 "rx";
833
834 interrupt-parent = <&intc>;
835 interrupts = <67>,
836 <68>;
837 };
838
839 ssi_port2: ssi-port@4805b000 {
840 compatible = "ti,omap3-ssi-port";
841
842 reg = <0x4805b000 0x800>,
843 <0x4805b800 0x800>;
844 reg-names = "tx",
845 "rx";
846
847 interrupt-parent = <&intc>;
848 interrupts = <69>,
849 <70>;
850 };
851 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]852 };
853};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]854
855/include/ "omap3xxx-clocks.dtsi"