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gerrit-public.fairphone.software / kernel / msm-4.19 / 6797cdbe14b262c3bcb5a65b1488ae46fdc6b4db / . / arch / arm / boot / dts / am33xx.dtsi
blob: 4d1c6321b25217acbd8f8394eeaf8cbd891ef26e [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]29 usb0 = &usb0;
30 usb1 = &usb1;
31 phy0 = &usb0_phy;
32 phy1 = &usb1_phy;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]33 };
34
35 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]36 #address-cells = <1>;
37 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 cpu@0 {
39 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]40 device_type = "cpu";
41 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]42
43 /*
44 * To consider voltage drop between PMIC and SoC,
45 * tolerance value is reduced to 2% from 4% and
46 * voltage value is increased as a precaution.
47 */
48 operating-points = <
49 /* kHz uV */
50 720000 1285000
51 600000 1225000
52 500000 1125000
53 275000 1125000
54 >;
55 voltage-tolerance = <2>; /* 2 percentage */
56 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]57 };
58 };
59
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame^]60 pmu {
61 compatible = "arm,cortex-a8-pmu";
62 interrupts = <3>;
63 };
64
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]65 /*
66 * The soc node represents the soc top level view. It is uses for IPs
67 * that are not memory mapped in the MPU view or for the MPU itself.
68 */
69 soc {
70 compatible = "ti,omap-infra";
71 mpu {
72 compatible = "ti,omap3-mpu";
73 ti,hwmods = "mpu";
74 };
75 };
76
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]77 am33xx_pinmux: pinmux@44e10800 {
78 compatible = "pinctrl-single";
79 reg = <0x44e10800 0x0238>;
80 #address-cells = <1>;
81 #size-cells = <0>;
82 pinctrl-single,register-width = <32>;
83 pinctrl-single,function-mask = <0x7f>;
84 };
85
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
88 * The real AM33XX interconnect network is quite complex.Since
89 * that will not bring real advantage to represent that in DT
90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
100 intc: interrupt-controller@48200000 {
101 compatible = "ti,omap2-intc";
102 interrupt-controller;
103 #interrupt-cells = <1>;
104 ti,intc-size = <128>;
105 reg = <0x48200000 0x1000>;
106 };
107
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]108 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]109 compatible = "ti,omap4-gpio";
110 ti,hwmods = "gpio1";
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]115 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]116 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]117 };
118
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]119 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]120 compatible = "ti,omap4-gpio";
121 ti,hwmods = "gpio2";
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]126 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]127 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]128 };
129
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]130 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]131 compatible = "ti,omap4-gpio";
132 ti,hwmods = "gpio3";
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]137 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]138 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]139 };
140
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]141 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]142 compatible = "ti,omap4-gpio";
143 ti,hwmods = "gpio4";
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]148 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]149 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]150 };
151
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]152 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]153 compatible = "ti,omap3-uart";
154 ti,hwmods = "uart1";
155 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]156 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]157 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]158 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]159 };
160
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]161 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]162 compatible = "ti,omap3-uart";
163 ti,hwmods = "uart2";
164 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]165 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]166 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]167 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]168 };
169
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]170 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]171 compatible = "ti,omap3-uart";
172 ti,hwmods = "uart3";
173 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]174 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]175 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]176 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 };
178
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]179 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 compatible = "ti,omap3-uart";
181 ti,hwmods = "uart4";
182 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]183 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]184 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]185 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]188 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap3-uart";
190 ti,hwmods = "uart5";
191 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]192 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]193 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]194 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]195 };
196
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]197 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]198 compatible = "ti,omap3-uart";
199 ti,hwmods = "uart6";
200 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]201 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]202 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]203 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]204 };
205
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]206 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]207 compatible = "ti,omap4-i2c";
208 #address-cells = <1>;
209 #size-cells = <0>;
210 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]211 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]212 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]213 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]214 };
215
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]216 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]217 compatible = "ti,omap4-i2c";
218 #address-cells = <1>;
219 #size-cells = <0>;
220 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]221 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]222 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]223 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]224 };
225
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]226 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]227 compatible = "ti,omap4-i2c";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]231 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]232 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]233 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]234 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]235
236 wdt2: wdt@44e35000 {
237 compatible = "ti,omap3-wdt";
238 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]239 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]240 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]241 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]242
243 dcan0: d_can@481cc000 {
244 compatible = "bosch,d_can";
245 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]246 reg = <0x481cc000 0x2000
247 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]248 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]249 status = "disabled";
250 };
251
252 dcan1: d_can@481d0000 {
253 compatible = "bosch,d_can";
254 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]255 reg = <0x481d0000 0x2000
256 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]257 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]258 status = "disabled";
259 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]260
261 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]262 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]263 reg = <0x44e31000 0x400>;
264 interrupts = <67>;
265 ti,hwmods = "timer1";
266 ti,timer-alwon;
267 };
268
269 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]270 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]271 reg = <0x48040000 0x400>;
272 interrupts = <68>;
273 ti,hwmods = "timer2";
274 };
275
276 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]277 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]278 reg = <0x48042000 0x400>;
279 interrupts = <69>;
280 ti,hwmods = "timer3";
281 };
282
283 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]284 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]285 reg = <0x48044000 0x400>;
286 interrupts = <92>;
287 ti,hwmods = "timer4";
288 ti,timer-pwm;
289 };
290
291 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]292 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]293 reg = <0x48046000 0x400>;
294 interrupts = <93>;
295 ti,hwmods = "timer5";
296 ti,timer-pwm;
297 };
298
299 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]300 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]301 reg = <0x48048000 0x400>;
302 interrupts = <94>;
303 ti,hwmods = "timer6";
304 ti,timer-pwm;
305 };
306
307 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]308 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]309 reg = <0x4804a000 0x400>;
310 interrupts = <95>;
311 ti,hwmods = "timer7";
312 ti,timer-pwm;
313 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]314
315 rtc@44e3e000 {
316 compatible = "ti,da830-rtc";
317 reg = <0x44e3e000 0x1000>;
318 interrupts = <75
319 76>;
320 ti,hwmods = "rtc";
321 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]322
323 spi0: spi@48030000 {
324 compatible = "ti,omap4-mcspi";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]328 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]329 ti,spi-num-cs = <2>;
330 ti,hwmods = "spi0";
331 status = "disabled";
332 };
333
334 spi1: spi@481a0000 {
335 compatible = "ti,omap4-mcspi";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]339 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]340 ti,spi-num-cs = <2>;
341 ti,hwmods = "spi1";
342 status = "disabled";
343 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]344
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]345 usb: usb@47400000 {
346 compatible = "ti,am33xx-usb";
347 reg = <0x47400000 0x1000>;
348 ranges;
349 #address-cells = <1>;
350 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]351 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]352 status = "disabled";
353
354 ctrl_mod: control@44e10000 {
355 compatible = "ti,am335x-usb-ctrl-module";
356 reg = <0x44e10620 0x10
357 0x44e10648 0x4>;
358 reg-names = "phy_ctrl", "wakeup";
359 status = "disabled";
360 };
361
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]362 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]363 compatible = "ti,am335x-usb-phy";
364 reg = <0x47401300 0x100>;
365 reg-names = "phy";
366 status = "disabled";
367 ti,ctrl_mod = <&ctrl_mod>;
368 };
369
370 usb0: usb@47401000 {
371 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]372 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]373 reg = <0x47401400 0x400
374 0x47401000 0x200>;
375 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]376
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]377 interrupts = <18>;
378 interrupt-names = "mc";
379 dr_mode = "otg";
380 mentor,multipoint = <1>;
381 mentor,num-eps = <16>;
382 mentor,ram-bits = <12>;
383 mentor,power = <500>;
384 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]385
386 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
387 &cppi41dma 2 0 &cppi41dma 3 0
388 &cppi41dma 4 0 &cppi41dma 5 0
389 &cppi41dma 6 0 &cppi41dma 7 0
390 &cppi41dma 8 0 &cppi41dma 9 0
391 &cppi41dma 10 0 &cppi41dma 11 0
392 &cppi41dma 12 0 &cppi41dma 13 0
393 &cppi41dma 14 0 &cppi41dma 0 1
394 &cppi41dma 1 1 &cppi41dma 2 1
395 &cppi41dma 3 1 &cppi41dma 4 1
396 &cppi41dma 5 1 &cppi41dma 6 1
397 &cppi41dma 7 1 &cppi41dma 8 1
398 &cppi41dma 9 1 &cppi41dma 10 1
399 &cppi41dma 11 1 &cppi41dma 12 1
400 &cppi41dma 13 1 &cppi41dma 14 1>;
401 dma-names =
402 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
403 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
404 "rx14", "rx15",
405 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
406 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
407 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]408 };
409
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]410 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]411 compatible = "ti,am335x-usb-phy";
412 reg = <0x47401b00 0x100>;
413 reg-names = "phy";
414 status = "disabled";
415 ti,ctrl_mod = <&ctrl_mod>;
416 };
417
418 usb1: usb@47401800 {
419 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]420 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]421 reg = <0x47401c00 0x400
422 0x47401800 0x200>;
423 reg-names = "mc", "control";
424 interrupts = <19>;
425 interrupt-names = "mc";
426 dr_mode = "otg";
427 mentor,multipoint = <1>;
428 mentor,num-eps = <16>;
429 mentor,ram-bits = <12>;
430 mentor,power = <500>;
431 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]432
433 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
434 &cppi41dma 17 0 &cppi41dma 18 0
435 &cppi41dma 19 0 &cppi41dma 20 0
436 &cppi41dma 21 0 &cppi41dma 22 0
437 &cppi41dma 23 0 &cppi41dma 24 0
438 &cppi41dma 25 0 &cppi41dma 26 0
439 &cppi41dma 27 0 &cppi41dma 28 0
440 &cppi41dma 29 0 &cppi41dma 15 1
441 &cppi41dma 16 1 &cppi41dma 17 1
442 &cppi41dma 18 1 &cppi41dma 19 1
443 &cppi41dma 20 1 &cppi41dma 21 1
444 &cppi41dma 22 1 &cppi41dma 23 1
445 &cppi41dma 24 1 &cppi41dma 25 1
446 &cppi41dma 26 1 &cppi41dma 27 1
447 &cppi41dma 28 1 &cppi41dma 29 1>;
448 dma-names =
449 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
450 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
451 "rx14", "rx15",
452 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
453 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
454 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]455 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]456
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]457 cppi41dma: dma-controller@07402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]458 compatible = "ti,am3359-cppi41";
459 reg = <0x47400000 0x1000
460 0x47402000 0x1000
461 0x47403000 0x1000
462 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]463 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]464 interrupts = <17>;
465 interrupt-names = "glue";
466 #dma-cells = <2>;
467 #dma-channels = <30>;
468 #dma-requests = <256>;
469 status = "disabled";
470 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]471 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]472
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]473 epwmss0: epwmss@48300000 {
474 compatible = "ti,am33xx-pwmss";
475 reg = <0x48300000 0x10>;
476 ti,hwmods = "epwmss0";
477 #address-cells = <1>;
478 #size-cells = <1>;
479 status = "disabled";
480 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
481 0x48300180 0x48300180 0x80 /* EQEP */
482 0x48300200 0x48300200 0x80>; /* EHRPWM */
483
484 ecap0: ecap@48300100 {
485 compatible = "ti,am33xx-ecap";
486 #pwm-cells = <3>;
487 reg = <0x48300100 0x80>;
488 ti,hwmods = "ecap0";
489 status = "disabled";
490 };
491
492 ehrpwm0: ehrpwm@48300200 {
493 compatible = "ti,am33xx-ehrpwm";
494 #pwm-cells = <3>;
495 reg = <0x48300200 0x80>;
496 ti,hwmods = "ehrpwm0";
497 status = "disabled";
498 };
499 };
500
501 epwmss1: epwmss@48302000 {
502 compatible = "ti,am33xx-pwmss";
503 reg = <0x48302000 0x10>;
504 ti,hwmods = "epwmss1";
505 #address-cells = <1>;
506 #size-cells = <1>;
507 status = "disabled";
508 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
509 0x48302180 0x48302180 0x80 /* EQEP */
510 0x48302200 0x48302200 0x80>; /* EHRPWM */
511
512 ecap1: ecap@48302100 {
513 compatible = "ti,am33xx-ecap";
514 #pwm-cells = <3>;
515 reg = <0x48302100 0x80>;
516 ti,hwmods = "ecap1";
517 status = "disabled";
518 };
519
520 ehrpwm1: ehrpwm@48302200 {
521 compatible = "ti,am33xx-ehrpwm";
522 #pwm-cells = <3>;
523 reg = <0x48302200 0x80>;
524 ti,hwmods = "ehrpwm1";
525 status = "disabled";
526 };
527 };
528
529 epwmss2: epwmss@48304000 {
530 compatible = "ti,am33xx-pwmss";
531 reg = <0x48304000 0x10>;
532 ti,hwmods = "epwmss2";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 status = "disabled";
536 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
537 0x48304180 0x48304180 0x80 /* EQEP */
538 0x48304200 0x48304200 0x80>; /* EHRPWM */
539
540 ecap2: ecap@48304100 {
541 compatible = "ti,am33xx-ecap";
542 #pwm-cells = <3>;
543 reg = <0x48304100 0x80>;
544 ti,hwmods = "ecap2";
545 status = "disabled";
546 };
547
548 ehrpwm2: ehrpwm@48304200 {
549 compatible = "ti,am33xx-ehrpwm";
550 #pwm-cells = <3>;
551 reg = <0x48304200 0x80>;
552 ti,hwmods = "ehrpwm2";
553 status = "disabled";
554 };
555 };
556
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]557 mac: ethernet@4a100000 {
558 compatible = "ti,cpsw";
559 ti,hwmods = "cpgmac0";
560 cpdma_channels = <8>;
561 ale_entries = <1024>;
562 bd_ram_size = <0x2000>;
563 no_bd_ram = <0>;
564 rx_descs = <64>;
565 mac_control = <0x20>;
566 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]567 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]568 cpts_clock_mult = <0x80000000>;
569 cpts_clock_shift = <29>;
570 reg = <0x4a100000 0x800
571 0x4a101200 0x100>;
572 #address-cells = <1>;
573 #size-cells = <1>;
574 interrupt-parent = <&intc>;
575 /*
576 * c0_rx_thresh_pend
577 * c0_rx_pend
578 * c0_tx_pend
579 * c0_misc_pend
580 */
581 interrupts = <40 41 42 43>;
582 ranges;
583
584 davinci_mdio: mdio@4a101000 {
585 compatible = "ti,davinci_mdio";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 ti,hwmods = "davinci_mdio";
589 bus_freq = <1000000>;
590 reg = <0x4a101000 0x100>;
591 };
592
593 cpsw_emac0: slave@4a100200 {
594 /* Filled in by U-Boot */
595 mac-address = [ 00 00 00 00 00 00 ];
596 };
597
598 cpsw_emac1: slave@4a100300 {
599 /* Filled in by U-Boot */
600 mac-address = [ 00 00 00 00 00 00 ];
601 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]602 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]603
604 ocmcram: ocmcram@40300000 {
605 compatible = "ti,am3352-ocmcram";
606 reg = <0x40300000 0x10000>;
607 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]608 };
609
610 wkup_m3: wkup_m3@44d00000 {
611 compatible = "ti,am3353-wkup-m3";
612 reg = <0x44d00000 0x4000 /* M3 UMEM */
613 0x44d80000 0x2000>; /* M3 DMEM */
614 ti,hwmods = "wkup_m3";
615 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]616
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]617 elm: elm@48080000 {
618 compatible = "ti,am3352-elm";
619 reg = <0x48080000 0x2000>;
620 interrupts = <4>;
621 ti,hwmods = "elm";
622 status = "disabled";
623 };
624
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]625 tscadc: tscadc@44e0d000 {
626 compatible = "ti,am3359-tscadc";
627 reg = <0x44e0d000 0x1000>;
628 interrupt-parent = <&intc>;
629 interrupts = <16>;
630 ti,hwmods = "adc_tsc";
631 status = "disabled";
632
633 tsc {
634 compatible = "ti,am3359-tsc";
635 };
636 am335x_adc: adc {
637 #io-channel-cells = <1>;
638 compatible = "ti,am3359-adc";
639 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]640 };
641
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]642 gpmc: gpmc@50000000 {
643 compatible = "ti,am3352-gpmc";
644 ti,hwmods = "gpmc";
645 reg = <0x50000000 0x2000>;
646 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]647 gpmc,num-cs = <7>;
648 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]649 #address-cells = <2>;
650 #size-cells = <1>;
651 status = "disabled";
652 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]653 };
654};