Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / 8331c055b23c4155b896a2c3791704ae68992d2b / . / drivers / irqchip / Kconfig
blob: fb50911b3940c0bd7234a1312e320ccff020f492 [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +0100[diff] [blame]1config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]5config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +0800[diff] [blame]8 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]9 select MULTI_IRQ_HANDLER
10
Linus Walleija27d21e2015-12-18 10:44:53 +0100[diff] [blame]11config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +0000[diff] [blame]16config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]22config GIC_NON_BANKED
23 bool
24
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]25config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +0000[diff] [blame]29 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]30
Marc Zyngier19812722014-11-24 14:35:19 +0000[diff] [blame]31config ARM_GIC_V3_ITS
32 bool
33 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +0200[diff] [blame]34
Ma Jun717c3db2015-12-17 19:56:35 +0800[diff] [blame]35config HISILICON_IRQ_MBIGEN
36 bool "Support mbigen interrupt controller"
37 default n
38 depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
39 help
40 Enable the mbigen interrupt controller used on
41 Hisilicon platform.
42
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]43config ARM_NVIC
44 bool
45 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +0200[diff] [blame]46 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]47 select GENERIC_IRQ_CHIP
48
49config ARM_VIC
50 bool
51 select IRQ_DOMAIN
52 select MULTI_IRQ_HANDLER
53
54config ARM_VIC_NR
55 int
56 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]57 default 2
58 depends on ARM_VIC
59 help
60 The maximum number of VICs available in the system, for
61 power management.
62
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200[diff] [blame]63config ATMEL_AIC_IRQ
64 bool
65 select GENERIC_IRQ_CHIP
66 select IRQ_DOMAIN
67 select MULTI_IRQ_HANDLER
68 select SPARSE_IRQ
69
70config ATMEL_AIC5_IRQ
71 bool
72 select GENERIC_IRQ_CHIP
73 select IRQ_DOMAIN
74 select MULTI_IRQ_HANDLER
75 select SPARSE_IRQ
76
Ralf Baechle0509cfd2015-07-08 14:46:08 +0200[diff] [blame]77config I8259
78 bool
79 select IRQ_DOMAIN
80
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800[diff] [blame]81config BCM7038_L1_IRQ
82 bool
83 select GENERIC_IRQ_CHIP
84 select IRQ_DOMAIN
85
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800[diff] [blame]86config BCM7120_L2_IRQ
87 bool
88 select GENERIC_IRQ_CHIP
89 select IRQ_DOMAIN
90
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]91config BRCMSTB_L2_IRQ
92 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]93 select GENERIC_IRQ_CHIP
94 select IRQ_DOMAIN
95
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]96config DW_APB_ICTL
97 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800[diff] [blame]98 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]99 select IRQ_DOMAIN
100
James Hoganb6ef9162013-04-22 15:43:50 +0100[diff] [blame]101config IMGPDC_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
105
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200[diff] [blame]106config IRQ_MIPS_CPU
107 bool
108 select GENERIC_IRQ_CHIP
109 select IRQ_DOMAIN
110
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400[diff] [blame]111config CLPS711X_IRQCHIP
112 bool
113 depends on ARCH_CLPS711X
114 select IRQ_DOMAIN
115 select MULTI_IRQ_HANDLER
116 select SPARSE_IRQ
117 default y
118
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300[diff] [blame]119config OR1K_PIC
120 bool
121 select IRQ_DOMAIN
122
Felipe Balbi85980662014-09-15 16:15:02 -0500[diff] [blame]123config OMAP_IRQCHIP
124 bool
125 select GENERIC_IRQ_CHIP
126 select IRQ_DOMAIN
127
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200[diff] [blame]128config ORION_IRQCHIP
129 bool
130 select IRQ_DOMAIN
131 select MULTI_IRQ_HANDLER
132
Cristian Birsanaaa86662016-01-13 18:15:35 -0700[diff] [blame]133config PIC32_EVIC
134 bool
135 select GENERIC_IRQ_CHIP
136 select IRQ_DOMAIN
137
Magnus Damm44358042013-02-18 23:28:34 +0900[diff] [blame]138config RENESAS_INTC_IRQPIN
139 bool
140 select IRQ_DOMAIN
141
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]142config RENESAS_IRQC
143 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900[diff] [blame]144 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]145 select IRQ_DOMAIN
146
Lee Jones07088482015-02-18 15:13:58 +0000[diff] [blame]147config ST_IRQCHIP
148 bool
149 select REGMAP
150 select MFD_SYSCON
151 help
152 Enables SysCfg Controlled IRQs on STi based platforms.
153
Christian Ruppertb06eb012013-06-25 18:29:57 +0200[diff] [blame]154config TB10X_IRQC
155 bool
156 select IRQ_DOMAIN
157 select GENERIC_IRQ_CHIP
158
Damien Riegeld01f8632015-12-21 15:11:23 -0500[diff] [blame]159config TS4800_IRQ
160 tristate "TS-4800 IRQ controller"
161 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100[diff] [blame]162 depends on HAS_IOMEM
Damien Riegeld01f8632015-12-21 15:11:23 -0500[diff] [blame]163 help
164 Support for the TS-4800 FPGA IRQ controller
165
Linus Walleij2389d502012-10-31 22:04:31 +0100[diff] [blame]166config VERSATILE_FPGA_IRQ
167 bool
168 select IRQ_DOMAIN
169
170config VERSATILE_FPGA_IRQ_NR
171 int
172 default 4
173 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400[diff] [blame]174
175config XTENSA_MX
176 bool
177 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]178
179config IRQ_CROSSBAR
180 bool
181 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900[diff] [blame]182 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]183 The primary irqchip invokes the crossbar's callback which inturn allocates
184 a free irq and configures the IP. Thus the peripheral interrupts are
185 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300[diff] [blame]186
187config KEYSTONE_IRQ
188 tristate "Keystone 2 IRQ controller IP"
189 depends on ARCH_KEYSTONE
190 help
191 Support for Texas Instruments Keystone 2 IRQ controller IP which
192 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700[diff] [blame]193
194config MIPS_GIC
195 bool
196 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900[diff] [blame]197
Paul Burton44e08e72015-05-24 16:11:31 +0100[diff] [blame]198config INGENIC_IRQ
199 bool
200 depends on MACH_INGENIC
201 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700[diff] [blame]202
Yoshinori Sato8a764482015-05-10 02:30:47 +0900[diff] [blame]203config RENESAS_H8300H_INTC
204 bool
205 select IRQ_DOMAIN
206
207config RENESAS_H8S_INTC
208 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700[diff] [blame]209 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500[diff] [blame]210
211config IMX_GPCV2
212 bool
213 select IRQ_DOMAIN
214 help
215 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200[diff] [blame]216
217config IRQ_MXS
218 def_bool y if MACH_ASM9260 || ARCH_MXS
219 select IRQ_DOMAIN
220 select STMP_DEVICE