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Florian Fainelli246d7f72014-08-27 17:04:56 -07001/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
Florian Fainelli8b7c94e2015-10-23 12:11:08 -070024#include <linux/of_net.h>
Florian Fainelli461cd1b02016-06-07 16:32:43 -070025#include <linux/of_mdio.h>
Florian Fainelli246d7f72014-08-27 17:04:56 -070026#include <net/dsa.h>
Florian Fainelli96e65d72014-09-18 17:31:25 -070027#include <linux/ethtool.h>
Florian Fainelli12f460f2015-02-24 13:15:34 -080028#include <linux/if_bridge.h>
Florian Fainelliaafc66f2015-06-10 18:08:01 -070029#include <linux/brcmphy.h>
Florian Fainelli680060d2015-10-23 11:38:07 -070030#include <linux/etherdevice.h>
31#include <net/switchdev.h>
Florian Fainelli246d7f72014-08-27 17:04:56 -070032
33#include "bcm_sf2.h"
34#include "bcm_sf2_regs.h"
35
36/* String, offset, and register size in bytes if different from 4 bytes */
37static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
38 { "TxOctets", 0x000, 8 },
39 { "TxDropPkts", 0x020 },
40 { "TxQPKTQ0", 0x030 },
41 { "TxBroadcastPkts", 0x040 },
42 { "TxMulticastPkts", 0x050 },
43 { "TxUnicastPKts", 0x060 },
44 { "TxCollisions", 0x070 },
45 { "TxSingleCollision", 0x080 },
46 { "TxMultipleCollision", 0x090 },
47 { "TxDeferredCollision", 0x0a0 },
48 { "TxLateCollision", 0x0b0 },
49 { "TxExcessiveCollision", 0x0c0 },
50 { "TxFrameInDisc", 0x0d0 },
51 { "TxPausePkts", 0x0e0 },
52 { "TxQPKTQ1", 0x0f0 },
53 { "TxQPKTQ2", 0x100 },
54 { "TxQPKTQ3", 0x110 },
55 { "TxQPKTQ4", 0x120 },
56 { "TxQPKTQ5", 0x130 },
57 { "RxOctets", 0x140, 8 },
58 { "RxUndersizePkts", 0x160 },
59 { "RxPausePkts", 0x170 },
60 { "RxPkts64Octets", 0x180 },
61 { "RxPkts65to127Octets", 0x190 },
62 { "RxPkts128to255Octets", 0x1a0 },
63 { "RxPkts256to511Octets", 0x1b0 },
64 { "RxPkts512to1023Octets", 0x1c0 },
65 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
66 { "RxOversizePkts", 0x1e0 },
67 { "RxJabbers", 0x1f0 },
68 { "RxAlignmentErrors", 0x200 },
69 { "RxFCSErrors", 0x210 },
70 { "RxGoodOctets", 0x220, 8 },
71 { "RxDropPkts", 0x240 },
72 { "RxUnicastPkts", 0x250 },
73 { "RxMulticastPkts", 0x260 },
74 { "RxBroadcastPkts", 0x270 },
75 { "RxSAChanges", 0x280 },
76 { "RxFragments", 0x290 },
77 { "RxJumboPkt", 0x2a0 },
78 { "RxSymblErr", 0x2b0 },
79 { "InRangeErrCount", 0x2c0 },
80 { "OutRangeErrCount", 0x2d0 },
81 { "EEELpiEvent", 0x2e0 },
82 { "EEELpiDuration", 0x2f0 },
83 { "RxDiscard", 0x300, 8 },
84 { "TxQPKTQ6", 0x320 },
85 { "TxQPKTQ7", 0x330 },
86 { "TxPkts64Octets", 0x340 },
87 { "TxPkts65to127Octets", 0x350 },
88 { "TxPkts128to255Octets", 0x360 },
89 { "TxPkts256to511Ocets", 0x370 },
90 { "TxPkts512to1023Ocets", 0x380 },
91 { "TxPkts1024toMaxPktOcets", 0x390 },
92};
93
94#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
95
96static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
97 int port, uint8_t *data)
98{
99 unsigned int i;
100
101 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
102 memcpy(data + i * ETH_GSTRING_LEN,
103 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
104}
105
106static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
107 int port, uint64_t *data)
108{
109 struct bcm_sf2_priv *priv = ds_to_priv(ds);
110 const struct bcm_sf2_hw_stats *s;
111 unsigned int i;
112 u64 val = 0;
113 u32 offset;
114
115 mutex_lock(&priv->stats_mutex);
116
117 /* Now fetch the per-port counters */
118 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
119 s = &bcm_sf2_mib[i];
120
121 /* Do a latched 64-bit read if needed */
122 offset = s->reg + CORE_P_MIB_OFFSET(port);
123 if (s->sizeof_stat == 8)
124 val = core_readq(priv, offset);
125 else
126 val = core_readl(priv, offset);
127
128 data[i] = (u64)val;
129 }
130
131 mutex_unlock(&priv->stats_mutex);
132}
133
134static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
135{
136 return BCM_SF2_STATS_SIZE;
137}
138
Vivien Didelot0209d142016-04-17 13:23:55 -0400139static const char *bcm_sf2_sw_drv_probe(struct device *dsa_dev,
140 struct device *host_dev, int sw_addr,
141 void **_priv)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700142{
Andrew Lunn7543a6d2016-04-13 02:40:40 +0200143 struct bcm_sf2_priv *priv;
144
145 priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
146 if (!priv)
147 return NULL;
148 *_priv = priv;
149
Florian Fainelli246d7f72014-08-27 17:04:56 -0700150 return "Broadcom Starfighter 2";
151}
152
Florian Fainellib6d045d2014-09-24 17:05:20 -0700153static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700154{
155 struct bcm_sf2_priv *priv = ds_to_priv(ds);
156 unsigned int i;
Florian Fainellib6d045d2014-09-24 17:05:20 -0700157 u32 reg;
158
159 /* Enable the IMP Port to be in the same VLAN as the other ports
160 * on a per-port basis such that we only have Port i and IMP in
161 * the same VLAN.
162 */
163 for (i = 0; i < priv->hw_params.num_ports; i++) {
Andrew Lunn74c3e2a2016-04-13 02:40:44 +0200164 if (!((1 << i) & ds->enabled_port_mask))
Florian Fainellib6d045d2014-09-24 17:05:20 -0700165 continue;
166
167 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
168 reg |= (1 << cpu_port);
169 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
170 }
171}
172
173static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
174{
175 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700176 u32 reg, val;
177
178 /* Enable the port memories */
179 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
180 reg &= ~P_TXQ_PSM_VDD(port);
181 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
182
183 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
184 reg = core_readl(priv, CORE_IMP_CTL);
185 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
186 reg &= ~(RX_DIS | TX_DIS);
187 core_writel(priv, reg, CORE_IMP_CTL);
188
189 /* Enable forwarding */
190 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
191
192 /* Enable IMP port in dumb mode */
193 reg = core_readl(priv, CORE_SWITCH_CTRL);
194 reg |= MII_DUMB_FWDG_EN;
195 core_writel(priv, reg, CORE_SWITCH_CTRL);
196
197 /* Resolve which bit controls the Broadcom tag */
198 switch (port) {
199 case 8:
200 val = BRCM_HDR_EN_P8;
201 break;
202 case 7:
203 val = BRCM_HDR_EN_P7;
204 break;
205 case 5:
206 val = BRCM_HDR_EN_P5;
207 break;
208 default:
209 val = 0;
210 break;
211 }
212
213 /* Enable Broadcom tags for IMP port */
214 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
215 reg |= val;
216 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
217
218 /* Enable reception Broadcom tag for CPU TX (switch RX) to
219 * allow us to tag outgoing frames
220 */
221 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
222 reg &= ~(1 << port);
223 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
224
225 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
226 * allow delivering frames to the per-port net_devices
227 */
228 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
229 reg &= ~(1 << port);
230 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
231
232 /* Force link status for IMP port */
233 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
234 reg |= (MII_SW_OR | LINK_STS);
235 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700236}
237
Florian Fainelli450b05c2014-09-24 17:05:22 -0700238static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
239{
240 struct bcm_sf2_priv *priv = ds_to_priv(ds);
241 u32 reg;
242
243 reg = core_readl(priv, CORE_EEE_EN_CTRL);
244 if (enable)
245 reg |= 1 << port;
246 else
247 reg &= ~(1 << port);
248 core_writel(priv, reg, CORE_EEE_EN_CTRL);
249}
250
Florian Fainellib0836682015-02-05 11:40:41 -0800251static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
252{
253 struct bcm_sf2_priv *priv = ds_to_priv(ds);
254 u32 reg;
255
Florian Fainelli9af197a2015-02-05 11:40:42 -0800256 reg = reg_readl(priv, REG_SPHY_CNTRL);
257 if (enable) {
258 reg |= PHY_RESET;
259 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
260 reg_writel(priv, reg, REG_SPHY_CNTRL);
261 udelay(21);
262 reg = reg_readl(priv, REG_SPHY_CNTRL);
263 reg &= ~PHY_RESET;
264 } else {
265 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
266 reg_writel(priv, reg, REG_SPHY_CNTRL);
267 mdelay(1);
268 reg |= CK25_DIS;
269 }
270 reg_writel(priv, reg, REG_SPHY_CNTRL);
Florian Fainellib0836682015-02-05 11:40:41 -0800271
Florian Fainelli9af197a2015-02-05 11:40:42 -0800272 /* Use PHY-driven LED signaling */
273 if (!enable) {
274 reg = reg_readl(priv, REG_LED_CNTRL(0));
275 reg |= SPDLNK_SRC_SEL;
276 reg_writel(priv, reg, REG_LED_CNTRL(0));
277 }
Florian Fainellib0836682015-02-05 11:40:41 -0800278}
279
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700280static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
281 int port)
282{
283 unsigned int off;
284
285 switch (port) {
286 case 7:
287 off = P7_IRQ_OFF;
288 break;
289 case 0:
290 /* Port 0 interrupts are located on the first bank */
291 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
292 return;
293 default:
294 off = P_IRQ_OFF(port);
295 break;
296 }
297
298 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
299}
300
301static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
302 int port)
303{
304 unsigned int off;
305
306 switch (port) {
307 case 7:
308 off = P7_IRQ_OFF;
309 break;
310 case 0:
311 /* Port 0 interrupts are located on the first bank */
312 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
313 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
314 return;
315 default:
316 off = P_IRQ_OFF(port);
317 break;
318 }
319
320 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
321 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
322}
323
Florian Fainellib6d045d2014-09-24 17:05:20 -0700324static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
325 struct phy_device *phy)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700326{
327 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainellib6d045d2014-09-24 17:05:20 -0700328 s8 cpu_port = ds->dst[ds->index].cpu_port;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700329 u32 reg;
330
331 /* Clear the memory power down */
332 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
333 reg &= ~P_TXQ_PSM_VDD(port);
334 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
335
336 /* Clear the Rx and Tx disable bits and set to no spanning tree */
337 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
338
Florian Fainelli9af197a2015-02-05 11:40:42 -0800339 /* Re-enable the GPHY and re-apply workarounds */
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700340 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
Florian Fainelli9af197a2015-02-05 11:40:42 -0800341 bcm_sf2_gphy_enable_set(ds, true);
342 if (phy) {
343 /* if phy_stop() has been called before, phy
344 * will be in halted state, and phy_start()
345 * will call resume.
346 *
347 * the resume path does not configure back
348 * autoneg settings, and since we hard reset
349 * the phy manually here, we need to reset the
350 * state machine also.
351 */
352 phy->state = PHY_READY;
353 phy_init_hw(phy);
354 }
355 }
356
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700357 /* Enable MoCA port interrupts to get notified */
358 if (port == priv->moca_port)
359 bcm_sf2_port_intr_enable(priv, port);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700360
Florian Fainelli12f460f2015-02-24 13:15:34 -0800361 /* Set this port, and only this one to be in the default VLAN,
362 * if member of a bridge, restore its membership prior to
363 * bringing down this port.
364 */
Florian Fainelli246d7f72014-08-27 17:04:56 -0700365 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
366 reg &= ~PORT_VLAN_CTRL_MASK;
367 reg |= (1 << port);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800368 reg |= priv->port_sts[port].vlan_ctl_mask;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700369 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
Florian Fainellib6d045d2014-09-24 17:05:20 -0700370
371 bcm_sf2_imp_vlan_setup(ds, cpu_port);
372
Florian Fainelli450b05c2014-09-24 17:05:22 -0700373 /* If EEE was enabled, restore it */
374 if (priv->port_sts[port].eee.eee_enabled)
375 bcm_sf2_eee_enable_set(ds, port, true);
376
Florian Fainellib6d045d2014-09-24 17:05:20 -0700377 return 0;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700378}
379
Florian Fainellib6d045d2014-09-24 17:05:20 -0700380static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
381 struct phy_device *phy)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700382{
383 struct bcm_sf2_priv *priv = ds_to_priv(ds);
384 u32 off, reg;
385
Florian Fainelli96e65d72014-09-18 17:31:25 -0700386 if (priv->wol_ports_mask & (1 << port))
387 return;
388
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700389 if (port == priv->moca_port)
390 bcm_sf2_port_intr_disable(priv, port);
Florian Fainellib6d045d2014-09-24 17:05:20 -0700391
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700392 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
Florian Fainelli9af197a2015-02-05 11:40:42 -0800393 bcm_sf2_gphy_enable_set(ds, false);
394
Florian Fainelli246d7f72014-08-27 17:04:56 -0700395 if (dsa_is_cpu_port(ds, port))
396 off = CORE_IMP_CTL;
397 else
398 off = CORE_G_PCTL_PORT(port);
399
400 reg = core_readl(priv, off);
401 reg |= RX_DIS | TX_DIS;
402 core_writel(priv, reg, off);
403
404 /* Power down the port memory */
405 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
406 reg |= P_TXQ_PSM_VDD(port);
407 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
408}
409
Florian Fainelli450b05c2014-09-24 17:05:22 -0700410/* Returns 0 if EEE was not enabled, or 1 otherwise
411 */
412static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
413 struct phy_device *phy)
414{
415 struct bcm_sf2_priv *priv = ds_to_priv(ds);
416 struct ethtool_eee *p = &priv->port_sts[port].eee;
417 int ret;
418
419 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
420
421 ret = phy_init_eee(phy, 0);
422 if (ret)
423 return 0;
424
425 bcm_sf2_eee_enable_set(ds, port, true);
426
427 return 1;
428}
429
430static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
431 struct ethtool_eee *e)
432{
433 struct bcm_sf2_priv *priv = ds_to_priv(ds);
434 struct ethtool_eee *p = &priv->port_sts[port].eee;
435 u32 reg;
436
437 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
438 e->eee_enabled = p->eee_enabled;
439 e->eee_active = !!(reg & (1 << port));
440
441 return 0;
442}
443
444static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
445 struct phy_device *phydev,
446 struct ethtool_eee *e)
447{
448 struct bcm_sf2_priv *priv = ds_to_priv(ds);
449 struct ethtool_eee *p = &priv->port_sts[port].eee;
450
451 p->eee_enabled = e->eee_enabled;
452
453 if (!p->eee_enabled) {
454 bcm_sf2_eee_enable_set(ds, port, false);
455 } else {
456 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
457 if (!p->eee_enabled)
458 return -EOPNOTSUPP;
459 }
460
461 return 0;
462}
463
Florian Fainellia468ef42016-06-09 17:42:05 -0700464static int bcm_sf2_fast_age_op(struct bcm_sf2_priv *priv)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800465{
Florian Fainelli12f460f2015-02-24 13:15:34 -0800466 unsigned int timeout = 1000;
467 u32 reg;
468
Florian Fainelli12f460f2015-02-24 13:15:34 -0800469 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
Florian Fainelli39797a22015-09-05 13:07:27 -0700470 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800471 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
472
473 do {
474 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
475 if (!(reg & FAST_AGE_STR_DONE))
476 break;
477
478 cpu_relax();
479 } while (timeout--);
480
481 if (!timeout)
482 return -ETIMEDOUT;
483
Florian Fainelli39797a22015-09-05 13:07:27 -0700484 core_writel(priv, 0, CORE_FAST_AGE_CTRL);
485
Florian Fainelli12f460f2015-02-24 13:15:34 -0800486 return 0;
487}
488
Florian Fainellia468ef42016-06-09 17:42:05 -0700489/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
490 * flush for that port.
491 */
492static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
493{
494 struct bcm_sf2_priv *priv = ds_to_priv(ds);
495
496 core_writel(priv, port, CORE_FAST_AGE_PORT);
497
498 return bcm_sf2_fast_age_op(priv);
499}
500
Florian Fainelli12f460f2015-02-24 13:15:34 -0800501static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
Vivien Didelota6692752016-02-12 12:09:39 -0500502 struct net_device *bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800503{
504 struct bcm_sf2_priv *priv = ds_to_priv(ds);
505 unsigned int i;
506 u32 reg, p_ctl;
507
Vivien Didelota6692752016-02-12 12:09:39 -0500508 priv->port_sts[port].bridge_dev = bridge;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800509 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
510
511 for (i = 0; i < priv->hw_params.num_ports; i++) {
Vivien Didelota6692752016-02-12 12:09:39 -0500512 if (priv->port_sts[i].bridge_dev != bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800513 continue;
514
515 /* Add this local port to the remote port VLAN control
516 * membership and update the remote port bitmask
517 */
518 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
519 reg |= 1 << port;
520 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
521 priv->port_sts[i].vlan_ctl_mask = reg;
522
523 p_ctl |= 1 << i;
524 }
525
526 /* Configure the local port VLAN control membership to include
527 * remote ports and update the local port bitmask
528 */
529 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
530 priv->port_sts[port].vlan_ctl_mask = p_ctl;
531
532 return 0;
533}
534
Vivien Didelot16bfa702016-03-13 16:21:33 -0400535static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800536{
537 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Vivien Didelota6692752016-02-12 12:09:39 -0500538 struct net_device *bridge = priv->port_sts[port].bridge_dev;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800539 unsigned int i;
540 u32 reg, p_ctl;
541
542 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
543
544 for (i = 0; i < priv->hw_params.num_ports; i++) {
545 /* Don't touch the remaining ports */
Vivien Didelota6692752016-02-12 12:09:39 -0500546 if (priv->port_sts[i].bridge_dev != bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800547 continue;
548
549 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
550 reg &= ~(1 << port);
551 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
552 priv->port_sts[port].vlan_ctl_mask = reg;
553
554 /* Prevent self removal to preserve isolation */
555 if (port != i)
556 p_ctl &= ~(1 << i);
557 }
558
559 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
560 priv->port_sts[port].vlan_ctl_mask = p_ctl;
Vivien Didelota6692752016-02-12 12:09:39 -0500561 priv->port_sts[port].bridge_dev = NULL;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800562}
563
Vivien Didelot43c44a92016-04-06 11:55:03 -0400564static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
565 u8 state)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800566{
567 struct bcm_sf2_priv *priv = ds_to_priv(ds);
568 u8 hw_state, cur_hw_state;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800569 u32 reg;
570
571 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
Florian Fainelli39797a22015-09-05 13:07:27 -0700572 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800573
574 switch (state) {
575 case BR_STATE_DISABLED:
576 hw_state = G_MISTP_DIS_STATE;
577 break;
578 case BR_STATE_LISTENING:
579 hw_state = G_MISTP_LISTEN_STATE;
580 break;
581 case BR_STATE_LEARNING:
582 hw_state = G_MISTP_LEARN_STATE;
583 break;
584 case BR_STATE_FORWARDING:
585 hw_state = G_MISTP_FWD_STATE;
586 break;
587 case BR_STATE_BLOCKING:
588 hw_state = G_MISTP_BLOCK_STATE;
589 break;
590 default:
591 pr_err("%s: invalid STP state: %d\n", __func__, state);
Vivien Didelot43c44a92016-04-06 11:55:03 -0400592 return;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800593 }
594
595 /* Fast-age ARL entries if we are moving a port from Learning or
Florian Fainelli39797a22015-09-05 13:07:27 -0700596 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
597 * state (hw_state)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800598 */
599 if (cur_hw_state != hw_state) {
Florian Fainelli39797a22015-09-05 13:07:27 -0700600 if (cur_hw_state >= G_MISTP_LEARN_STATE &&
601 hw_state <= G_MISTP_LISTEN_STATE) {
Vivien Didelot43c44a92016-04-06 11:55:03 -0400602 if (bcm_sf2_sw_fast_age_port(ds, port)) {
Florian Fainelli12f460f2015-02-24 13:15:34 -0800603 pr_err("%s: fast-ageing failed\n", __func__);
Vivien Didelot43c44a92016-04-06 11:55:03 -0400604 return;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800605 }
606 }
607 }
608
609 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
610 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
611 reg |= hw_state;
612 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
Florian Fainelli12f460f2015-02-24 13:15:34 -0800613}
614
Florian Fainelli680060d2015-10-23 11:38:07 -0700615/* Address Resolution Logic routines */
616static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv *priv)
617{
618 unsigned int timeout = 10;
619 u32 reg;
620
621 do {
622 reg = core_readl(priv, CORE_ARLA_RWCTL);
623 if (!(reg & ARL_STRTDN))
624 return 0;
625
626 usleep_range(1000, 2000);
627 } while (timeout--);
628
629 return -ETIMEDOUT;
630}
631
632static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv *priv, unsigned int op)
633{
634 u32 cmd;
635
636 if (op > ARL_RW)
637 return -EINVAL;
638
639 cmd = core_readl(priv, CORE_ARLA_RWCTL);
640 cmd &= ~IVL_SVL_SELECT;
641 cmd |= ARL_STRTDN;
642 if (op)
643 cmd |= ARL_RW;
644 else
645 cmd &= ~ARL_RW;
646 core_writel(priv, cmd, CORE_ARLA_RWCTL);
647
648 return bcm_sf2_arl_op_wait(priv);
649}
650
651static int bcm_sf2_arl_read(struct bcm_sf2_priv *priv, u64 mac,
652 u16 vid, struct bcm_sf2_arl_entry *ent, u8 *idx,
653 bool is_valid)
654{
655 unsigned int i;
656 int ret;
657
658 ret = bcm_sf2_arl_op_wait(priv);
659 if (ret)
660 return ret;
661
662 /* Read the 4 bins */
663 for (i = 0; i < 4; i++) {
664 u64 mac_vid;
665 u32 fwd_entry;
666
667 mac_vid = core_readq(priv, CORE_ARLA_MACVID_ENTRY(i));
668 fwd_entry = core_readl(priv, CORE_ARLA_FWD_ENTRY(i));
669 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
670
671 if (ent->is_valid && is_valid) {
672 *idx = i;
673 return 0;
674 }
675
676 /* This is the MAC we just deleted */
677 if (!is_valid && (mac_vid & mac))
678 return 0;
679 }
680
681 return -ENOENT;
682}
683
684static int bcm_sf2_arl_op(struct bcm_sf2_priv *priv, int op, int port,
685 const unsigned char *addr, u16 vid, bool is_valid)
686{
687 struct bcm_sf2_arl_entry ent;
688 u32 fwd_entry;
689 u64 mac, mac_vid = 0;
690 u8 idx = 0;
691 int ret;
692
693 /* Convert the array into a 64-bit MAC */
694 mac = bcm_sf2_mac_to_u64(addr);
695
696 /* Perform a read for the given MAC and VID */
697 core_writeq(priv, mac, CORE_ARLA_MAC);
698 core_writel(priv, vid, CORE_ARLA_VID);
699
700 /* Issue a read operation for this MAC */
701 ret = bcm_sf2_arl_rw_op(priv, 1);
702 if (ret)
703 return ret;
704
705 ret = bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
706 /* If this is a read, just finish now */
707 if (op)
708 return ret;
709
710 /* We could not find a matching MAC, so reset to a new entry */
711 if (ret) {
712 fwd_entry = 0;
713 idx = 0;
714 }
715
716 memset(&ent, 0, sizeof(ent));
717 ent.port = port;
718 ent.is_valid = is_valid;
719 ent.vid = vid;
720 ent.is_static = true;
721 memcpy(ent.mac, addr, ETH_ALEN);
722 bcm_sf2_arl_from_entry(&mac_vid, &fwd_entry, &ent);
723
724 core_writeq(priv, mac_vid, CORE_ARLA_MACVID_ENTRY(idx));
725 core_writel(priv, fwd_entry, CORE_ARLA_FWD_ENTRY(idx));
726
727 ret = bcm_sf2_arl_rw_op(priv, 0);
728 if (ret)
729 return ret;
730
731 /* Re-read the entry to check */
732 return bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
733}
734
735static int bcm_sf2_sw_fdb_prepare(struct dsa_switch *ds, int port,
736 const struct switchdev_obj_port_fdb *fdb,
737 struct switchdev_trans *trans)
738{
739 /* We do not need to do anything specific here yet */
740 return 0;
741}
742
Vivien Didelot8497aa62016-04-06 11:55:04 -0400743static void bcm_sf2_sw_fdb_add(struct dsa_switch *ds, int port,
744 const struct switchdev_obj_port_fdb *fdb,
745 struct switchdev_trans *trans)
Florian Fainelli680060d2015-10-23 11:38:07 -0700746{
747 struct bcm_sf2_priv *priv = ds_to_priv(ds);
748
Vivien Didelot8497aa62016-04-06 11:55:04 -0400749 if (bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
750 pr_err("%s: failed to add MAC address\n", __func__);
Florian Fainelli680060d2015-10-23 11:38:07 -0700751}
752
753static int bcm_sf2_sw_fdb_del(struct dsa_switch *ds, int port,
754 const struct switchdev_obj_port_fdb *fdb)
755{
756 struct bcm_sf2_priv *priv = ds_to_priv(ds);
757
758 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
759}
760
761static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv *priv)
762{
763 unsigned timeout = 1000;
764 u32 reg;
765
766 do {
767 reg = core_readl(priv, CORE_ARLA_SRCH_CTL);
768 if (!(reg & ARLA_SRCH_STDN))
769 return 0;
770
771 if (reg & ARLA_SRCH_VLID)
772 return 0;
773
774 usleep_range(1000, 2000);
775 } while (timeout--);
776
777 return -ETIMEDOUT;
778}
779
780static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx,
781 struct bcm_sf2_arl_entry *ent)
782{
783 u64 mac_vid;
784 u32 fwd_entry;
785
786 mac_vid = core_readq(priv, CORE_ARLA_SRCH_RSLT_MACVID(idx));
787 fwd_entry = core_readl(priv, CORE_ARLA_SRCH_RSLT(idx));
788 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
789}
790
791static int bcm_sf2_sw_fdb_copy(struct net_device *dev, int port,
792 const struct bcm_sf2_arl_entry *ent,
793 struct switchdev_obj_port_fdb *fdb,
794 int (*cb)(struct switchdev_obj *obj))
795{
796 if (!ent->is_valid)
797 return 0;
798
799 if (port != ent->port)
800 return 0;
801
802 ether_addr_copy(fdb->addr, ent->mac);
803 fdb->vid = ent->vid;
804 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
805
806 return cb(&fdb->obj);
807}
808
809static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port,
810 struct switchdev_obj_port_fdb *fdb,
811 int (*cb)(struct switchdev_obj *obj))
812{
813 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Andrew Lunnc8b09802016-06-04 21:16:57 +0200814 struct net_device *dev = ds->ports[port].netdev;
Florian Fainelli680060d2015-10-23 11:38:07 -0700815 struct bcm_sf2_arl_entry results[2];
816 unsigned int count = 0;
817 int ret;
818
819 /* Start search operation */
820 core_writel(priv, ARLA_SRCH_STDN, CORE_ARLA_SRCH_CTL);
821
822 do {
823 ret = bcm_sf2_arl_search_wait(priv);
824 if (ret)
825 return ret;
826
827 /* Read both entries, then return their values back */
828 bcm_sf2_arl_search_rd(priv, 0, &results[0]);
829 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[0], fdb, cb);
830 if (ret)
831 return ret;
832
833 bcm_sf2_arl_search_rd(priv, 1, &results[1]);
834 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[1], fdb, cb);
835 if (ret)
836 return ret;
837
838 if (!results[0].is_valid && !results[1].is_valid)
839 break;
840
841 } while (count++ < CORE_ARLA_NUM_ENTRIES);
842
843 return 0;
844}
845
Florian Fainelli461cd1b02016-06-07 16:32:43 -0700846static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
847 int regnum, u16 val)
848{
849 int ret = 0;
850 u32 reg;
851
852 reg = reg_readl(priv, REG_SWITCH_CNTRL);
853 reg |= MDIO_MASTER_SEL;
854 reg_writel(priv, reg, REG_SWITCH_CNTRL);
855
856 /* Page << 8 | offset */
857 reg = 0x70;
858 reg <<= 2;
859 core_writel(priv, addr, reg);
860
861 /* Page << 8 | offset */
862 reg = 0x80 << 8 | regnum << 1;
863 reg <<= 2;
864
865 if (op)
866 ret = core_readl(priv, reg);
867 else
868 core_writel(priv, val, reg);
869
870 reg = reg_readl(priv, REG_SWITCH_CNTRL);
871 reg &= ~MDIO_MASTER_SEL;
872 reg_writel(priv, reg, REG_SWITCH_CNTRL);
873
874 return ret & 0xffff;
875}
876
877static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
878{
879 struct bcm_sf2_priv *priv = bus->priv;
880
881 /* Intercept reads from Broadcom pseudo-PHY address, else, send
882 * them to our master MDIO bus controller
883 */
884 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
885 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
886 else
887 return mdiobus_read(priv->master_mii_bus, addr, regnum);
888}
889
890static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
891 u16 val)
892{
893 struct bcm_sf2_priv *priv = bus->priv;
894
895 /* Intercept writes to the Broadcom pseudo-PHY address, else,
896 * send them to our master MDIO bus controller
897 */
898 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
899 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
900 else
901 mdiobus_write(priv->master_mii_bus, addr, regnum, val);
902
903 return 0;
904}
905
Florian Fainelli246d7f72014-08-27 17:04:56 -0700906static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
907{
908 struct bcm_sf2_priv *priv = dev_id;
909
910 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
911 ~priv->irq0_mask;
912 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
913
914 return IRQ_HANDLED;
915}
916
917static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
918{
919 struct bcm_sf2_priv *priv = dev_id;
920
921 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
922 ~priv->irq1_mask;
923 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
924
925 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
926 priv->port_sts[7].link = 1;
927 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
928 priv->port_sts[7].link = 0;
929
930 return IRQ_HANDLED;
931}
932
Florian Fainelli33f84612014-11-25 18:08:49 -0800933static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
934{
935 unsigned int timeout = 1000;
936 u32 reg;
937
938 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
939 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
940 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
941
942 do {
943 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
944 if (!(reg & SOFTWARE_RESET))
945 break;
946
947 usleep_range(1000, 2000);
948 } while (timeout-- > 0);
949
950 if (timeout == 0)
951 return -ETIMEDOUT;
952
953 return 0;
954}
955
Florian Fainelli691c9a82015-01-20 16:42:00 -0800956static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
957{
958 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
959 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
960 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
961 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
962 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
963 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
964}
965
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700966static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
967 struct device_node *dn)
968{
969 struct device_node *port;
970 const char *phy_mode_str;
971 int mode;
972 unsigned int port_num;
973 int ret;
974
975 priv->moca_port = -1;
976
977 for_each_available_child_of_node(dn, port) {
978 if (of_property_read_u32(port, "reg", &port_num))
979 continue;
980
981 /* Internal PHYs get assigned a specific 'phy-mode' property
982 * value: "internal" to help flag them before MDIO probing
983 * has completed, since they might be turned off at that
984 * time
985 */
986 mode = of_get_phy_mode(port);
987 if (mode < 0) {
988 ret = of_property_read_string(port, "phy-mode",
989 &phy_mode_str);
990 if (ret < 0)
991 continue;
992
993 if (!strcasecmp(phy_mode_str, "internal"))
994 priv->int_phy_mask |= 1 << port_num;
995 }
996
997 if (mode == PHY_INTERFACE_MODE_MOCA)
998 priv->moca_port = port_num;
999 }
1000}
1001
Florian Fainelli461cd1b02016-06-07 16:32:43 -07001002static int bcm_sf2_mdio_register(struct dsa_switch *ds)
1003{
1004 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1005 struct device_node *dn;
1006 static int index;
1007 int err;
1008
1009 /* Find our integrated MDIO bus node */
1010 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
1011 priv->master_mii_bus = of_mdio_find_bus(dn);
1012 if (!priv->master_mii_bus)
1013 return -EPROBE_DEFER;
1014
1015 get_device(&priv->master_mii_bus->dev);
1016 priv->master_mii_dn = dn;
1017
1018 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
1019 if (!priv->slave_mii_bus)
1020 return -ENOMEM;
1021
1022 priv->slave_mii_bus->priv = priv;
1023 priv->slave_mii_bus->name = "sf2 slave mii";
1024 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
1025 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
1026 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
1027 index++);
1028 priv->slave_mii_bus->dev.of_node = dn;
1029
1030 /* Include the pseudo-PHY address to divert reads towards our
1031 * workaround. This is only required for 7445D0, since 7445E0
1032 * disconnects the internal switch pseudo-PHY such that we can use the
1033 * regular SWITCH_MDIO master controller instead.
1034 *
1035 * Here we flag the pseudo PHY as needing special treatment and would
1036 * otherwise make all other PHY read/writes go to the master MDIO bus
1037 * controller that comes with this switch backed by the "mdio-unimac"
1038 * driver.
1039 */
1040 if (of_machine_is_compatible("brcm,bcm7445d0"))
1041 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
1042 else
1043 priv->indir_phy_mask = 0;
1044
1045 ds->phys_mii_mask = priv->indir_phy_mask;
1046 ds->slave_mii_bus = priv->slave_mii_bus;
1047 priv->slave_mii_bus->parent = ds->dev->parent;
1048 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
1049
1050 if (dn)
1051 err = of_mdiobus_register(priv->slave_mii_bus, dn);
1052 else
1053 err = mdiobus_register(priv->slave_mii_bus);
1054
1055 if (err)
1056 of_node_put(dn);
1057
1058 return err;
1059}
1060
1061static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
1062{
1063 mdiobus_unregister(priv->slave_mii_bus);
1064 if (priv->master_mii_dn)
1065 of_node_put(priv->master_mii_dn);
1066}
1067
Florian Fainelli246d7f72014-08-27 17:04:56 -07001068static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1069{
1070 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1071 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1072 struct device_node *dn;
1073 void __iomem **base;
1074 unsigned int port;
1075 unsigned int i;
1076 u32 reg, rev;
1077 int ret;
1078
1079 spin_lock_init(&priv->indir_lock);
1080 mutex_init(&priv->stats_mutex);
1081
1082 /* All the interesting properties are at the parent device_node
1083 * level
1084 */
Andrew Lunnff049552016-05-10 23:27:24 +02001085 dn = ds->cd->of_node->parent;
1086 bcm_sf2_identify_ports(priv, ds->cd->of_node);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001087
1088 priv->irq0 = irq_of_parse_and_map(dn, 0);
1089 priv->irq1 = irq_of_parse_and_map(dn, 1);
1090
1091 base = &priv->core;
1092 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1093 *base = of_iomap(dn, i);
1094 if (*base == NULL) {
1095 pr_err("unable to find register: %s\n", reg_names[i]);
Florian Fainellia5660592014-11-25 18:08:48 -08001096 ret = -ENOMEM;
1097 goto out_unmap;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001098 }
1099 base++;
1100 }
1101
Florian Fainelli33f84612014-11-25 18:08:49 -08001102 ret = bcm_sf2_sw_rst(priv);
1103 if (ret) {
1104 pr_err("unable to software reset switch: %d\n", ret);
1105 goto out_unmap;
1106 }
1107
Florian Fainelli461cd1b02016-06-07 16:32:43 -07001108 ret = bcm_sf2_mdio_register(ds);
1109 if (ret) {
1110 pr_err("failed to register MDIO bus\n");
1111 goto out_unmap;
1112 }
1113
Florian Fainelli246d7f72014-08-27 17:04:56 -07001114 /* Disable all interrupts and request them */
Florian Fainelli691c9a82015-01-20 16:42:00 -08001115 bcm_sf2_intr_disable(priv);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001116
1117 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
1118 "switch_0", priv);
1119 if (ret < 0) {
1120 pr_err("failed to request switch_0 IRQ\n");
1121 goto out_unmap;
1122 }
1123
1124 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
1125 "switch_1", priv);
1126 if (ret < 0) {
1127 pr_err("failed to request switch_1 IRQ\n");
1128 goto out_free_irq0;
1129 }
1130
1131 /* Reset the MIB counters */
1132 reg = core_readl(priv, CORE_GMNCFGCFG);
1133 reg |= RST_MIB_CNT;
1134 core_writel(priv, reg, CORE_GMNCFGCFG);
1135 reg &= ~RST_MIB_CNT;
1136 core_writel(priv, reg, CORE_GMNCFGCFG);
1137
1138 /* Get the maximum number of ports for this switch */
1139 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1140 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1141 priv->hw_params.num_ports = DSA_MAX_PORTS;
1142
1143 /* Assume a single GPHY setup if we can't read that property */
1144 if (of_property_read_u32(dn, "brcm,num-gphy",
1145 &priv->hw_params.num_gphy))
1146 priv->hw_params.num_gphy = 1;
1147
1148 /* Enable all valid ports and disable those unused */
1149 for (port = 0; port < priv->hw_params.num_ports; port++) {
1150 /* IMP port receives special treatment */
Andrew Lunn74c3e2a2016-04-13 02:40:44 +02001151 if ((1 << port) & ds->enabled_port_mask)
Florian Fainellib6d045d2014-09-24 17:05:20 -07001152 bcm_sf2_port_setup(ds, port, NULL);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001153 else if (dsa_is_cpu_port(ds, port))
1154 bcm_sf2_imp_setup(ds, port);
1155 else
Florian Fainellib6d045d2014-09-24 17:05:20 -07001156 bcm_sf2_port_disable(ds, port, NULL);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001157 }
1158
Florian Fainelli246d7f72014-08-27 17:04:56 -07001159 rev = reg_readl(priv, REG_SWITCH_REVISION);
1160 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1161 SWITCH_TOP_REV_MASK;
1162 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1163
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001164 rev = reg_readl(priv, REG_PHY_REVISION);
1165 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1166
Florian Fainelli246d7f72014-08-27 17:04:56 -07001167 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1168 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1169 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1170 priv->core, priv->irq0, priv->irq1);
1171
1172 return 0;
1173
1174out_free_irq0:
1175 free_irq(priv->irq0, priv);
1176out_unmap:
1177 base = &priv->core;
1178 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
Florian Fainellia5660592014-11-25 18:08:48 -08001179 if (*base)
1180 iounmap(*base);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001181 base++;
1182 }
Florian Fainelli461cd1b02016-06-07 16:32:43 -07001183 bcm_sf2_mdio_unregister(priv);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001184 return ret;
1185}
1186
1187static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
1188{
1189 return 0;
1190}
1191
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001192static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
1193{
1194 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1195
1196 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
1197 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
1198 * the REG_PHY_REVISION register layout is.
1199 */
1200
1201 return priv->hw_params.gphy_rev;
1202}
1203
Florian Fainelli246d7f72014-08-27 17:04:56 -07001204static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
1205 struct phy_device *phydev)
1206{
1207 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1208 u32 id_mode_dis = 0, port_mode;
1209 const char *str = NULL;
1210 u32 reg;
1211
1212 switch (phydev->interface) {
1213 case PHY_INTERFACE_MODE_RGMII:
1214 str = "RGMII (no delay)";
1215 id_mode_dis = 1;
1216 case PHY_INTERFACE_MODE_RGMII_TXID:
1217 if (!str)
1218 str = "RGMII (TX delay)";
1219 port_mode = EXT_GPHY;
1220 break;
1221 case PHY_INTERFACE_MODE_MII:
1222 str = "MII";
1223 port_mode = EXT_EPHY;
1224 break;
1225 case PHY_INTERFACE_MODE_REVMII:
1226 str = "Reverse MII";
1227 port_mode = EXT_REVMII;
1228 break;
1229 default:
Florian Fainelli7de15572014-09-24 17:05:19 -07001230 /* All other PHYs: internal and MoCA */
1231 goto force_link;
1232 }
1233
1234 /* If the link is down, just disable the interface to conserve power */
1235 if (!phydev->link) {
1236 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1237 reg &= ~RGMII_MODE_EN;
1238 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
Florian Fainelli246d7f72014-08-27 17:04:56 -07001239 goto force_link;
1240 }
1241
1242 /* Clear id_mode_dis bit, and the existing port mode, but
1243 * make sure we enable the RGMII block for data to pass
1244 */
1245 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1246 reg &= ~ID_MODE_DIS;
1247 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
1248 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
1249
1250 reg |= port_mode | RGMII_MODE_EN;
1251 if (id_mode_dis)
1252 reg |= ID_MODE_DIS;
1253
1254 if (phydev->pause) {
1255 if (phydev->asym_pause)
1256 reg |= TX_PAUSE_EN;
1257 reg |= RX_PAUSE_EN;
1258 }
1259
1260 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
1261
1262 pr_info("Port %d configured for %s\n", port, str);
1263
1264force_link:
1265 /* Force link settings detected from the PHY */
1266 reg = SW_OVERRIDE;
1267 switch (phydev->speed) {
1268 case SPEED_1000:
1269 reg |= SPDSTS_1000 << SPEED_SHIFT;
1270 break;
1271 case SPEED_100:
1272 reg |= SPDSTS_100 << SPEED_SHIFT;
1273 break;
1274 }
1275
1276 if (phydev->link)
1277 reg |= LINK_STS;
1278 if (phydev->duplex == DUPLEX_FULL)
1279 reg |= DUPLX_MODE;
1280
1281 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1282}
1283
1284static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
1285 struct fixed_phy_status *status)
1286{
1287 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainellid2eac982015-07-20 17:49:55 -07001288 u32 duplex, pause;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001289 u32 reg;
1290
Florian Fainelli246d7f72014-08-27 17:04:56 -07001291 duplex = core_readl(priv, CORE_DUPSTS);
1292 pause = core_readl(priv, CORE_PAUSESTS);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001293
1294 status->link = 0;
1295
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001296 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001297 * which means that we need to force the link at the port override
1298 * level to get the data to flow. We do use what the interrupt handler
1299 * did determine before.
Florian Fainelli7855f672014-12-11 18:12:42 -08001300 *
1301 * For the other ports, we just force the link status, since this is
1302 * a fixed PHY device.
Florian Fainelli246d7f72014-08-27 17:04:56 -07001303 */
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001304 if (port == priv->moca_port) {
Florian Fainelli246d7f72014-08-27 17:04:56 -07001305 status->link = priv->port_sts[port].link;
Florian Fainelli4ab7f912015-05-15 12:38:01 -07001306 /* For MoCA interfaces, also force a link down notification
1307 * since some version of the user-space daemon (mocad) use
1308 * cmd->autoneg to force the link, which messes up the PHY
1309 * state machine and make it go in PHY_FORCING state instead.
1310 */
1311 if (!status->link)
Andrew Lunnc8b09802016-06-04 21:16:57 +02001312 netif_carrier_off(ds->ports[port].netdev);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001313 status->duplex = 1;
1314 } else {
Florian Fainelli7855f672014-12-11 18:12:42 -08001315 status->link = 1;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001316 status->duplex = !!(duplex & (1 << port));
1317 }
1318
Florian Fainelli7855f672014-12-11 18:12:42 -08001319 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1320 reg |= SW_OVERRIDE;
1321 if (status->link)
1322 reg |= LINK_STS;
1323 else
1324 reg &= ~LINK_STS;
1325 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1326
Florian Fainelli246d7f72014-08-27 17:04:56 -07001327 if ((pause & (1 << port)) &&
1328 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
1329 status->asym_pause = 1;
1330 status->pause = 1;
1331 }
1332
1333 if (pause & (1 << port))
1334 status->pause = 1;
1335}
1336
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001337static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
1338{
1339 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1340 unsigned int port;
1341
Florian Fainelli691c9a82015-01-20 16:42:00 -08001342 bcm_sf2_intr_disable(priv);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001343
1344 /* Disable all ports physically present including the IMP
1345 * port, the other ones have already been disabled during
1346 * bcm_sf2_sw_setup
1347 */
1348 for (port = 0; port < DSA_MAX_PORTS; port++) {
Andrew Lunn74c3e2a2016-04-13 02:40:44 +02001349 if ((1 << port) & ds->enabled_port_mask ||
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001350 dsa_is_cpu_port(ds, port))
Florian Fainellib6d045d2014-09-24 17:05:20 -07001351 bcm_sf2_port_disable(ds, port, NULL);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001352 }
1353
1354 return 0;
1355}
1356
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001357static int bcm_sf2_sw_resume(struct dsa_switch *ds)
1358{
1359 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1360 unsigned int port;
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001361 int ret;
1362
1363 ret = bcm_sf2_sw_rst(priv);
1364 if (ret) {
1365 pr_err("%s: failed to software reset switch\n", __func__);
1366 return ret;
1367 }
1368
Florian Fainellib0836682015-02-05 11:40:41 -08001369 if (priv->hw_params.num_gphy == 1)
1370 bcm_sf2_gphy_enable_set(ds, true);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001371
1372 for (port = 0; port < DSA_MAX_PORTS; port++) {
Andrew Lunn74c3e2a2016-04-13 02:40:44 +02001373 if ((1 << port) & ds->enabled_port_mask)
Florian Fainellib6d045d2014-09-24 17:05:20 -07001374 bcm_sf2_port_setup(ds, port, NULL);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001375 else if (dsa_is_cpu_port(ds, port))
1376 bcm_sf2_imp_setup(ds, port);
1377 }
1378
1379 return 0;
1380}
1381
Florian Fainelli96e65d72014-09-18 17:31:25 -07001382static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
1383 struct ethtool_wolinfo *wol)
1384{
1385 struct net_device *p = ds->dst[ds->index].master_netdev;
1386 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1387 struct ethtool_wolinfo pwol;
1388
1389 /* Get the parent device WoL settings */
1390 p->ethtool_ops->get_wol(p, &pwol);
1391
1392 /* Advertise the parent device supported settings */
1393 wol->supported = pwol.supported;
1394 memset(&wol->sopass, 0, sizeof(wol->sopass));
1395
1396 if (pwol.wolopts & WAKE_MAGICSECURE)
1397 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1398
1399 if (priv->wol_ports_mask & (1 << port))
1400 wol->wolopts = pwol.wolopts;
1401 else
1402 wol->wolopts = 0;
1403}
1404
1405static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1406 struct ethtool_wolinfo *wol)
1407{
1408 struct net_device *p = ds->dst[ds->index].master_netdev;
1409 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1410 s8 cpu_port = ds->dst[ds->index].cpu_port;
1411 struct ethtool_wolinfo pwol;
1412
1413 p->ethtool_ops->get_wol(p, &pwol);
1414 if (wol->wolopts & ~pwol.supported)
1415 return -EINVAL;
1416
1417 if (wol->wolopts)
1418 priv->wol_ports_mask |= (1 << port);
1419 else
1420 priv->wol_ports_mask &= ~(1 << port);
1421
1422 /* If we have at least one port enabled, make sure the CPU port
1423 * is also enabled. If the CPU port is the last one enabled, we disable
1424 * it since this configuration does not make sense.
1425 */
1426 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1427 priv->wol_ports_mask |= (1 << cpu_port);
1428 else
1429 priv->wol_ports_mask &= ~(1 << cpu_port);
1430
1431 return p->ethtool_ops->set_wol(p, wol);
1432}
1433
Florian Fainelli246d7f72014-08-27 17:04:56 -07001434static struct dsa_switch_driver bcm_sf2_switch_driver = {
Florian Fainelliac7a04c2014-09-11 21:18:09 -07001435 .tag_protocol = DSA_TAG_PROTO_BRCM,
Andrew Lunne49bad32016-04-13 02:40:43 +02001436 .probe = bcm_sf2_sw_drv_probe,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001437 .setup = bcm_sf2_sw_setup,
1438 .set_addr = bcm_sf2_sw_set_addr,
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001439 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001440 .get_strings = bcm_sf2_sw_get_strings,
1441 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1442 .get_sset_count = bcm_sf2_sw_get_sset_count,
1443 .adjust_link = bcm_sf2_sw_adjust_link,
1444 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001445 .suspend = bcm_sf2_sw_suspend,
1446 .resume = bcm_sf2_sw_resume,
Florian Fainelli96e65d72014-09-18 17:31:25 -07001447 .get_wol = bcm_sf2_sw_get_wol,
1448 .set_wol = bcm_sf2_sw_set_wol,
Florian Fainellib6d045d2014-09-24 17:05:20 -07001449 .port_enable = bcm_sf2_port_setup,
1450 .port_disable = bcm_sf2_port_disable,
Florian Fainelli450b05c2014-09-24 17:05:22 -07001451 .get_eee = bcm_sf2_sw_get_eee,
1452 .set_eee = bcm_sf2_sw_set_eee,
Vivien Didelot71327a42016-03-13 16:21:32 -04001453 .port_bridge_join = bcm_sf2_sw_br_join,
1454 .port_bridge_leave = bcm_sf2_sw_br_leave,
Vivien Didelot43c44a92016-04-06 11:55:03 -04001455 .port_stp_state_set = bcm_sf2_sw_br_set_stp_state,
Florian Fainelli680060d2015-10-23 11:38:07 -07001456 .port_fdb_prepare = bcm_sf2_sw_fdb_prepare,
1457 .port_fdb_add = bcm_sf2_sw_fdb_add,
1458 .port_fdb_del = bcm_sf2_sw_fdb_del,
1459 .port_fdb_dump = bcm_sf2_sw_fdb_dump,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001460};
1461
1462static int __init bcm_sf2_init(void)
1463{
1464 register_switch_driver(&bcm_sf2_switch_driver);
1465
1466 return 0;
1467}
1468module_init(bcm_sf2_init);
1469
1470static void __exit bcm_sf2_exit(void)
1471{
1472 unregister_switch_driver(&bcm_sf2_switch_driver);
1473}
1474module_exit(bcm_sf2_exit);
1475
1476MODULE_AUTHOR("Broadcom Corporation");
1477MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1478MODULE_LICENSE("GPL");
1479MODULE_ALIAS("platform:brcm-sf2");