Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #include "skeleton64.dtsi" |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 7 | |
| 8 | #include <dt-bindings/clock/qcom,aop-qmp.h> |
| 9 | #include <dt-bindings/clock/qcom,camcc-kona.h> |
| 10 | #include <dt-bindings/clock/qcom,cpucc-kona.h> |
| 11 | #include <dt-bindings/clock/qcom,dispcc-kona.h> |
| 12 | #include <dt-bindings/clock/qcom,gcc-kona.h> |
| 13 | #include <dt-bindings/clock/qcom,gpucc-kona.h> |
| 14 | #include <dt-bindings/clock/qcom,npucc-kona.h> |
| 15 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 16 | #include <dt-bindings/clock/qcom,videocc-kona.h> |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
David Dai | b1d6848 | 2018-10-01 19:40:35 -0700 | [diff] [blame] | 18 | #include <dt-bindings/msm/msm-bus-ids.h> |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 19 | #include <dt-bindings/soc/qcom,ipcc.h> |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 20 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
Rishabh Bhatnagar | 2b66dc1 | 2018-10-18 10:36:27 -0700 | [diff] [blame] | 21 | #include <dt-bindings/gpio/gpio.h> |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 22 | |
David Collins | 54e4530 | 2018-06-29 18:46:53 -0700 | [diff] [blame] | 23 | #include "kona-regulators.dtsi" |
| 24 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 25 | / { |
| 26 | model = "Qualcomm Technologies, Inc. kona"; |
| 27 | compatible = "qcom,kona"; |
| 28 | qcom,msm-id = <356 0x10000>; |
| 29 | interrupt-parent = <&intc>; |
| 30 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 31 | aliases { |
| 32 | ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
Tony Truong | c972c64 | 2018-09-12 10:03:51 -0700 | [diff] [blame] | 33 | pci-domain2 = &pcie2; /* PCIe2 domain */ |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 34 | }; |
| 35 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 36 | cpus { |
| 37 | #address-cells = <2>; |
| 38 | #size-cells = <0>; |
| 39 | |
| 40 | CPU0: cpu@0 { |
| 41 | device_type = "cpu"; |
| 42 | compatible = "qcom,kryo"; |
| 43 | reg = <0x0 0x0>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 44 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 45 | cache-size = <0x8000>; |
| 46 | cpu-release-addr = <0x0 0x90000000>; |
| 47 | next-level-cache = <&L2_0>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 48 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 49 | L2_0: l2-cache { |
| 50 | compatible = "arm,arch-cache"; |
| 51 | cache-size = <0x20000>; |
| 52 | cache-level = <2>; |
| 53 | next-level-cache = <&L3_0>; |
| 54 | |
| 55 | L3_0: l3-cache { |
| 56 | compatible = "arm,arch-cache"; |
| 57 | cache-size = <0x400000>; |
| 58 | cache-level = <3>; |
| 59 | }; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | CPU1: cpu@100 { |
| 64 | device_type = "cpu"; |
| 65 | compatible = "qcom,kryo"; |
| 66 | reg = <0x0 0x100>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 67 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 68 | cache-size = <0x8000>; |
| 69 | cpu-release-addr = <0x0 0x90000000>; |
| 70 | next-level-cache = <&L2_1>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 71 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 72 | L2_1: l2-cache { |
| 73 | compatible = "arm,arch-cache"; |
| 74 | cache-size = <0x20000>; |
| 75 | cache-level = <2>; |
| 76 | next-level-cache = <&L3_0>; |
| 77 | }; |
| 78 | }; |
| 79 | |
| 80 | CPU2: cpu@200 { |
| 81 | device_type = "cpu"; |
| 82 | compatible = "qcom,kryo"; |
| 83 | reg = <0x0 0x200>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 84 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 85 | cache-size = <0x8000>; |
| 86 | cpu-release-addr = <0x0 0x90000000>; |
| 87 | next-level-cache = <&L2_2>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 88 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 89 | L2_2: l2-cache { |
| 90 | compatible = "arm,arch-cache"; |
| 91 | cache-size = <0x20000>; |
| 92 | cache-level = <2>; |
| 93 | next-level-cache = <&L3_0>; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | CPU3: cpu@300 { |
| 98 | device_type = "cpu"; |
| 99 | compatible = "qcom,kryo"; |
| 100 | reg = <0x0 0x300>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 101 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 102 | cache-size = <0x8000>; |
| 103 | cpu-release-addr = <0x0 0x90000000>; |
| 104 | next-level-cache = <&L2_3>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 105 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 106 | L2_3: l2-cache { |
| 107 | compatible = "arm,arch-cache"; |
| 108 | cache-size = <0x20000>; |
| 109 | cache-level = <2>; |
| 110 | next-level-cache = <&L3_0>; |
| 111 | }; |
| 112 | }; |
| 113 | |
| 114 | CPU4: cpu@400 { |
| 115 | device_type = "cpu"; |
| 116 | compatible = "qcom,kryo"; |
| 117 | reg = <0x0 0x400>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 118 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 119 | cache-size = <0x10000>; |
| 120 | cpu-release-addr = <0x0 0x90000000>; |
| 121 | next-level-cache = <&L2_4>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 122 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 123 | L2_4: l2-cache { |
| 124 | compatible = "arm,arch-cache"; |
| 125 | cache-size = <0x20000>; |
| 126 | cache-level = <2>; |
| 127 | next-level-cache = <&L3_0>; |
| 128 | }; |
| 129 | }; |
| 130 | |
| 131 | CPU5: cpu@500 { |
| 132 | device_type = "cpu"; |
| 133 | compatible = "qcom,kryo"; |
| 134 | reg = <0x0 0x500>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 135 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 136 | cache-size = <0x10000>; |
| 137 | cpu-release-addr = <0x0 0x90000000>; |
| 138 | next-level-cache = <&L2_5>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 139 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 140 | L2_5: l2-cache { |
| 141 | compatible = "arm,arch-cache"; |
| 142 | cache-size = <0x20000>; |
| 143 | cache-level = <2>; |
| 144 | next-level-cache = <&L3_0>; |
| 145 | }; |
| 146 | }; |
| 147 | |
| 148 | CPU6: cpu@600 { |
| 149 | device_type = "cpu"; |
| 150 | compatible = "qcom,kryo"; |
| 151 | reg = <0x0 0x600>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 152 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 153 | cache-size = <0x10000>; |
| 154 | cpu-release-addr = <0x0 0x90000000>; |
| 155 | next-level-cache = <&L2_6>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 156 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 157 | L2_6: l2-cache { |
| 158 | compatible = "arm,arch-cache"; |
| 159 | cache-size = <0x20000>; |
| 160 | cache-level = <2>; |
| 161 | next-level-cache = <&L3_0>; |
| 162 | }; |
| 163 | }; |
| 164 | |
| 165 | CPU7: cpu@700 { |
| 166 | device_type = "cpu"; |
| 167 | compatible = "qcom,kryo"; |
| 168 | reg = <0x0 0x700>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 169 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 170 | cache-size = <0x10000>; |
| 171 | cpu-release-addr = <0x0 0x90000000>; |
| 172 | next-level-cache = <&L2_7>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 173 | qcom,freq-domain = <&cpufreq_hw 2 4>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 174 | L2_7: l2-cache { |
| 175 | compatible = "arm,arch-cache"; |
| 176 | cache-size = <0x80000>; |
| 177 | cache-level = <2>; |
| 178 | next-level-cache = <&L3_0>; |
| 179 | }; |
| 180 | }; |
| 181 | |
| 182 | cpu-map { |
| 183 | cluster0 { |
| 184 | core0 { |
| 185 | cpu = <&CPU0>; |
| 186 | }; |
| 187 | |
| 188 | core1 { |
| 189 | cpu = <&CPU1>; |
| 190 | }; |
| 191 | |
| 192 | core2 { |
| 193 | cpu = <&CPU2>; |
| 194 | }; |
| 195 | |
| 196 | core3 { |
| 197 | cpu = <&CPU3>; |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | cluster1 { |
| 202 | core0 { |
| 203 | cpu = <&CPU4>; |
| 204 | }; |
| 205 | |
| 206 | core1 { |
| 207 | cpu = <&CPU5>; |
| 208 | }; |
| 209 | |
| 210 | core2 { |
| 211 | cpu = <&CPU6>; |
| 212 | }; |
| 213 | |
| 214 | core3 { |
| 215 | cpu = <&CPU7>; |
| 216 | }; |
| 217 | }; |
| 218 | }; |
| 219 | }; |
| 220 | |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 221 | |
Channagoud Kadabi | cdd72a0 | 2018-09-21 14:46:21 -0700 | [diff] [blame] | 222 | cpu_pmu: cpu-pmu { |
| 223 | compatible = "arm,armv8-pmuv3"; |
| 224 | qcom,irq-is-percpu; |
| 225 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | }; |
| 227 | |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 228 | soc: soc { |
| 229 | cpufreq_hw: qcom,cpufreq-hw { |
| 230 | compatible = "qcom,cpufreq-hw"; |
| 231 | reg = <0x18591000 0x1000>, <0x18592000 0x1000>, |
| 232 | <0x18593000 0x1000>; |
| 233 | reg-names = "freq-domain0", "freq-domain1", |
| 234 | "freq-domain2"; |
| 235 | |
| 236 | clocks = <&clock_xo>, <&clock_gcc GPLL0>; |
| 237 | clock-names = "xo", "cpu_clk"; |
| 238 | |
| 239 | #freq-domain-cells = <2>; |
| 240 | }; |
| 241 | }; |
| 242 | |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 243 | psci { |
| 244 | compatible = "arm,psci-1.0"; |
| 245 | method = "smc"; |
| 246 | }; |
| 247 | |
Bruce Levy | 3bd8d1b | 2018-09-11 11:31:13 -0700 | [diff] [blame] | 248 | firmware: firmware { |
| 249 | android { |
| 250 | compatible = "android,firmware"; |
| 251 | fstab { |
| 252 | compatible = "android,fstab"; |
| 253 | vendor { |
| 254 | compatible = "android,vendor"; |
| 255 | dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; |
| 256 | type = "ext4"; |
| 257 | mnt_flags = "ro,barrier=1,discard"; |
| 258 | fsmgr_flags = "wait,slotselect,avb"; |
| 259 | status = "ok"; |
| 260 | }; |
| 261 | }; |
| 262 | }; |
| 263 | }; |
| 264 | |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 265 | psci { |
| 266 | compatible = "arm,psci-1.0"; |
| 267 | method = "smc"; |
| 268 | }; |
| 269 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 270 | reserved-memory { |
| 271 | #address-cells = <2>; |
| 272 | #size-cells = <2>; |
| 273 | ranges; |
| 274 | |
| 275 | hyp_mem: hyp_region@80000000 { |
| 276 | no-map; |
| 277 | reg = <0x0 0x80000000 0x0 0x600000>; |
| 278 | }; |
| 279 | |
| 280 | xbl_aop_mem: xbl_aop_region@80700000 { |
| 281 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 282 | reg = <0x0 0x80700000 0x0 0x120000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 283 | }; |
| 284 | |
Lina Iyer | 5d609fa | 2018-10-03 14:26:55 -0600 | [diff] [blame] | 285 | cmd_db: reserved-memory@80820000 { |
| 286 | reg = <0x0 0x80820000 0x0 0x20000>; |
| 287 | compatible = "qcom,cmd-db"; |
| 288 | no-map; |
| 289 | }; |
| 290 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 291 | smem_mem: smem_region@80900000 { |
| 292 | no-map; |
| 293 | reg = <0x0 0x80900000 0x0 0x200000>; |
| 294 | }; |
| 295 | |
| 296 | removed_mem: removed_region@80b00000 { |
| 297 | no-map; |
| 298 | reg = <0x0 0x80b00000 0x0 0xc00000>; |
| 299 | }; |
| 300 | |
| 301 | qtee_apps_mem: qtee_apps_region@81e00000 { |
| 302 | no-map; |
| 303 | reg = <0x0 0x81e00000 0x0 0x2600000>; |
| 304 | }; |
| 305 | |
| 306 | pil_camera_mem: pil_camera_region@86000000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 307 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 308 | no-map; |
| 309 | reg = <0x0 0x86000000 0x0 0x500000>; |
| 310 | }; |
| 311 | |
| 312 | pil_wlan_fw_mem: pil_wlan_fw_region@86500000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 313 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 314 | no-map; |
| 315 | reg = <0x0 0x86500000 0x0 0x100000>; |
| 316 | }; |
| 317 | |
| 318 | pil_ipa_fw_mem: pil_ipa_fw_region@86600000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 319 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 320 | no-map; |
| 321 | reg = <0x0 0x86600000 0x0 0x10000>; |
| 322 | }; |
| 323 | |
| 324 | pil_ipa_gsi_mem: pil_ipa_gsi_region@86610000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 325 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 326 | no-map; |
| 327 | reg = <0x0 0x86610000 0x0 0x5000>; |
| 328 | }; |
| 329 | |
| 330 | pil_gpu_mem: pil_gpu_region@86615000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 331 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 332 | no-map; |
| 333 | reg = <0x0 0x86615000 0x0 0x2000>; |
| 334 | }; |
| 335 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 336 | pil_npu_mem: pil_npu_region@86700000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 337 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 338 | no-map; |
| 339 | reg = <0x0 0x86700000 0x0 0x500000>; |
| 340 | }; |
| 341 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 342 | pil_video_mem: pil_video_region@86c00000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 343 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 344 | no-map; |
| 345 | reg = <0x0 0x86c00000 0x0 0x500000>; |
| 346 | }; |
| 347 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 348 | pil_cvp_mem: pil_cvp_region@87100000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 349 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 350 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 351 | reg = <0x0 0x87100000 0x0 0x500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 352 | }; |
| 353 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 354 | pil_cdsp_mem: pil_cdsp_region@87600000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 355 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 356 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 357 | reg = <0x0 0x87600000 0x0 0x800000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 358 | }; |
| 359 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 360 | pil_slpi_mem: pil_slpi_region@87e00000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 361 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 362 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 363 | reg = <0x0 0x87e00000 0x0 0x1500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 364 | }; |
| 365 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 366 | pil_adsp_mem: pil_adsp_region@89300000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 367 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 368 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 369 | reg = <0x0 0x89300000 0x0 0x1900000>; |
| 370 | }; |
| 371 | |
| 372 | pil_spss_mem: pil_spss_region@8ac00000 { |
| 373 | compatible = "removed-dma-pool"; |
| 374 | no-map; |
| 375 | reg = <0x0 0x8ac00000 0x0 0x100000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 376 | }; |
| 377 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 378 | adsp_mem: adsp_region { |
| 379 | compatible = "shared-dma-pool"; |
| 380 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 381 | reusable; |
| 382 | alignment = <0x0 0x400000>; |
| 383 | size = <0x0 0x1000000>; |
| 384 | }; |
| 385 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 386 | /* global autoconfigured region for contiguous allocations */ |
| 387 | linux,cma { |
| 388 | compatible = "shared-dma-pool"; |
| 389 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 390 | reusable; |
| 391 | alignment = <0x0 0x400000>; |
| 392 | size = <0x0 0x2000000>; |
| 393 | linux,cma-default; |
| 394 | }; |
| 395 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 396 | }; |
| 397 | |
| 398 | &soc { |
| 399 | #address-cells = <1>; |
| 400 | #size-cells = <1>; |
| 401 | ranges = <0 0 0 0xffffffff>; |
| 402 | compatible = "simple-bus"; |
| 403 | |
David Collins | 692dff7 | 2018-11-12 17:09:49 -0800 | [diff] [blame] | 404 | thermal_zones: thermal-zones { |
| 405 | }; |
| 406 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 407 | intc: interrupt-controller@17a00000 { |
| 408 | compatible = "arm,gic-v3"; |
| 409 | #interrupt-cells = <3>; |
| 410 | interrupt-controller; |
| 411 | #redistributor-regions = <1>; |
| 412 | redistributor-stride = <0x0 0x20000>; |
| 413 | reg = <0x17a00000 0x10000>, /* GICD */ |
| 414 | <0x17a60000 0x100000>; /* GICR * 8 */ |
| 415 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 416 | }; |
| 417 | |
Rishabh Bhatnagar | fd73eb1 | 2018-09-04 15:00:46 -0700 | [diff] [blame] | 418 | qcom,chd_silver { |
| 419 | compatible = "qcom,core-hang-detect"; |
| 420 | label = "silver"; |
| 421 | qcom,threshold-arr = <0x18000058 0x18010058 |
| 422 | 0x18020058 0x18030058>; |
| 423 | qcom,config-arr = <0x18000060 0x18010060 |
| 424 | 0x18020060 0x18030060>; |
| 425 | }; |
| 426 | |
| 427 | qcom,chd_gold { |
| 428 | compatible = "qcom,core-hang-detect"; |
| 429 | label = "gold"; |
| 430 | qcom,threshold-arr = <0x18040058 0x18050058 |
| 431 | 0x18060058 0x18070058>; |
| 432 | qcom,config-arr = <0x18040060 0x18050060 |
| 433 | 0x18060060 0x18070060>; |
| 434 | }; |
| 435 | |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 436 | cache-controller@9200000 { |
| 437 | compatible = "qcom,kona-llcc"; |
| 438 | reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; |
| 439 | reg-names = "llcc_base", "llcc_broadcast_base"; |
Channagoud Kadabi | a13ed0a | 2018-09-26 16:10:35 -0700 | [diff] [blame] | 440 | interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 441 | }; |
| 442 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 443 | arch_timer: timer { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 444 | compatible = "arm,armv8-timer"; |
| 445 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 446 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 447 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 448 | <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| 449 | clock-frequency = <19200000>; |
| 450 | }; |
| 451 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 452 | memtimer: timer@17c20000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 453 | #address-cells = <1>; |
| 454 | #size-cells = <1>; |
| 455 | ranges; |
| 456 | compatible = "arm,armv7-timer-mem"; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 457 | reg = <0x17c20000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 458 | clock-frequency = <19200000>; |
| 459 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 460 | frame@17c21000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 461 | frame-number = <0>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 462 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 463 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 464 | reg = <0x17c21000 0x1000>, |
| 465 | <0x17c22000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 466 | }; |
| 467 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 468 | frame@17c23000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 469 | frame-number = <1>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 470 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 471 | reg = <0x17c23000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 475 | frame@17c25000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 476 | frame-number = <2>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 477 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 478 | reg = <0x17c25000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 479 | status = "disabled"; |
| 480 | }; |
| 481 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 482 | frame@17c27000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 483 | frame-number = <3>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 484 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 485 | reg = <0x17c27000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 486 | status = "disabled"; |
| 487 | }; |
| 488 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 489 | frame@17c29000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 490 | frame-number = <4>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 491 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 492 | reg = <0x17c29000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 493 | status = "disabled"; |
| 494 | }; |
| 495 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 496 | frame@17c2b000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 497 | frame-number = <5>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 498 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 499 | reg = <0x17c2b000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 500 | status = "disabled"; |
| 501 | }; |
| 502 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 503 | frame@17c2d000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 504 | frame-number = <6>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 505 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 506 | reg = <0x17c2d000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 507 | status = "disabled"; |
| 508 | }; |
| 509 | }; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 510 | |
Tingwei Zhang | 020594a | 2018-11-27 21:58:09 -0800 | [diff] [blame] | 511 | jtag_mm0: jtagmm@7040000 { |
| 512 | compatible = "qcom,jtagv8-mm"; |
| 513 | reg = <0x7040000 0x1000>; |
| 514 | reg-names = "etm-base"; |
| 515 | |
| 516 | clocks = <&clock_aop QDSS_CLK>; |
| 517 | clock-names = "core_clk"; |
| 518 | |
| 519 | qcom,coresight-jtagmm-cpu = <&CPU0>; |
| 520 | }; |
| 521 | |
| 522 | jtag_mm1: jtagmm@7140000 { |
| 523 | compatible = "qcom,jtagv8-mm"; |
| 524 | reg = <0x7140000 0x1000>; |
| 525 | reg-names = "etm-base"; |
| 526 | |
| 527 | clocks = <&clock_aop QDSS_CLK>; |
| 528 | clock-names = "core_clk"; |
| 529 | |
| 530 | qcom,coresight-jtagmm-cpu = <&CPU1>; |
| 531 | }; |
| 532 | |
| 533 | jtag_mm2: jtagmm@7240000 { |
| 534 | compatible = "qcom,jtagv8-mm"; |
| 535 | reg = <0x7240000 0x1000>; |
| 536 | reg-names = "etm-base"; |
| 537 | |
| 538 | clocks = <&clock_aop QDSS_CLK>; |
| 539 | clock-names = "core_clk"; |
| 540 | |
| 541 | qcom,coresight-jtagmm-cpu = <&CPU2>; |
| 542 | }; |
| 543 | |
| 544 | jtag_mm3: jtagmm@7340000 { |
| 545 | compatible = "qcom,jtagv8-mm"; |
| 546 | reg = <0x7340000 0x1000>; |
| 547 | reg-names = "etm-base"; |
| 548 | |
| 549 | clocks = <&clock_aop QDSS_CLK>; |
| 550 | clock-names = "core_clk"; |
| 551 | |
| 552 | qcom,coresight-jtagmm-cpu = <&CPU3>; |
| 553 | }; |
| 554 | |
| 555 | jtag_mm4: jtagmm@7440000 { |
| 556 | compatible = "qcom,jtagv8-mm"; |
| 557 | reg = <0x7440000 0x1000>; |
| 558 | reg-names = "etm-base"; |
| 559 | |
| 560 | clocks = <&clock_aop QDSS_CLK>; |
| 561 | clock-names = "core_clk"; |
| 562 | |
| 563 | qcom,coresight-jtagmm-cpu = <&CPU4>; |
| 564 | }; |
| 565 | |
| 566 | jtag_mm5: jtagmm@7540000 { |
| 567 | compatible = "qcom,jtagv8-mm"; |
| 568 | reg = <0x7540000 0x1000>; |
| 569 | reg-names = "etm-base"; |
| 570 | |
| 571 | clocks = <&clock_aop QDSS_CLK>; |
| 572 | clock-names = "core_clk"; |
| 573 | |
| 574 | qcom,coresight-jtagmm-cpu = <&CPU5>; |
| 575 | }; |
| 576 | |
| 577 | jtag_mm6: jtagmm@7640000 { |
| 578 | compatible = "qcom,jtagv8-mm"; |
| 579 | reg = <0x7640000 0x1000>; |
| 580 | reg-names = "etm-base"; |
| 581 | |
| 582 | clocks = <&clock_aop QDSS_CLK>; |
| 583 | clock-names = "core_clk"; |
| 584 | |
| 585 | qcom,coresight-jtagmm-cpu = <&CPU6>; |
| 586 | }; |
| 587 | |
| 588 | jtag_mm7: jtagmm@7740000 { |
| 589 | compatible = "qcom,jtagv8-mm"; |
| 590 | reg = <0x7740000 0x1000>; |
| 591 | reg-names = "etm-base"; |
| 592 | |
| 593 | clocks = <&clock_aop QDSS_CLK>; |
| 594 | clock-names = "core_clk"; |
| 595 | |
| 596 | qcom,coresight-jtagmm-cpu = <&CPU7>; |
| 597 | }; |
| 598 | |
David Dai | 3c42780 | 2018-10-17 14:40:08 -0700 | [diff] [blame] | 599 | qcom,devfreq-l3 { |
| 600 | compatible = "qcom,devfreq-fw"; |
| 601 | reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>; |
| 602 | reg-names = "en-base", "ftbl-base", "perf-base"; |
| 603 | |
| 604 | qcom,cpu0-l3 { |
| 605 | compatible = "qcom,devfreq-fw-voter"; |
| 606 | }; |
| 607 | |
| 608 | qcom,cpu4-l3 { |
| 609 | compatible = "qcom,devfreq-fw-voter"; |
| 610 | }; |
| 611 | }; |
| 612 | |
Rishabh Bhatnagar | f35ba02 | 2018-09-18 15:17:22 -0700 | [diff] [blame] | 613 | qcom,msm-imem@146bf000 { |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 614 | compatible = "qcom,msm-imem"; |
| 615 | reg = <0x146bf000 0x1000>; |
| 616 | ranges = <0x0 0x146bf000 0x1000>; |
| 617 | #address-cells = <1>; |
| 618 | #size-cells = <1>; |
| 619 | |
| 620 | restart_reason@65c { |
| 621 | compatible = "qcom,msm-imem-restart_reason"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 622 | reg = <0x65c 0x4>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 623 | }; |
| 624 | |
| 625 | dload_type@1c { |
| 626 | compatible = "qcom,msm-imem-dload-type"; |
| 627 | reg = <0x1c 0x4>; |
| 628 | }; |
| 629 | |
| 630 | boot_stats@6b0 { |
| 631 | compatible = "qcom,msm-imem-boot_stats"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 632 | reg = <0x6b0 0x20>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 633 | }; |
| 634 | |
| 635 | kaslr_offset@6d0 { |
| 636 | compatible = "qcom,msm-imem-kaslr_offset"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 637 | reg = <0x6d0 0xc>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 638 | }; |
| 639 | |
| 640 | pil@94c { |
| 641 | compatible = "qcom,msm-imem-pil"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 642 | reg = <0x94c 0xc8>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 643 | }; |
| 644 | }; |
| 645 | |
Rishabh Bhatnagar | 811170f | 2018-11-09 13:44:32 -0800 | [diff] [blame] | 646 | restart@c264000 { |
| 647 | compatible = "qcom,pshold"; |
| 648 | reg = <0xc264000 0x4>, |
| 649 | <0x1fd3000 0x4>; |
| 650 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 651 | }; |
| 652 | |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 653 | mdm0: qcom,mdm0 { |
Rishabh Bhatnagar | 134ede8 | 2018-10-16 10:54:12 -0700 | [diff] [blame] | 654 | compatible = "qcom,ext-sdx55m"; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 655 | cell-index = <0>; |
| 656 | #address-cells = <0>; |
| 657 | interrupt-parent = <&mdm0>; |
| 658 | #interrupt-cells = <1>; |
| 659 | interrupt-map-mask = <0xffffffff>; |
| 660 | interrupt-names = |
| 661 | "err_fatal_irq", |
| 662 | "status_irq", |
| 663 | "mdm2ap_vddmin_irq"; |
| 664 | /* modem attributes */ |
| 665 | qcom,ramdump-delay-ms = <3000>; |
| 666 | qcom,ramdump-timeout-ms = <120000>; |
| 667 | qcom,vddmin-modes = "normal"; |
| 668 | qcom,vddmin-drive-strength = <8>; |
| 669 | qcom,sfr-query; |
| 670 | qcom,sysmon-id = <20>; |
| 671 | qcom,ssctl-instance-id = <0x10>; |
| 672 | qcom,support-shutdown; |
| 673 | qcom,pil-force-shutdown; |
| 674 | qcom,esoc-skip-restart-for-mdm-crash; |
| 675 | pinctrl-names = "default", "mdm_active", "mdm_suspend"; |
| 676 | pinctrl-0 = <&ap2mdm_pon_reset_default>; |
| 677 | pinctrl-1 = <&ap2mdm_active &mdm2ap_active>; |
| 678 | pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>; |
| 679 | interrupt-map = <0 &tlmm 1 0x3 |
| 680 | 1 &tlmm 3 0x3>; |
| 681 | qcom,mdm2ap-errfatal-gpio = <&tlmm 1 0x00>; |
| 682 | qcom,ap2mdm-errfatal-gpio = <&tlmm 57 0x00>; |
| 683 | qcom,mdm2ap-status-gpio = <&tlmm 3 0x00>; |
| 684 | qcom,ap2mdm-status-gpio = <&tlmm 56 0x00>; |
Rishabh Bhatnagar | 2b66dc1 | 2018-10-18 10:36:27 -0700 | [diff] [blame] | 685 | qcom,ap2mdm-soft-reset-gpio = <&tlmm 145 GPIO_ACTIVE_LOW>; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 686 | qcom,mdm-link-info = "0306_02.01.00"; |
| 687 | status = "ok"; |
| 688 | }; |
| 689 | |
Lina Iyer | 8551c79 | 2018-06-21 16:06:53 -0600 | [diff] [blame] | 690 | pdc: interrupt-controller@b220000 { |
| 691 | compatible = "qcom,kona-pdc"; |
| 692 | reg = <0xb220000 0x30000>; |
| 693 | qcom,pdc-ranges = <0 480 29>, <42 522 52>, <94 609 30>; |
| 694 | #interrupt-cells = <2>; |
| 695 | interrupt-parent = <&intc>; |
| 696 | interrupt-controller; |
| 697 | }; |
| 698 | |
David Collins | a6d833b | 2018-09-25 14:44:32 -0700 | [diff] [blame] | 699 | clock_xo: bi_tcxo { |
| 700 | compatible = "fixed-clock"; |
| 701 | #clock-cells = <0>; |
| 702 | clock-frequency = <19200000>; |
| 703 | clock-output-names = "bi_tcxo"; |
| 704 | }; |
| 705 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 706 | clocks { |
| 707 | sleep_clk: sleep-clk { |
| 708 | compatible = "fixed-clock"; |
| 709 | clock-frequency = <32000>; |
| 710 | clock-output-names = "chip_sleep_clk"; |
| 711 | #clock-cells = <1>; |
| 712 | }; |
| 713 | }; |
| 714 | |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 715 | clock_rpmh: qcom,rpmhclk { |
| 716 | compatible = "qcom,dummycc"; |
| 717 | clock-output-names = "rpmh_clocks"; |
| 718 | #clock-cells = <1>; |
| 719 | }; |
| 720 | |
| 721 | clock_aop: qcom,aopclk { |
| 722 | compatible = "qcom,dummycc"; |
| 723 | clock-output-names = "qdss_clocks"; |
| 724 | #clock-cells = <1>; |
| 725 | }; |
| 726 | |
Vivek Aknurwar | 7e9ecb9 | 2018-09-07 14:27:58 -0700 | [diff] [blame] | 727 | clock_gcc: qcom,gcc@100000 { |
| 728 | compatible = "qcom,gcc-kona"; |
| 729 | reg = <0x100000 0x1f0000>; |
| 730 | reg-names = "cc_base"; |
| 731 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 732 | vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; |
| 733 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 734 | #clock-cells = <1>; |
| 735 | #reset-cells = <1>; |
| 736 | }; |
| 737 | |
| 738 | clock_npucc: qcom,npucc { |
| 739 | compatible = "qcom,dummycc"; |
| 740 | clock-output-names = "npucc_clocks"; |
| 741 | #clock-cells = <1>; |
| 742 | #reset-cells = <1>; |
| 743 | }; |
| 744 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 745 | clock_videocc: qcom,videocc@abf0000 { |
| 746 | compatible = "qcom,videocc-kona", "syscon"; |
| 747 | reg = <0xabf0000 0x10000>; |
| 748 | reg-names = "cc_base"; |
| 749 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 750 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 751 | clock-names = "cfg_ahb_clk"; |
| 752 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 753 | #clock-cells = <1>; |
| 754 | #reset-cells = <1>; |
| 755 | }; |
| 756 | |
| 757 | clock_camcc: qcom,camcc { |
| 758 | compatible = "qcom,dummycc"; |
| 759 | clock-output-names = "camcc_clocks"; |
| 760 | #clock-cells = <1>; |
| 761 | #reset-cells = <1>; |
| 762 | }; |
| 763 | |
David Dai | dc93e48 | 2018-11-27 17:32:50 -0800 | [diff] [blame] | 764 | clock_dispcc: qcom,dispcc@af00000 { |
| 765 | compatible = "qcom,kona-dispcc"; |
| 766 | reg = <0xaf00000 0x20000>; |
| 767 | reg-names = "cc_base"; |
| 768 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 769 | clock-names = "cfg_ahb_clk"; |
| 770 | clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 771 | #clock-cells = <1>; |
| 772 | #reset-cells = <1>; |
| 773 | }; |
| 774 | |
| 775 | clock_gpucc: qcom,gpucc { |
| 776 | compatible = "qcom,dummycc"; |
| 777 | clock-output-names = "gpucc_clocks"; |
| 778 | #clock-cells = <1>; |
| 779 | #reset-cells = <1>; |
| 780 | }; |
| 781 | |
| 782 | clock_cpucc: qcom,cpucc { |
| 783 | compatible = "qcom,dummycc"; |
| 784 | clock-output-names = "cpucc_clocks"; |
| 785 | #clock-cells = <1>; |
| 786 | }; |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 787 | |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 788 | /* GCC GDSCs */ |
| 789 | pcie_0_gdsc: qcom,gdsc@16b004 { |
| 790 | compatible = "qcom,gdsc"; |
| 791 | reg = <0x16b004 0x4>; |
| 792 | regulator-name = "pcie_0_gdsc"; |
| 793 | }; |
| 794 | |
| 795 | pcie_1_gdsc: qcom,gdsc@18d004 { |
| 796 | compatible = "qcom,gdsc"; |
| 797 | reg = <0x18d004 0x4>; |
| 798 | regulator-name = "pcie_1_gdsc"; |
| 799 | }; |
| 800 | |
| 801 | pcie_2_gdsc: qcom,gdsc@106004 { |
| 802 | compatible = "qcom,gdsc"; |
| 803 | reg = <0x106004 0x4>; |
| 804 | regulator-name = "pcie_2_gdsc"; |
| 805 | }; |
| 806 | |
| 807 | ufs_card_gdsc: qcom,gdsc@175004 { |
| 808 | compatible = "qcom,gdsc"; |
| 809 | reg = <0x175004 0x4>; |
| 810 | regulator-name = "ufs_card_gdsc"; |
| 811 | }; |
| 812 | |
| 813 | ufs_phy_gdsc: qcom,gdsc@177004 { |
| 814 | compatible = "qcom,gdsc"; |
| 815 | reg = <0x177004 0x4>; |
| 816 | regulator-name = "ufs_phy_gdsc"; |
| 817 | }; |
| 818 | |
| 819 | usb30_prim_gdsc: qcom,gdsc@10f004 { |
| 820 | compatible = "qcom,gdsc"; |
| 821 | reg = <0x10f004 0x4>; |
| 822 | regulator-name = "usb30_prim_gdsc"; |
| 823 | }; |
| 824 | |
| 825 | usb30_sec_gdsc: qcom,gdsc@110004 { |
| 826 | compatible = "qcom,gdsc"; |
| 827 | reg = <0x110004 0x4>; |
| 828 | regulator-name = "usb30_sec_gdsc"; |
| 829 | }; |
| 830 | |
| 831 | hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { |
| 832 | compatible = "qcom,gdsc"; |
| 833 | reg = <0x17d050 0x4>; |
| 834 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; |
| 835 | qcom,no-status-check-on-disable; |
| 836 | qcom,gds-timeout = <500>; |
| 837 | }; |
| 838 | |
| 839 | hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { |
| 840 | compatible = "qcom,gdsc"; |
| 841 | reg = <0x17d058 0x4>; |
| 842 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; |
| 843 | qcom,no-status-check-on-disable; |
| 844 | qcom,gds-timeout = <500>; |
| 845 | }; |
| 846 | |
| 847 | hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 { |
| 848 | compatible = "qcom,gdsc"; |
| 849 | reg = <0x17d054 0x4>; |
| 850 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; |
| 851 | qcom,no-status-check-on-disable; |
| 852 | qcom,gds-timeout = <500>; |
| 853 | }; |
| 854 | |
| 855 | hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c { |
| 856 | compatible = "qcom,gdsc"; |
| 857 | reg = <0x17d06c 0x4>; |
| 858 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; |
| 859 | qcom,no-status-check-on-disable; |
| 860 | qcom,gds-timeout = <500>; |
| 861 | }; |
| 862 | |
| 863 | /* CAM_CC GDSCs */ |
| 864 | bps_gdsc: qcom,gdsc@ad07004 { |
| 865 | compatible = "qcom,gdsc"; |
| 866 | reg = <0xad07004 0x4>; |
| 867 | regulator-name = "bps_gdsc"; |
| 868 | clock-names = "ahb_clk"; |
| 869 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 870 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 871 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 872 | qcom,support-hw-trigger; |
| 873 | }; |
| 874 | |
| 875 | ife_0_gdsc: qcom,gdsc@ad0a004 { |
| 876 | compatible = "qcom,gdsc"; |
| 877 | reg = <0xad0a004 0x4>; |
| 878 | regulator-name = "ife_0_gdsc"; |
| 879 | clock-names = "ahb_clk"; |
| 880 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 881 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 882 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 883 | }; |
| 884 | |
| 885 | ife_1_gdsc: qcom,gdsc@ad0b004 { |
| 886 | compatible = "qcom,gdsc"; |
| 887 | reg = <0xad0b004 0x4>; |
| 888 | regulator-name = "ife_1_gdsc"; |
| 889 | clock-names = "ahb_clk"; |
| 890 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 891 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 892 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 893 | }; |
| 894 | |
| 895 | ipe_0_gdsc: qcom,gdsc@ad08004 { |
| 896 | compatible = "qcom,gdsc"; |
| 897 | reg = <0xad08004 0x4>; |
| 898 | regulator-name = "ipe_0_gdsc"; |
| 899 | clock-names = "ahb_clk"; |
| 900 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 901 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 902 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 903 | qcom,support-hw-trigger; |
| 904 | }; |
| 905 | |
| 906 | sbi_gdsc: qcom,gdsc@ad09004 { |
| 907 | compatible = "qcom,gdsc"; |
| 908 | reg = <0xad09004 0x4>; |
| 909 | regulator-name = "sbi_gdsc"; |
| 910 | clock-names = "ahb_clk"; |
| 911 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 912 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 913 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 914 | }; |
| 915 | |
| 916 | titan_top_gdsc: qcom,gdsc@ad0c144 { |
| 917 | compatible = "qcom,gdsc"; |
| 918 | reg = <0xad0c144 0x4>; |
| 919 | regulator-name = "titan_top_gdsc"; |
| 920 | clock-names = "ahb_clk"; |
| 921 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 922 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 923 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 924 | }; |
| 925 | |
| 926 | /* DISP_CC GDSC */ |
| 927 | mdss_core_gdsc: qcom,gdsc@af03000 { |
| 928 | compatible = "qcom,gdsc"; |
| 929 | reg = <0xaf03000 0x4>; |
| 930 | regulator-name = "mdss_core_gdsc"; |
| 931 | clock-names = "ahb_clk"; |
| 932 | clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
| 933 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 934 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 935 | qcom,support-hw-trigger; |
| 936 | }; |
| 937 | |
| 938 | /* GPU_CC GDSCs */ |
| 939 | gpu_cx_hw_ctrl: syscon@3d91540 { |
| 940 | compatible = "syscon"; |
| 941 | reg = <0x3d91540 0x4>; |
| 942 | }; |
| 943 | |
| 944 | gpu_cx_gdsc: qcom,gdsc@3d9106c { |
| 945 | compatible = "qcom,gdsc"; |
| 946 | reg = <0x3d9106c 0x4>; |
| 947 | regulator-name = "gpu_cx_gdsc"; |
| 948 | hw-ctrl-addr = <&gpu_cx_hw_ctrl>; |
| 949 | parent-supply = <&VDD_CX_LEVEL>; |
| 950 | qcom,no-status-check-on-disable; |
| 951 | qcom,clk-dis-wait-val = <8>; |
| 952 | qcom,gds-timeout = <500>; |
| 953 | }; |
| 954 | |
David Collins | d7eea14 | 2018-10-08 17:32:48 -0700 | [diff] [blame] | 955 | gpu_gx_domain_addr: syscon@3d91508 { |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 956 | compatible = "syscon"; |
| 957 | reg = <0x3d91508 0x4>; |
| 958 | }; |
| 959 | |
David Collins | d7eea14 | 2018-10-08 17:32:48 -0700 | [diff] [blame] | 960 | gpu_gx_sw_reset: syscon@3d91008 { |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 961 | compatible = "syscon"; |
| 962 | reg = <0x3d91008 0x4>; |
| 963 | }; |
| 964 | |
| 965 | gpu_gx_gdsc: qcom,gdsc@3d9100c { |
| 966 | compatible = "qcom,gdsc"; |
| 967 | reg = <0x3d9100c 0x4>; |
| 968 | regulator-name = "gpu_gx_gdsc"; |
| 969 | domain-addr = <&gpu_gx_domain_addr>; |
| 970 | sw-reset = <&gpu_gx_sw_reset>; |
| 971 | parent-supply = <&VDD_GFX_LEVEL>; |
| 972 | vdd_parent-supply = <&VDD_GFX_LEVEL>; |
| 973 | qcom,reset-aon-logic; |
| 974 | }; |
| 975 | |
| 976 | /* NPU GDSC */ |
| 977 | npu_core_gdsc: qcom,gdsc@9981004 { |
| 978 | compatible = "qcom,gdsc"; |
| 979 | reg = <0x9981004 0x4>; |
| 980 | regulator-name = "npu_core_gdsc"; |
| 981 | clock-names = "ahb_clk"; |
| 982 | clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; |
| 983 | }; |
| 984 | |
Jishnu Prakash | 793bf5b | 2018-11-09 16:28:55 +0530 | [diff] [blame] | 985 | qcom,sps { |
| 986 | compatible = "qcom,msm-sps-4k"; |
| 987 | qcom,pipe-attr-ee; |
| 988 | }; |
| 989 | |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 990 | /* VIDEO_CC GDSCs */ |
| 991 | mvs0_gdsc: qcom,gdsc@abf0d18 { |
| 992 | compatible = "qcom,gdsc"; |
| 993 | reg = <0xabf0d18 0x4>; |
| 994 | regulator-name = "mvs0_gdsc"; |
| 995 | clock-names = "ahb_clk"; |
| 996 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 997 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 998 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 999 | }; |
| 1000 | |
| 1001 | mvs0c_gdsc: qcom,gdsc@abf0bf8 { |
| 1002 | compatible = "qcom,gdsc"; |
| 1003 | reg = <0xabf0bf8 0x4>; |
| 1004 | regulator-name = "mvs0c_gdsc"; |
| 1005 | clock-names = "ahb_clk"; |
| 1006 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1007 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1008 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1009 | }; |
| 1010 | |
| 1011 | mvs1_gdsc: qcom,gdsc@abf0d98 { |
| 1012 | compatible = "qcom,gdsc"; |
| 1013 | reg = <0xabf0d98 0x4>; |
| 1014 | regulator-name = "mvs1_gdsc"; |
| 1015 | clock-names = "ahb_clk"; |
| 1016 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1017 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1018 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1019 | }; |
| 1020 | |
| 1021 | mvs1c_gdsc: qcom,gdsc@abf0c98 { |
| 1022 | compatible = "qcom,gdsc"; |
| 1023 | reg = <0xabf0c98 0x4>; |
| 1024 | regulator-name = "mvs1c_gdsc"; |
| 1025 | clock-names = "ahb_clk"; |
| 1026 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1027 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1028 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1029 | }; |
| 1030 | |
David Collins | c2c02f6 | 2018-11-05 16:23:24 -0800 | [diff] [blame] | 1031 | spmi_bus: qcom,spmi@c440000 { |
| 1032 | compatible = "qcom,spmi-pmic-arb"; |
| 1033 | reg = <0xc440000 0x1100>, |
| 1034 | <0xc600000 0x2000000>, |
| 1035 | <0xe600000 0x100000>, |
| 1036 | <0xe700000 0xa0000>, |
| 1037 | <0xc40a000 0x26000>; |
| 1038 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 1039 | interrupt-names = "periph_irq"; |
| 1040 | interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; |
| 1041 | qcom,ee = <0>; |
| 1042 | qcom,channel = <0>; |
| 1043 | #address-cells = <2>; |
| 1044 | #size-cells = <0>; |
| 1045 | interrupt-controller; |
| 1046 | #interrupt-cells = <4>; |
| 1047 | cell-index = <0>; |
| 1048 | }; |
| 1049 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1050 | ufsphy_mem: ufsphy_mem@1d87000 { |
| 1051 | reg = <0x1d87000 0xe00>; /* PHY regs */ |
| 1052 | reg-names = "phy_mem"; |
| 1053 | #phy-cells = <0>; |
| 1054 | |
| 1055 | lanes-per-direction = <2>; |
| 1056 | |
| 1057 | clock-names = "ref_clk_src", |
| 1058 | "ref_clk", |
| 1059 | "ref_aux_clk"; |
| 1060 | clocks = <&clock_rpmh RPMH_CXO_CLK>, |
Vivek Aknurwar | ec5c93d | 2018-08-28 14:52:33 -0700 | [diff] [blame] | 1061 | <&clock_gcc GCC_UFS_1X_CLKREF_EN>, |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1062 | <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| 1063 | |
| 1064 | status = "disabled"; |
| 1065 | }; |
| 1066 | |
| 1067 | ufshc_mem: ufshc@1d84000 { |
| 1068 | compatible = "qcom,ufshc"; |
| 1069 | reg = <0x1d84000 0x3000>; |
| 1070 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| 1071 | phys = <&ufsphy_mem>; |
| 1072 | phy-names = "ufsphy"; |
| 1073 | |
| 1074 | lanes-per-direction = <2>; |
| 1075 | dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| 1076 | |
| 1077 | clock-names = |
| 1078 | "core_clk", |
| 1079 | "bus_aggr_clk", |
| 1080 | "iface_clk", |
| 1081 | "core_clk_unipro", |
| 1082 | "core_clk_ice", |
| 1083 | "ref_clk", |
| 1084 | "tx_lane0_sync_clk", |
| 1085 | "rx_lane0_sync_clk", |
| 1086 | "rx_lane1_sync_clk"; |
| 1087 | clocks = |
| 1088 | <&clock_gcc GCC_UFS_PHY_AXI_CLK>, |
| 1089 | <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| 1090 | <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| 1091 | <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| 1092 | <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, |
| 1093 | <&clock_rpmh RPMH_CXO_CLK>, |
| 1094 | <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| 1095 | <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| 1096 | <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| 1097 | freq-table-hz = |
| 1098 | <37500000 300000000>, |
| 1099 | <0 0>, |
| 1100 | <0 0>, |
| 1101 | <37500000 300000000>, |
| 1102 | <75000000 300000000>, |
| 1103 | <0 0>, |
| 1104 | <0 0>, |
| 1105 | <0 0>, |
| 1106 | <0 0>; |
| 1107 | |
| 1108 | qcom,msm-bus,name = "ufshc_mem"; |
| 1109 | qcom,msm-bus,num-cases = <22>; |
| 1110 | qcom,msm-bus,num-paths = <2>; |
| 1111 | qcom,msm-bus,vectors-KBps = |
| 1112 | /* |
| 1113 | * During HS G3 UFS runs at nominal voltage corner, vote |
| 1114 | * higher bandwidth to push other buses in the data path |
| 1115 | * to run at nominal to achieve max throughput. |
| 1116 | * 4GBps pushes BIMC to run at nominal. |
| 1117 | * 200MBps pushes CNOC to run at nominal. |
| 1118 | * Vote for half of this bandwidth for HS G3 1-lane. |
| 1119 | * For max bandwidth, vote high enough to push the buses |
| 1120 | * to run in turbo voltage corner. |
| 1121 | */ |
| 1122 | <123 512 0 0>, <1 757 0 0>, /* No vote */ |
| 1123 | <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ |
| 1124 | <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ |
| 1125 | <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ |
| 1126 | <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ |
| 1127 | <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */ |
| 1128 | <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */ |
| 1129 | <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */ |
| 1130 | <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */ |
| 1131 | <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ |
| 1132 | <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ |
| 1133 | <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ |
| 1134 | <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ |
| 1135 | <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ |
| 1136 | <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ |
| 1137 | <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ |
| 1138 | <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ |
| 1139 | <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ |
| 1140 | <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ |
| 1141 | <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ |
| 1142 | /* As UFS working in HS G3 RB L2 mode, aggregated |
| 1143 | * bandwidth (AB) should take care of providing |
| 1144 | * optimum throughput requested. However, as tested, |
| 1145 | * in order to scale up CNOC clock, instantaneous |
| 1146 | * bindwidth (IB) needs to be given a proper value too. |
| 1147 | */ |
| 1148 | <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ |
| 1149 | <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ |
| 1150 | |
| 1151 | qcom,bus-vector-names = "MIN", |
| 1152 | "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", |
| 1153 | "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", |
| 1154 | "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", |
| 1155 | "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", |
| 1156 | "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", |
| 1157 | "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", |
| 1158 | "MAX"; |
| 1159 | |
| 1160 | /* PM QoS */ |
| 1161 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1162 | qcom,pm-qos-cpu-group-latency-us = <44 44>; |
| 1163 | qcom,pm-qos-default-cpu = <0>; |
| 1164 | |
| 1165 | pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; |
| 1166 | pinctrl-0 = <&ufs_dev_reset_assert>; |
| 1167 | pinctrl-1 = <&ufs_dev_reset_deassert>; |
| 1168 | |
| 1169 | resets = <&clock_gcc GCC_UFS_PHY_BCR>; |
| 1170 | reset-names = "core_reset"; |
| 1171 | |
| 1172 | status = "disabled"; |
| 1173 | }; |
| 1174 | |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 1175 | ipcc_mproc: qcom,ipcc@408000 { |
| 1176 | compatible = "qcom,kona-ipcc"; |
| 1177 | reg = <0x408000 0x1000>; |
| 1178 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| 1179 | interrupt-controller; |
| 1180 | #interrupt-cells = <3>; |
| 1181 | #mbox-cells = <2>; |
| 1182 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1183 | |
Raghavendra Rao Ananta | 5da54b3 | 2018-08-09 10:04:50 -0700 | [diff] [blame] | 1184 | ipcc_self_ping: ipcc-self-ping { |
| 1185 | compatible = "qcom,ipcc-self-ping"; |
| 1186 | interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS |
| 1187 | IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>; |
| 1188 | mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>; |
| 1189 | }; |
| 1190 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 1191 | apps_rsc: rsc@18200000 { |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1192 | label = "apps_rsc"; |
| 1193 | compatible = "qcom,rpmh-rsc"; |
| 1194 | reg = <0x18200000 0x10000>, |
| 1195 | <0x18210000 0x10000>, |
| 1196 | <0x18220000 0x10000>; |
| 1197 | reg-names = "drv-0", "drv-1", "drv-2"; |
| 1198 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 1199 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 1200 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 1201 | qcom,tcs-offset = <0xd00>; |
| 1202 | qcom,drv-id = <2>; |
| 1203 | qcom,tcs-config = <ACTIVE_TCS 2>, |
| 1204 | <SLEEP_TCS 3>, |
| 1205 | <WAKE_TCS 3>, |
| 1206 | <CONTROL_TCS 1>; |
David Dai | 07c8d4e | 2018-10-09 14:22:06 -0700 | [diff] [blame] | 1207 | |
| 1208 | msm_bus_apps_rsc { |
| 1209 | compatible = "qcom,msm-bus-rsc"; |
| 1210 | qcom,msm-bus-id = <MSM_BUS_RSC_APPS>; |
| 1211 | }; |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 1212 | |
| 1213 | system_pm { |
| 1214 | compatible = "qcom,system-pm"; |
| 1215 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1216 | }; |
| 1217 | |
| 1218 | disp_rsc: rsc@af20000 { |
| 1219 | label = "disp_rsc"; |
| 1220 | compatible = "qcom,rpmh-rsc"; |
| 1221 | reg = <0xaf20000 0x10000>; |
| 1222 | reg-names = "drv-0"; |
| 1223 | interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
| 1224 | qcom,tcs-offset = <0x1c00>; |
| 1225 | qcom,drv-id = <0>; |
| 1226 | qcom,tcs-config = <ACTIVE_TCS 0>, |
| 1227 | <SLEEP_TCS 1>, |
| 1228 | <WAKE_TCS 1>, |
| 1229 | <CONTROL_TCS 0>; |
| 1230 | status = "disabled"; |
| 1231 | }; |
Chris Lew | 86f6bde | 2018-09-06 16:40:39 -0700 | [diff] [blame] | 1232 | |
| 1233 | tcsr_mutex_block: syscon@1f40000 { |
| 1234 | compatible = "syscon"; |
| 1235 | reg = <0x1f40000 0x20000>; |
| 1236 | }; |
| 1237 | |
| 1238 | tcsr_mutex: hwlock { |
| 1239 | compatible = "qcom,tcsr-mutex"; |
| 1240 | syscon = <&tcsr_mutex_block 0 0x1000>; |
| 1241 | #hwlock-cells = <1>; |
| 1242 | }; |
| 1243 | |
| 1244 | smem: qcom,smem { |
| 1245 | compatible = "qcom,smem"; |
| 1246 | memory-region = <&smem_mem>; |
| 1247 | hwlocks = <&tcsr_mutex 3>; |
| 1248 | }; |
Venkata Narendra Kumar Gutta | 1781e56 | 2018-10-09 14:44:10 -0700 | [diff] [blame] | 1249 | |
| 1250 | kryo-erp { |
| 1251 | compatible = "arm,arm64-kryo-cpu-erp"; |
| 1252 | interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 1253 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 1254 | interrupt-names = "l1-l2-faultirq", |
| 1255 | "l3-scu-faultirq"; |
| 1256 | }; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1257 | |
Chris Lew | 3b1f098 | 2018-10-05 17:28:21 -0700 | [diff] [blame] | 1258 | sp_scsr: mailbox@188501c { |
| 1259 | compatible = "qcom,kona-spcs-global"; |
| 1260 | reg = <0x188501c 0x4>; |
| 1261 | |
| 1262 | #mbox-cells = <1>; |
| 1263 | }; |
| 1264 | |
| 1265 | sp_scsr_block: syscon@1880000 { |
| 1266 | compatible = "syscon"; |
| 1267 | reg = <0x1880000 0x10000>; |
| 1268 | }; |
| 1269 | |
| 1270 | intsp: qcom,qsee_irq { |
| 1271 | compatible = "qcom,kona-qsee-irq"; |
| 1272 | |
| 1273 | syscon = <&sp_scsr_block>; |
| 1274 | interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, |
| 1275 | <0 349 IRQ_TYPE_LEVEL_HIGH>; |
| 1276 | |
| 1277 | interrupt-names = "sp_ipc0", |
| 1278 | "sp_ipc1"; |
| 1279 | |
| 1280 | interrupt-controller; |
| 1281 | #interrupt-cells = <3>; |
| 1282 | }; |
| 1283 | |
| 1284 | qcom,qsee_irq_bridge { |
| 1285 | compatible = "qcom,qsee-ipc-irq-bridge"; |
| 1286 | |
| 1287 | qcom,qsee-ipc-irq-spss { |
| 1288 | qcom,dev-name = "qsee_ipc_irq_spss"; |
| 1289 | label = "spss"; |
| 1290 | interrupt-parent = <&intsp>; |
| 1291 | interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; |
| 1292 | }; |
| 1293 | }; |
| 1294 | |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 1295 | qcom,msm_gsi { |
| 1296 | compatible = "qcom,msm_gsi"; |
| 1297 | }; |
| 1298 | |
| 1299 | qcom,rmnet-ipa { |
| 1300 | compatible = "qcom,rmnet-ipa3"; |
| 1301 | qcom,rmnet-ipa-ssr; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 1302 | qcom,ipa-advertise-sg-support; |
| 1303 | qcom,ipa-napi-enable; |
| 1304 | }; |
| 1305 | |
| 1306 | qcom,ipa_fws { |
| 1307 | compatible = "qcom,pil-tz-generic"; |
| 1308 | qcom,pas-id = <0xf>; |
| 1309 | qcom,firmware-name = "ipa_fws"; |
| 1310 | qcom,pil-force-shutdown; |
| 1311 | memory-region = <&pil_ipa_fw_mem>; |
| 1312 | }; |
| 1313 | |
| 1314 | ipa_hw: qcom,ipa@1e00000 { |
| 1315 | compatible = "qcom,ipa"; |
| 1316 | reg = |
| 1317 | <0x1e00000 0x84000>, |
| 1318 | <0x1e04000 0x23000>; |
| 1319 | reg-names = "ipa-base", "gsi-base"; |
| 1320 | interrupts = |
| 1321 | <0 311 IRQ_TYPE_LEVEL_HIGH>, |
| 1322 | <0 432 IRQ_TYPE_LEVEL_HIGH>; |
| 1323 | interrupt-names = "ipa-irq", "gsi-irq"; |
| 1324 | qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */ |
| 1325 | qcom,ipa-hw-mode = <0>; |
Ghanim Fodi | f8dcdbf | 2018-11-04 17:58:22 +0200 | [diff] [blame^] | 1326 | qcom,platform-type = <2>; /* APQ platform */ |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 1327 | qcom,ee = <0>; |
| 1328 | qcom,use-ipa-tethering-bridge; |
| 1329 | qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ |
| 1330 | qcom,modem-cfg-emb-pipe-flt; |
| 1331 | qcom,use-ipa-pm; |
| 1332 | qcom,bandwidth-vote-for-ipa; |
| 1333 | qcom,use-64-bit-dma-mask; |
| 1334 | qcom,msm-bus,name = "ipa"; |
| 1335 | qcom,msm-bus,num-cases = <5>; |
| 1336 | qcom,msm-bus,num-paths = <4>; |
| 1337 | qcom,msm-bus,vectors-KBps = |
| 1338 | /* No vote */ |
| 1339 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 1340 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>, |
| 1341 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>, |
| 1342 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>, |
| 1343 | |
| 1344 | /* SVS2 */ |
| 1345 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 600000>, |
| 1346 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 350000>, |
| 1347 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 40000 40000>, |
| 1348 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 125>, |
| 1349 | |
| 1350 | /* SVS */ |
| 1351 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 640000>, |
| 1352 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 640000>, |
| 1353 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 80000>, |
| 1354 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 250>, |
| 1355 | |
| 1356 | /* NOMINAL */ |
| 1357 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 960000>, |
| 1358 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 960000>, |
| 1359 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 160000>, |
| 1360 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 500>, |
| 1361 | |
| 1362 | /* TURBO */ |
| 1363 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 3600000>, |
| 1364 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 3600000>, |
| 1365 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 300000>, |
| 1366 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 600>; |
| 1367 | |
| 1368 | qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", |
| 1369 | "TURBO"; |
| 1370 | qcom,throughput-threshold = <310 600 1000>; |
| 1371 | qcom,scaling-exceptions = <>; |
| 1372 | }; |
| 1373 | |
| 1374 | ipa_smmu_ap: ipa_smmu_ap { |
| 1375 | compatible = "qcom,ipa-smmu-ap-cb"; |
| 1376 | iommus = <&apps_smmu 0x5C0 0x0>; |
| 1377 | qcom,iommu-dma = "bypass"; |
| 1378 | }; |
| 1379 | |
| 1380 | ipa_smmu_wlan: ipa_smmu_wlan { |
| 1381 | compatible = "qcom,ipa-smmu-wlan-cb"; |
| 1382 | iommus = <&apps_smmu 0x5C1 0x0>; |
| 1383 | qcom,iommu-dma = "bypass"; |
| 1384 | }; |
| 1385 | |
| 1386 | ipa_smmu_uc: ipa_smmu_uc { |
| 1387 | compatible = "qcom,ipa-smmu-uc-cb"; |
| 1388 | iommus = <&apps_smmu 0x5C2 0x0>; |
| 1389 | qcom,iommu-dma = "bypass"; |
| 1390 | }; |
| 1391 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1392 | qcom,glink { |
| 1393 | compatible = "qcom,glink"; |
| 1394 | #address-cells = <1>; |
| 1395 | #size-cells = <1>; |
| 1396 | ranges; |
| 1397 | |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 1398 | glink_npu: npu { |
| 1399 | qcom,remote-pid = <10>; |
| 1400 | transport = "smem"; |
| 1401 | mboxes = <&ipcc_mproc IPCC_CLIENT_NPU |
| 1402 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1403 | mbox-names = "npu_smem"; |
| 1404 | interrupt-parent = <&ipcc_mproc>; |
| 1405 | interrupts = <IPCC_CLIENT_NPU |
| 1406 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1407 | IRQ_TYPE_EDGE_RISING>; |
| 1408 | |
| 1409 | label = "npu"; |
| 1410 | qcom,glink-label = "npu"; |
| 1411 | |
| 1412 | qcom,npu_qrtr { |
| 1413 | qcom,glink-channels = "IPCRTR"; |
| 1414 | qcom,intents = <0x800 5 |
| 1415 | 0x2000 3 |
| 1416 | 0x4400 2>; |
| 1417 | }; |
| 1418 | |
| 1419 | qcom,npu_glink_ssr { |
| 1420 | qcom,glink-channels = "glink_ssr"; |
| 1421 | qcom,notify-edges = <&glink_cdsp>; |
| 1422 | }; |
| 1423 | }; |
| 1424 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1425 | glink_adsp: adsp { |
| 1426 | qcom,remote-pid = <2>; |
| 1427 | transport = "smem"; |
| 1428 | mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS |
| 1429 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1430 | mbox-names = "adsp_smem"; |
| 1431 | interrupt-parent = <&ipcc_mproc>; |
| 1432 | interrupts = <IPCC_CLIENT_LPASS |
| 1433 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1434 | IRQ_TYPE_EDGE_RISING>; |
| 1435 | |
| 1436 | label = "adsp"; |
| 1437 | qcom,glink-label = "lpass"; |
| 1438 | |
| 1439 | qcom,adsp_qrtr { |
| 1440 | qcom,glink-channels = "IPCRTR"; |
| 1441 | qcom,intents = <0x800 5 |
| 1442 | 0x2000 3 |
| 1443 | 0x4400 2>; |
| 1444 | }; |
| 1445 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1446 | qcom,msm_fastrpc_rpmsg { |
| 1447 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 1448 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 1449 | qcom,intents = <0x64 64>; |
| 1450 | }; |
| 1451 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1452 | qcom,adsp_glink_ssr { |
| 1453 | qcom,glink-channels = "glink_ssr"; |
| 1454 | qcom,notify-edges = <&glink_slpi>, |
| 1455 | <&glink_cdsp>; |
| 1456 | }; |
| 1457 | }; |
| 1458 | |
| 1459 | glink_slpi: dsps { |
| 1460 | qcom,remote-pid = <3>; |
| 1461 | transport = "smem"; |
| 1462 | mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI |
| 1463 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1464 | mbox-names = "dsps_smem"; |
| 1465 | interrupt-parent = <&ipcc_mproc>; |
| 1466 | interrupts = <IPCC_CLIENT_SLPI |
| 1467 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1468 | IRQ_TYPE_EDGE_RISING>; |
| 1469 | |
| 1470 | label = "slpi"; |
| 1471 | qcom,glink-label = "dsps"; |
| 1472 | |
| 1473 | qcom,slpi_qrtr { |
| 1474 | qcom,glink-channels = "IPCRTR"; |
| 1475 | qcom,intents = <0x800 5 |
| 1476 | 0x2000 3 |
| 1477 | 0x4400 2>; |
| 1478 | }; |
| 1479 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1480 | qcom,msm_fastrpc_rpmsg { |
| 1481 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 1482 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 1483 | qcom,intents = <0x64 64>; |
| 1484 | }; |
| 1485 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1486 | qcom,slpi_glink_ssr { |
| 1487 | qcom,glink-channels = "glink_ssr"; |
| 1488 | qcom,notify-edges = <&glink_adsp>, |
| 1489 | <&glink_cdsp>; |
| 1490 | }; |
| 1491 | }; |
| 1492 | |
| 1493 | glink_cdsp: cdsp { |
| 1494 | qcom,remote-pid = <5>; |
| 1495 | transport = "smem"; |
| 1496 | mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP |
| 1497 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1498 | mbox-names = "dsps_smem"; |
| 1499 | interrupt-parent = <&ipcc_mproc>; |
| 1500 | interrupts = <IPCC_CLIENT_CDSP |
| 1501 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1502 | IRQ_TYPE_EDGE_RISING>; |
| 1503 | |
| 1504 | label = "cdsp"; |
| 1505 | qcom,glink-label = "cdsp"; |
| 1506 | |
| 1507 | qcom,cdsp_qrtr { |
| 1508 | qcom,glink-channels = "IPCRTR"; |
| 1509 | qcom,intents = <0x800 5 |
| 1510 | 0x2000 3 |
| 1511 | 0x4400 2>; |
| 1512 | }; |
| 1513 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1514 | qcom,msm_fastrpc_rpmsg { |
| 1515 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 1516 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 1517 | qcom,intents = <0x64 64>; |
| 1518 | }; |
| 1519 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1520 | qcom,cdsp_glink_ssr { |
| 1521 | qcom,glink-channels = "glink_ssr"; |
| 1522 | qcom,notify-edges = <&glink_adsp>, |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 1523 | <&glink_slpi>, |
| 1524 | <&glink_npu>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1525 | }; |
| 1526 | }; |
Chris Lew | 3b1f098 | 2018-10-05 17:28:21 -0700 | [diff] [blame] | 1527 | |
| 1528 | glink_spss: spss { |
| 1529 | qcom,remote-pid = <8>; |
| 1530 | transport = "spss"; |
| 1531 | mboxes = <&sp_scsr 0>; |
| 1532 | mbox-names = "spss_spss"; |
| 1533 | interrupt-parent = <&intsp>; |
| 1534 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
| 1535 | |
| 1536 | reg = <0x1885008 0x8>, |
| 1537 | <0x1885010 0x4>; |
| 1538 | reg-names = "qcom,spss-addr", |
| 1539 | "qcom,spss-size"; |
| 1540 | |
| 1541 | label = "spss"; |
| 1542 | qcom,glink-label = "spss"; |
| 1543 | }; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1544 | }; |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 1545 | |
| 1546 | qcom,lpass@17300000 { |
| 1547 | compatible = "qcom,pil-tz-generic"; |
| 1548 | reg = <0x17300000 0x00100>; |
| 1549 | |
| 1550 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1551 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 1552 | qcom,proxy-reg-names = "vdd_cx"; |
| 1553 | |
| 1554 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 1555 | clock-names = "xo"; |
| 1556 | qcom,proxy-clock-names = "xo"; |
| 1557 | |
| 1558 | qcom,pas-id = <1>; |
| 1559 | qcom,proxy-timeout-ms = <10000>; |
| 1560 | qcom,smem-id = <423>; |
| 1561 | qcom,sysmon-id = <1>; |
| 1562 | qcom,ssctl-instance-id = <0x14>; |
| 1563 | qcom,firmware-name = "adsp"; |
| 1564 | memory-region = <&pil_adsp_mem>; |
| 1565 | qcom,complete-ramdump; |
| 1566 | |
| 1567 | /* Inputs from lpass */ |
| 1568 | interrupts-extended = <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, |
| 1569 | <&adsp_smp2p_in 0 0>, |
| 1570 | <&adsp_smp2p_in 2 0>, |
| 1571 | <&adsp_smp2p_in 1 0>, |
| 1572 | <&adsp_smp2p_in 3 0>; |
| 1573 | |
| 1574 | interrupt-names = "qcom,wdog", |
| 1575 | "qcom,err-fatal", |
| 1576 | "qcom,proxy-unvote", |
| 1577 | "qcom,err-ready", |
| 1578 | "qcom,stop-ack"; |
| 1579 | |
| 1580 | /* Outputs to lpass */ |
| 1581 | qcom,smem-states = <&adsp_smp2p_out 0>; |
| 1582 | qcom,smem-state-names = "qcom,force-stop"; |
| 1583 | |
| 1584 | mbox-names = "adsp-pil"; |
| 1585 | }; |
| 1586 | |
| 1587 | qcom,turing@8300000 { |
| 1588 | compatible = "qcom,pil-tz-generic"; |
| 1589 | reg = <0x8300000 0x100000>; |
| 1590 | |
| 1591 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1592 | qcom,proxy-reg-names = "vdd_cx"; |
| 1593 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 1594 | |
| 1595 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 1596 | clock-names = "xo"; |
| 1597 | qcom,proxy-clock-names = "xo"; |
| 1598 | |
| 1599 | qcom,pas-id = <18>; |
| 1600 | qcom,proxy-timeout-ms = <10000>; |
| 1601 | qcom,smem-id = <601>; |
| 1602 | qcom,sysmon-id = <7>; |
| 1603 | qcom,ssctl-instance-id = <0x17>; |
| 1604 | qcom,firmware-name = "cdsp"; |
| 1605 | memory-region = <&pil_cdsp_mem>; |
| 1606 | qcom,complete-ramdump; |
| 1607 | |
| 1608 | qcom,msm-bus,name = "pil-cdsp"; |
| 1609 | qcom,msm-bus,num-cases = <2>; |
| 1610 | qcom,msm-bus,num-paths = <1>; |
| 1611 | qcom,msm-bus,vectors-KBps = |
| 1612 | <154 10070 0 0>, |
| 1613 | <154 10070 0 1>; |
| 1614 | |
| 1615 | /* Inputs from turing */ |
Bruce Levy | 821133c | 2018-11-29 11:34:45 -0800 | [diff] [blame] | 1616 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 1617 | <&cdsp_smp2p_in 0 0>, |
| 1618 | <&cdsp_smp2p_in 2 0>, |
| 1619 | <&cdsp_smp2p_in 1 0>, |
| 1620 | <&cdsp_smp2p_in 3 0>; |
| 1621 | |
| 1622 | interrupt-names = "qcom,wdog", |
| 1623 | "qcom,err-fatal", |
| 1624 | "qcom,proxy-unvote", |
| 1625 | "qcom,err-ready", |
| 1626 | "qcom,stop-ack"; |
| 1627 | |
| 1628 | /* Outputs to turing */ |
| 1629 | qcom,smem-states = <&cdsp_smp2p_out 0>; |
| 1630 | qcom,smem-state-names = "qcom,force-stop"; |
| 1631 | |
| 1632 | mbox-names = "cdsp-pil"; |
| 1633 | }; |
Akshay Chandrashekhar Kalghatgi | f7905ad | 2018-11-08 16:30:42 -0800 | [diff] [blame] | 1634 | |
| 1635 | qcom,venus@aab0000 { |
| 1636 | compatible = "qcom,pil-tz-generic"; |
| 1637 | reg = <0xaab0000 0x2000>; |
Chinmay Sawarkar | 2cfeca0 | 2018-11-15 17:59:36 -0800 | [diff] [blame] | 1638 | |
| 1639 | vdd-supply = <&mvs0c_gdsc>; |
| 1640 | qcom,proxy-reg-names = "vdd"; |
| 1641 | qcom,complete-ramdump; |
| 1642 | |
| 1643 | clocks = <&clock_videocc VIDEO_CC_XO_CLK>, |
| 1644 | <&clock_videocc VIDEO_CC_MVS0C_CLK>, |
| 1645 | <&clock_videocc VIDEO_CC_AHB_CLK>; |
| 1646 | clock-names = "xo", "core", "ahb"; |
| 1647 | qcom,proxy-clock-names = "xo", "core", "ahb"; |
| 1648 | |
Akshay Chandrashekhar Kalghatgi | f7905ad | 2018-11-08 16:30:42 -0800 | [diff] [blame] | 1649 | qcom,core-freq = <200000000>; |
| 1650 | qcom,ahb-freq = <200000000>; |
| 1651 | |
| 1652 | qcom,pas-id = <9>; |
| 1653 | qcom,msm-bus,name = "pil-venus"; |
| 1654 | qcom,msm-bus,num-cases = <2>; |
| 1655 | qcom,msm-bus,num-paths = <1>; |
| 1656 | qcom,msm-bus,vectors-KBps = |
| 1657 | <63 512 0 0>, |
| 1658 | <63 512 0 304000>; |
| 1659 | qcom,proxy-timeout-ms = <100>; |
| 1660 | qcom,firmware-name = "venus"; |
| 1661 | memory-region = <&pil_video_mem>; |
| 1662 | }; |
Tharun Kumar Merugu | b8d79dd | 2018-11-02 23:07:31 +0530 | [diff] [blame] | 1663 | |
| 1664 | qcom,msm-cdsp-loader { |
| 1665 | compatible = "qcom,cdsp-loader"; |
| 1666 | qcom,proc-img-to-load = "cdsp"; |
| 1667 | }; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1668 | |
| 1669 | qcom,msm-adsprpc-mem { |
| 1670 | compatible = "qcom,msm-adsprpc-mem-region"; |
| 1671 | memory-region = <&adsp_mem>; |
| 1672 | }; |
| 1673 | |
| 1674 | msm_fastrpc: qcom,msm_fastrpc { |
| 1675 | compatible = "qcom,msm-fastrpc-compute"; |
| 1676 | qcom,fastrpc-adsp-audio-pdr; |
| 1677 | qcom,rpc-latency-us = <235>; |
| 1678 | |
| 1679 | qcom,msm_fastrpc_compute_cb1 { |
| 1680 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1681 | label = "cdsprpc-smd"; |
| 1682 | iommus = <&apps_smmu 0x1001 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1683 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1684 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1685 | dma-coherent; |
| 1686 | }; |
| 1687 | |
| 1688 | qcom,msm_fastrpc_compute_cb2 { |
| 1689 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1690 | label = "cdsprpc-smd"; |
| 1691 | iommus = <&apps_smmu 0x1002 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1692 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1693 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1694 | dma-coherent; |
| 1695 | }; |
| 1696 | |
| 1697 | qcom,msm_fastrpc_compute_cb3 { |
| 1698 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1699 | label = "cdsprpc-smd"; |
| 1700 | iommus = <&apps_smmu 0x1003 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1701 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1702 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1703 | dma-coherent; |
| 1704 | }; |
| 1705 | |
| 1706 | qcom,msm_fastrpc_compute_cb4 { |
| 1707 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1708 | label = "cdsprpc-smd"; |
| 1709 | iommus = <&apps_smmu 0x1004 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1710 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1711 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1712 | dma-coherent; |
| 1713 | }; |
| 1714 | |
| 1715 | qcom,msm_fastrpc_compute_cb5 { |
| 1716 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1717 | label = "cdsprpc-smd"; |
| 1718 | iommus = <&apps_smmu 0x1005 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1719 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1720 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1721 | dma-coherent; |
| 1722 | }; |
| 1723 | |
| 1724 | qcom,msm_fastrpc_compute_cb6 { |
| 1725 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1726 | label = "cdsprpc-smd"; |
| 1727 | iommus = <&apps_smmu 0x1006 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1728 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1729 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1730 | dma-coherent; |
| 1731 | }; |
| 1732 | |
| 1733 | qcom,msm_fastrpc_compute_cb7 { |
| 1734 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1735 | label = "cdsprpc-smd"; |
| 1736 | iommus = <&apps_smmu 0x1007 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1737 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1738 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1739 | dma-coherent; |
| 1740 | }; |
| 1741 | |
| 1742 | qcom,msm_fastrpc_compute_cb8 { |
| 1743 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1744 | label = "cdsprpc-smd"; |
| 1745 | iommus = <&apps_smmu 0x1008 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1746 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1747 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1748 | dma-coherent; |
| 1749 | }; |
| 1750 | |
| 1751 | qcom,msm_fastrpc_compute_cb9 { |
| 1752 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1753 | label = "cdsprpc-smd"; |
| 1754 | qcom,secure-context-bank; |
| 1755 | iommus = <&apps_smmu 0x1009 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1756 | dma-ranges = <0x60000000 0x60000000 0x78000000>; |
| 1757 | qcom,iommu-faults = "stall-disable"; |
| 1758 | qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1759 | dma-coherent; |
| 1760 | }; |
| 1761 | |
| 1762 | qcom,msm_fastrpc_compute_cb10 { |
| 1763 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1764 | label = "adsprpc-smd"; |
| 1765 | iommus = <&apps_smmu 0x1803 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1766 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1767 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1768 | dma-coherent; |
| 1769 | }; |
| 1770 | |
| 1771 | qcom,msm_fastrpc_compute_cb11 { |
| 1772 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1773 | label = "adsprpc-smd"; |
| 1774 | iommus = <&apps_smmu 0x1804 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1775 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1776 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1777 | dma-coherent; |
| 1778 | }; |
| 1779 | |
| 1780 | qcom,msm_fastrpc_compute_cb12 { |
| 1781 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1782 | label = "adsprpc-smd"; |
| 1783 | iommus = <&apps_smmu 0x1805 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1784 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1785 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1786 | dma-coherent; |
| 1787 | }; |
| 1788 | |
| 1789 | qcom,msm_fastrpc_compute_cb13 { |
| 1790 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1791 | label = "sdsprpc-smd"; |
| 1792 | iommus = <&apps_smmu 0x0541 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1793 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1794 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1795 | dma-coherent; |
| 1796 | }; |
| 1797 | |
| 1798 | qcom,msm_fastrpc_compute_cb14 { |
| 1799 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1800 | label = "sdsprpc-smd"; |
| 1801 | iommus = <&apps_smmu 0x0542 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1802 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1803 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1804 | dma-coherent; |
| 1805 | }; |
| 1806 | |
| 1807 | qcom,msm_fastrpc_compute_cb15 { |
| 1808 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1809 | label = "sdsprpc-smd"; |
| 1810 | iommus = <&apps_smmu 0x0543 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1811 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1812 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1813 | shared-cb = <4>; |
| 1814 | dma-coherent; |
| 1815 | }; |
| 1816 | }; |
Shaikh Shadul | bfdfdda | 2018-11-14 15:36:21 +0530 | [diff] [blame] | 1817 | |
| 1818 | qcom,ssc@5c00000 { |
| 1819 | compatible = "qcom,pil-tz-generic"; |
| 1820 | reg = <0x5c00000 0x4000>; |
| 1821 | |
| 1822 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1823 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 1824 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 1825 | qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 1826 | |
| 1827 | qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; |
| 1828 | qcom,keep-proxy-regs-on; |
| 1829 | |
| 1830 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 1831 | clock-names = "xo"; |
| 1832 | qcom,proxy-clock-names = "xo"; |
| 1833 | |
| 1834 | qcom,pas-id = <12>; |
| 1835 | qcom,proxy-timeout-ms = <10000>; |
| 1836 | qcom,smem-id = <424>; |
| 1837 | qcom,sysmon-id = <3>; |
| 1838 | qcom,ssctl-instance-id = <0x16>; |
| 1839 | qcom,firmware-name = "slpi"; |
| 1840 | status = "ok"; |
| 1841 | memory-region = <&pil_slpi_mem>; |
| 1842 | qcom,complete-ramdump; |
| 1843 | |
| 1844 | /* Inputs from ssc */ |
| 1845 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, |
| 1846 | <&dsps_smp2p_in 0 0>, |
| 1847 | <&dsps_smp2p_in 2 0>, |
| 1848 | <&dsps_smp2p_in 1 0>, |
| 1849 | <&dsps_smp2p_in 3 0>; |
| 1850 | |
| 1851 | interrupt-names = "qcom,wdog", |
| 1852 | "qcom,err-fatal", |
| 1853 | "qcom,proxy-unvote", |
| 1854 | "qcom,err-ready", |
| 1855 | "qcom,stop-ack"; |
| 1856 | |
| 1857 | /* Outputs to ssc */ |
| 1858 | qcom,smem-states = <&dsps_smp2p_out 0>; |
| 1859 | qcom,smem-state-names = "qcom,force-stop"; |
| 1860 | |
| 1861 | mbox-names = "slpi-pil"; |
| 1862 | }; |
| 1863 | |
| 1864 | ssc_sensors: qcom,msm-ssc-sensors { |
| 1865 | compatible = "qcom,msm-ssc-sensors"; |
| 1866 | status = "ok"; |
| 1867 | qcom,firmware-name = "slpi"; |
| 1868 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 1869 | }; |
Swathi Sridhar | 4008eb4 | 2018-07-17 15:34:46 -0700 | [diff] [blame] | 1870 | |
David Dai | b1d6848 | 2018-10-01 19:40:35 -0700 | [diff] [blame] | 1871 | #include "kona-bus.dtsi" |
Swathi Sridhar | bbbc80b | 2018-07-13 10:02:08 -0700 | [diff] [blame] | 1872 | #include "kona-ion.dtsi" |
Tony Truong | c972c64 | 2018-09-12 10:03:51 -0700 | [diff] [blame] | 1873 | #include "kona-pcie.dtsi" |
Sujeev Dias | 5399e55 | 2018-09-18 17:57:54 -0700 | [diff] [blame] | 1874 | #include "kona-mhi.dtsi" |
Swathi Sridhar | 4008eb4 | 2018-07-17 15:34:46 -0700 | [diff] [blame] | 1875 | #include "msm-arm-smmu-kona.dtsi" |
Rishabh Bhatnagar | a740b0e | 2018-07-20 15:08:35 -0700 | [diff] [blame] | 1876 | #include "kona-pinctrl.dtsi" |
Chris Lew | 86f6bde | 2018-09-06 16:40:39 -0700 | [diff] [blame] | 1877 | #include "kona-smp2p.dtsi" |
Hemant Kumar | 5f58bad | 2018-08-31 14:25:23 -0700 | [diff] [blame] | 1878 | #include "kona-usb.dtsi" |
Tingwei Zhang | 564fa69 | 2018-11-28 00:31:17 -0800 | [diff] [blame] | 1879 | #include "kona-coresight.dtsi" |
Samantha Tran | 7e309f0 | 2018-08-31 17:23:00 -0700 | [diff] [blame] | 1880 | #include "kona-sde.dtsi" |
Satya Rama Aditya Pinapala | 09600b3 | 2018-10-29 10:52:37 -0700 | [diff] [blame] | 1881 | #include "kona-sde-pll.dtsi" |
Samantha Tran | 7e309f0 | 2018-08-31 17:23:00 -0700 | [diff] [blame] | 1882 | #include "kona-sde-display.dtsi" |
Vignesh Kulothungan | d728f71 | 2018-10-26 17:49:46 -0700 | [diff] [blame] | 1883 | #include "kona-audio.dtsi" |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 1884 | #include "kona-pm.dtsi" |