Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 1 | config IRQCHIP |
| 2 | def_bool y |
| 3 | depends on OF_IRQ |
| 4 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 5 | config ARM_GIC |
| 6 | bool |
| 7 | select IRQ_DOMAIN |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 8 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 9 | select MULTI_IRQ_HANDLER |
| 10 | |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 11 | config ARM_GIC_MAX_NR |
| 12 | int |
| 13 | default 2 if ARCH_REALVIEW |
| 14 | default 1 |
| 15 | |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 16 | config ARM_GIC_V2M |
| 17 | bool |
| 18 | depends on ARM_GIC |
| 19 | depends on PCI && PCI_MSI |
| 20 | select PCI_MSI_IRQ_DOMAIN |
| 21 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 22 | config GIC_NON_BANKED |
| 23 | bool |
| 24 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 25 | config ARM_GIC_V3 |
| 26 | bool |
| 27 | select IRQ_DOMAIN |
| 28 | select MULTI_IRQ_HANDLER |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 29 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 30 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 31 | config ARM_GIC_V3_ITS |
| 32 | bool |
| 33 | select PCI_MSI_IRQ_DOMAIN |
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 34 | |
Ma Jun | 717c3db | 2015-12-17 19:56:35 +0800 | [diff] [blame] | 35 | config HISILICON_IRQ_MBIGEN |
| 36 | bool "Support mbigen interrupt controller" |
| 37 | default n |
| 38 | depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN |
| 39 | help |
| 40 | Enable the mbigen interrupt controller used on |
| 41 | Hisilicon platform. |
| 42 | |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 43 | config ARM_NVIC |
| 44 | bool |
| 45 | select IRQ_DOMAIN |
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 46 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 47 | select GENERIC_IRQ_CHIP |
| 48 | |
| 49 | config ARM_VIC |
| 50 | bool |
| 51 | select IRQ_DOMAIN |
| 52 | select MULTI_IRQ_HANDLER |
| 53 | |
| 54 | config ARM_VIC_NR |
| 55 | int |
| 56 | default 4 if ARCH_S5PV210 |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 57 | default 2 |
| 58 | depends on ARM_VIC |
| 59 | help |
| 60 | The maximum number of VICs available in the system, for |
| 61 | power management. |
| 62 | |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 63 | config ARMADA_370_XP_IRQ |
| 64 | bool |
| 65 | default y if ARCH_MVEBU |
| 66 | select GENERIC_IRQ_CHIP |
Thomas Petazzoni | fcc392d | 2016-02-10 15:46:57 +0100 | [diff] [blame^] | 67 | select PCI_MSI_IRQ_DOMAIN if PCI_MSI |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 68 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 69 | config ATMEL_AIC_IRQ |
| 70 | bool |
| 71 | select GENERIC_IRQ_CHIP |
| 72 | select IRQ_DOMAIN |
| 73 | select MULTI_IRQ_HANDLER |
| 74 | select SPARSE_IRQ |
| 75 | |
| 76 | config ATMEL_AIC5_IRQ |
| 77 | bool |
| 78 | select GENERIC_IRQ_CHIP |
| 79 | select IRQ_DOMAIN |
| 80 | select MULTI_IRQ_HANDLER |
| 81 | select SPARSE_IRQ |
| 82 | |
Ralf Baechle | 0509cfd | 2015-07-08 14:46:08 +0200 | [diff] [blame] | 83 | config I8259 |
| 84 | bool |
| 85 | select IRQ_DOMAIN |
| 86 | |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 87 | config BCM7038_L1_IRQ |
| 88 | bool |
| 89 | select GENERIC_IRQ_CHIP |
| 90 | select IRQ_DOMAIN |
| 91 | |
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 92 | config BCM7120_L2_IRQ |
| 93 | bool |
| 94 | select GENERIC_IRQ_CHIP |
| 95 | select IRQ_DOMAIN |
| 96 | |
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 97 | config BRCMSTB_L2_IRQ |
| 98 | bool |
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 99 | select GENERIC_IRQ_CHIP |
| 100 | select IRQ_DOMAIN |
| 101 | |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 102 | config DW_APB_ICTL |
| 103 | bool |
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 104 | select GENERIC_IRQ_CHIP |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 105 | select IRQ_DOMAIN |
| 106 | |
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 107 | config IMGPDC_IRQ |
| 108 | bool |
| 109 | select GENERIC_IRQ_CHIP |
| 110 | select IRQ_DOMAIN |
| 111 | |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 112 | config IRQ_MIPS_CPU |
| 113 | bool |
| 114 | select GENERIC_IRQ_CHIP |
| 115 | select IRQ_DOMAIN |
| 116 | |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 117 | config CLPS711X_IRQCHIP |
| 118 | bool |
| 119 | depends on ARCH_CLPS711X |
| 120 | select IRQ_DOMAIN |
| 121 | select MULTI_IRQ_HANDLER |
| 122 | select SPARSE_IRQ |
| 123 | default y |
| 124 | |
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 125 | config OR1K_PIC |
| 126 | bool |
| 127 | select IRQ_DOMAIN |
| 128 | |
Felipe Balbi | 8598066 | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 129 | config OMAP_IRQCHIP |
| 130 | bool |
| 131 | select GENERIC_IRQ_CHIP |
| 132 | select IRQ_DOMAIN |
| 133 | |
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 134 | config ORION_IRQCHIP |
| 135 | bool |
| 136 | select IRQ_DOMAIN |
| 137 | select MULTI_IRQ_HANDLER |
| 138 | |
Cristian Birsan | aaa8666 | 2016-01-13 18:15:35 -0700 | [diff] [blame] | 139 | config PIC32_EVIC |
| 140 | bool |
| 141 | select GENERIC_IRQ_CHIP |
| 142 | select IRQ_DOMAIN |
| 143 | |
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 144 | config RENESAS_INTC_IRQPIN |
| 145 | bool |
| 146 | select IRQ_DOMAIN |
| 147 | |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 148 | config RENESAS_IRQC |
| 149 | bool |
Magnus Damm | 99c221d | 2015-09-28 18:42:37 +0900 | [diff] [blame] | 150 | select GENERIC_IRQ_CHIP |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 151 | select IRQ_DOMAIN |
| 152 | |
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 153 | config ST_IRQCHIP |
| 154 | bool |
| 155 | select REGMAP |
| 156 | select MFD_SYSCON |
| 157 | help |
| 158 | Enables SysCfg Controlled IRQs on STi based platforms. |
| 159 | |
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 160 | config TB10X_IRQC |
| 161 | bool |
| 162 | select IRQ_DOMAIN |
| 163 | select GENERIC_IRQ_CHIP |
| 164 | |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 165 | config TS4800_IRQ |
| 166 | tristate "TS-4800 IRQ controller" |
| 167 | select IRQ_DOMAIN |
Richard Weinberger | 0df337c | 2016-01-25 23:24:17 +0100 | [diff] [blame] | 168 | depends on HAS_IOMEM |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 169 | help |
| 170 | Support for the TS-4800 FPGA IRQ controller |
| 171 | |
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 172 | config VERSATILE_FPGA_IRQ |
| 173 | bool |
| 174 | select IRQ_DOMAIN |
| 175 | |
| 176 | config VERSATILE_FPGA_IRQ_NR |
| 177 | int |
| 178 | default 4 |
| 179 | depends on VERSATILE_FPGA_IRQ |
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 180 | |
| 181 | config XTENSA_MX |
| 182 | bool |
| 183 | select IRQ_DOMAIN |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 184 | |
| 185 | config IRQ_CROSSBAR |
| 186 | bool |
| 187 | help |
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 188 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 189 | The primary irqchip invokes the crossbar's callback which inturn allocates |
| 190 | a free irq and configures the IP. Thus the peripheral interrupts are |
| 191 | routed to one of the free irqchip interrupt lines. |
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 192 | |
| 193 | config KEYSTONE_IRQ |
| 194 | tristate "Keystone 2 IRQ controller IP" |
| 195 | depends on ARCH_KEYSTONE |
| 196 | help |
| 197 | Support for Texas Instruments Keystone 2 IRQ controller IP which |
| 198 | is part of the Keystone 2 IPC mechanism |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 199 | |
| 200 | config MIPS_GIC |
| 201 | bool |
| 202 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 203 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 204 | config INGENIC_IRQ |
| 205 | bool |
| 206 | depends on MACH_INGENIC |
| 207 | default y |
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 208 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 209 | config RENESAS_H8300H_INTC |
| 210 | bool |
| 211 | select IRQ_DOMAIN |
| 212 | |
| 213 | config RENESAS_H8S_INTC |
| 214 | bool |
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 215 | select IRQ_DOMAIN |
Shenwei Wang | e324c4d | 2015-08-24 14:04:15 -0500 | [diff] [blame] | 216 | |
| 217 | config IMX_GPCV2 |
| 218 | bool |
| 219 | select IRQ_DOMAIN |
| 220 | help |
| 221 | Enables the wakeup IRQs for IMX platforms with GPCv2 block |
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 222 | |
| 223 | config IRQ_MXS |
| 224 | def_bool y if MACH_ASM9260 || ARCH_MXS |
| 225 | select IRQ_DOMAIN |
| 226 | select STMP_DEVICE |