Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * arch/arm/mach-at91/at91sam9260.c |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 SAN People |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
Andrew Victor | 3ef2fb4 | 2008-04-02 21:36:06 +0100 | [diff] [blame] | 14 | #include <linux/pm.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 15 | |
Russell King | 80b02c1 | 2009-01-08 10:01:47 +0000 | [diff] [blame] | 16 | #include <asm/irq.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 17 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 19 | #include <mach/cpu.h> |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 20 | #include <mach/at91_dbgu.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 21 | #include <mach/at91sam9260.h> |
| 22 | #include <mach/at91_pmc.h> |
| 23 | #include <mach/at91_rstc.h> |
| 24 | #include <mach/at91_shdwc.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 25 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 26 | #include "soc.h" |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 27 | #include "generic.h" |
| 28 | #include "clock.h" |
| 29 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 30 | /* -------------------------------------------------------------------- |
| 31 | * Clocks |
| 32 | * -------------------------------------------------------------------- */ |
| 33 | |
| 34 | /* |
| 35 | * The peripheral clocks. |
| 36 | */ |
| 37 | static struct clk pioA_clk = { |
| 38 | .name = "pioA_clk", |
| 39 | .pmc_mask = 1 << AT91SAM9260_ID_PIOA, |
| 40 | .type = CLK_TYPE_PERIPHERAL, |
| 41 | }; |
| 42 | static struct clk pioB_clk = { |
| 43 | .name = "pioB_clk", |
| 44 | .pmc_mask = 1 << AT91SAM9260_ID_PIOB, |
| 45 | .type = CLK_TYPE_PERIPHERAL, |
| 46 | }; |
| 47 | static struct clk pioC_clk = { |
| 48 | .name = "pioC_clk", |
| 49 | .pmc_mask = 1 << AT91SAM9260_ID_PIOC, |
| 50 | .type = CLK_TYPE_PERIPHERAL, |
| 51 | }; |
| 52 | static struct clk adc_clk = { |
| 53 | .name = "adc_clk", |
| 54 | .pmc_mask = 1 << AT91SAM9260_ID_ADC, |
| 55 | .type = CLK_TYPE_PERIPHERAL, |
| 56 | }; |
| 57 | static struct clk usart0_clk = { |
| 58 | .name = "usart0_clk", |
| 59 | .pmc_mask = 1 << AT91SAM9260_ID_US0, |
| 60 | .type = CLK_TYPE_PERIPHERAL, |
| 61 | }; |
| 62 | static struct clk usart1_clk = { |
| 63 | .name = "usart1_clk", |
| 64 | .pmc_mask = 1 << AT91SAM9260_ID_US1, |
| 65 | .type = CLK_TYPE_PERIPHERAL, |
| 66 | }; |
| 67 | static struct clk usart2_clk = { |
| 68 | .name = "usart2_clk", |
| 69 | .pmc_mask = 1 << AT91SAM9260_ID_US2, |
| 70 | .type = CLK_TYPE_PERIPHERAL, |
| 71 | }; |
| 72 | static struct clk mmc_clk = { |
| 73 | .name = "mci_clk", |
| 74 | .pmc_mask = 1 << AT91SAM9260_ID_MCI, |
| 75 | .type = CLK_TYPE_PERIPHERAL, |
| 76 | }; |
| 77 | static struct clk udc_clk = { |
| 78 | .name = "udc_clk", |
| 79 | .pmc_mask = 1 << AT91SAM9260_ID_UDP, |
| 80 | .type = CLK_TYPE_PERIPHERAL, |
| 81 | }; |
| 82 | static struct clk twi_clk = { |
| 83 | .name = "twi_clk", |
| 84 | .pmc_mask = 1 << AT91SAM9260_ID_TWI, |
| 85 | .type = CLK_TYPE_PERIPHERAL, |
| 86 | }; |
| 87 | static struct clk spi0_clk = { |
| 88 | .name = "spi0_clk", |
| 89 | .pmc_mask = 1 << AT91SAM9260_ID_SPI0, |
| 90 | .type = CLK_TYPE_PERIPHERAL, |
| 91 | }; |
| 92 | static struct clk spi1_clk = { |
| 93 | .name = "spi1_clk", |
| 94 | .pmc_mask = 1 << AT91SAM9260_ID_SPI1, |
| 95 | .type = CLK_TYPE_PERIPHERAL, |
| 96 | }; |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 97 | static struct clk ssc_clk = { |
| 98 | .name = "ssc_clk", |
| 99 | .pmc_mask = 1 << AT91SAM9260_ID_SSC, |
| 100 | .type = CLK_TYPE_PERIPHERAL, |
| 101 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 102 | static struct clk tc0_clk = { |
| 103 | .name = "tc0_clk", |
| 104 | .pmc_mask = 1 << AT91SAM9260_ID_TC0, |
| 105 | .type = CLK_TYPE_PERIPHERAL, |
| 106 | }; |
| 107 | static struct clk tc1_clk = { |
| 108 | .name = "tc1_clk", |
| 109 | .pmc_mask = 1 << AT91SAM9260_ID_TC1, |
| 110 | .type = CLK_TYPE_PERIPHERAL, |
| 111 | }; |
| 112 | static struct clk tc2_clk = { |
| 113 | .name = "tc2_clk", |
| 114 | .pmc_mask = 1 << AT91SAM9260_ID_TC2, |
| 115 | .type = CLK_TYPE_PERIPHERAL, |
| 116 | }; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 117 | static struct clk ohci_clk = { |
| 118 | .name = "ohci_clk", |
| 119 | .pmc_mask = 1 << AT91SAM9260_ID_UHP, |
| 120 | .type = CLK_TYPE_PERIPHERAL, |
| 121 | }; |
Andrew Victor | 69b2e99 | 2007-02-14 08:44:43 +0100 | [diff] [blame] | 122 | static struct clk macb_clk = { |
| 123 | .name = "macb_clk", |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 124 | .pmc_mask = 1 << AT91SAM9260_ID_EMAC, |
| 125 | .type = CLK_TYPE_PERIPHERAL, |
| 126 | }; |
| 127 | static struct clk isi_clk = { |
| 128 | .name = "isi_clk", |
| 129 | .pmc_mask = 1 << AT91SAM9260_ID_ISI, |
| 130 | .type = CLK_TYPE_PERIPHERAL, |
| 131 | }; |
| 132 | static struct clk usart3_clk = { |
| 133 | .name = "usart3_clk", |
| 134 | .pmc_mask = 1 << AT91SAM9260_ID_US3, |
| 135 | .type = CLK_TYPE_PERIPHERAL, |
| 136 | }; |
| 137 | static struct clk usart4_clk = { |
| 138 | .name = "usart4_clk", |
| 139 | .pmc_mask = 1 << AT91SAM9260_ID_US4, |
| 140 | .type = CLK_TYPE_PERIPHERAL, |
| 141 | }; |
| 142 | static struct clk usart5_clk = { |
| 143 | .name = "usart5_clk", |
| 144 | .pmc_mask = 1 << AT91SAM9260_ID_US5, |
| 145 | .type = CLK_TYPE_PERIPHERAL, |
| 146 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 147 | static struct clk tc3_clk = { |
| 148 | .name = "tc3_clk", |
| 149 | .pmc_mask = 1 << AT91SAM9260_ID_TC3, |
| 150 | .type = CLK_TYPE_PERIPHERAL, |
| 151 | }; |
| 152 | static struct clk tc4_clk = { |
| 153 | .name = "tc4_clk", |
| 154 | .pmc_mask = 1 << AT91SAM9260_ID_TC4, |
| 155 | .type = CLK_TYPE_PERIPHERAL, |
| 156 | }; |
| 157 | static struct clk tc5_clk = { |
| 158 | .name = "tc5_clk", |
| 159 | .pmc_mask = 1 << AT91SAM9260_ID_TC5, |
| 160 | .type = CLK_TYPE_PERIPHERAL, |
| 161 | }; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 162 | |
| 163 | static struct clk *periph_clocks[] __initdata = { |
| 164 | &pioA_clk, |
| 165 | &pioB_clk, |
| 166 | &pioC_clk, |
| 167 | &adc_clk, |
| 168 | &usart0_clk, |
| 169 | &usart1_clk, |
| 170 | &usart2_clk, |
| 171 | &mmc_clk, |
| 172 | &udc_clk, |
| 173 | &twi_clk, |
| 174 | &spi0_clk, |
| 175 | &spi1_clk, |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 176 | &ssc_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 177 | &tc0_clk, |
| 178 | &tc1_clk, |
| 179 | &tc2_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 180 | &ohci_clk, |
Andrew Victor | 69b2e99 | 2007-02-14 08:44:43 +0100 | [diff] [blame] | 181 | &macb_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 182 | &isi_clk, |
| 183 | &usart3_clk, |
| 184 | &usart4_clk, |
| 185 | &usart5_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 186 | &tc3_clk, |
| 187 | &tc4_clk, |
| 188 | &tc5_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 189 | // irq0 .. irq2 |
| 190 | }; |
| 191 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 192 | static struct clk_lookup periph_clocks_lookups[] = { |
| 193 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
| 194 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), |
| 195 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), |
| 196 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), |
| 197 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), |
| 198 | CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk), |
| 199 | CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), |
| 200 | CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), |
| 201 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), |
Jean-Christophe PLAGNIOL-VILLARD | fea3158 | 2011-10-14 09:40:52 +0800 | [diff] [blame^] | 202 | /* more usart lookup table for DT entries */ |
| 203 | CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), |
| 204 | CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), |
| 205 | CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk), |
| 206 | CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk), |
| 207 | CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk), |
| 208 | CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk), |
| 209 | CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 210 | }; |
| 211 | |
| 212 | static struct clk_lookup usart_clocks_lookups[] = { |
| 213 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 214 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 215 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 216 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 217 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), |
| 218 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk), |
| 219 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk), |
| 220 | }; |
| 221 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 222 | /* |
| 223 | * The two programmable clocks. |
| 224 | * You must configure pin multiplexing to bring these signals out. |
| 225 | */ |
| 226 | static struct clk pck0 = { |
| 227 | .name = "pck0", |
| 228 | .pmc_mask = AT91_PMC_PCK0, |
| 229 | .type = CLK_TYPE_PROGRAMMABLE, |
| 230 | .id = 0, |
| 231 | }; |
| 232 | static struct clk pck1 = { |
| 233 | .name = "pck1", |
| 234 | .pmc_mask = AT91_PMC_PCK1, |
| 235 | .type = CLK_TYPE_PROGRAMMABLE, |
| 236 | .id = 1, |
| 237 | }; |
| 238 | |
| 239 | static void __init at91sam9260_register_clocks(void) |
| 240 | { |
| 241 | int i; |
| 242 | |
| 243 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 244 | clk_register(periph_clocks[i]); |
| 245 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 246 | clkdev_add_table(periph_clocks_lookups, |
| 247 | ARRAY_SIZE(periph_clocks_lookups)); |
| 248 | clkdev_add_table(usart_clocks_lookups, |
| 249 | ARRAY_SIZE(usart_clocks_lookups)); |
| 250 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 251 | clk_register(&pck0); |
| 252 | clk_register(&pck1); |
| 253 | } |
| 254 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 255 | static struct clk_lookup console_clock_lookup; |
| 256 | |
| 257 | void __init at91sam9260_set_console_clock(int id) |
| 258 | { |
| 259 | if (id >= ARRAY_SIZE(usart_clocks_lookups)) |
| 260 | return; |
| 261 | |
| 262 | console_clock_lookup.con_id = "usart"; |
| 263 | console_clock_lookup.clk = usart_clocks_lookups[id].clk; |
| 264 | clkdev_add(&console_clock_lookup); |
| 265 | } |
| 266 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 267 | /* -------------------------------------------------------------------- |
| 268 | * GPIO |
| 269 | * -------------------------------------------------------------------- */ |
| 270 | |
| 271 | static struct at91_gpio_bank at91sam9260_gpio[] = { |
| 272 | { |
| 273 | .id = AT91SAM9260_ID_PIOA, |
| 274 | .offset = AT91_PIOA, |
| 275 | .clock = &pioA_clk, |
| 276 | }, { |
| 277 | .id = AT91SAM9260_ID_PIOB, |
| 278 | .offset = AT91_PIOB, |
| 279 | .clock = &pioB_clk, |
| 280 | }, { |
| 281 | .id = AT91SAM9260_ID_PIOC, |
| 282 | .offset = AT91_PIOC, |
| 283 | .clock = &pioC_clk, |
| 284 | } |
| 285 | }; |
| 286 | |
Andrew Victor | 3ef2fb4 | 2008-04-02 21:36:06 +0100 | [diff] [blame] | 287 | static void at91sam9260_poweroff(void) |
| 288 | { |
| 289 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); |
| 290 | } |
| 291 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 292 | |
| 293 | /* -------------------------------------------------------------------- |
| 294 | * AT91SAM9260 processor initialization |
| 295 | * -------------------------------------------------------------------- */ |
| 296 | |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 297 | static void __init at91sam9xe_map_io(void) |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 298 | { |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 299 | unsigned long sram_size; |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 300 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 301 | switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) { |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 302 | case AT91_CIDR_SRAMSIZ_32K: |
| 303 | sram_size = 2 * SZ_16K; |
| 304 | break; |
| 305 | case AT91_CIDR_SRAMSIZ_16K: |
| 306 | default: |
| 307 | sram_size = SZ_16K; |
| 308 | } |
| 309 | |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 310 | at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size); |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 311 | } |
| 312 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 313 | static void __init at91sam9260_map_io(void) |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 314 | { |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 315 | if (cpu_is_at91sam9xe()) { |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 316 | at91sam9xe_map_io(); |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 317 | } else if (cpu_is_at91sam9g20()) { |
| 318 | at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); |
| 319 | at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); |
| 320 | } else { |
| 321 | at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE); |
| 322 | at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE); |
| 323 | } |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 324 | } |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 325 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 326 | static void __init at91sam9260_initialize(void) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 327 | { |
Nicolas Ferre | bb413db | 2010-10-14 19:14:00 +0200 | [diff] [blame] | 328 | at91_arch_reset = at91sam9_alt_reset; |
Andrew Victor | 3ef2fb4 | 2008-04-02 21:36:06 +0100 | [diff] [blame] | 329 | pm_power_off = at91sam9260_poweroff; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 330 | at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) |
| 331 | | (1 << AT91SAM9260_ID_IRQ2); |
| 332 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 333 | /* Register GPIO subsystem */ |
| 334 | at91_gpio_init(at91sam9260_gpio, 3); |
| 335 | } |
| 336 | |
| 337 | /* -------------------------------------------------------------------- |
| 338 | * Interrupt initialization |
| 339 | * -------------------------------------------------------------------- */ |
| 340 | |
| 341 | /* |
| 342 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 343 | */ |
| 344 | static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 345 | 7, /* Advanced Interrupt Controller */ |
| 346 | 7, /* System Peripherals */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 347 | 1, /* Parallel IO Controller A */ |
| 348 | 1, /* Parallel IO Controller B */ |
| 349 | 1, /* Parallel IO Controller C */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 350 | 0, /* Analog-to-Digital Converter */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 351 | 5, /* USART 0 */ |
| 352 | 5, /* USART 1 */ |
| 353 | 5, /* USART 2 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 354 | 0, /* Multimedia Card Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 355 | 2, /* USB Device Port */ |
| 356 | 6, /* Two-Wire Interface */ |
| 357 | 5, /* Serial Peripheral Interface 0 */ |
| 358 | 5, /* Serial Peripheral Interface 1 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 359 | 5, /* Serial Synchronous Controller */ |
| 360 | 0, |
| 361 | 0, |
| 362 | 0, /* Timer Counter 0 */ |
| 363 | 0, /* Timer Counter 1 */ |
| 364 | 0, /* Timer Counter 2 */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 365 | 2, /* USB Host port */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 366 | 3, /* Ethernet */ |
| 367 | 0, /* Image Sensor Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 368 | 5, /* USART 3 */ |
| 369 | 5, /* USART 4 */ |
| 370 | 5, /* USART 5 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 371 | 0, /* Timer Counter 3 */ |
| 372 | 0, /* Timer Counter 4 */ |
| 373 | 0, /* Timer Counter 5 */ |
| 374 | 0, /* Advanced Interrupt Controller */ |
| 375 | 0, /* Advanced Interrupt Controller */ |
| 376 | 0, /* Advanced Interrupt Controller */ |
| 377 | }; |
| 378 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 379 | struct at91_init_soc __initdata at91sam9260_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 380 | .map_io = at91sam9260_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 381 | .default_irq_priority = at91sam9260_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 382 | .register_clocks = at91sam9260_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 383 | .init = at91sam9260_initialize, |
| 384 | }; |