Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2014-2017 The Linux Foundation. All rights reserved. |
| 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 5 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame^] | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 9 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame^] | 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 17 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 18 | |
| 19 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
| 20 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 21 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 22 | #include <uapi/drm/sde_drm.h> |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 23 | #include <uapi/drm/msm_drm_pp.h> |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 24 | |
| 25 | #include "msm_prop.h" |
| 26 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 27 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 28 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 29 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 30 | #include "sde_hw_sspp.h" |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 31 | #include "sde_trace.h" |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 32 | #include "sde_crtc.h" |
Lloyd Atkinson | 8772e20 | 2016-09-26 17:52:16 -0400 | [diff] [blame] | 33 | #include "sde_vbif.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 34 | #include "sde_plane.h" |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 35 | #include "sde_color_processing.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 36 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 37 | #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\ |
| 38 | (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) |
| 39 | |
| 40 | #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\ |
| 41 | (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) |
| 42 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 43 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 44 | #define PHASE_STEP_SHIFT 21 |
| 45 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 46 | #define PHASE_RESIDUAL 15 |
| 47 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 48 | #define SHARP_STRENGTH_DEFAULT 32 |
| 49 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 50 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 51 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 52 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 53 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 54 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 55 | #define SDE_PLANE_COLOR_FILL_FLAG BIT(31) |
| 56 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 57 | /* dirty bits for update function */ |
| 58 | #define SDE_PLANE_DIRTY_RECTS 0x1 |
| 59 | #define SDE_PLANE_DIRTY_FORMAT 0x2 |
| 60 | #define SDE_PLANE_DIRTY_SHARPEN 0x4 |
| 61 | #define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF |
| 62 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 63 | /** |
| 64 | * enum sde_plane_qos - Different qos configurations for each pipe |
| 65 | * |
| 66 | * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. |
| 67 | * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. |
| 68 | * this configuration is mutually exclusive from VBLANK_CTRL. |
| 69 | * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. |
| 70 | */ |
| 71 | enum sde_plane_qos { |
| 72 | SDE_PLANE_QOS_VBLANK_CTRL = BIT(0), |
| 73 | SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), |
| 74 | SDE_PLANE_QOS_PANIC_CTRL = BIT(2), |
| 75 | }; |
| 76 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 77 | /* |
| 78 | * struct sde_plane - local sde plane structure |
| 79 | * @csc_cfg: Decoded user configuration for csc |
| 80 | * @csc_usr_ptr: Points to csc_cfg if valid user config available |
| 81 | * @csc_ptr: Points to sde_csc_cfg structure to use for current |
| 82 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 83 | struct sde_plane { |
| 84 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 85 | |
| 86 | int mmu_id; |
| 87 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 88 | struct mutex lock; |
| 89 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 90 | enum sde_sspp pipe; |
| 91 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 92 | uint32_t nformats; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 93 | uint32_t formats[64]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 94 | |
| 95 | struct sde_hw_pipe *pipe_hw; |
| 96 | struct sde_hw_pipe_cfg pipe_cfg; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 97 | struct sde_hw_sharp_cfg sharp_cfg; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 98 | struct sde_hw_scaler3_cfg *scaler3_cfg; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 99 | struct sde_hw_pipe_qos_cfg pipe_qos_cfg; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 100 | uint32_t color_fill; |
| 101 | bool is_error; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 102 | bool is_rt_pipe; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 103 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 104 | struct sde_hw_pixel_ext pixel_ext; |
| 105 | bool pixel_ext_usr; |
| 106 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 107 | struct sde_csc_cfg csc_cfg; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 108 | struct sde_csc_cfg *csc_usr_ptr; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 109 | struct sde_csc_cfg *csc_ptr; |
| 110 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 111 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 112 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 113 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 114 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 115 | struct msm_property_info property_info; |
| 116 | struct msm_property_data property_data[PLANE_PROP_COUNT]; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 117 | struct drm_property_blob *blob_info; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 118 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 119 | /* debugfs related stuff */ |
| 120 | struct dentry *debugfs_root; |
| 121 | struct sde_debugfs_regset32 debugfs_src; |
| 122 | struct sde_debugfs_regset32 debugfs_scaler; |
| 123 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 124 | }; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 125 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 126 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 127 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 128 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 129 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 130 | return state && state->fb && state->crtc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 131 | } |
| 132 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 133 | /** |
| 134 | * _sde_plane_calc_fill_level - calculate fill level of the given source format |
| 135 | * @plane: Pointer to drm plane |
| 136 | * @fmt: Pointer to source buffer format |
| 137 | * @src_wdith: width of source buffer |
| 138 | * Return: fill level corresponding to the source buffer/format or 0 if error |
| 139 | */ |
| 140 | static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, |
| 141 | const struct sde_format *fmt, u32 src_width) |
| 142 | { |
| 143 | struct sde_plane *psde; |
| 144 | u32 fixed_buff_size; |
| 145 | u32 total_fl; |
| 146 | |
| 147 | if (!plane || !fmt) { |
| 148 | SDE_ERROR("invalid arguments\n"); |
| 149 | return 0; |
| 150 | } |
| 151 | |
| 152 | psde = to_sde_plane(plane); |
| 153 | fixed_buff_size = psde->pipe_sblk->pixel_ram_size; |
| 154 | |
| 155 | if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) { |
| 156 | if (fmt->chroma_sample == SDE_CHROMA_420) { |
| 157 | /* NV12 */ |
| 158 | total_fl = (fixed_buff_size / 2) / |
| 159 | ((src_width + 32) * fmt->bpp); |
| 160 | } else { |
| 161 | /* non NV12 */ |
| 162 | total_fl = (fixed_buff_size) / |
| 163 | ((src_width + 32) * fmt->bpp); |
| 164 | } |
| 165 | } else { |
| 166 | total_fl = (fixed_buff_size * 2) / |
| 167 | ((src_width + 32) * fmt->bpp); |
| 168 | } |
| 169 | |
| 170 | SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n", |
| 171 | plane->base.id, psde->pipe - SSPP_VIG0, |
| 172 | fmt->base.pixel_format, src_width, total_fl); |
| 173 | |
| 174 | return total_fl; |
| 175 | } |
| 176 | |
| 177 | /** |
| 178 | * _sde_plane_get_qos_lut_linear - get linear LUT mapping |
| 179 | * @total_fl: fill level |
| 180 | * Return: LUT setting corresponding to the fill level |
| 181 | */ |
| 182 | static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl) |
| 183 | { |
| 184 | u32 qos_lut; |
| 185 | |
| 186 | if (total_fl <= 4) |
| 187 | qos_lut = 0x1B; |
| 188 | else if (total_fl <= 5) |
| 189 | qos_lut = 0x5B; |
| 190 | else if (total_fl <= 6) |
| 191 | qos_lut = 0x15B; |
| 192 | else if (total_fl <= 7) |
| 193 | qos_lut = 0x55B; |
| 194 | else if (total_fl <= 8) |
| 195 | qos_lut = 0x155B; |
| 196 | else if (total_fl <= 9) |
| 197 | qos_lut = 0x555B; |
| 198 | else if (total_fl <= 10) |
| 199 | qos_lut = 0x1555B; |
| 200 | else if (total_fl <= 11) |
| 201 | qos_lut = 0x5555B; |
| 202 | else if (total_fl <= 12) |
| 203 | qos_lut = 0x15555B; |
| 204 | else |
| 205 | qos_lut = 0x55555B; |
| 206 | |
| 207 | return qos_lut; |
| 208 | } |
| 209 | |
| 210 | /** |
| 211 | * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping |
| 212 | * @total_fl: fill level |
| 213 | * Return: LUT setting corresponding to the fill level |
| 214 | */ |
| 215 | static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl) |
| 216 | { |
| 217 | u32 qos_lut; |
| 218 | |
| 219 | if (total_fl <= 10) |
| 220 | qos_lut = 0x1AAff; |
| 221 | else if (total_fl <= 11) |
| 222 | qos_lut = 0x5AAFF; |
| 223 | else if (total_fl <= 12) |
| 224 | qos_lut = 0x15AAFF; |
| 225 | else |
| 226 | qos_lut = 0x55AAFF; |
| 227 | |
| 228 | return qos_lut; |
| 229 | } |
| 230 | |
| 231 | /** |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 232 | * _sde_plane_set_qos_lut - set QoS LUT of the given plane |
| 233 | * @plane: Pointer to drm plane |
| 234 | * @fb: Pointer to framebuffer associated with the given plane |
| 235 | */ |
| 236 | static void _sde_plane_set_qos_lut(struct drm_plane *plane, |
| 237 | struct drm_framebuffer *fb) |
| 238 | { |
| 239 | struct sde_plane *psde; |
| 240 | const struct sde_format *fmt = NULL; |
| 241 | u32 qos_lut; |
| 242 | u32 total_fl = 0; |
| 243 | |
| 244 | if (!plane || !fb) { |
| 245 | SDE_ERROR("invalid arguments plane %d fb %d\n", |
| 246 | plane != 0, fb != 0); |
| 247 | return; |
| 248 | } |
| 249 | |
| 250 | psde = to_sde_plane(plane); |
| 251 | |
| 252 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 253 | SDE_ERROR("invalid arguments\n"); |
| 254 | return; |
| 255 | } else if (!psde->pipe_hw->ops.setup_creq_lut) { |
| 256 | return; |
| 257 | } |
| 258 | |
| 259 | if (!psde->is_rt_pipe) { |
| 260 | qos_lut = psde->pipe_sblk->creq_lut_nrt; |
| 261 | } else { |
| 262 | fmt = sde_get_sde_format_ext( |
| 263 | fb->pixel_format, |
| 264 | fb->modifier, |
| 265 | drm_format_num_planes(fb->pixel_format)); |
| 266 | total_fl = _sde_plane_calc_fill_level(plane, fmt, |
| 267 | psde->pipe_cfg.src_rect.w); |
| 268 | |
| 269 | if (SDE_FORMAT_IS_LINEAR(fmt)) |
| 270 | qos_lut = _sde_plane_get_qos_lut_linear(total_fl); |
| 271 | else |
| 272 | qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl); |
| 273 | } |
| 274 | |
| 275 | psde->pipe_qos_cfg.creq_lut = qos_lut; |
| 276 | |
| 277 | trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, |
| 278 | (fmt) ? fmt->base.pixel_format : 0, |
| 279 | psde->is_rt_pipe, total_fl, qos_lut, |
| 280 | (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0); |
| 281 | |
| 282 | SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n", |
| 283 | plane->base.id, |
| 284 | psde->pipe - SSPP_VIG0, |
| 285 | (fmt) ? fmt->base.pixel_format : 0, |
| 286 | psde->is_rt_pipe, total_fl, qos_lut); |
| 287 | |
| 288 | psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg); |
| 289 | } |
| 290 | |
| 291 | /** |
| 292 | * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane |
| 293 | * @plane: Pointer to drm plane |
| 294 | * @fb: Pointer to framebuffer associated with the given plane |
| 295 | */ |
| 296 | static void _sde_plane_set_danger_lut(struct drm_plane *plane, |
| 297 | struct drm_framebuffer *fb) |
| 298 | { |
| 299 | struct sde_plane *psde; |
| 300 | const struct sde_format *fmt = NULL; |
| 301 | u32 danger_lut, safe_lut; |
| 302 | |
| 303 | if (!plane || !fb) { |
| 304 | SDE_ERROR("invalid arguments\n"); |
| 305 | return; |
| 306 | } |
| 307 | |
| 308 | psde = to_sde_plane(plane); |
| 309 | |
| 310 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 311 | SDE_ERROR("invalid arguments\n"); |
| 312 | return; |
| 313 | } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) { |
| 314 | return; |
| 315 | } |
| 316 | |
| 317 | if (!psde->is_rt_pipe) { |
| 318 | danger_lut = psde->pipe_sblk->danger_lut_nrt; |
| 319 | safe_lut = psde->pipe_sblk->safe_lut_nrt; |
| 320 | } else { |
| 321 | fmt = sde_get_sde_format_ext( |
| 322 | fb->pixel_format, |
| 323 | fb->modifier, |
| 324 | drm_format_num_planes(fb->pixel_format)); |
| 325 | |
| 326 | if (SDE_FORMAT_IS_LINEAR(fmt)) { |
| 327 | danger_lut = psde->pipe_sblk->danger_lut_linear; |
| 328 | safe_lut = psde->pipe_sblk->safe_lut_linear; |
| 329 | } else { |
| 330 | danger_lut = psde->pipe_sblk->danger_lut_tile; |
| 331 | safe_lut = psde->pipe_sblk->safe_lut_tile; |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | psde->pipe_qos_cfg.danger_lut = danger_lut; |
| 336 | psde->pipe_qos_cfg.safe_lut = safe_lut; |
| 337 | |
| 338 | trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0, |
| 339 | (fmt) ? fmt->base.pixel_format : 0, |
| 340 | (fmt) ? fmt->fetch_mode : 0, |
| 341 | psde->pipe_qos_cfg.danger_lut, |
| 342 | psde->pipe_qos_cfg.safe_lut); |
| 343 | |
| 344 | SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n", |
| 345 | plane->base.id, |
| 346 | psde->pipe - SSPP_VIG0, |
| 347 | fmt ? fmt->base.pixel_format : 0, |
| 348 | fmt ? fmt->fetch_mode : -1, |
| 349 | psde->pipe_qos_cfg.danger_lut, |
| 350 | psde->pipe_qos_cfg.safe_lut); |
| 351 | |
| 352 | psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw, |
| 353 | &psde->pipe_qos_cfg); |
| 354 | } |
| 355 | |
| 356 | /** |
| 357 | * _sde_plane_set_qos_ctrl - set QoS control of the given plane |
| 358 | * @plane: Pointer to drm plane |
| 359 | * @enable: true to enable QoS control |
| 360 | * @flags: QoS control mode (enum sde_plane_qos) |
| 361 | */ |
| 362 | static void _sde_plane_set_qos_ctrl(struct drm_plane *plane, |
| 363 | bool enable, u32 flags) |
| 364 | { |
| 365 | struct sde_plane *psde; |
| 366 | |
| 367 | if (!plane) { |
| 368 | SDE_ERROR("invalid arguments\n"); |
| 369 | return; |
| 370 | } |
| 371 | |
| 372 | psde = to_sde_plane(plane); |
| 373 | |
| 374 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 375 | SDE_ERROR("invalid arguments\n"); |
| 376 | return; |
| 377 | } else if (!psde->pipe_hw->ops.setup_qos_ctrl) { |
| 378 | return; |
| 379 | } |
| 380 | |
| 381 | if (flags & SDE_PLANE_QOS_VBLANK_CTRL) { |
| 382 | psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank; |
| 383 | psde->pipe_qos_cfg.danger_vblank = |
| 384 | psde->pipe_sblk->danger_vblank; |
| 385 | psde->pipe_qos_cfg.vblank_en = enable; |
| 386 | } |
| 387 | |
| 388 | if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) { |
| 389 | /* this feature overrules previous VBLANK_CTRL */ |
| 390 | psde->pipe_qos_cfg.vblank_en = false; |
| 391 | psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ |
| 392 | } |
| 393 | |
| 394 | if (flags & SDE_PLANE_QOS_PANIC_CTRL) |
| 395 | psde->pipe_qos_cfg.danger_safe_en = enable; |
| 396 | |
| 397 | if (!psde->is_rt_pipe) { |
| 398 | psde->pipe_qos_cfg.vblank_en = false; |
| 399 | psde->pipe_qos_cfg.danger_safe_en = false; |
| 400 | } |
| 401 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 402 | SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 403 | plane->base.id, |
| 404 | psde->pipe - SSPP_VIG0, |
| 405 | psde->pipe_qos_cfg.danger_safe_en, |
| 406 | psde->pipe_qos_cfg.vblank_en, |
| 407 | psde->pipe_qos_cfg.creq_vblank, |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 408 | psde->pipe_qos_cfg.danger_vblank, |
| 409 | psde->is_rt_pipe); |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 410 | |
| 411 | psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw, |
| 412 | &psde->pipe_qos_cfg); |
| 413 | } |
| 414 | |
Alan Kwong | f0fd851 | 2016-10-24 21:39:26 -0400 | [diff] [blame] | 415 | int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) |
| 416 | { |
| 417 | struct sde_plane *psde; |
| 418 | struct msm_drm_private *priv; |
| 419 | struct sde_kms *sde_kms; |
| 420 | |
| 421 | if (!plane || !plane->dev) { |
| 422 | SDE_ERROR("invalid arguments\n"); |
| 423 | return -EINVAL; |
| 424 | } |
| 425 | |
| 426 | priv = plane->dev->dev_private; |
| 427 | if (!priv || !priv->kms) { |
| 428 | SDE_ERROR("invalid KMS reference\n"); |
| 429 | return -EINVAL; |
| 430 | } |
| 431 | |
| 432 | sde_kms = to_sde_kms(priv->kms); |
| 433 | psde = to_sde_plane(plane); |
| 434 | |
| 435 | if (!psde->is_rt_pipe) |
| 436 | goto end; |
| 437 | |
| 438 | sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true); |
| 439 | |
| 440 | _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL); |
| 441 | |
| 442 | sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false); |
| 443 | |
| 444 | end: |
| 445 | return 0; |
| 446 | } |
| 447 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 448 | /** |
| 449 | * _sde_plane_set_ot_limit - set OT limit for the given plane |
| 450 | * @plane: Pointer to drm plane |
| 451 | * @crtc: Pointer to drm crtc |
| 452 | */ |
| 453 | static void _sde_plane_set_ot_limit(struct drm_plane *plane, |
| 454 | struct drm_crtc *crtc) |
| 455 | { |
| 456 | struct sde_plane *psde; |
| 457 | struct sde_vbif_set_ot_params ot_params; |
| 458 | struct msm_drm_private *priv; |
| 459 | struct sde_kms *sde_kms; |
| 460 | |
| 461 | if (!plane || !plane->dev || !crtc) { |
| 462 | SDE_ERROR("invalid arguments plane %d crtc %d\n", |
| 463 | plane != 0, crtc != 0); |
| 464 | return; |
| 465 | } |
| 466 | |
| 467 | priv = plane->dev->dev_private; |
| 468 | if (!priv || !priv->kms) { |
| 469 | SDE_ERROR("invalid KMS reference\n"); |
| 470 | return; |
| 471 | } |
| 472 | |
| 473 | sde_kms = to_sde_kms(priv->kms); |
| 474 | psde = to_sde_plane(plane); |
| 475 | if (!psde->pipe_hw) { |
| 476 | SDE_ERROR("invalid pipe reference\n"); |
| 477 | return; |
| 478 | } |
| 479 | |
| 480 | memset(&ot_params, 0, sizeof(ot_params)); |
| 481 | ot_params.xin_id = psde->pipe_hw->cap->xin_id; |
| 482 | ot_params.num = psde->pipe_hw->idx - SSPP_NONE; |
| 483 | ot_params.width = psde->pipe_cfg.src_rect.w; |
| 484 | ot_params.height = psde->pipe_cfg.src_rect.h; |
| 485 | ot_params.is_wfd = !psde->is_rt_pipe; |
| 486 | ot_params.frame_rate = crtc->mode.vrefresh; |
| 487 | ot_params.vbif_idx = VBIF_RT; |
| 488 | ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl; |
| 489 | ot_params.rd = true; |
| 490 | |
| 491 | sde_vbif_set_ot_limit(sde_kms, &ot_params); |
| 492 | } |
| 493 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 494 | /* helper to update a state's input fence pointer from the property */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 495 | static void _sde_plane_set_input_fence(struct sde_plane *psde, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 496 | struct sde_plane_state *pstate, uint64_t fd) |
| 497 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 498 | if (!psde || !pstate) { |
| 499 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 500 | psde != 0, pstate != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 501 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 502 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 503 | |
| 504 | /* clear previous reference */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 505 | if (pstate->input_fence) |
| 506 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 507 | |
| 508 | /* get fence pointer for later */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 509 | pstate->input_fence = sde_sync_get(fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 510 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 511 | SDE_DEBUG_PLANE(psde, "0x%llX\n", fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 512 | } |
| 513 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 514 | int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 515 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 516 | struct sde_plane *psde; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 517 | struct sde_plane_state *pstate; |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 518 | uint32_t prefix; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 519 | void *input_fence; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 520 | int ret = -EINVAL; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 521 | |
| 522 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 523 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 524 | } else if (!plane->state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 525 | SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 526 | } else { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 527 | psde = to_sde_plane(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 528 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 529 | input_fence = pstate->input_fence; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 530 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 531 | if (input_fence) { |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 532 | prefix = sde_sync_get_name_prefix(input_fence); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 533 | ret = sde_sync_wait(input_fence, wait_ms); |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 534 | |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 535 | SDE_EVT32(DRMID(plane), -ret, prefix); |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 536 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 537 | switch (ret) { |
| 538 | case 0: |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 539 | SDE_DEBUG_PLANE(psde, "signaled\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 540 | break; |
| 541 | case -ETIME: |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 542 | SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n", |
| 543 | wait_ms, prefix); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 544 | psde->is_error = true; |
| 545 | break; |
| 546 | default: |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 547 | SDE_ERROR_PLANE(psde, "error %d on %08X\n", |
| 548 | ret, prefix); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 549 | psde->is_error = true; |
| 550 | break; |
| 551 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 552 | } else { |
| 553 | ret = 0; |
| 554 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 555 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 556 | return ret; |
| 557 | } |
| 558 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 559 | static inline void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 560 | struct sde_plane_state *pstate, |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 561 | struct sde_hw_pipe_cfg *pipe_cfg, |
| 562 | struct drm_framebuffer *fb) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 563 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 564 | struct sde_plane *psde; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 565 | int ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 566 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 567 | if (!plane || !pstate || !pipe_cfg || !fb) { |
| 568 | SDE_ERROR( |
| 569 | "invalid arg(s), plane %d state %d cfg %d fb %d\n", |
| 570 | plane != 0, pstate != 0, pipe_cfg != 0, fb != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 571 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 572 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 573 | |
| 574 | psde = to_sde_plane(plane); |
Clarence Ip | b6eb236 | 2016-09-08 16:18:13 -0400 | [diff] [blame] | 575 | if (!psde->pipe_hw) { |
| 576 | SDE_ERROR_PLANE(psde, "invalid pipe_hw\n"); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 577 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 578 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 579 | |
Clarence Ip | b6eb236 | 2016-09-08 16:18:13 -0400 | [diff] [blame] | 580 | ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout); |
| 581 | if (ret == -EAGAIN) |
| 582 | SDE_DEBUG_PLANE(psde, "not updating same src addrs\n"); |
| 583 | else if (ret) |
| 584 | SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret); |
| 585 | else if (psde->pipe_hw->ops.setup_sourceaddress) |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 586 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 587 | } |
| 588 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 589 | static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde, |
| 590 | struct sde_plane_state *pstate) |
| 591 | { |
| 592 | struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg; |
| 593 | int ret = 0; |
| 594 | |
| 595 | cfg->dir_lut = msm_property_get_blob( |
| 596 | &psde->property_info, |
| 597 | pstate->property_blobs, &cfg->dir_len, |
| 598 | PLANE_PROP_SCALER_LUT_ED); |
| 599 | cfg->cir_lut = msm_property_get_blob( |
| 600 | &psde->property_info, |
| 601 | pstate->property_blobs, &cfg->cir_len, |
| 602 | PLANE_PROP_SCALER_LUT_CIR); |
| 603 | cfg->sep_lut = msm_property_get_blob( |
| 604 | &psde->property_info, |
| 605 | pstate->property_blobs, &cfg->sep_len, |
| 606 | PLANE_PROP_SCALER_LUT_SEP); |
| 607 | if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut) |
| 608 | ret = -ENODATA; |
| 609 | return ret; |
| 610 | } |
| 611 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 612 | static void _sde_plane_setup_scaler3(struct sde_plane *psde, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 613 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 614 | struct sde_hw_scaler3_cfg *scale_cfg, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 615 | const struct sde_format *fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 616 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 617 | { |
| 618 | } |
| 619 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 620 | /** |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 621 | * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 622 | * @psde: Pointer to SDE plane object |
| 623 | * @src: Source size |
| 624 | * @dst: Destination size |
| 625 | * @phase_steps: Pointer to output array for phase steps |
| 626 | * @filter: Pointer to output array for filter type |
| 627 | * @fmt: Pointer to format definition |
| 628 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 629 | * |
| 630 | * Returns: 0 on success |
| 631 | */ |
| 632 | static int _sde_plane_setup_scaler2(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 633 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 634 | enum sde_hw_filter *filter, const struct sde_format *fmt, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 635 | uint32_t chroma_subsampling) |
| 636 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 637 | if (!psde || !phase_steps || !filter || !fmt) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 638 | SDE_ERROR( |
| 639 | "invalid arg(s), plane %d phase %d filter %d fmt %d\n", |
| 640 | psde != 0, phase_steps != 0, filter != 0, fmt != 0); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 641 | return -EINVAL; |
| 642 | } |
| 643 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 644 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 645 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 646 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 647 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 648 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 649 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 650 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 651 | |
| 652 | /* calculate scaler config, if necessary */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 653 | if (SDE_FORMAT_IS_YUV(fmt) || src != dst) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 654 | filter[SDE_SSPP_COMP_3] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 655 | (src <= dst) ? SDE_SCALE_FILTER_BIL : |
| 656 | SDE_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 657 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 658 | if (SDE_FORMAT_IS_YUV(fmt)) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 659 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 660 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 661 | } else { |
| 662 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 663 | filter[SDE_SSPP_COMP_1_2] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 664 | SDE_SCALE_FILTER_NEAREST; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 665 | } |
| 666 | } else { |
| 667 | /* disable scaler */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 668 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX; |
| 669 | filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX; |
| 670 | filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 671 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 672 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 673 | } |
| 674 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 675 | /** |
| 676 | * _sde_plane_setup_pixel_ext - determine default pixel extension values |
| 677 | * @psde: Pointer to SDE plane object |
| 678 | * @src: Source size |
| 679 | * @dst: Destination size |
| 680 | * @decimated_src: Source size after decimation, if any |
| 681 | * @phase_steps: Pointer to output array for phase steps |
| 682 | * @out_src: Output array for pixel extension values |
| 683 | * @out_edge1: Output array for pixel extension first edge |
| 684 | * @out_edge2: Output array for pixel extension second edge |
| 685 | * @filter: Pointer to array for filter type |
| 686 | * @fmt: Pointer to format definition |
| 687 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 688 | * @post_compare: Whether to chroma subsampled source size for comparisions |
| 689 | */ |
| 690 | static void _sde_plane_setup_pixel_ext(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 691 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 692 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 693 | int *out_edge2, enum sde_hw_filter *filter, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 694 | const struct sde_format *fmt, uint32_t chroma_subsampling, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 695 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 696 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 697 | int64_t edge1, edge2, caf; |
| 698 | uint32_t src_work; |
| 699 | int i, tmp; |
| 700 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 701 | if (psde && phase_steps && out_src && out_edge1 && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 702 | out_edge2 && filter && fmt) { |
| 703 | /* handle CAF for YUV formats */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 704 | if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 705 | caf = PHASE_STEP_UNIT_SCALE; |
| 706 | else |
| 707 | caf = 0; |
| 708 | |
| 709 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 710 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 711 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 712 | src_work /= chroma_subsampling; |
| 713 | if (post_compare) |
| 714 | src = src_work; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 715 | if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 716 | /* unity */ |
| 717 | edge1 = 0; |
| 718 | edge2 = 0; |
| 719 | } else if (dst >= src) { |
| 720 | /* upscale */ |
| 721 | edge1 = (1 << PHASE_RESIDUAL); |
| 722 | edge1 -= caf; |
| 723 | edge2 = (1 << PHASE_RESIDUAL); |
| 724 | edge2 += (dst - 1) * *(phase_steps + i); |
| 725 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 726 | edge2 += caf; |
| 727 | edge2 = -(edge2); |
| 728 | } else { |
| 729 | /* downscale */ |
| 730 | edge1 = 0; |
| 731 | edge2 = (dst - 1) * *(phase_steps + i); |
| 732 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 733 | edge2 += *(phase_steps + i); |
| 734 | edge2 = -(edge2); |
| 735 | } |
| 736 | |
| 737 | /* only enable CAF for luma plane */ |
| 738 | caf = 0; |
| 739 | |
| 740 | /* populate output arrays */ |
| 741 | *(out_src + i) = src_work; |
| 742 | |
| 743 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 744 | if (edge1 >= 0) { |
| 745 | tmp = (uint32_t)edge1; |
| 746 | tmp >>= PHASE_STEP_SHIFT; |
| 747 | *(out_edge1 + i) = -tmp; |
| 748 | } else { |
| 749 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 750 | *(out_edge1 + i) = |
| 751 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 752 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 753 | } |
| 754 | if (edge2 >= 0) { |
| 755 | tmp = (uint32_t)edge2; |
| 756 | tmp >>= PHASE_STEP_SHIFT; |
| 757 | *(out_edge2 + i) = -tmp; |
| 758 | } else { |
| 759 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 760 | *(out_edge2 + i) = |
| 761 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 762 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 763 | } |
| 764 | } |
| 765 | } |
| 766 | } |
| 767 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 768 | static inline void _sde_plane_setup_csc(struct sde_plane *psde) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 769 | { |
| 770 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 771 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 772 | /* S15.16 format */ |
| 773 | 0x00012A00, 0x00000000, 0x00019880, |
| 774 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 775 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 776 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 777 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 778 | { 0xfff0, 0xff80, 0xff80,}, |
| 779 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 780 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 781 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 782 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 783 | }; |
abeykun | 1c312f6 | 2016-08-26 09:47:12 -0400 | [diff] [blame] | 784 | static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = { |
| 785 | { |
| 786 | /* S15.16 format */ |
| 787 | 0x00012A00, 0x00000000, 0x00019880, |
| 788 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 789 | 0x00012A00, 0x00020480, 0x00000000, |
| 790 | }, |
| 791 | /* signed bias */ |
| 792 | { 0xffc0, 0xfe00, 0xfe00,}, |
| 793 | { 0x0, 0x0, 0x0,}, |
| 794 | /* unsigned clamp */ |
| 795 | { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, |
| 796 | { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, |
| 797 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 798 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 799 | if (!psde) { |
| 800 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 801 | return; |
| 802 | } |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 803 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 804 | /* revert to kernel default if override not available */ |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 805 | if (psde->csc_usr_ptr) |
| 806 | psde->csc_ptr = psde->csc_usr_ptr; |
abeykun | 1c312f6 | 2016-08-26 09:47:12 -0400 | [diff] [blame] | 807 | else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features) |
| 808 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 809 | else |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 810 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 811 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 812 | SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n", |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 813 | psde->csc_ptr->csc_mv[0], |
| 814 | psde->csc_ptr->csc_mv[1], |
| 815 | psde->csc_ptr->csc_mv[2]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 816 | } |
| 817 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 818 | static void sde_color_process_plane_setup(struct drm_plane *plane) |
| 819 | { |
| 820 | struct sde_plane *psde; |
| 821 | struct sde_plane_state *pstate; |
| 822 | uint32_t hue, saturation, value, contrast; |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 823 | struct drm_msm_memcol *memcol = NULL; |
| 824 | size_t memcol_sz = 0; |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 825 | |
| 826 | psde = to_sde_plane(plane); |
| 827 | pstate = to_sde_plane_state(plane->state); |
| 828 | |
| 829 | hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST); |
| 830 | if (psde->pipe_hw->ops.setup_pa_hue) |
| 831 | psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue); |
| 832 | saturation = (uint32_t) sde_plane_get_property(pstate, |
| 833 | PLANE_PROP_SATURATION_ADJUST); |
| 834 | if (psde->pipe_hw->ops.setup_pa_sat) |
| 835 | psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation); |
| 836 | value = (uint32_t) sde_plane_get_property(pstate, |
| 837 | PLANE_PROP_VALUE_ADJUST); |
| 838 | if (psde->pipe_hw->ops.setup_pa_val) |
| 839 | psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value); |
| 840 | contrast = (uint32_t) sde_plane_get_property(pstate, |
| 841 | PLANE_PROP_CONTRAST_ADJUST); |
| 842 | if (psde->pipe_hw->ops.setup_pa_cont) |
| 843 | psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast); |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 844 | |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 845 | if (psde->pipe_hw->ops.setup_pa_memcolor) { |
| 846 | /* Skin memory color setup */ |
| 847 | memcol = msm_property_get_blob(&psde->property_info, |
| 848 | pstate->property_blobs, |
| 849 | &memcol_sz, |
| 850 | PLANE_PROP_SKIN_COLOR); |
| 851 | psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw, |
| 852 | MEMCOLOR_SKIN, memcol); |
| 853 | |
| 854 | /* Sky memory color setup */ |
| 855 | memcol = msm_property_get_blob(&psde->property_info, |
| 856 | pstate->property_blobs, |
| 857 | &memcol_sz, |
| 858 | PLANE_PROP_SKY_COLOR); |
| 859 | psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw, |
| 860 | MEMCOLOR_SKY, memcol); |
| 861 | |
| 862 | /* Foliage memory color setup */ |
| 863 | memcol = msm_property_get_blob(&psde->property_info, |
| 864 | pstate->property_blobs, |
| 865 | &memcol_sz, |
| 866 | PLANE_PROP_FOLIAGE_COLOR); |
| 867 | psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw, |
| 868 | MEMCOLOR_FOLIAGE, memcol); |
| 869 | } |
| 870 | } |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 871 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 872 | static void _sde_plane_setup_scaler(struct sde_plane *psde, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 873 | const struct sde_format *fmt, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 874 | struct sde_plane_state *pstate) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 875 | { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 876 | struct sde_hw_pixel_ext *pe; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 877 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 878 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 879 | if (!psde || !fmt) { |
| 880 | SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n", |
| 881 | psde != 0, fmt != 0, pstate != 0); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 882 | return; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 883 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 884 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 885 | pe = &(psde->pixel_ext); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 886 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 887 | psde->pipe_cfg.horz_decimation = |
| 888 | sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE); |
| 889 | psde->pipe_cfg.vert_decimation = |
| 890 | sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 891 | |
| 892 | /* don't chroma subsample if decimating */ |
| 893 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 894 | drm_format_horz_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 895 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 896 | drm_format_vert_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 897 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 898 | /* update scaler */ |
| 899 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 900 | int error; |
| 901 | |
| 902 | error = _sde_plane_setup_scaler3_lut(psde, pstate); |
| 903 | if (error || !psde->pixel_ext_usr) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 904 | /* calculate default config for QSEED3 */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 905 | _sde_plane_setup_scaler3(psde, |
| 906 | psde->pipe_cfg.src_rect.w, |
| 907 | psde->pipe_cfg.src_rect.h, |
| 908 | psde->pipe_cfg.dst_rect.w, |
| 909 | psde->pipe_cfg.dst_rect.h, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 910 | psde->scaler3_cfg, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 911 | chroma_subsmpl_h, chroma_subsmpl_v); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 912 | } |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 913 | } else if (!psde->pixel_ext_usr) { |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 914 | uint32_t deci_dim, i; |
| 915 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 916 | /* calculate default configuration for QSEED2 */ |
| 917 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 918 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 919 | SDE_DEBUG_PLANE(psde, "default config\n"); |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 920 | deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w, |
| 921 | psde->pipe_cfg.horz_decimation); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 922 | _sde_plane_setup_scaler2(psde, |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 923 | deci_dim, |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 924 | psde->pipe_cfg.dst_rect.w, |
| 925 | pe->phase_step_x, |
| 926 | pe->horz_filter, fmt, chroma_subsmpl_h); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 927 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 928 | if (SDE_FORMAT_IS_YUV(fmt)) |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 929 | deci_dim &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 930 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w, |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 931 | psde->pipe_cfg.dst_rect.w, deci_dim, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 932 | pe->phase_step_x, |
| 933 | pe->roi_w, |
| 934 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 935 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 936 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 937 | |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 938 | deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 939 | psde->pipe_cfg.vert_decimation); |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 940 | _sde_plane_setup_scaler2(psde, |
| 941 | deci_dim, |
| 942 | psde->pipe_cfg.dst_rect.h, |
| 943 | pe->phase_step_y, |
| 944 | pe->vert_filter, fmt, chroma_subsmpl_v); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 945 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h, |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 946 | psde->pipe_cfg.dst_rect.h, deci_dim, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 947 | pe->phase_step_y, |
| 948 | pe->roi_h, |
| 949 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 950 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 951 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 952 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 953 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 954 | if (pe->num_ext_pxls_left[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 955 | pe->left_rpt[i] = pe->num_ext_pxls_left[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 956 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 957 | pe->left_ftch[i] = pe->num_ext_pxls_left[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 958 | |
| 959 | if (pe->num_ext_pxls_right[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 960 | pe->right_rpt[i] = pe->num_ext_pxls_right[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 961 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 962 | pe->right_ftch[i] = pe->num_ext_pxls_right[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 963 | |
| 964 | if (pe->num_ext_pxls_top[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 965 | pe->top_rpt[i] = pe->num_ext_pxls_top[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 966 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 967 | pe->top_ftch[i] = pe->num_ext_pxls_top[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 968 | |
| 969 | if (pe->num_ext_pxls_btm[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 970 | pe->btm_rpt[i] = pe->num_ext_pxls_btm[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 971 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 972 | pe->btm_ftch[i] = pe->num_ext_pxls_btm[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 973 | } |
| 974 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 975 | } |
| 976 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 977 | /** |
| 978 | * _sde_plane_color_fill - enables color fill on plane |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 979 | * @psde: Pointer to SDE plane object |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 980 | * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red |
| 981 | * @alpha: 8-bit fill alpha value, 255 selects 100% alpha |
| 982 | * Returns: 0 on success |
| 983 | */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 984 | static int _sde_plane_color_fill(struct sde_plane *psde, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 985 | uint32_t color, uint32_t alpha) |
| 986 | { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 987 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 988 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 989 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 990 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 991 | return -EINVAL; |
| 992 | } |
| 993 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 994 | if (!psde->pipe_hw) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 995 | SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 996 | return -EINVAL; |
| 997 | } |
| 998 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 999 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1000 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1001 | /* |
| 1002 | * select fill format to match user property expectation, |
| 1003 | * h/w only supports RGB variants |
| 1004 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1005 | fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1006 | |
| 1007 | /* update sspp */ |
| 1008 | if (fmt && psde->pipe_hw->ops.setup_solidfill) { |
| 1009 | psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw, |
| 1010 | (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); |
| 1011 | |
| 1012 | /* override scaler/decimation if solid fill */ |
| 1013 | psde->pipe_cfg.src_rect.x = 0; |
| 1014 | psde->pipe_cfg.src_rect.y = 0; |
| 1015 | psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w; |
| 1016 | psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h; |
| 1017 | |
| 1018 | _sde_plane_setup_scaler(psde, fmt, 0); |
| 1019 | |
| 1020 | if (psde->pipe_hw->ops.setup_format) |
| 1021 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
| 1022 | fmt, SDE_SSPP_SOLID_FILL); |
| 1023 | |
| 1024 | if (psde->pipe_hw->ops.setup_rects) |
| 1025 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1026 | &psde->pipe_cfg, &psde->pixel_ext, |
| 1027 | psde->scaler3_cfg); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1028 | } |
| 1029 | |
| 1030 | return 0; |
| 1031 | } |
| 1032 | |
| 1033 | static int _sde_plane_mode_set(struct drm_plane *plane, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1034 | struct drm_plane_state *state) |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1035 | { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1036 | uint32_t nplanes, src_flags; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1037 | struct sde_plane *psde; |
| 1038 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1039 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1040 | struct drm_crtc *crtc; |
| 1041 | struct drm_framebuffer *fb; |
| 1042 | struct sde_rect src, dst; |
| 1043 | bool q16_data = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1044 | int idx; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1045 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1046 | if (!plane) { |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1047 | SDE_ERROR("invalid plane\n"); |
| 1048 | return -EINVAL; |
| 1049 | } else if (!plane->state) { |
| 1050 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1051 | return -EINVAL; |
| 1052 | } |
| 1053 | |
| 1054 | psde = to_sde_plane(plane); |
| 1055 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1056 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1057 | crtc = state->crtc; |
| 1058 | fb = state->fb; |
| 1059 | if (!crtc || !fb) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1060 | SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n", |
| 1061 | crtc != 0, fb != 0); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1062 | return -EINVAL; |
| 1063 | } |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1064 | fmt = to_sde_format(msm_framebuffer_format(fb)); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1065 | nplanes = fmt->num_planes; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1066 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1067 | /* determine what needs to be refreshed */ |
| 1068 | while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) { |
| 1069 | switch (idx) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1070 | case PLANE_PROP_SCALER_V1: |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1071 | case PLANE_PROP_SCALER_V2: |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1072 | case PLANE_PROP_H_DECIMATE: |
| 1073 | case PLANE_PROP_V_DECIMATE: |
| 1074 | case PLANE_PROP_SRC_CONFIG: |
| 1075 | case PLANE_PROP_ZPOS: |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1076 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1077 | break; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1078 | case PLANE_PROP_CSC_V1: |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1079 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 1080 | break; |
| 1081 | case PLANE_PROP_COLOR_FILL: |
| 1082 | /* potentially need to refresh everything */ |
| 1083 | pstate->dirty = SDE_PLANE_DIRTY_ALL; |
| 1084 | break; |
| 1085 | case PLANE_PROP_ROTATION: |
| 1086 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 1087 | break; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1088 | case PLANE_PROP_INFO: |
| 1089 | case PLANE_PROP_ALPHA: |
| 1090 | case PLANE_PROP_INPUT_FENCE: |
| 1091 | case PLANE_PROP_BLEND_OP: |
| 1092 | /* no special action required */ |
| 1093 | break; |
| 1094 | default: |
| 1095 | /* unknown property, refresh everything */ |
| 1096 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
| 1097 | SDE_ERROR("executing full mode set, prp_idx %d\n", idx); |
| 1098 | break; |
| 1099 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1100 | } |
| 1101 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1102 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) |
| 1103 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1104 | |
| 1105 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 1106 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1107 | /* early out if nothing dirty */ |
| 1108 | if (!pstate->dirty) |
| 1109 | return 0; |
| 1110 | pstate->pending = true; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1111 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1112 | psde->is_rt_pipe = sde_crtc_is_rt(crtc); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1113 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1114 | |
| 1115 | /* update roi config */ |
| 1116 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) { |
| 1117 | POPULATE_RECT(&src, state->src_x, state->src_y, |
| 1118 | state->src_w, state->src_h, q16_data); |
| 1119 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, |
| 1120 | state->crtc_w, state->crtc_h, !q16_data); |
| 1121 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1122 | SDE_DEBUG_PLANE(psde, |
| 1123 | "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n", |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1124 | fb->base.id, src.x, src.y, src.w, src.h, |
| 1125 | crtc->base.id, dst.x, dst.y, dst.w, dst.h, |
| 1126 | drm_get_format_name(fmt->base.pixel_format), |
| 1127 | SDE_FORMAT_IS_UBWC(fmt)); |
| 1128 | |
| 1129 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 1130 | BIT(SDE_DRM_DEINTERLACE)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1131 | SDE_DEBUG_PLANE(psde, "deinterlace\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1132 | for (idx = 0; idx < SDE_MAX_PLANES; ++idx) |
| 1133 | psde->pipe_cfg.layout.plane_pitch[idx] <<= 1; |
| 1134 | src.h /= 2; |
| 1135 | src.y = DIV_ROUND_UP(src.y, 2); |
| 1136 | src.y &= ~0x1; |
| 1137 | } |
| 1138 | |
| 1139 | psde->pipe_cfg.src_rect = src; |
| 1140 | psde->pipe_cfg.dst_rect = dst; |
| 1141 | |
| 1142 | /* check for color fill */ |
| 1143 | psde->color_fill = (uint32_t)sde_plane_get_property(pstate, |
| 1144 | PLANE_PROP_COLOR_FILL); |
| 1145 | if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) { |
| 1146 | /* skip remaining processing on color fill */ |
| 1147 | pstate->dirty = 0x0; |
| 1148 | } else if (psde->pipe_hw->ops.setup_rects) { |
| 1149 | _sde_plane_setup_scaler(psde, fmt, pstate); |
| 1150 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1151 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1152 | &psde->pipe_cfg, &psde->pixel_ext, |
| 1153 | psde->scaler3_cfg); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1154 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1155 | } |
| 1156 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1157 | if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) && |
| 1158 | psde->pipe_hw->ops.setup_format) { |
| 1159 | src_flags = 0x0; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1160 | SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n", |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1161 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 1162 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1163 | BIT(DRM_REFLECT_X)) |
| 1164 | src_flags |= SDE_SSPP_FLIP_LR; |
| 1165 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1166 | BIT(DRM_REFLECT_Y)) |
| 1167 | src_flags |= SDE_SSPP_FLIP_UD; |
| 1168 | |
| 1169 | /* update format */ |
| 1170 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags); |
| 1171 | |
| 1172 | /* update csc */ |
| 1173 | if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1174 | _sde_plane_setup_csc(psde); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1175 | else |
| 1176 | psde->csc_ptr = 0; |
| 1177 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1178 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1179 | sde_color_process_plane_setup(plane); |
| 1180 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1181 | /* update sharpening */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1182 | if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) && |
| 1183 | psde->pipe_hw->ops.setup_sharpening) { |
| 1184 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 1185 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 1186 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 1187 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1188 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1189 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1190 | &psde->sharp_cfg); |
| 1191 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1192 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1193 | _sde_plane_set_qos_lut(plane, fb); |
| 1194 | _sde_plane_set_danger_lut(plane, fb); |
| 1195 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1196 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1197 | _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL); |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1198 | _sde_plane_set_ot_limit(plane, crtc); |
| 1199 | } |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1200 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1201 | /* clear dirty */ |
| 1202 | pstate->dirty = 0x0; |
| 1203 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1204 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1205 | } |
| 1206 | |
| 1207 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 1208 | struct drm_plane_state *new_state) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1209 | { |
| 1210 | struct drm_framebuffer *fb = new_state->fb; |
| 1211 | struct sde_plane *psde = to_sde_plane(plane); |
| 1212 | |
| 1213 | if (!new_state->fb) |
| 1214 | return 0; |
| 1215 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1216 | SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1217 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 1218 | } |
| 1219 | |
| 1220 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 1221 | struct drm_plane_state *old_state) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1222 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1223 | struct drm_framebuffer *fb = old_state ? old_state->fb : NULL; |
| 1224 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1225 | |
| 1226 | if (!fb) |
| 1227 | return; |
| 1228 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1229 | SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1230 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 1231 | } |
| 1232 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1233 | static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde, |
| 1234 | struct drm_plane_state *state, |
| 1235 | struct drm_plane_state *old_state) |
| 1236 | { |
| 1237 | struct sde_plane_state *pstate = to_sde_plane_state(state); |
| 1238 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1239 | /* no need to check it again */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1240 | if (pstate->dirty == SDE_PLANE_DIRTY_ALL) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1241 | return; |
| 1242 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1243 | if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state) |
| 1244 | || psde->is_error) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1245 | SDE_DEBUG_PLANE(psde, |
| 1246 | "enabling/disabling full modeset required\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1247 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1248 | } else if (to_sde_plane_state(old_state)->pending) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1249 | SDE_DEBUG_PLANE(psde, "still pending\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1250 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1251 | } else if (state->src_w != old_state->src_w || |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1252 | state->src_h != old_state->src_h || |
| 1253 | state->src_x != old_state->src_x || |
| 1254 | state->src_y != old_state->src_y) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1255 | SDE_DEBUG_PLANE(psde, "src rect updated\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1256 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1257 | } else if (state->crtc_w != old_state->crtc_w || |
| 1258 | state->crtc_h != old_state->crtc_h || |
| 1259 | state->crtc_x != old_state->crtc_x || |
| 1260 | state->crtc_y != old_state->crtc_y) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1261 | SDE_DEBUG_PLANE(psde, "crtc rect updated\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1262 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1263 | } |
| 1264 | |
| 1265 | if (!state->fb || !old_state->fb) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1266 | SDE_DEBUG_PLANE(psde, "can't compare fb handles\n"); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1267 | } else if (state->fb->pixel_format != old_state->fb->pixel_format) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1268 | SDE_DEBUG_PLANE(psde, "format change\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1269 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1270 | } else { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1271 | uint64_t *new_mods = state->fb->modifier; |
| 1272 | uint64_t *old_mods = old_state->fb->modifier; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1273 | uint32_t *new_pitches = state->fb->pitches; |
| 1274 | uint32_t *old_pitches = old_state->fb->pitches; |
| 1275 | uint32_t *new_offset = state->fb->offsets; |
| 1276 | uint32_t *old_offset = old_state->fb->offsets; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1277 | int i; |
| 1278 | |
| 1279 | for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) { |
| 1280 | if (new_mods[i] != old_mods[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1281 | SDE_DEBUG_PLANE(psde, |
| 1282 | "format modifiers change\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1283 | plane:%d new_mode:%llu old_mode:%llu\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1284 | i, new_mods[i], old_mods[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1285 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1286 | SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1287 | break; |
| 1288 | } |
| 1289 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1290 | for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) { |
| 1291 | if (new_pitches[i] != old_pitches[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1292 | SDE_DEBUG_PLANE(psde, |
| 1293 | "pitches change plane:%d\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1294 | old_pitches:%u new_pitches:%u\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1295 | i, old_pitches[i], new_pitches[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1296 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1297 | break; |
| 1298 | } |
| 1299 | } |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1300 | for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) { |
| 1301 | if (new_offset[i] != old_offset[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1302 | SDE_DEBUG_PLANE(psde, |
| 1303 | "offset change plane:%d\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1304 | old_offset:%u new_offset:%u\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1305 | i, old_offset[i], new_offset[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1306 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1307 | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1308 | break; |
| 1309 | } |
| 1310 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1311 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1312 | } |
| 1313 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1314 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 1315 | struct drm_plane_state *state) |
| 1316 | { |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1317 | int ret = 0; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1318 | struct sde_plane *psde; |
| 1319 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1320 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1321 | struct sde_rect src, dst; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1322 | uint32_t deci_w, deci_h, src_deci_w, src_deci_h; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1323 | uint32_t max_upscale, max_downscale, min_src_size, max_linewidth; |
| 1324 | bool q16_data = true; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1325 | |
| 1326 | if (!plane || !state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1327 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 1328 | plane != 0, state != 0); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1329 | ret = -EINVAL; |
| 1330 | goto exit; |
| 1331 | } |
| 1332 | |
| 1333 | psde = to_sde_plane(plane); |
| 1334 | pstate = to_sde_plane_state(state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1335 | |
| 1336 | if (!psde->pipe_sblk) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1337 | SDE_ERROR_PLANE(psde, "invalid catalog\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1338 | ret = -EINVAL; |
| 1339 | goto exit; |
| 1340 | } |
| 1341 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1342 | deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE); |
| 1343 | deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1344 | |
| 1345 | /* src values are in Q16 fixed point, convert to integer */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1346 | POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w, |
| 1347 | state->src_h, q16_data); |
| 1348 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w, |
| 1349 | state->crtc_h, !q16_data); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1350 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1351 | src_deci_w = DECIMATED_DIMENSION(src.w, deci_w); |
| 1352 | src_deci_h = DECIMATED_DIMENSION(src.h, deci_h); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1353 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1354 | max_upscale = psde->pipe_sblk->maxupscale; |
| 1355 | max_downscale = psde->pipe_sblk->maxdwnscale; |
| 1356 | max_linewidth = psde->pipe_sblk->maxlinewidth; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1357 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1358 | SDE_DEBUG_PLANE(psde, "check %d -> %d\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1359 | sde_plane_enabled(plane->state), sde_plane_enabled(state)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1360 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1361 | if (!sde_plane_enabled(state)) |
| 1362 | goto modeset_update; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1363 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1364 | fmt = to_sde_format(msm_framebuffer_format(state->fb)); |
| 1365 | |
| 1366 | min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1; |
| 1367 | |
| 1368 | if (SDE_FORMAT_IS_YUV(fmt) && |
| 1369 | (!(psde->features & SDE_SSPP_SCALER) || |
abeykun | 1c312f6 | 2016-08-26 09:47:12 -0400 | [diff] [blame] | 1370 | !(psde->features & (BIT(SDE_SSPP_CSC) |
| 1371 | | BIT(SDE_SSPP_CSC_10BIT))))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1372 | SDE_ERROR_PLANE(psde, |
| 1373 | "plane doesn't have scaler/csc for yuv\n"); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1374 | ret = -EINVAL; |
| 1375 | |
| 1376 | /* check src bounds */ |
| 1377 | } else if (state->fb->width > MAX_IMG_WIDTH || |
| 1378 | state->fb->height > MAX_IMG_HEIGHT || |
| 1379 | src.w < min_src_size || src.h < min_src_size || |
| 1380 | CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) || |
| 1381 | CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1382 | SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1383 | src.x, src.y, src.w, src.h); |
| 1384 | ret = -E2BIG; |
| 1385 | |
| 1386 | /* valid yuv image */ |
| 1387 | } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) || |
| 1388 | (src.w & 0x1) || (src.h & 0x1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1389 | SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1390 | src.x, src.y, src.w, src.h); |
| 1391 | ret = -EINVAL; |
| 1392 | |
| 1393 | /* min dst support */ |
| 1394 | } else if (dst.w < 0x1 || dst.h < 0x1) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1395 | SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1396 | dst.x, dst.y, dst.w, dst.h); |
| 1397 | ret = -EINVAL; |
| 1398 | |
| 1399 | /* decimation validation */ |
| 1400 | } else if (deci_w || deci_h) { |
| 1401 | if ((deci_w > psde->pipe_sblk->maxhdeciexp) || |
| 1402 | (deci_h > psde->pipe_sblk->maxvdeciexp)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1403 | SDE_ERROR_PLANE(psde, |
| 1404 | "too much decimation requested\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1405 | ret = -EINVAL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1406 | } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1407 | SDE_ERROR_PLANE(psde, |
| 1408 | "decimation requires linear fetch\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1409 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1410 | } |
| 1411 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1412 | } else if (!(psde->features & SDE_SSPP_SCALER) && |
| 1413 | ((src.w != dst.w) || (src.h != dst.h))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1414 | SDE_ERROR_PLANE(psde, |
| 1415 | "pipe doesn't support scaling %ux%u->%ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1416 | src.w, src.h, dst.w, dst.h); |
| 1417 | ret = -EINVAL; |
| 1418 | |
| 1419 | /* check decimated source width */ |
| 1420 | } else if (src_deci_w > max_linewidth) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1421 | SDE_ERROR_PLANE(psde, |
| 1422 | "invalid src w:%u, deci w:%u, line w:%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1423 | src.w, src_deci_w, max_linewidth); |
| 1424 | ret = -E2BIG; |
| 1425 | |
| 1426 | /* check max scaler capability */ |
| 1427 | } else if (((src_deci_w * max_upscale) < dst.w) || |
| 1428 | ((src_deci_h * max_upscale) < dst.h) || |
| 1429 | ((dst.w * max_downscale) < src_deci_w) || |
| 1430 | ((dst.h * max_downscale) < src_deci_h)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1431 | SDE_ERROR_PLANE(psde, |
| 1432 | "too much scaling requested %ux%u->%ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1433 | src_deci_w, src_deci_h, dst.w, dst.h); |
| 1434 | ret = -E2BIG; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1435 | } |
| 1436 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1437 | modeset_update: |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1438 | if (!ret) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1439 | _sde_plane_atomic_check_mode_changed(psde, state, plane->state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1440 | exit: |
| 1441 | return ret; |
| 1442 | } |
| 1443 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1444 | /** |
| 1445 | * sde_plane_flush - final plane operations before commit flush |
| 1446 | * @plane: Pointer to drm plane structure |
| 1447 | */ |
| 1448 | void sde_plane_flush(struct drm_plane *plane) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1449 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1450 | struct sde_plane *psde; |
| 1451 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1452 | if (!plane) { |
| 1453 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1454 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1455 | } |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1456 | |
| 1457 | psde = to_sde_plane(plane); |
| 1458 | |
| 1459 | /* |
| 1460 | * These updates have to be done immediately before the plane flush |
| 1461 | * timing, and may not be moved to the atomic_update/mode_set functions. |
| 1462 | */ |
| 1463 | if (psde->is_error) |
| 1464 | /* force white frame with 0% alpha pipe output on error */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1465 | _sde_plane_color_fill(psde, 0xFFFFFF, 0x0); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1466 | else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) |
| 1467 | /* force 100% alpha */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1468 | _sde_plane_color_fill(psde, psde->color_fill, 0xFF); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1469 | else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc) |
| 1470 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
| 1471 | |
| 1472 | /* flag h/w flush complete */ |
| 1473 | if (plane->state) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1474 | to_sde_plane_state(plane->state)->pending = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1475 | } |
| 1476 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1477 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1478 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1479 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1480 | struct sde_plane *psde; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1481 | struct drm_plane_state *state; |
| 1482 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1483 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1484 | if (!plane) { |
| 1485 | SDE_ERROR("invalid plane\n"); |
| 1486 | return; |
| 1487 | } else if (!plane->state) { |
| 1488 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1489 | return; |
| 1490 | } |
| 1491 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1492 | psde = to_sde_plane(plane); |
| 1493 | psde->is_error = false; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1494 | state = plane->state; |
| 1495 | pstate = to_sde_plane_state(state); |
| 1496 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1497 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1498 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1499 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1500 | pstate->pending = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1501 | } else { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1502 | int ret; |
| 1503 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1504 | ret = _sde_plane_mode_set(plane, state); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1505 | /* atomic_check should have ensured that this doesn't fail */ |
| 1506 | WARN_ON(ret < 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1507 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1508 | } |
| 1509 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1510 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1511 | /* helper to install properties which are common to planes and crtcs */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1512 | static void _sde_plane_install_properties(struct drm_plane *plane, |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1513 | struct sde_mdss_cfg *catalog) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1514 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1515 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 1516 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 1517 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 1518 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 1519 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 1520 | }; |
| 1521 | static const struct drm_prop_enum_list e_src_config[] = { |
| 1522 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 1523 | }; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1524 | const struct sde_format_extended *format_list; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1525 | struct sde_kms_info *info; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1526 | struct sde_plane *psde = to_sde_plane(plane); |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1527 | int zpos_max = 255; |
| 1528 | int zpos_def = 0; |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1529 | char feature_name[256]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1530 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1531 | if (!plane || !psde) { |
| 1532 | SDE_ERROR("invalid plane\n"); |
| 1533 | return; |
| 1534 | } else if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 1535 | SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n", |
| 1536 | psde->pipe_hw != 0, psde->pipe_sblk != 0); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1537 | return; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1538 | } else if (!catalog) { |
| 1539 | SDE_ERROR("invalid catalog\n"); |
| 1540 | return; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1541 | } |
| 1542 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1543 | if (sde_is_custom_client()) { |
Clarence Ip | 649989a | 2016-10-21 14:28:34 -0400 | [diff] [blame] | 1544 | if (catalog->mixer_count && catalog->mixer && |
| 1545 | catalog->mixer[0].sblk->maxblendstages) { |
| 1546 | zpos_max = catalog->mixer[0].sblk->maxblendstages - 1; |
| 1547 | if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1) |
| 1548 | zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1; |
| 1549 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1550 | } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) { |
| 1551 | /* reserve zpos == 0 for primary planes */ |
| 1552 | zpos_def = drm_plane_index(plane) + 1; |
| 1553 | } |
| 1554 | |
| 1555 | msm_property_install_range(&psde->property_info, "zpos", |
| 1556 | 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1557 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1558 | msm_property_install_range(&psde->property_info, "alpha", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1559 | 0x0, 0, 255, 255, PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1560 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1561 | /* linux default file descriptor range on each process */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1562 | msm_property_install_range(&psde->property_info, "input_fence", |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1563 | 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1564 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1565 | if (psde->pipe_sblk->maxhdeciexp) { |
| 1566 | msm_property_install_range(&psde->property_info, "h_decimate", |
| 1567 | 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0, |
| 1568 | PLANE_PROP_H_DECIMATE); |
| 1569 | } |
| 1570 | |
| 1571 | if (psde->pipe_sblk->maxvdeciexp) { |
| 1572 | msm_property_install_range(&psde->property_info, "v_decimate", |
| 1573 | 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0, |
| 1574 | PLANE_PROP_V_DECIMATE); |
| 1575 | } |
| 1576 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1577 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 1578 | msm_property_install_volatile_range(&psde->property_info, |
| 1579 | "scaler_v2", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2); |
| 1580 | msm_property_install_blob(&psde->property_info, "lut_ed", 0, |
| 1581 | PLANE_PROP_SCALER_LUT_ED); |
| 1582 | msm_property_install_blob(&psde->property_info, "lut_cir", 0, |
| 1583 | PLANE_PROP_SCALER_LUT_CIR); |
| 1584 | msm_property_install_blob(&psde->property_info, "lut_sep", 0, |
| 1585 | PLANE_PROP_SCALER_LUT_SEP); |
| 1586 | } else if (psde->features & SDE_SSPP_SCALER) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1587 | msm_property_install_volatile_range(&psde->property_info, |
| 1588 | "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1); |
| 1589 | } |
| 1590 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1591 | if (psde->features & BIT(SDE_SSPP_CSC)) { |
| 1592 | msm_property_install_volatile_range(&psde->property_info, |
| 1593 | "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1); |
| 1594 | } |
| 1595 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1596 | if (psde->features & BIT(SDE_SSPP_HSIC)) { |
| 1597 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1598 | "SDE_SSPP_HUE_V", |
| 1599 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1600 | msm_property_install_range(&psde->property_info, |
| 1601 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1602 | PLANE_PROP_HUE_ADJUST); |
| 1603 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1604 | "SDE_SSPP_SATURATION_V", |
| 1605 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1606 | msm_property_install_range(&psde->property_info, |
| 1607 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1608 | PLANE_PROP_SATURATION_ADJUST); |
| 1609 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1610 | "SDE_SSPP_VALUE_V", |
| 1611 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1612 | msm_property_install_range(&psde->property_info, |
| 1613 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1614 | PLANE_PROP_VALUE_ADJUST); |
| 1615 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1616 | "SDE_SSPP_CONTRAST_V", |
| 1617 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1618 | msm_property_install_range(&psde->property_info, |
| 1619 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1620 | PLANE_PROP_CONTRAST_ADJUST); |
| 1621 | } |
| 1622 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1623 | /* standard properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1624 | msm_property_install_rotation(&psde->property_info, |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 1625 | (unsigned int) (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y)), |
| 1626 | PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1627 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1628 | msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1629 | e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1630 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1631 | msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1, |
| 1632 | e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG); |
| 1633 | |
| 1634 | if (psde->pipe_hw->ops.setup_solidfill) |
| 1635 | msm_property_install_range(&psde->property_info, "color_fill", |
| 1636 | 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL); |
| 1637 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1638 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1639 | if (!info) { |
| 1640 | SDE_ERROR("failed to allocate info memory\n"); |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1641 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1642 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1643 | |
| 1644 | msm_property_install_blob(&psde->property_info, "capabilities", |
| 1645 | DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO); |
| 1646 | sde_kms_info_reset(info); |
| 1647 | |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1648 | format_list = psde->pipe_sblk->format_list; |
| 1649 | if (format_list) { |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1650 | sde_kms_info_start(info, "pixel_formats"); |
| 1651 | while (format_list->fourcc_format) { |
| 1652 | sde_kms_info_append_format(info, |
| 1653 | format_list->fourcc_format, |
| 1654 | format_list->modifier); |
| 1655 | ++format_list; |
| 1656 | } |
| 1657 | sde_kms_info_stop(info); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1658 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1659 | |
| 1660 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 1661 | psde->pipe_sblk->maxlinewidth); |
| 1662 | sde_kms_info_add_keyint(info, "max_upscale", |
| 1663 | psde->pipe_sblk->maxupscale); |
| 1664 | sde_kms_info_add_keyint(info, "max_downscale", |
| 1665 | psde->pipe_sblk->maxdwnscale); |
| 1666 | sde_kms_info_add_keyint(info, "max_horizontal_deci", |
| 1667 | psde->pipe_sblk->maxhdeciexp); |
| 1668 | sde_kms_info_add_keyint(info, "max_vertical_deci", |
| 1669 | psde->pipe_sblk->maxvdeciexp); |
| 1670 | msm_property_set_blob(&psde->property_info, &psde->blob_info, |
| 1671 | info->data, info->len, PLANE_PROP_INFO); |
| 1672 | |
| 1673 | kfree(info); |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 1674 | |
| 1675 | if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) { |
| 1676 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1677 | "SDE_SSPP_SKIN_COLOR_V", |
| 1678 | psde->pipe_sblk->memcolor_blk.version >> 16); |
| 1679 | msm_property_install_blob(&psde->property_info, feature_name, 0, |
| 1680 | PLANE_PROP_SKIN_COLOR); |
| 1681 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1682 | "SDE_SSPP_SKY_COLOR_V", |
| 1683 | psde->pipe_sblk->memcolor_blk.version >> 16); |
| 1684 | msm_property_install_blob(&psde->property_info, feature_name, 0, |
| 1685 | PLANE_PROP_SKY_COLOR); |
| 1686 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1687 | "SDE_SSPP_FOLIAGE_COLOR_V", |
| 1688 | psde->pipe_sblk->memcolor_blk.version >> 16); |
| 1689 | msm_property_install_blob(&psde->property_info, feature_name, 0, |
| 1690 | PLANE_PROP_FOLIAGE_COLOR); |
| 1691 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1692 | } |
| 1693 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1694 | static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr) |
| 1695 | { |
| 1696 | struct sde_drm_csc_v1 csc_v1; |
| 1697 | int i; |
| 1698 | |
| 1699 | if (!psde) { |
| 1700 | SDE_ERROR("invalid plane\n"); |
| 1701 | return; |
| 1702 | } |
| 1703 | |
| 1704 | psde->csc_usr_ptr = NULL; |
| 1705 | if (!usr_ptr) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1706 | SDE_DEBUG_PLANE(psde, "csc data removed\n"); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1707 | return; |
| 1708 | } |
| 1709 | |
| 1710 | if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1711 | SDE_ERROR_PLANE(psde, "failed to copy csc data\n"); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1712 | return; |
| 1713 | } |
| 1714 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1715 | /* populate from user space */ |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1716 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
| 1717 | psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16; |
| 1718 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
| 1719 | psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i]; |
| 1720 | psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i]; |
| 1721 | } |
| 1722 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
| 1723 | psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i]; |
| 1724 | psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i]; |
| 1725 | } |
| 1726 | psde->csc_usr_ptr = &psde->csc_cfg; |
| 1727 | } |
| 1728 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1729 | static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr) |
| 1730 | { |
| 1731 | struct sde_drm_scaler_v1 scale_v1; |
| 1732 | struct sde_hw_pixel_ext *pe; |
| 1733 | int i; |
| 1734 | |
| 1735 | if (!psde) { |
| 1736 | SDE_ERROR("invalid plane\n"); |
| 1737 | return; |
| 1738 | } |
| 1739 | |
| 1740 | psde->pixel_ext_usr = false; |
| 1741 | if (!usr) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1742 | SDE_DEBUG_PLANE(psde, "scale data removed\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1743 | return; |
| 1744 | } |
| 1745 | |
| 1746 | if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1747 | SDE_ERROR_PLANE(psde, "failed to copy scale data\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1748 | return; |
| 1749 | } |
| 1750 | |
| 1751 | /* populate from user space */ |
| 1752 | pe = &(psde->pixel_ext); |
| 1753 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
| 1754 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 1755 | pe->init_phase_x[i] = scale_v1.init_phase_x[i]; |
| 1756 | pe->phase_step_x[i] = scale_v1.phase_step_x[i]; |
| 1757 | pe->init_phase_y[i] = scale_v1.init_phase_y[i]; |
| 1758 | pe->phase_step_y[i] = scale_v1.phase_step_y[i]; |
| 1759 | |
| 1760 | pe->horz_filter[i] = scale_v1.horz_filter[i]; |
| 1761 | pe->vert_filter[i] = scale_v1.vert_filter[i]; |
| 1762 | } |
| 1763 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1764 | pe->left_ftch[i] = scale_v1.pe.left_ftch[i]; |
| 1765 | pe->right_ftch[i] = scale_v1.pe.right_ftch[i]; |
| 1766 | pe->left_rpt[i] = scale_v1.pe.left_rpt[i]; |
| 1767 | pe->right_rpt[i] = scale_v1.pe.right_rpt[i]; |
| 1768 | pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i]; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1769 | |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1770 | pe->top_ftch[i] = scale_v1.pe.top_ftch[i]; |
| 1771 | pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i]; |
| 1772 | pe->top_rpt[i] = scale_v1.pe.top_rpt[i]; |
| 1773 | pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i]; |
| 1774 | pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i]; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1775 | } |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1776 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1777 | psde->pixel_ext_usr = true; |
| 1778 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1779 | SDE_DEBUG_PLANE(psde, "user property data copied\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1780 | } |
| 1781 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1782 | static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde, |
| 1783 | struct sde_plane_state *pstate, void *usr) |
| 1784 | { |
| 1785 | struct sde_drm_scaler_v2 scale_v2; |
| 1786 | struct sde_hw_pixel_ext *pe; |
| 1787 | int i; |
| 1788 | struct sde_hw_scaler3_cfg *cfg; |
| 1789 | |
| 1790 | if (!psde) { |
| 1791 | SDE_ERROR("invalid plane\n"); |
| 1792 | return; |
| 1793 | } |
| 1794 | |
| 1795 | cfg = psde->scaler3_cfg; |
| 1796 | psde->pixel_ext_usr = false; |
| 1797 | if (!usr) { |
| 1798 | SDE_DEBUG_PLANE(psde, "scale data removed\n"); |
| 1799 | return; |
| 1800 | } |
| 1801 | |
| 1802 | if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) { |
| 1803 | SDE_ERROR_PLANE(psde, "failed to copy scale data\n"); |
| 1804 | return; |
| 1805 | } |
| 1806 | |
| 1807 | /* populate from user space */ |
| 1808 | pe = &(psde->pixel_ext); |
| 1809 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
| 1810 | cfg->enable = scale_v2.enable; |
| 1811 | cfg->dir_en = scale_v2.dir_en; |
| 1812 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 1813 | cfg->init_phase_x[i] = scale_v2.init_phase_x[i]; |
| 1814 | cfg->phase_step_x[i] = scale_v2.phase_step_x[i]; |
| 1815 | cfg->init_phase_y[i] = scale_v2.init_phase_y[i]; |
| 1816 | cfg->phase_step_y[i] = scale_v2.phase_step_y[i]; |
| 1817 | |
| 1818 | cfg->preload_x[i] = scale_v2.preload_x[i]; |
| 1819 | cfg->preload_y[i] = scale_v2.preload_y[i]; |
| 1820 | cfg->src_width[i] = scale_v2.src_width[i]; |
| 1821 | cfg->src_height[i] = scale_v2.src_height[i]; |
| 1822 | } |
| 1823 | cfg->dst_width = scale_v2.dst_width; |
| 1824 | cfg->dst_height = scale_v2.dst_height; |
| 1825 | |
| 1826 | cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg; |
| 1827 | cfg->uv_filter_cfg = scale_v2.uv_filter_cfg; |
| 1828 | cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg; |
| 1829 | cfg->blend_cfg = scale_v2.blend_cfg; |
| 1830 | |
| 1831 | cfg->lut_flag = scale_v2.lut_flag; |
| 1832 | cfg->dir_lut_idx = scale_v2.dir_lut_idx; |
| 1833 | cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx; |
| 1834 | cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx; |
| 1835 | cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx; |
| 1836 | cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx; |
| 1837 | |
| 1838 | cfg->de.enable = scale_v2.de.enable; |
| 1839 | cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1; |
| 1840 | cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2; |
| 1841 | cfg->de.clip = scale_v2.de.clip; |
| 1842 | cfg->de.limit = scale_v2.de.limit; |
| 1843 | cfg->de.thr_quiet = scale_v2.de.thr_quiet; |
| 1844 | cfg->de.thr_dieout = scale_v2.de.thr_dieout; |
| 1845 | cfg->de.thr_low = scale_v2.de.thr_low; |
| 1846 | cfg->de.thr_high = scale_v2.de.thr_high; |
| 1847 | cfg->de.prec_shift = scale_v2.de.prec_shift; |
| 1848 | for (i = 0; i < SDE_MAX_DE_CURVES; i++) { |
| 1849 | cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i]; |
| 1850 | cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i]; |
| 1851 | cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i]; |
| 1852 | } |
| 1853 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1854 | pe->left_ftch[i] = scale_v2.pe.left_ftch[i]; |
| 1855 | pe->right_ftch[i] = scale_v2.pe.right_ftch[i]; |
| 1856 | pe->left_rpt[i] = scale_v2.pe.left_rpt[i]; |
| 1857 | pe->right_rpt[i] = scale_v2.pe.right_rpt[i]; |
| 1858 | pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i]; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1859 | |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1860 | pe->top_ftch[i] = scale_v2.pe.top_ftch[i]; |
| 1861 | pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i]; |
| 1862 | pe->top_rpt[i] = scale_v2.pe.top_rpt[i]; |
| 1863 | pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i]; |
| 1864 | pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i]; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1865 | } |
| 1866 | psde->pixel_ext_usr = true; |
| 1867 | |
| 1868 | SDE_DEBUG_PLANE(psde, "user property data copied\n"); |
| 1869 | } |
| 1870 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1871 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1872 | struct drm_plane_state *state, struct drm_property *property, |
| 1873 | uint64_t val) |
| 1874 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1875 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1876 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1877 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1878 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1879 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1880 | |
| 1881 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1882 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1883 | } else if (!state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1884 | SDE_ERROR_PLANE(psde, "invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1885 | } else { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1886 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1887 | ret = msm_property_atomic_set(&psde->property_info, |
| 1888 | pstate->property_values, pstate->property_blobs, |
| 1889 | property, val); |
| 1890 | if (!ret) { |
| 1891 | idx = msm_property_index(&psde->property_info, |
| 1892 | property); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1893 | switch (idx) { |
| 1894 | case PLANE_PROP_INPUT_FENCE: |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1895 | _sde_plane_set_input_fence(psde, pstate, val); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1896 | break; |
| 1897 | case PLANE_PROP_CSC_V1: |
| 1898 | _sde_plane_set_csc_v1(psde, (void *)val); |
| 1899 | break; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1900 | case PLANE_PROP_SCALER_V1: |
| 1901 | _sde_plane_set_scaler_v1(psde, (void *)val); |
| 1902 | break; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1903 | case PLANE_PROP_SCALER_V2: |
| 1904 | _sde_plane_set_scaler_v2(psde, pstate, |
| 1905 | (void *)val); |
| 1906 | break; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1907 | default: |
| 1908 | /* nothing to do */ |
| 1909 | break; |
| 1910 | } |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1911 | } |
| 1912 | } |
| 1913 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1914 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1915 | } |
| 1916 | |
| 1917 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1918 | struct drm_property *property, uint64_t val) |
| 1919 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1920 | SDE_DEBUG("\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1921 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1922 | return sde_plane_atomic_set_property(plane, |
| 1923 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1924 | } |
| 1925 | |
| 1926 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1927 | const struct drm_plane_state *state, |
| 1928 | struct drm_property *property, uint64_t *val) |
| 1929 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1930 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1931 | struct sde_plane_state *pstate; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1932 | int ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1933 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1934 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1935 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1936 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1937 | SDE_ERROR("invalid state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1938 | } else { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1939 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1940 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1941 | ret = msm_property_atomic_get(&psde->property_info, |
| 1942 | pstate->property_values, pstate->property_blobs, |
| 1943 | property, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1944 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1945 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1946 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1947 | } |
| 1948 | |
| 1949 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1950 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1951 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1952 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1953 | SDE_DEBUG_PLANE(psde, "\n"); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1954 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1955 | if (psde) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1956 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1957 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1958 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1959 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1960 | if (psde->blob_info) |
| 1961 | drm_property_unreference_blob(psde->blob_info); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1962 | msm_property_destroy(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1963 | mutex_destroy(&psde->lock); |
| 1964 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1965 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1966 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1967 | /* this will destroy the states as well */ |
| 1968 | drm_plane_cleanup(plane); |
| 1969 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1970 | if (psde->pipe_hw) |
| 1971 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1972 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1973 | kfree(psde); |
| 1974 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1975 | } |
| 1976 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1977 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1978 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1979 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1980 | struct sde_plane *psde; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1981 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1982 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1983 | if (!plane || !state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1984 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 1985 | plane != 0, state != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1986 | return; |
| 1987 | } |
| 1988 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1989 | psde = to_sde_plane(plane); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1990 | pstate = to_sde_plane_state(state); |
| 1991 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1992 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1993 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1994 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1995 | if (state->fb) |
| 1996 | drm_framebuffer_unreference(state->fb); |
| 1997 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1998 | /* remove ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1999 | if (pstate->input_fence) |
| 2000 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2001 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2002 | /* destroy value helper */ |
| 2003 | msm_property_destroy_state(&psde->property_info, pstate, |
| 2004 | pstate->property_values, pstate->property_blobs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2005 | } |
| 2006 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2007 | static struct drm_plane_state * |
| 2008 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2009 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2010 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2011 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2012 | struct sde_plane_state *old_state; |
Clarence Ip | 17e908b | 2016-09-29 15:58:00 -0400 | [diff] [blame] | 2013 | uint64_t input_fence_default; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2014 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2015 | if (!plane) { |
| 2016 | SDE_ERROR("invalid plane\n"); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2017 | return NULL; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2018 | } else if (!plane->state) { |
| 2019 | SDE_ERROR("invalid plane state\n"); |
| 2020 | return NULL; |
| 2021 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2022 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2023 | old_state = to_sde_plane_state(plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2024 | psde = to_sde_plane(plane); |
| 2025 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2026 | if (!pstate) { |
| 2027 | SDE_ERROR_PLANE(psde, "failed to allocate state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2028 | return NULL; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2029 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2030 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2031 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2032 | |
| 2033 | /* duplicate value helper */ |
| 2034 | msm_property_duplicate_state(&psde->property_info, old_state, pstate, |
| 2035 | pstate->property_values, pstate->property_blobs); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2036 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2037 | /* add ref count for frame buffer */ |
| 2038 | if (pstate->base.fb) |
| 2039 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2040 | |
Clarence Ip | 17e908b | 2016-09-29 15:58:00 -0400 | [diff] [blame] | 2041 | /* clear out any input fence */ |
| 2042 | pstate->input_fence = 0; |
| 2043 | input_fence_default = msm_property_get_default( |
| 2044 | &psde->property_info, PLANE_PROP_INPUT_FENCE); |
| 2045 | msm_property_set_property(&psde->property_info, pstate->property_values, |
| 2046 | PLANE_PROP_INPUT_FENCE, input_fence_default); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2047 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 2048 | pstate->dirty = 0x0; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2049 | pstate->pending = false; |
| 2050 | |
| 2051 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2052 | } |
| 2053 | |
| 2054 | static void sde_plane_reset(struct drm_plane *plane) |
| 2055 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2056 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2057 | struct sde_plane_state *pstate; |
| 2058 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2059 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2060 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2061 | return; |
| 2062 | } |
| 2063 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2064 | psde = to_sde_plane(plane); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2065 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2066 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2067 | /* remove previous state, if present */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2068 | if (plane->state) { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2069 | sde_plane_destroy_state(plane, plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2070 | plane->state = 0; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2071 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2072 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2073 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2074 | if (!pstate) { |
| 2075 | SDE_ERROR_PLANE(psde, "failed to allocate state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2076 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2077 | } |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2078 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2079 | /* reset value helper */ |
| 2080 | msm_property_reset_state(&psde->property_info, pstate, |
| 2081 | pstate->property_values, pstate->property_blobs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2082 | |
| 2083 | pstate->base.plane = plane; |
| 2084 | |
| 2085 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2086 | } |
| 2087 | |
| 2088 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2089 | .update_plane = drm_atomic_helper_update_plane, |
| 2090 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2091 | .destroy = sde_plane_destroy, |
| 2092 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2093 | .atomic_set_property = sde_plane_atomic_set_property, |
| 2094 | .atomic_get_property = sde_plane_atomic_get_property, |
| 2095 | .reset = sde_plane_reset, |
| 2096 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 2097 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2098 | }; |
| 2099 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2100 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 2101 | .prepare_fb = sde_plane_prepare_fb, |
| 2102 | .cleanup_fb = sde_plane_cleanup_fb, |
| 2103 | .atomic_check = sde_plane_atomic_check, |
| 2104 | .atomic_update = sde_plane_atomic_update, |
| 2105 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2106 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2107 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2108 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2109 | return plane ? to_sde_plane(plane)->pipe : SSPP_NONE; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2110 | } |
| 2111 | |
Alan Kwong | f0fd851 | 2016-10-24 21:39:26 -0400 | [diff] [blame] | 2112 | static ssize_t _sde_plane_danger_read(struct file *file, |
| 2113 | char __user *buff, size_t count, loff_t *ppos) |
| 2114 | { |
| 2115 | struct sde_kms *kms = file->private_data; |
| 2116 | struct sde_mdss_cfg *cfg = kms->catalog; |
| 2117 | int len = 0; |
| 2118 | char buf[40] = {'\0'}; |
| 2119 | |
| 2120 | if (!cfg) |
| 2121 | return -ENODEV; |
| 2122 | |
| 2123 | if (*ppos) |
| 2124 | return 0; /* the end */ |
| 2125 | |
| 2126 | len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); |
| 2127 | if (len < 0 || len >= sizeof(buf)) |
| 2128 | return 0; |
| 2129 | |
| 2130 | if ((count < sizeof(buf)) || copy_to_user(buff, buf, len)) |
| 2131 | return -EFAULT; |
| 2132 | |
| 2133 | *ppos += len; /* increase offset */ |
| 2134 | |
| 2135 | return len; |
| 2136 | } |
| 2137 | |
| 2138 | static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable) |
| 2139 | { |
| 2140 | struct drm_plane *plane; |
| 2141 | |
| 2142 | drm_for_each_plane(plane, kms->dev) { |
| 2143 | if (plane->fb && plane->state) { |
| 2144 | sde_plane_danger_signal_ctrl(plane, enable); |
| 2145 | SDE_DEBUG("plane:%d img:%dx%d ", |
| 2146 | plane->base.id, plane->fb->width, |
| 2147 | plane->fb->height); |
| 2148 | SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", |
| 2149 | plane->state->src_x >> 16, |
| 2150 | plane->state->src_y >> 16, |
| 2151 | plane->state->src_w >> 16, |
| 2152 | plane->state->src_h >> 16, |
| 2153 | plane->state->crtc_x, plane->state->crtc_y, |
| 2154 | plane->state->crtc_w, plane->state->crtc_h); |
| 2155 | } else { |
| 2156 | SDE_DEBUG("Inactive plane:%d\n", plane->base.id); |
| 2157 | } |
| 2158 | } |
| 2159 | } |
| 2160 | |
| 2161 | static ssize_t _sde_plane_danger_write(struct file *file, |
| 2162 | const char __user *user_buf, size_t count, loff_t *ppos) |
| 2163 | { |
| 2164 | struct sde_kms *kms = file->private_data; |
| 2165 | struct sde_mdss_cfg *cfg = kms->catalog; |
| 2166 | int disable_panic; |
| 2167 | char buf[10]; |
| 2168 | |
| 2169 | if (!cfg) |
| 2170 | return -EFAULT; |
| 2171 | |
| 2172 | if (count >= sizeof(buf)) |
| 2173 | return -EFAULT; |
| 2174 | |
| 2175 | if (copy_from_user(buf, user_buf, count)) |
| 2176 | return -EFAULT; |
| 2177 | |
| 2178 | buf[count] = 0; /* end of string */ |
| 2179 | |
| 2180 | if (kstrtoint(buf, 0, &disable_panic)) |
| 2181 | return -EFAULT; |
| 2182 | |
| 2183 | if (disable_panic) { |
| 2184 | /* Disable panic signal for all active pipes */ |
| 2185 | SDE_DEBUG("Disabling danger:\n"); |
| 2186 | _sde_plane_set_danger_state(kms, false); |
| 2187 | kms->has_danger_ctrl = false; |
| 2188 | } else { |
| 2189 | /* Enable panic signal for all active pipes */ |
| 2190 | SDE_DEBUG("Enabling danger:\n"); |
| 2191 | kms->has_danger_ctrl = true; |
| 2192 | _sde_plane_set_danger_state(kms, true); |
| 2193 | } |
| 2194 | |
| 2195 | return count; |
| 2196 | } |
| 2197 | |
| 2198 | static const struct file_operations sde_plane_danger_enable = { |
| 2199 | .open = simple_open, |
| 2200 | .read = _sde_plane_danger_read, |
| 2201 | .write = _sde_plane_danger_write, |
| 2202 | }; |
| 2203 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2204 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 2205 | { |
| 2206 | const struct sde_sspp_sub_blks *sblk = 0; |
| 2207 | const struct sde_sspp_cfg *cfg = 0; |
| 2208 | |
| 2209 | if (psde && psde->pipe_hw) |
| 2210 | cfg = psde->pipe_hw->cap; |
| 2211 | if (cfg) |
| 2212 | sblk = cfg->sblk; |
| 2213 | |
| 2214 | if (kms && sblk) { |
| 2215 | /* create overall sub-directory for the pipe */ |
| 2216 | psde->debugfs_root = |
| 2217 | debugfs_create_dir(psde->pipe_name, |
| 2218 | sde_debugfs_get_root(kms)); |
| 2219 | if (psde->debugfs_root) { |
| 2220 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2221 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2222 | psde->debugfs_root, &psde->features); |
| 2223 | |
| 2224 | /* add register dump support */ |
| 2225 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 2226 | sblk->src_blk.base + cfg->base, |
| 2227 | sblk->src_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 2228 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2229 | sde_debugfs_create_regset32("src_blk", 0444, |
| 2230 | psde->debugfs_root, &psde->debugfs_src); |
| 2231 | |
| 2232 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 2233 | sblk->scaler_blk.base + cfg->base, |
| 2234 | sblk->scaler_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 2235 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2236 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 2237 | psde->debugfs_root, |
| 2238 | &psde->debugfs_scaler); |
| 2239 | |
| 2240 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 2241 | sblk->csc_blk.base + cfg->base, |
| 2242 | sblk->csc_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 2243 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2244 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 2245 | psde->debugfs_root, &psde->debugfs_csc); |
Alan Kwong | f0fd851 | 2016-10-24 21:39:26 -0400 | [diff] [blame] | 2246 | |
| 2247 | debugfs_create_u32("xin_id", |
| 2248 | 0444, |
| 2249 | psde->debugfs_root, |
| 2250 | (u32 *) &cfg->xin_id); |
| 2251 | debugfs_create_u32("clk_ctrl", |
| 2252 | 0444, |
| 2253 | psde->debugfs_root, |
| 2254 | (u32 *) &cfg->clk_ctrl); |
| 2255 | debugfs_create_x32("creq_vblank", |
| 2256 | 0644, |
| 2257 | psde->debugfs_root, |
| 2258 | (u32 *) &sblk->creq_vblank); |
| 2259 | debugfs_create_x32("danger_vblank", |
| 2260 | 0644, |
| 2261 | psde->debugfs_root, |
| 2262 | (u32 *) &sblk->danger_vblank); |
| 2263 | |
| 2264 | debugfs_create_file("disable_danger", |
| 2265 | 0644, |
| 2266 | psde->debugfs_root, |
| 2267 | kms, &sde_plane_danger_enable); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2268 | } |
| 2269 | } |
| 2270 | } |
| 2271 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2272 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 2273 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 2bbf7b3 | 2016-09-23 15:07:16 -0400 | [diff] [blame] | 2274 | uint32_t pipe, bool primary_plane, |
| 2275 | unsigned long possible_crtcs) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2276 | { |
| 2277 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2278 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2279 | struct msm_drm_private *priv; |
| 2280 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2281 | enum drm_plane_type type; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2282 | int ret = -EINVAL; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2283 | |
| 2284 | if (!dev) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2285 | SDE_ERROR("[%u]device is NULL\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2286 | goto exit; |
| 2287 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2288 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2289 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2290 | if (!priv) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2291 | SDE_ERROR("[%u]private data is NULL\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2292 | goto exit; |
| 2293 | } |
| 2294 | |
| 2295 | if (!priv->kms) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2296 | SDE_ERROR("[%u]invalid KMS reference\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2297 | goto exit; |
| 2298 | } |
| 2299 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2300 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2301 | if (!kms->catalog) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2302 | SDE_ERROR("[%u]invalid catalog reference\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2303 | goto exit; |
| 2304 | } |
| 2305 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2306 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2307 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 2308 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2309 | SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2310 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2311 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2312 | } |
| 2313 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2314 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2315 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2316 | psde->pipe = pipe; |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 2317 | psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2318 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2319 | /* initialize underlying h/w driver */ |
| 2320 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 2321 | if (IS_ERR(psde->pipe_hw)) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2322 | SDE_ERROR("[%u]SSPP init failed\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2323 | ret = PTR_ERR(psde->pipe_hw); |
| 2324 | goto clean_plane; |
| 2325 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2326 | SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2327 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2328 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2329 | |
| 2330 | /* cache features mask for later */ |
| 2331 | psde->features = psde->pipe_hw->cap->features; |
| 2332 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 2333 | if (!psde->pipe_sblk) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2334 | SDE_ERROR("[%u]invalid sblk\n", pipe); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 2335 | goto clean_sspp; |
| 2336 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2337 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 2338 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 2339 | psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg), |
| 2340 | GFP_KERNEL); |
| 2341 | if (!psde->scaler3_cfg) { |
| 2342 | SDE_ERROR("[%u]failed to allocate scale struct\n", |
| 2343 | pipe); |
| 2344 | ret = -ENOMEM; |
| 2345 | goto clean_sspp; |
| 2346 | } |
| 2347 | } |
| 2348 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2349 | /* add plane to DRM framework */ |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 2350 | psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list, |
| 2351 | psde->formats, |
| 2352 | 0, |
| 2353 | ARRAY_SIZE(psde->formats)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2354 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2355 | if (!psde->nformats) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2356 | SDE_ERROR("[%u]no valid formats for plane\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2357 | goto clean_sspp; |
| 2358 | } |
| 2359 | |
| 2360 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 2361 | type = DRM_PLANE_TYPE_CURSOR; |
| 2362 | else if (primary_plane) |
| 2363 | type = DRM_PLANE_TYPE_PRIMARY; |
| 2364 | else |
| 2365 | type = DRM_PLANE_TYPE_OVERLAY; |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2366 | ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs, |
| 2367 | psde->formats, psde->nformats, |
| 2368 | type, NULL); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2369 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2370 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2371 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2372 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2373 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2374 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2375 | msm_property_init(&psde->property_info, &plane->base, dev, |
| 2376 | priv->plane_property, psde->property_data, |
| 2377 | PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT, |
| 2378 | sizeof(struct sde_plane_state)); |
| 2379 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2380 | _sde_plane_install_properties(plane, kms->catalog); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 2381 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2382 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 2383 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2384 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2385 | mutex_init(&psde->lock); |
| 2386 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2387 | _sde_plane_init_debugfs(psde, kms); |
| 2388 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2389 | DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2390 | return plane; |
| 2391 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2392 | clean_sspp: |
| 2393 | if (psde && psde->pipe_hw) |
| 2394 | sde_hw_sspp_destroy(psde->pipe_hw); |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 2395 | |
| 2396 | if (psde && psde->scaler3_cfg) |
| 2397 | kfree(psde->scaler3_cfg); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2398 | clean_plane: |
| 2399 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2400 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2401 | return ERR_PTR(ret); |
| 2402 | } |