blob: 5368cbd15c4f9767cd5cd901295598c74bc1c48e [file] [log] [blame]
Clarence Ipaac9f332016-08-31 15:46:35 -04001/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040012
13#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
Clarence Ip4ce59322016-06-26 22:27:51 -040015#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040016#include <uapi/drm/sde_drm.h>
Benet Clarkd009b1d2016-06-27 14:45:59 -070017#include <uapi/drm/msm_drm_pp.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040018
19#include "msm_prop.h"
20
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070021#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040022#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040023#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040024#include "sde_hw_sspp.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040025#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070026#include "sde_crtc.h"
Lloyd Atkinson8772e202016-09-26 17:52:16 -040027#include "sde_vbif.h"
Alan Kwong83285fb2016-10-21 20:51:17 -040028#include "sde_plane.h"
Benet Clarkd009b1d2016-06-27 14:45:59 -070029#include "sde_color_processing.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040030
Clarence Ip13a8cf42016-09-29 17:27:47 -040031#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
33
34#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
35 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
36
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040037#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
38#define PHASE_STEP_SHIFT 21
39#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
40#define PHASE_RESIDUAL 15
41
Clarence Ipe78efb72016-06-24 18:35:21 -040042#define SHARP_STRENGTH_DEFAULT 32
43#define SHARP_EDGE_THR_DEFAULT 112
44#define SHARP_SMOOTH_THR_DEFAULT 8
45#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040046
Clarence Ip5e2a9222016-06-26 22:38:24 -040047#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070048
Clarence Ipcae1bb62016-07-07 12:07:13 -040049#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
50
Clarence Ip282dad62016-09-27 17:07:35 -040051/* dirty bits for update function */
52#define SDE_PLANE_DIRTY_RECTS 0x1
53#define SDE_PLANE_DIRTY_FORMAT 0x2
54#define SDE_PLANE_DIRTY_SHARPEN 0x4
55#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
56
Alan Kwong1a00e4d2016-07-18 09:42:30 -040057/**
58 * enum sde_plane_qos - Different qos configurations for each pipe
59 *
60 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
61 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
62 * this configuration is mutually exclusive from VBLANK_CTRL.
63 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
64 */
65enum sde_plane_qos {
66 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
67 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
68 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
69};
70
Clarence Ip5fc00c52016-09-23 15:03:34 -040071/*
72 * struct sde_plane - local sde plane structure
73 * @csc_cfg: Decoded user configuration for csc
74 * @csc_usr_ptr: Points to csc_cfg if valid user config available
75 * @csc_ptr: Points to sde_csc_cfg structure to use for current
76 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070077struct sde_plane {
78 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040079
80 int mmu_id;
81
Clarence Ip730e7192016-06-26 22:45:09 -040082 struct mutex lock;
83
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040084 enum sde_sspp pipe;
85 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070086 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -040087 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040088
89 struct sde_hw_pipe *pipe_hw;
90 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -040091 struct sde_hw_sharp_cfg sharp_cfg;
abeykun48f407a2016-08-25 12:06:44 -040092 struct sde_hw_scaler3_cfg *scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040093 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -040094 uint32_t color_fill;
95 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040096 bool is_rt_pipe;
Clarence Ip4ce59322016-06-26 22:27:51 -040097
Clarence Ipb43d4592016-09-08 14:21:35 -040098 struct sde_hw_pixel_ext pixel_ext;
99 bool pixel_ext_usr;
100
Clarence Ip373f8592016-05-26 00:58:42 -0400101 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400102 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -0400103 struct sde_csc_cfg *csc_ptr;
104
Clarence Ip4c1d9772016-06-26 09:35:38 -0400105 const struct sde_sspp_sub_blks *pipe_sblk;
106
Clarence Ip5e2a9222016-06-26 22:38:24 -0400107 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400108
Clarence Ipaa0faf42016-05-30 12:07:48 -0400109 struct msm_property_info property_info;
110 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700111 struct drm_property_blob *blob_info;
Clarence Ip730e7192016-06-26 22:45:09 -0400112
Clarence Ip4ce59322016-06-26 22:27:51 -0400113 /* debugfs related stuff */
114 struct dentry *debugfs_root;
115 struct sde_debugfs_regset32 debugfs_src;
116 struct sde_debugfs_regset32 debugfs_scaler;
117 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700118};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700119
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700120#define to_sde_plane(x) container_of(x, struct sde_plane, base)
121
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400122static bool sde_plane_enabled(struct drm_plane_state *state)
123{
Clarence Ipdbde9832016-06-26 09:48:36 -0400124 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400125}
126
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400127/**
128 * _sde_plane_calc_fill_level - calculate fill level of the given source format
129 * @plane: Pointer to drm plane
130 * @fmt: Pointer to source buffer format
131 * @src_wdith: width of source buffer
132 * Return: fill level corresponding to the source buffer/format or 0 if error
133 */
134static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
135 const struct sde_format *fmt, u32 src_width)
136{
137 struct sde_plane *psde;
138 u32 fixed_buff_size;
139 u32 total_fl;
140
141 if (!plane || !fmt) {
142 SDE_ERROR("invalid arguments\n");
143 return 0;
144 }
145
146 psde = to_sde_plane(plane);
147 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
148
149 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
150 if (fmt->chroma_sample == SDE_CHROMA_420) {
151 /* NV12 */
152 total_fl = (fixed_buff_size / 2) /
153 ((src_width + 32) * fmt->bpp);
154 } else {
155 /* non NV12 */
156 total_fl = (fixed_buff_size) /
157 ((src_width + 32) * fmt->bpp);
158 }
159 } else {
160 total_fl = (fixed_buff_size * 2) /
161 ((src_width + 32) * fmt->bpp);
162 }
163
164 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
165 plane->base.id, psde->pipe - SSPP_VIG0,
166 fmt->base.pixel_format, src_width, total_fl);
167
168 return total_fl;
169}
170
171/**
172 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
173 * @total_fl: fill level
174 * Return: LUT setting corresponding to the fill level
175 */
176static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
177{
178 u32 qos_lut;
179
180 if (total_fl <= 4)
181 qos_lut = 0x1B;
182 else if (total_fl <= 5)
183 qos_lut = 0x5B;
184 else if (total_fl <= 6)
185 qos_lut = 0x15B;
186 else if (total_fl <= 7)
187 qos_lut = 0x55B;
188 else if (total_fl <= 8)
189 qos_lut = 0x155B;
190 else if (total_fl <= 9)
191 qos_lut = 0x555B;
192 else if (total_fl <= 10)
193 qos_lut = 0x1555B;
194 else if (total_fl <= 11)
195 qos_lut = 0x5555B;
196 else if (total_fl <= 12)
197 qos_lut = 0x15555B;
198 else
199 qos_lut = 0x55555B;
200
201 return qos_lut;
202}
203
204/**
205 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
206 * @total_fl: fill level
207 * Return: LUT setting corresponding to the fill level
208 */
209static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
210{
211 u32 qos_lut;
212
213 if (total_fl <= 10)
214 qos_lut = 0x1AAff;
215 else if (total_fl <= 11)
216 qos_lut = 0x5AAFF;
217 else if (total_fl <= 12)
218 qos_lut = 0x15AAFF;
219 else
220 qos_lut = 0x55AAFF;
221
222 return qos_lut;
223}
224
225/**
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400226 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
227 * @plane: Pointer to drm plane
228 * @fb: Pointer to framebuffer associated with the given plane
229 */
230static void _sde_plane_set_qos_lut(struct drm_plane *plane,
231 struct drm_framebuffer *fb)
232{
233 struct sde_plane *psde;
234 const struct sde_format *fmt = NULL;
235 u32 qos_lut;
236 u32 total_fl = 0;
237
238 if (!plane || !fb) {
239 SDE_ERROR("invalid arguments plane %d fb %d\n",
240 plane != 0, fb != 0);
241 return;
242 }
243
244 psde = to_sde_plane(plane);
245
246 if (!psde->pipe_hw || !psde->pipe_sblk) {
247 SDE_ERROR("invalid arguments\n");
248 return;
249 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
250 return;
251 }
252
253 if (!psde->is_rt_pipe) {
254 qos_lut = psde->pipe_sblk->creq_lut_nrt;
255 } else {
256 fmt = sde_get_sde_format_ext(
257 fb->pixel_format,
258 fb->modifier,
259 drm_format_num_planes(fb->pixel_format));
260 total_fl = _sde_plane_calc_fill_level(plane, fmt,
261 psde->pipe_cfg.src_rect.w);
262
263 if (SDE_FORMAT_IS_LINEAR(fmt))
264 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
265 else
266 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
267 }
268
269 psde->pipe_qos_cfg.creq_lut = qos_lut;
270
271 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
272 (fmt) ? fmt->base.pixel_format : 0,
273 psde->is_rt_pipe, total_fl, qos_lut,
274 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
275
276 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
277 plane->base.id,
278 psde->pipe - SSPP_VIG0,
279 (fmt) ? fmt->base.pixel_format : 0,
280 psde->is_rt_pipe, total_fl, qos_lut);
281
282 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
283}
284
285/**
286 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
287 * @plane: Pointer to drm plane
288 * @fb: Pointer to framebuffer associated with the given plane
289 */
290static void _sde_plane_set_danger_lut(struct drm_plane *plane,
291 struct drm_framebuffer *fb)
292{
293 struct sde_plane *psde;
294 const struct sde_format *fmt = NULL;
295 u32 danger_lut, safe_lut;
296
297 if (!plane || !fb) {
298 SDE_ERROR("invalid arguments\n");
299 return;
300 }
301
302 psde = to_sde_plane(plane);
303
304 if (!psde->pipe_hw || !psde->pipe_sblk) {
305 SDE_ERROR("invalid arguments\n");
306 return;
307 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
308 return;
309 }
310
311 if (!psde->is_rt_pipe) {
312 danger_lut = psde->pipe_sblk->danger_lut_nrt;
313 safe_lut = psde->pipe_sblk->safe_lut_nrt;
314 } else {
315 fmt = sde_get_sde_format_ext(
316 fb->pixel_format,
317 fb->modifier,
318 drm_format_num_planes(fb->pixel_format));
319
320 if (SDE_FORMAT_IS_LINEAR(fmt)) {
321 danger_lut = psde->pipe_sblk->danger_lut_linear;
322 safe_lut = psde->pipe_sblk->safe_lut_linear;
323 } else {
324 danger_lut = psde->pipe_sblk->danger_lut_tile;
325 safe_lut = psde->pipe_sblk->safe_lut_tile;
326 }
327 }
328
329 psde->pipe_qos_cfg.danger_lut = danger_lut;
330 psde->pipe_qos_cfg.safe_lut = safe_lut;
331
332 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
333 (fmt) ? fmt->base.pixel_format : 0,
334 (fmt) ? fmt->fetch_mode : 0,
335 psde->pipe_qos_cfg.danger_lut,
336 psde->pipe_qos_cfg.safe_lut);
337
338 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
339 plane->base.id,
340 psde->pipe - SSPP_VIG0,
341 fmt ? fmt->base.pixel_format : 0,
342 fmt ? fmt->fetch_mode : -1,
343 psde->pipe_qos_cfg.danger_lut,
344 psde->pipe_qos_cfg.safe_lut);
345
346 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
347 &psde->pipe_qos_cfg);
348}
349
350/**
351 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
352 * @plane: Pointer to drm plane
353 * @enable: true to enable QoS control
354 * @flags: QoS control mode (enum sde_plane_qos)
355 */
356static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
357 bool enable, u32 flags)
358{
359 struct sde_plane *psde;
360
361 if (!plane) {
362 SDE_ERROR("invalid arguments\n");
363 return;
364 }
365
366 psde = to_sde_plane(plane);
367
368 if (!psde->pipe_hw || !psde->pipe_sblk) {
369 SDE_ERROR("invalid arguments\n");
370 return;
371 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
372 return;
373 }
374
375 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
376 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
377 psde->pipe_qos_cfg.danger_vblank =
378 psde->pipe_sblk->danger_vblank;
379 psde->pipe_qos_cfg.vblank_en = enable;
380 }
381
382 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
383 /* this feature overrules previous VBLANK_CTRL */
384 psde->pipe_qos_cfg.vblank_en = false;
385 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
386 }
387
388 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
389 psde->pipe_qos_cfg.danger_safe_en = enable;
390
391 if (!psde->is_rt_pipe) {
392 psde->pipe_qos_cfg.vblank_en = false;
393 psde->pipe_qos_cfg.danger_safe_en = false;
394 }
395
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400396 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400397 plane->base.id,
398 psde->pipe - SSPP_VIG0,
399 psde->pipe_qos_cfg.danger_safe_en,
400 psde->pipe_qos_cfg.vblank_en,
401 psde->pipe_qos_cfg.creq_vblank,
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400402 psde->pipe_qos_cfg.danger_vblank,
403 psde->is_rt_pipe);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400404
405 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
406 &psde->pipe_qos_cfg);
407}
408
Alan Kwong5d324e42016-07-28 22:56:18 -0400409/**
410 * _sde_plane_set_ot_limit - set OT limit for the given plane
411 * @plane: Pointer to drm plane
412 * @crtc: Pointer to drm crtc
413 */
414static void _sde_plane_set_ot_limit(struct drm_plane *plane,
415 struct drm_crtc *crtc)
416{
417 struct sde_plane *psde;
418 struct sde_vbif_set_ot_params ot_params;
419 struct msm_drm_private *priv;
420 struct sde_kms *sde_kms;
421
422 if (!plane || !plane->dev || !crtc) {
423 SDE_ERROR("invalid arguments plane %d crtc %d\n",
424 plane != 0, crtc != 0);
425 return;
426 }
427
428 priv = plane->dev->dev_private;
429 if (!priv || !priv->kms) {
430 SDE_ERROR("invalid KMS reference\n");
431 return;
432 }
433
434 sde_kms = to_sde_kms(priv->kms);
435 psde = to_sde_plane(plane);
436 if (!psde->pipe_hw) {
437 SDE_ERROR("invalid pipe reference\n");
438 return;
439 }
440
441 memset(&ot_params, 0, sizeof(ot_params));
442 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
443 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
444 ot_params.width = psde->pipe_cfg.src_rect.w;
445 ot_params.height = psde->pipe_cfg.src_rect.h;
446 ot_params.is_wfd = !psde->is_rt_pipe;
447 ot_params.frame_rate = crtc->mode.vrefresh;
448 ot_params.vbif_idx = VBIF_RT;
449 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
450 ot_params.rd = true;
451
452 sde_vbif_set_ot_limit(sde_kms, &ot_params);
453}
454
Clarence Ipcae1bb62016-07-07 12:07:13 -0400455/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400456static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400457 struct sde_plane_state *pstate, uint64_t fd)
458{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400459 if (!psde || !pstate) {
460 SDE_ERROR("invalid arg(s), plane %d state %d\n",
461 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400462 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400463 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400464
465 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400466 if (pstate->input_fence)
467 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400468
469 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400470 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400471
Clarence Ip13a8cf42016-09-29 17:27:47 -0400472 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400473}
474
Clarence Ipcae1bb62016-07-07 12:07:13 -0400475int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400476{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400477 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400478 struct sde_plane_state *pstate;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400479 uint32_t prefix;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400480 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400481 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400482
483 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700484 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400485 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400486 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400487 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400488 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400489 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400490 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400491
Clarence Ipcae1bb62016-07-07 12:07:13 -0400492 if (input_fence) {
Clarence Ip78a04ed2016-10-04 15:57:45 -0400493 prefix = sde_sync_get_name_prefix(input_fence);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400494 ret = sde_sync_wait(input_fence, wait_ms);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400495
Lloyd Atkinson5d40d312016-09-06 08:34:13 -0400496 SDE_EVT32(DRMID(plane), -ret, prefix);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400497
Clarence Ipcae1bb62016-07-07 12:07:13 -0400498 switch (ret) {
499 case 0:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400500 SDE_DEBUG_PLANE(psde, "signaled\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400501 break;
502 case -ETIME:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400503 SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
504 wait_ms, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400505 psde->is_error = true;
506 break;
507 default:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400508 SDE_ERROR_PLANE(psde, "error %d on %08X\n",
509 ret, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400510 psde->is_error = true;
511 break;
512 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400513 } else {
514 ret = 0;
515 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400516 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400517 return ret;
518}
519
Clarence Ip282dad62016-09-27 17:07:35 -0400520static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400521 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400522 struct sde_hw_pipe_cfg *pipe_cfg,
523 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400524{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400525 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400526 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400527
Clarence Ip13a8cf42016-09-29 17:27:47 -0400528 if (!plane || !pstate || !pipe_cfg || !fb) {
529 SDE_ERROR(
530 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
531 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400532 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400533 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400534
535 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400536 if (!psde->pipe_hw) {
537 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400538 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400539 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400540
Clarence Ipb6eb2362016-09-08 16:18:13 -0400541 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
542 if (ret == -EAGAIN)
543 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
544 else if (ret)
545 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
546 else if (psde->pipe_hw->ops.setup_sourceaddress)
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400547 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400548}
549
abeykun48f407a2016-08-25 12:06:44 -0400550static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
551 struct sde_plane_state *pstate)
552{
553 struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg;
554 int ret = 0;
555
556 cfg->dir_lut = msm_property_get_blob(
557 &psde->property_info,
558 pstate->property_blobs, &cfg->dir_len,
559 PLANE_PROP_SCALER_LUT_ED);
560 cfg->cir_lut = msm_property_get_blob(
561 &psde->property_info,
562 pstate->property_blobs, &cfg->cir_len,
563 PLANE_PROP_SCALER_LUT_CIR);
564 cfg->sep_lut = msm_property_get_blob(
565 &psde->property_info,
566 pstate->property_blobs, &cfg->sep_len,
567 PLANE_PROP_SCALER_LUT_SEP);
568 if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
569 ret = -ENODATA;
570 return ret;
571}
572
Clarence Ipcb410d42016-06-26 22:52:33 -0400573static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400574 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
575 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400576 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400577 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
578{
579}
580
Clarence Ipcb410d42016-06-26 22:52:33 -0400581/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400582 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400583 * @psde: Pointer to SDE plane object
584 * @src: Source size
585 * @dst: Destination size
586 * @phase_steps: Pointer to output array for phase steps
587 * @filter: Pointer to output array for filter type
588 * @fmt: Pointer to format definition
589 * @chroma_subsampling: Subsampling amount for chroma channel
590 *
591 * Returns: 0 on success
592 */
593static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400594 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400595 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400596 uint32_t chroma_subsampling)
597{
Clarence Ipcb410d42016-06-26 22:52:33 -0400598 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400599 SDE_ERROR(
600 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
601 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400602 return -EINVAL;
603 }
604
Clarence Ip4c1d9772016-06-26 09:35:38 -0400605 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400606 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400607 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400608 phase_steps[SDE_SSPP_COMP_1_2] =
609 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
610 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
611 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400612
613 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400614 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400615 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400616 (src <= dst) ? SDE_SCALE_FILTER_BIL :
617 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400618
Clarence Ipdbde9832016-06-26 09:48:36 -0400619 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400620 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400621 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
622 } else {
623 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
624 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400625 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400626 }
627 } else {
628 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400629 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
630 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
631 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400632 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400633 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400634}
635
Clarence Ipcb410d42016-06-26 22:52:33 -0400636/**
637 * _sde_plane_setup_pixel_ext - determine default pixel extension values
638 * @psde: Pointer to SDE plane object
639 * @src: Source size
640 * @dst: Destination size
641 * @decimated_src: Source size after decimation, if any
642 * @phase_steps: Pointer to output array for phase steps
643 * @out_src: Output array for pixel extension values
644 * @out_edge1: Output array for pixel extension first edge
645 * @out_edge2: Output array for pixel extension second edge
646 * @filter: Pointer to array for filter type
647 * @fmt: Pointer to format definition
648 * @chroma_subsampling: Subsampling amount for chroma channel
649 * @post_compare: Whether to chroma subsampled source size for comparisions
650 */
651static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400652 uint32_t src, uint32_t dst, uint32_t decimated_src,
653 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400654 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400655 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400656 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400657{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400658 int64_t edge1, edge2, caf;
659 uint32_t src_work;
660 int i, tmp;
661
Clarence Ipcb410d42016-06-26 22:52:33 -0400662 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400663 out_edge2 && filter && fmt) {
664 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400665 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400666 caf = PHASE_STEP_UNIT_SCALE;
667 else
668 caf = 0;
669
670 for (i = 0; i < SDE_MAX_PLANES; i++) {
671 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400672 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400673 src_work /= chroma_subsampling;
674 if (post_compare)
675 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400676 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400677 /* unity */
678 edge1 = 0;
679 edge2 = 0;
680 } else if (dst >= src) {
681 /* upscale */
682 edge1 = (1 << PHASE_RESIDUAL);
683 edge1 -= caf;
684 edge2 = (1 << PHASE_RESIDUAL);
685 edge2 += (dst - 1) * *(phase_steps + i);
686 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
687 edge2 += caf;
688 edge2 = -(edge2);
689 } else {
690 /* downscale */
691 edge1 = 0;
692 edge2 = (dst - 1) * *(phase_steps + i);
693 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
694 edge2 += *(phase_steps + i);
695 edge2 = -(edge2);
696 }
697
698 /* only enable CAF for luma plane */
699 caf = 0;
700
701 /* populate output arrays */
702 *(out_src + i) = src_work;
703
704 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400705 if (edge1 >= 0) {
706 tmp = (uint32_t)edge1;
707 tmp >>= PHASE_STEP_SHIFT;
708 *(out_edge1 + i) = -tmp;
709 } else {
710 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400711 *(out_edge1 + i) =
712 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
713 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400714 }
715 if (edge2 >= 0) {
716 tmp = (uint32_t)edge2;
717 tmp >>= PHASE_STEP_SHIFT;
718 *(out_edge2 + i) = -tmp;
719 } else {
720 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400721 *(out_edge2 + i) =
722 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
723 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400724 }
725 }
726 }
727}
728
Clarence Ip5fc00c52016-09-23 15:03:34 -0400729static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400730{
731 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
732 {
Clarence Ip373f8592016-05-26 00:58:42 -0400733 /* S15.16 format */
734 0x00012A00, 0x00000000, 0x00019880,
735 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
736 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400737 },
Clarence Ip373f8592016-05-26 00:58:42 -0400738 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400739 { 0xfff0, 0xff80, 0xff80,},
740 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400741 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400742 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400743 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400744 };
abeykun1c312f62016-08-26 09:47:12 -0400745 static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
746 {
747 /* S15.16 format */
748 0x00012A00, 0x00000000, 0x00019880,
749 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
750 0x00012A00, 0x00020480, 0x00000000,
751 },
752 /* signed bias */
753 { 0xffc0, 0xfe00, 0xfe00,},
754 { 0x0, 0x0, 0x0,},
755 /* unsigned clamp */
756 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
757 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
758 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400759
Clarence Ip5fc00c52016-09-23 15:03:34 -0400760 if (!psde) {
761 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400762 return;
763 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400764
Clarence Ipcae1bb62016-07-07 12:07:13 -0400765 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400766 if (psde->csc_usr_ptr)
767 psde->csc_ptr = psde->csc_usr_ptr;
abeykun1c312f62016-08-26 09:47:12 -0400768 else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
769 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400770 else
Clarence Ip373f8592016-05-26 00:58:42 -0400771 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400772
Clarence Ip13a8cf42016-09-29 17:27:47 -0400773 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400774 psde->csc_ptr->csc_mv[0],
775 psde->csc_ptr->csc_mv[1],
776 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400777}
778
Benet Clarkeb1b4462016-06-27 14:43:06 -0700779static void sde_color_process_plane_setup(struct drm_plane *plane)
780{
781 struct sde_plane *psde;
782 struct sde_plane_state *pstate;
783 uint32_t hue, saturation, value, contrast;
Benet Clarkd009b1d2016-06-27 14:45:59 -0700784 struct drm_msm_memcol *memcol = NULL;
785 size_t memcol_sz = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -0700786
787 psde = to_sde_plane(plane);
788 pstate = to_sde_plane_state(plane->state);
789
790 hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
791 if (psde->pipe_hw->ops.setup_pa_hue)
792 psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
793 saturation = (uint32_t) sde_plane_get_property(pstate,
794 PLANE_PROP_SATURATION_ADJUST);
795 if (psde->pipe_hw->ops.setup_pa_sat)
796 psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
797 value = (uint32_t) sde_plane_get_property(pstate,
798 PLANE_PROP_VALUE_ADJUST);
799 if (psde->pipe_hw->ops.setup_pa_val)
800 psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
801 contrast = (uint32_t) sde_plane_get_property(pstate,
802 PLANE_PROP_CONTRAST_ADJUST);
803 if (psde->pipe_hw->ops.setup_pa_cont)
804 psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
Benet Clarkeb1b4462016-06-27 14:43:06 -0700805
Benet Clarkd009b1d2016-06-27 14:45:59 -0700806 if (psde->pipe_hw->ops.setup_pa_memcolor) {
807 /* Skin memory color setup */
808 memcol = msm_property_get_blob(&psde->property_info,
809 pstate->property_blobs,
810 &memcol_sz,
811 PLANE_PROP_SKIN_COLOR);
812 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
813 MEMCOLOR_SKIN, memcol);
814
815 /* Sky memory color setup */
816 memcol = msm_property_get_blob(&psde->property_info,
817 pstate->property_blobs,
818 &memcol_sz,
819 PLANE_PROP_SKY_COLOR);
820 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
821 MEMCOLOR_SKY, memcol);
822
823 /* Foliage memory color setup */
824 memcol = msm_property_get_blob(&psde->property_info,
825 pstate->property_blobs,
826 &memcol_sz,
827 PLANE_PROP_FOLIAGE_COLOR);
828 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
829 MEMCOLOR_FOLIAGE, memcol);
830 }
831}
Benet Clarkeb1b4462016-06-27 14:43:06 -0700832
Clarence Ipcb410d42016-06-26 22:52:33 -0400833static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400834 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400835 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700836{
Clarence Ipb43d4592016-09-08 14:21:35 -0400837 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -0400838 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400839
Clarence Ipb43d4592016-09-08 14:21:35 -0400840 if (!psde || !fmt) {
841 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
842 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400843 return;
Clarence Ipb43d4592016-09-08 14:21:35 -0400844 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400845
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400846 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400847
Clarence Ipdedbba92016-09-27 17:43:10 -0400848 psde->pipe_cfg.horz_decimation =
849 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
850 psde->pipe_cfg.vert_decimation =
851 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400852
853 /* don't chroma subsample if decimating */
854 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400855 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400856 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400857 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400858
Clarence Ip5e2a9222016-06-26 22:38:24 -0400859 /* update scaler */
860 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
abeykun48f407a2016-08-25 12:06:44 -0400861 int error;
862
863 error = _sde_plane_setup_scaler3_lut(psde, pstate);
864 if (error || !psde->pixel_ext_usr) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400865 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -0400866 _sde_plane_setup_scaler3(psde,
867 psde->pipe_cfg.src_rect.w,
868 psde->pipe_cfg.src_rect.h,
869 psde->pipe_cfg.dst_rect.w,
870 psde->pipe_cfg.dst_rect.h,
abeykun48f407a2016-08-25 12:06:44 -0400871 psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400872 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400873 }
Clarence Ipb43d4592016-09-08 14:21:35 -0400874 } else if (!psde->pixel_ext_usr) {
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500875 uint32_t deci_dim, i;
876
Clarence Ipb43d4592016-09-08 14:21:35 -0400877 /* calculate default configuration for QSEED2 */
878 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400879
Clarence Ip13a8cf42016-09-29 17:27:47 -0400880 SDE_DEBUG_PLANE(psde, "default config\n");
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500881 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
882 psde->pipe_cfg.horz_decimation);
Clarence Ipb43d4592016-09-08 14:21:35 -0400883 _sde_plane_setup_scaler2(psde,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500884 deci_dim,
Clarence Ipb43d4592016-09-08 14:21:35 -0400885 psde->pipe_cfg.dst_rect.w,
886 pe->phase_step_x,
887 pe->horz_filter, fmt, chroma_subsmpl_h);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400888
Clarence Ipdbde9832016-06-26 09:48:36 -0400889 if (SDE_FORMAT_IS_YUV(fmt))
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500890 deci_dim &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400891 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500892 psde->pipe_cfg.dst_rect.w, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400893 pe->phase_step_x,
894 pe->roi_w,
895 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400896 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400897 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400898
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500899 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400900 psde->pipe_cfg.vert_decimation);
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500901 _sde_plane_setup_scaler2(psde,
902 deci_dim,
903 psde->pipe_cfg.dst_rect.h,
904 pe->phase_step_y,
905 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ipcb410d42016-06-26 22:52:33 -0400906 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500907 psde->pipe_cfg.dst_rect.h, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400908 pe->phase_step_y,
909 pe->roi_h,
910 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400911 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400912 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400913
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400914 for (i = 0; i < SDE_MAX_PLANES; i++) {
915 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400916 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400917 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400918 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400919
920 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400921 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400922 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400923 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400924
925 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400926 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400927 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400928 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400929
930 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400931 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400932 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400933 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400934 }
935 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400936}
937
Clarence Ipcae1bb62016-07-07 12:07:13 -0400938/**
939 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -0400940 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -0400941 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
942 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
943 * Returns: 0 on success
944 */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400945static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -0400946 uint32_t color, uint32_t alpha)
947{
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400948 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400949
Clarence Ip13a8cf42016-09-29 17:27:47 -0400950 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700951 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400952 return -EINVAL;
953 }
954
Clarence Ipcb410d42016-06-26 22:52:33 -0400955 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400956 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400957 return -EINVAL;
958 }
959
Clarence Ip13a8cf42016-09-29 17:27:47 -0400960 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400961
Clarence Ipcb410d42016-06-26 22:52:33 -0400962 /*
963 * select fill format to match user property expectation,
964 * h/w only supports RGB variants
965 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400966 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400967
968 /* update sspp */
969 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
970 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
971 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
972
973 /* override scaler/decimation if solid fill */
974 psde->pipe_cfg.src_rect.x = 0;
975 psde->pipe_cfg.src_rect.y = 0;
976 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
977 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
978
979 _sde_plane_setup_scaler(psde, fmt, 0);
980
981 if (psde->pipe_hw->ops.setup_format)
982 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
983 fmt, SDE_SSPP_SOLID_FILL);
984
985 if (psde->pipe_hw->ops.setup_rects)
986 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
abeykun48f407a2016-08-25 12:06:44 -0400987 &psde->pipe_cfg, &psde->pixel_ext,
988 psde->scaler3_cfg);
Clarence Ipcb410d42016-06-26 22:52:33 -0400989 }
990
991 return 0;
992}
993
994static int _sde_plane_mode_set(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -0700995 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -0400996{
Clarence Ipc47a0692016-10-11 10:54:17 -0400997 uint32_t nplanes, src_flags;
Clarence Ipcb410d42016-06-26 22:52:33 -0400998 struct sde_plane *psde;
999 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001000 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001001 struct drm_crtc *crtc;
1002 struct drm_framebuffer *fb;
1003 struct sde_rect src, dst;
1004 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001005 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -04001006
Clarence Ip13a8cf42016-09-29 17:27:47 -04001007 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -04001008 SDE_ERROR("invalid plane\n");
1009 return -EINVAL;
1010 } else if (!plane->state) {
1011 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001012 return -EINVAL;
1013 }
1014
1015 psde = to_sde_plane(plane);
1016 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -04001017
Dhaval Patel47302cf2016-08-18 15:04:28 -07001018 crtc = state->crtc;
1019 fb = state->fb;
1020 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001021 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
1022 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -07001023 return -EINVAL;
1024 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001025 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001026 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -04001027
Clarence Ip282dad62016-09-27 17:07:35 -04001028 /* determine what needs to be refreshed */
1029 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
1030 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -04001031 case PLANE_PROP_SCALER_V1:
abeykun48f407a2016-08-25 12:06:44 -04001032 case PLANE_PROP_SCALER_V2:
Clarence Ipdedbba92016-09-27 17:43:10 -04001033 case PLANE_PROP_H_DECIMATE:
1034 case PLANE_PROP_V_DECIMATE:
1035 case PLANE_PROP_SRC_CONFIG:
1036 case PLANE_PROP_ZPOS:
Clarence Ip282dad62016-09-27 17:07:35 -04001037 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1038 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001039 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04001040 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
1041 break;
1042 case PLANE_PROP_COLOR_FILL:
1043 /* potentially need to refresh everything */
1044 pstate->dirty = SDE_PLANE_DIRTY_ALL;
1045 break;
1046 case PLANE_PROP_ROTATION:
1047 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
1048 break;
Clarence Ip282dad62016-09-27 17:07:35 -04001049 case PLANE_PROP_INFO:
1050 case PLANE_PROP_ALPHA:
1051 case PLANE_PROP_INPUT_FENCE:
1052 case PLANE_PROP_BLEND_OP:
1053 /* no special action required */
1054 break;
1055 default:
1056 /* unknown property, refresh everything */
1057 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
1058 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
1059 break;
1060 }
Clarence Ipcb410d42016-06-26 22:52:33 -04001061 }
1062
Clarence Ip282dad62016-09-27 17:07:35 -04001063 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
1064 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -04001065
1066 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
1067
Clarence Ip282dad62016-09-27 17:07:35 -04001068 /* early out if nothing dirty */
1069 if (!pstate->dirty)
1070 return 0;
1071 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001072
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001073 psde->is_rt_pipe = sde_crtc_is_rt(crtc);
Clarence Ip282dad62016-09-27 17:07:35 -04001074 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1075
1076 /* update roi config */
1077 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
1078 POPULATE_RECT(&src, state->src_x, state->src_y,
1079 state->src_w, state->src_h, q16_data);
1080 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
1081 state->crtc_w, state->crtc_h, !q16_data);
1082
Clarence Ip13a8cf42016-09-29 17:27:47 -04001083 SDE_DEBUG_PLANE(psde,
1084 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001085 fb->base.id, src.x, src.y, src.w, src.h,
1086 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
1087 drm_get_format_name(fmt->base.pixel_format),
1088 SDE_FORMAT_IS_UBWC(fmt));
1089
1090 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
1091 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001092 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001093 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
1094 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
1095 src.h /= 2;
1096 src.y = DIV_ROUND_UP(src.y, 2);
1097 src.y &= ~0x1;
1098 }
1099
1100 psde->pipe_cfg.src_rect = src;
1101 psde->pipe_cfg.dst_rect = dst;
1102
1103 /* check for color fill */
1104 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
1105 PLANE_PROP_COLOR_FILL);
1106 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
1107 /* skip remaining processing on color fill */
1108 pstate->dirty = 0x0;
1109 } else if (psde->pipe_hw->ops.setup_rects) {
1110 _sde_plane_setup_scaler(psde, fmt, pstate);
1111
Clarence Ip282dad62016-09-27 17:07:35 -04001112 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
abeykun48f407a2016-08-25 12:06:44 -04001113 &psde->pipe_cfg, &psde->pixel_ext,
1114 psde->scaler3_cfg);
Clarence Ip282dad62016-09-27 17:07:35 -04001115 }
Dhaval Patel48c76022016-09-01 17:51:23 -07001116 }
1117
Clarence Ip282dad62016-09-27 17:07:35 -04001118 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
1119 psde->pipe_hw->ops.setup_format) {
1120 src_flags = 0x0;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001121 SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001122 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
1123 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1124 BIT(DRM_REFLECT_X))
1125 src_flags |= SDE_SSPP_FLIP_LR;
1126 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1127 BIT(DRM_REFLECT_Y))
1128 src_flags |= SDE_SSPP_FLIP_UD;
1129
1130 /* update format */
1131 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags);
1132
1133 /* update csc */
1134 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04001135 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04001136 else
1137 psde->csc_ptr = 0;
1138 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001139
Benet Clarkeb1b4462016-06-27 14:43:06 -07001140 sde_color_process_plane_setup(plane);
1141
Clarence Ipe78efb72016-06-24 18:35:21 -04001142 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04001143 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
1144 psde->pipe_hw->ops.setup_sharpening) {
1145 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
1146 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
1147 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
1148 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04001149
Clarence Ipe78efb72016-06-24 18:35:21 -04001150 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04001151 &psde->sharp_cfg);
1152 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001153
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001154 _sde_plane_set_qos_lut(plane, fb);
1155 _sde_plane_set_danger_lut(plane, fb);
1156
Alan Kwong5d324e42016-07-28 22:56:18 -04001157 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001158 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04001159 _sde_plane_set_ot_limit(plane, crtc);
1160 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001161
Clarence Ip282dad62016-09-27 17:07:35 -04001162 /* clear dirty */
1163 pstate->dirty = 0x0;
1164
Clarence Ip5e2a9222016-06-26 22:38:24 -04001165 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001166}
1167
1168static int sde_plane_prepare_fb(struct drm_plane *plane,
1169 const struct drm_plane_state *new_state)
1170{
1171 struct drm_framebuffer *fb = new_state->fb;
1172 struct sde_plane *psde = to_sde_plane(plane);
1173
1174 if (!new_state->fb)
1175 return 0;
1176
Clarence Ip13a8cf42016-09-29 17:27:47 -04001177 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001178 return msm_framebuffer_prepare(fb, psde->mmu_id);
1179}
1180
1181static void sde_plane_cleanup_fb(struct drm_plane *plane,
1182 const struct drm_plane_state *old_state)
1183{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001184 struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
1185 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001186
1187 if (!fb)
1188 return;
1189
Clarence Ip13a8cf42016-09-29 17:27:47 -04001190 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001191 msm_framebuffer_cleanup(fb, psde->mmu_id);
1192}
1193
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001194static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
1195 struct drm_plane_state *state,
1196 struct drm_plane_state *old_state)
1197{
1198 struct sde_plane_state *pstate = to_sde_plane_state(state);
1199
Dhaval Patel47302cf2016-08-18 15:04:28 -07001200 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04001201 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001202 return;
1203
Clarence Ip282dad62016-09-27 17:07:35 -04001204 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
1205 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001206 SDE_DEBUG_PLANE(psde,
1207 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001208 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001209 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001210 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001211 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001212 } else if (state->src_w != old_state->src_w ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07001213 state->src_h != old_state->src_h ||
1214 state->src_x != old_state->src_x ||
1215 state->src_y != old_state->src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001216 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001217 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001218 } else if (state->crtc_w != old_state->crtc_w ||
1219 state->crtc_h != old_state->crtc_h ||
1220 state->crtc_x != old_state->crtc_x ||
1221 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001222 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001223 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1224 }
1225
1226 if (!state->fb || !old_state->fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001227 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001228 } else if (state->fb->pixel_format != old_state->fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001229 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001230 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001231 } else {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001232 uint64_t *new_mods = state->fb->modifier;
1233 uint64_t *old_mods = old_state->fb->modifier;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001234 uint32_t *new_pitches = state->fb->pitches;
1235 uint32_t *old_pitches = old_state->fb->pitches;
1236 uint32_t *new_offset = state->fb->offsets;
1237 uint32_t *old_offset = old_state->fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001238 int i;
1239
1240 for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
1241 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001242 SDE_DEBUG_PLANE(psde,
1243 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001244 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001245 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001246 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1247 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001248 break;
1249 }
1250 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001251 for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
1252 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001253 SDE_DEBUG_PLANE(psde,
1254 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001255 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001256 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001257 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001258 break;
1259 }
1260 }
Dhaval Patel47302cf2016-08-18 15:04:28 -07001261 for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
1262 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001263 SDE_DEBUG_PLANE(psde,
1264 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001265 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001266 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001267 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1268 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001269 break;
1270 }
1271 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001272 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001273}
1274
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001275static int sde_plane_atomic_check(struct drm_plane *plane,
1276 struct drm_plane_state *state)
1277{
Clarence Ipdedbba92016-09-27 17:43:10 -04001278 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04001279 struct sde_plane *psde;
1280 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001281 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001282 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04001283 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001284 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
1285 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04001286
1287 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001288 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1289 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04001290 ret = -EINVAL;
1291 goto exit;
1292 }
1293
1294 psde = to_sde_plane(plane);
1295 pstate = to_sde_plane_state(state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001296
1297 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001298 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001299 ret = -EINVAL;
1300 goto exit;
1301 }
1302
Clarence Ipdedbba92016-09-27 17:43:10 -04001303 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1304 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04001305
1306 /* src values are in Q16 fixed point, convert to integer */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001307 POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
1308 state->src_h, q16_data);
1309 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
1310 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04001311
Dhaval Patel47302cf2016-08-18 15:04:28 -07001312 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
1313 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04001314
Dhaval Patel47302cf2016-08-18 15:04:28 -07001315 max_upscale = psde->pipe_sblk->maxupscale;
1316 max_downscale = psde->pipe_sblk->maxdwnscale;
1317 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04001318
Clarence Ip13a8cf42016-09-29 17:27:47 -04001319 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001320 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001321
Dhaval Patel47302cf2016-08-18 15:04:28 -07001322 if (!sde_plane_enabled(state))
1323 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04001324
Dhaval Patel47302cf2016-08-18 15:04:28 -07001325 fmt = to_sde_format(msm_framebuffer_format(state->fb));
1326
1327 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
1328
1329 if (SDE_FORMAT_IS_YUV(fmt) &&
1330 (!(psde->features & SDE_SSPP_SCALER) ||
abeykun1c312f62016-08-26 09:47:12 -04001331 !(psde->features & (BIT(SDE_SSPP_CSC)
1332 | BIT(SDE_SSPP_CSC_10BIT))))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001333 SDE_ERROR_PLANE(psde,
1334 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07001335 ret = -EINVAL;
1336
1337 /* check src bounds */
1338 } else if (state->fb->width > MAX_IMG_WIDTH ||
1339 state->fb->height > MAX_IMG_HEIGHT ||
1340 src.w < min_src_size || src.h < min_src_size ||
1341 CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
1342 CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001343 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001344 src.x, src.y, src.w, src.h);
1345 ret = -E2BIG;
1346
1347 /* valid yuv image */
1348 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
1349 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001350 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001351 src.x, src.y, src.w, src.h);
1352 ret = -EINVAL;
1353
1354 /* min dst support */
1355 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001356 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001357 dst.x, dst.y, dst.w, dst.h);
1358 ret = -EINVAL;
1359
1360 /* decimation validation */
1361 } else if (deci_w || deci_h) {
1362 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
1363 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001364 SDE_ERROR_PLANE(psde,
1365 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001366 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001367 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001368 SDE_ERROR_PLANE(psde,
1369 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001370 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001371 }
1372
Dhaval Patel47302cf2016-08-18 15:04:28 -07001373 } else if (!(psde->features & SDE_SSPP_SCALER) &&
1374 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001375 SDE_ERROR_PLANE(psde,
1376 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001377 src.w, src.h, dst.w, dst.h);
1378 ret = -EINVAL;
1379
1380 /* check decimated source width */
1381 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001382 SDE_ERROR_PLANE(psde,
1383 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001384 src.w, src_deci_w, max_linewidth);
1385 ret = -E2BIG;
1386
1387 /* check max scaler capability */
1388 } else if (((src_deci_w * max_upscale) < dst.w) ||
1389 ((src_deci_h * max_upscale) < dst.h) ||
1390 ((dst.w * max_downscale) < src_deci_w) ||
1391 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001392 SDE_ERROR_PLANE(psde,
1393 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001394 src_deci_w, src_deci_h, dst.w, dst.h);
1395 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001396 }
1397
Dhaval Patel47302cf2016-08-18 15:04:28 -07001398modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001399 if (!ret)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001400 _sde_plane_atomic_check_mode_changed(psde, state, plane->state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001401exit:
1402 return ret;
1403}
1404
Clarence Ipcae1bb62016-07-07 12:07:13 -04001405/**
1406 * sde_plane_flush - final plane operations before commit flush
1407 * @plane: Pointer to drm plane structure
1408 */
1409void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04001410{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001411 struct sde_plane *psde;
1412
Clarence Ip13a8cf42016-09-29 17:27:47 -04001413 if (!plane) {
1414 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001415 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001416 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04001417
1418 psde = to_sde_plane(plane);
1419
1420 /*
1421 * These updates have to be done immediately before the plane flush
1422 * timing, and may not be moved to the atomic_update/mode_set functions.
1423 */
1424 if (psde->is_error)
1425 /* force white frame with 0% alpha pipe output on error */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001426 _sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001427 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
1428 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001429 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001430 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
1431 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
1432
1433 /* flag h/w flush complete */
1434 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04001435 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001436}
1437
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001438static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001439 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001440{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001441 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001442 struct drm_plane_state *state;
1443 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001444
Clarence Ip13a8cf42016-09-29 17:27:47 -04001445 if (!plane) {
1446 SDE_ERROR("invalid plane\n");
1447 return;
1448 } else if (!plane->state) {
1449 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001450 return;
1451 }
1452
Clarence Ip13a8cf42016-09-29 17:27:47 -04001453 psde = to_sde_plane(plane);
1454 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001455 state = plane->state;
1456 pstate = to_sde_plane_state(state);
1457
Clarence Ip13a8cf42016-09-29 17:27:47 -04001458 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001459
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001460 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001461 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001462 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001463 int ret;
1464
Dhaval Patel47302cf2016-08-18 15:04:28 -07001465 ret = _sde_plane_mode_set(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001466 /* atomic_check should have ensured that this doesn't fail */
1467 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001468 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001469}
1470
Dhaval Patel47302cf2016-08-18 15:04:28 -07001471
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001472/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001473static void _sde_plane_install_properties(struct drm_plane *plane,
Clarence Ipc47a0692016-10-11 10:54:17 -04001474 struct sde_mdss_cfg *catalog)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001475{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001476 static const struct drm_prop_enum_list e_blend_op[] = {
1477 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1478 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1479 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1480 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1481 };
1482 static const struct drm_prop_enum_list e_src_config[] = {
1483 {SDE_DRM_DEINTERLACE, "deinterlace"}
1484 };
Clarence Ipea3d6262016-07-15 16:20:11 -04001485 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07001486 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001487 struct sde_plane *psde = to_sde_plane(plane);
Clarence Ipc47a0692016-10-11 10:54:17 -04001488 int zpos_max = 255;
1489 int zpos_def = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -07001490 char feature_name[256];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001491
Clarence Ip13a8cf42016-09-29 17:27:47 -04001492 if (!plane || !psde) {
1493 SDE_ERROR("invalid plane\n");
1494 return;
1495 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
1496 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
1497 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001498 return;
Clarence Ipc47a0692016-10-11 10:54:17 -04001499 } else if (!catalog) {
1500 SDE_ERROR("invalid catalog\n");
1501 return;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001502 }
1503
Clarence Ipc47a0692016-10-11 10:54:17 -04001504 if (sde_is_custom_client()) {
Clarence Ip649989a2016-10-21 14:28:34 -04001505 if (catalog->mixer_count && catalog->mixer &&
1506 catalog->mixer[0].sblk->maxblendstages) {
1507 zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
1508 if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
1509 zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
1510 }
Clarence Ipc47a0692016-10-11 10:54:17 -04001511 } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
1512 /* reserve zpos == 0 for primary planes */
1513 zpos_def = drm_plane_index(plane) + 1;
1514 }
1515
1516 msm_property_install_range(&psde->property_info, "zpos",
1517 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001518
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001519 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001520 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001521
Dhaval Patel47302cf2016-08-18 15:04:28 -07001522 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001523 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07001524 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001525
Clarence Ipdedbba92016-09-27 17:43:10 -04001526 if (psde->pipe_sblk->maxhdeciexp) {
1527 msm_property_install_range(&psde->property_info, "h_decimate",
1528 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0,
1529 PLANE_PROP_H_DECIMATE);
1530 }
1531
1532 if (psde->pipe_sblk->maxvdeciexp) {
1533 msm_property_install_range(&psde->property_info, "v_decimate",
1534 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0,
1535 PLANE_PROP_V_DECIMATE);
1536 }
1537
abeykun48f407a2016-08-25 12:06:44 -04001538 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
1539 msm_property_install_volatile_range(&psde->property_info,
1540 "scaler_v2", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
1541 msm_property_install_blob(&psde->property_info, "lut_ed", 0,
1542 PLANE_PROP_SCALER_LUT_ED);
1543 msm_property_install_blob(&psde->property_info, "lut_cir", 0,
1544 PLANE_PROP_SCALER_LUT_CIR);
1545 msm_property_install_blob(&psde->property_info, "lut_sep", 0,
1546 PLANE_PROP_SCALER_LUT_SEP);
1547 } else if (psde->features & SDE_SSPP_SCALER) {
Clarence Ipb43d4592016-09-08 14:21:35 -04001548 msm_property_install_volatile_range(&psde->property_info,
1549 "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
1550 }
1551
Clarence Ip5fc00c52016-09-23 15:03:34 -04001552 if (psde->features & BIT(SDE_SSPP_CSC)) {
1553 msm_property_install_volatile_range(&psde->property_info,
1554 "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1);
1555 }
1556
Benet Clarkeb1b4462016-06-27 14:43:06 -07001557 if (psde->features & BIT(SDE_SSPP_HSIC)) {
1558 snprintf(feature_name, sizeof(feature_name), "%s%d",
1559 "SDE_SSPP_HUE_V",
1560 psde->pipe_sblk->hsic_blk.version >> 16);
1561 msm_property_install_range(&psde->property_info,
1562 feature_name, 0, 0, 0xFFFFFFFF, 0,
1563 PLANE_PROP_HUE_ADJUST);
1564 snprintf(feature_name, sizeof(feature_name), "%s%d",
1565 "SDE_SSPP_SATURATION_V",
1566 psde->pipe_sblk->hsic_blk.version >> 16);
1567 msm_property_install_range(&psde->property_info,
1568 feature_name, 0, 0, 0xFFFFFFFF, 0,
1569 PLANE_PROP_SATURATION_ADJUST);
1570 snprintf(feature_name, sizeof(feature_name), "%s%d",
1571 "SDE_SSPP_VALUE_V",
1572 psde->pipe_sblk->hsic_blk.version >> 16);
1573 msm_property_install_range(&psde->property_info,
1574 feature_name, 0, 0, 0xFFFFFFFF, 0,
1575 PLANE_PROP_VALUE_ADJUST);
1576 snprintf(feature_name, sizeof(feature_name), "%s%d",
1577 "SDE_SSPP_CONTRAST_V",
1578 psde->pipe_sblk->hsic_blk.version >> 16);
1579 msm_property_install_range(&psde->property_info,
1580 feature_name, 0, 0, 0xFFFFFFFF, 0,
1581 PLANE_PROP_CONTRAST_ADJUST);
1582 }
1583
Clarence Ip5e2a9222016-06-26 22:38:24 -04001584 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001585 msm_property_install_rotation(&psde->property_info,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001586 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001587
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001588 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001589 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001590
Dhaval Patel47302cf2016-08-18 15:04:28 -07001591 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
1592 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
1593
1594 if (psde->pipe_hw->ops.setup_solidfill)
1595 msm_property_install_range(&psde->property_info, "color_fill",
1596 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
1597
Dhaval Patel4e574842016-08-23 15:11:37 -07001598 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001599 if (!info) {
1600 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07001601 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001602 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001603
1604 msm_property_install_blob(&psde->property_info, "capabilities",
1605 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
1606 sde_kms_info_reset(info);
1607
Clarence Ipea3d6262016-07-15 16:20:11 -04001608 format_list = psde->pipe_sblk->format_list;
1609 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04001610 sde_kms_info_start(info, "pixel_formats");
1611 while (format_list->fourcc_format) {
1612 sde_kms_info_append_format(info,
1613 format_list->fourcc_format,
1614 format_list->modifier);
1615 ++format_list;
1616 }
1617 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04001618 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001619
1620 sde_kms_info_add_keyint(info, "max_linewidth",
1621 psde->pipe_sblk->maxlinewidth);
1622 sde_kms_info_add_keyint(info, "max_upscale",
1623 psde->pipe_sblk->maxupscale);
1624 sde_kms_info_add_keyint(info, "max_downscale",
1625 psde->pipe_sblk->maxdwnscale);
1626 sde_kms_info_add_keyint(info, "max_horizontal_deci",
1627 psde->pipe_sblk->maxhdeciexp);
1628 sde_kms_info_add_keyint(info, "max_vertical_deci",
1629 psde->pipe_sblk->maxvdeciexp);
1630 msm_property_set_blob(&psde->property_info, &psde->blob_info,
1631 info->data, info->len, PLANE_PROP_INFO);
1632
1633 kfree(info);
Benet Clarkd009b1d2016-06-27 14:45:59 -07001634
1635 if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
1636 snprintf(feature_name, sizeof(feature_name), "%s%d",
1637 "SDE_SSPP_SKIN_COLOR_V",
1638 psde->pipe_sblk->memcolor_blk.version >> 16);
1639 msm_property_install_blob(&psde->property_info, feature_name, 0,
1640 PLANE_PROP_SKIN_COLOR);
1641 snprintf(feature_name, sizeof(feature_name), "%s%d",
1642 "SDE_SSPP_SKY_COLOR_V",
1643 psde->pipe_sblk->memcolor_blk.version >> 16);
1644 msm_property_install_blob(&psde->property_info, feature_name, 0,
1645 PLANE_PROP_SKY_COLOR);
1646 snprintf(feature_name, sizeof(feature_name), "%s%d",
1647 "SDE_SSPP_FOLIAGE_COLOR_V",
1648 psde->pipe_sblk->memcolor_blk.version >> 16);
1649 msm_property_install_blob(&psde->property_info, feature_name, 0,
1650 PLANE_PROP_FOLIAGE_COLOR);
1651 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001652}
1653
Clarence Ip5fc00c52016-09-23 15:03:34 -04001654static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
1655{
1656 struct sde_drm_csc_v1 csc_v1;
1657 int i;
1658
1659 if (!psde) {
1660 SDE_ERROR("invalid plane\n");
1661 return;
1662 }
1663
1664 psde->csc_usr_ptr = NULL;
1665 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001666 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001667 return;
1668 }
1669
1670 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001671 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001672 return;
1673 }
1674
Clarence Ipb43d4592016-09-08 14:21:35 -04001675 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04001676 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
1677 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
1678 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
1679 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
1680 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
1681 }
1682 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
1683 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
1684 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
1685 }
1686 psde->csc_usr_ptr = &psde->csc_cfg;
1687}
1688
Clarence Ipb43d4592016-09-08 14:21:35 -04001689static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
1690{
1691 struct sde_drm_scaler_v1 scale_v1;
1692 struct sde_hw_pixel_ext *pe;
1693 int i;
1694
1695 if (!psde) {
1696 SDE_ERROR("invalid plane\n");
1697 return;
1698 }
1699
1700 psde->pixel_ext_usr = false;
1701 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001702 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001703 return;
1704 }
1705
1706 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001707 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001708 return;
1709 }
1710
1711 /* populate from user space */
1712 pe = &(psde->pixel_ext);
1713 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1714 for (i = 0; i < SDE_MAX_PLANES; i++) {
1715 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
1716 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
1717 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
1718 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
1719
1720 pe->horz_filter[i] = scale_v1.horz_filter[i];
1721 pe->vert_filter[i] = scale_v1.vert_filter[i];
1722 }
1723 for (i = 0; i < SDE_MAX_PLANES; i++) {
1724 pe->num_ext_pxls_left[i] = scale_v1.lr.num_pxls_start[i];
1725 pe->num_ext_pxls_right[i] = scale_v1.lr.num_pxls_end[i];
1726 pe->left_ftch[i] = scale_v1.lr.ftch_start[i];
1727 pe->right_ftch[i] = scale_v1.lr.ftch_end[i];
1728 pe->left_rpt[i] = scale_v1.lr.rpt_start[i];
1729 pe->right_rpt[i] = scale_v1.lr.rpt_end[i];
1730 pe->roi_w[i] = scale_v1.lr.roi[i];
1731
1732 pe->num_ext_pxls_top[i] = scale_v1.tb.num_pxls_start[i];
1733 pe->num_ext_pxls_btm[i] = scale_v1.tb.num_pxls_end[i];
1734 pe->top_ftch[i] = scale_v1.tb.ftch_start[i];
1735 pe->btm_ftch[i] = scale_v1.tb.ftch_end[i];
1736 pe->top_rpt[i] = scale_v1.tb.rpt_start[i];
1737 pe->btm_rpt[i] = scale_v1.tb.rpt_end[i];
1738 pe->roi_h[i] = scale_v1.tb.roi[i];
1739 }
1740 psde->pixel_ext_usr = true;
1741
Clarence Ip13a8cf42016-09-29 17:27:47 -04001742 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001743}
1744
abeykun48f407a2016-08-25 12:06:44 -04001745static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
1746 struct sde_plane_state *pstate, void *usr)
1747{
1748 struct sde_drm_scaler_v2 scale_v2;
1749 struct sde_hw_pixel_ext *pe;
1750 int i;
1751 struct sde_hw_scaler3_cfg *cfg;
1752
1753 if (!psde) {
1754 SDE_ERROR("invalid plane\n");
1755 return;
1756 }
1757
1758 cfg = psde->scaler3_cfg;
1759 psde->pixel_ext_usr = false;
1760 if (!usr) {
1761 SDE_DEBUG_PLANE(psde, "scale data removed\n");
1762 return;
1763 }
1764
1765 if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
1766 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
1767 return;
1768 }
1769
1770 /* populate from user space */
1771 pe = &(psde->pixel_ext);
1772 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1773 cfg->enable = scale_v2.enable;
1774 cfg->dir_en = scale_v2.dir_en;
1775 for (i = 0; i < SDE_MAX_PLANES; i++) {
1776 cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
1777 cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
1778 cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
1779 cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
1780
1781 cfg->preload_x[i] = scale_v2.preload_x[i];
1782 cfg->preload_y[i] = scale_v2.preload_y[i];
1783 cfg->src_width[i] = scale_v2.src_width[i];
1784 cfg->src_height[i] = scale_v2.src_height[i];
1785 }
1786 cfg->dst_width = scale_v2.dst_width;
1787 cfg->dst_height = scale_v2.dst_height;
1788
1789 cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
1790 cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
1791 cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
1792 cfg->blend_cfg = scale_v2.blend_cfg;
1793
1794 cfg->lut_flag = scale_v2.lut_flag;
1795 cfg->dir_lut_idx = scale_v2.dir_lut_idx;
1796 cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
1797 cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
1798 cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
1799 cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
1800
1801 cfg->de.enable = scale_v2.de.enable;
1802 cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
1803 cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
1804 cfg->de.clip = scale_v2.de.clip;
1805 cfg->de.limit = scale_v2.de.limit;
1806 cfg->de.thr_quiet = scale_v2.de.thr_quiet;
1807 cfg->de.thr_dieout = scale_v2.de.thr_dieout;
1808 cfg->de.thr_low = scale_v2.de.thr_low;
1809 cfg->de.thr_high = scale_v2.de.thr_high;
1810 cfg->de.prec_shift = scale_v2.de.prec_shift;
1811 for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
1812 cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
1813 cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
1814 cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
1815 }
1816 for (i = 0; i < SDE_MAX_PLANES; i++) {
1817 pe->num_ext_pxls_left[i] = scale_v2.lr.num_pxls_start[i];
1818 pe->num_ext_pxls_right[i] = scale_v2.lr.num_pxls_end[i];
1819 pe->left_ftch[i] = scale_v2.lr.ftch_start[i];
1820 pe->right_ftch[i] = scale_v2.lr.ftch_end[i];
1821 pe->left_rpt[i] = scale_v2.lr.rpt_start[i];
1822 pe->right_rpt[i] = scale_v2.lr.rpt_end[i];
1823 pe->roi_w[i] = scale_v2.lr.roi[i];
1824
1825 pe->num_ext_pxls_top[i] = scale_v2.tb.num_pxls_start[i];
1826 pe->num_ext_pxls_btm[i] = scale_v2.tb.num_pxls_end[i];
1827 pe->top_ftch[i] = scale_v2.tb.ftch_start[i];
1828 pe->btm_ftch[i] = scale_v2.tb.ftch_end[i];
1829 pe->top_rpt[i] = scale_v2.tb.rpt_start[i];
1830 pe->btm_rpt[i] = scale_v2.tb.rpt_end[i];
1831 pe->roi_h[i] = scale_v2.tb.roi[i];
1832 }
1833 psde->pixel_ext_usr = true;
1834
1835 SDE_DEBUG_PLANE(psde, "user property data copied\n");
1836}
1837
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001838static int sde_plane_atomic_set_property(struct drm_plane *plane,
1839 struct drm_plane_state *state, struct drm_property *property,
1840 uint64_t val)
1841{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001842 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001843 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001844 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001845
Clarence Ip13a8cf42016-09-29 17:27:47 -04001846 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001847
1848 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001849 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001850 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001851 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001852 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001853 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001854 ret = msm_property_atomic_set(&psde->property_info,
1855 pstate->property_values, pstate->property_blobs,
1856 property, val);
1857 if (!ret) {
1858 idx = msm_property_index(&psde->property_info,
1859 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001860 switch (idx) {
1861 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04001862 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001863 break;
1864 case PLANE_PROP_CSC_V1:
1865 _sde_plane_set_csc_v1(psde, (void *)val);
1866 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04001867 case PLANE_PROP_SCALER_V1:
1868 _sde_plane_set_scaler_v1(psde, (void *)val);
1869 break;
abeykun48f407a2016-08-25 12:06:44 -04001870 case PLANE_PROP_SCALER_V2:
1871 _sde_plane_set_scaler_v2(psde, pstate,
1872 (void *)val);
1873 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001874 default:
1875 /* nothing to do */
1876 break;
1877 }
Clarence Ipe78efb72016-06-24 18:35:21 -04001878 }
1879 }
1880
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001881 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001882}
1883
1884static int sde_plane_set_property(struct drm_plane *plane,
1885 struct drm_property *property, uint64_t val)
1886{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001887 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001888
Clarence Ipae4e60c2016-06-26 22:44:04 -04001889 return sde_plane_atomic_set_property(plane,
1890 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001891}
1892
1893static int sde_plane_atomic_get_property(struct drm_plane *plane,
1894 const struct drm_plane_state *state,
1895 struct drm_property *property, uint64_t *val)
1896{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001897 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001898 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001899 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001900
Clarence Ipaa0faf42016-05-30 12:07:48 -04001901 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001902 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001903 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001904 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001905 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001906 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001907 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001908 ret = msm_property_atomic_get(&psde->property_info,
1909 pstate->property_values, pstate->property_blobs,
1910 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001911 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001912
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001913 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001914}
1915
1916static void sde_plane_destroy(struct drm_plane *plane)
1917{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001918 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001919
Clarence Ip13a8cf42016-09-29 17:27:47 -04001920 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001921
Clarence Ip13a8cf42016-09-29 17:27:47 -04001922 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001923 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1924
Clarence Ip4ce59322016-06-26 22:27:51 -04001925 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001926
Dhaval Patel4e574842016-08-23 15:11:37 -07001927 if (psde->blob_info)
1928 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001929 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001930 mutex_destroy(&psde->lock);
1931
Clarence Ip4ce59322016-06-26 22:27:51 -04001932 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001933
Clarence Ip4ce59322016-06-26 22:27:51 -04001934 /* this will destroy the states as well */
1935 drm_plane_cleanup(plane);
1936
Clarence Ip4c1d9772016-06-26 09:35:38 -04001937 if (psde->pipe_hw)
1938 sde_hw_sspp_destroy(psde->pipe_hw);
1939
Clarence Ip4ce59322016-06-26 22:27:51 -04001940 kfree(psde);
1941 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001942}
1943
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001944static void sde_plane_destroy_state(struct drm_plane *plane,
1945 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001946{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001947 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001948 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001949
Clarence Ipae4e60c2016-06-26 22:44:04 -04001950 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001951 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1952 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001953 return;
1954 }
1955
Clarence Ipaa0faf42016-05-30 12:07:48 -04001956 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001957 pstate = to_sde_plane_state(state);
1958
Clarence Ip13a8cf42016-09-29 17:27:47 -04001959 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001960
Clarence Ipe78efb72016-06-24 18:35:21 -04001961 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001962 if (state->fb)
1963 drm_framebuffer_unreference(state->fb);
1964
Clarence Ipae4e60c2016-06-26 22:44:04 -04001965 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001966 if (pstate->input_fence)
1967 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001968
Clarence Ipaa0faf42016-05-30 12:07:48 -04001969 /* destroy value helper */
1970 msm_property_destroy_state(&psde->property_info, pstate,
1971 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001972}
1973
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001974static struct drm_plane_state *
1975sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001976{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001977 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001978 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001979 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04001980 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001981
Clarence Ip13a8cf42016-09-29 17:27:47 -04001982 if (!plane) {
1983 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001984 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001985 } else if (!plane->state) {
1986 SDE_ERROR("invalid plane state\n");
1987 return NULL;
1988 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001989
Clarence Ip730e7192016-06-26 22:45:09 -04001990 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001991 psde = to_sde_plane(plane);
1992 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001993 if (!pstate) {
1994 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001995 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001996 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001997
Clarence Ip13a8cf42016-09-29 17:27:47 -04001998 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001999
2000 /* duplicate value helper */
2001 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
2002 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04002003
Clarence Ip730e7192016-06-26 22:45:09 -04002004 /* add ref count for frame buffer */
2005 if (pstate->base.fb)
2006 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002007
Clarence Ip17e908b2016-09-29 15:58:00 -04002008 /* clear out any input fence */
2009 pstate->input_fence = 0;
2010 input_fence_default = msm_property_get_default(
2011 &psde->property_info, PLANE_PROP_INPUT_FENCE);
2012 msm_property_set_property(&psde->property_info, pstate->property_values,
2013 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002014
Clarence Ip282dad62016-09-27 17:07:35 -04002015 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04002016 pstate->pending = false;
2017
2018 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002019}
2020
2021static void sde_plane_reset(struct drm_plane *plane)
2022{
Clarence Ipae4e60c2016-06-26 22:44:04 -04002023 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002024 struct sde_plane_state *pstate;
2025
Clarence Ipae4e60c2016-06-26 22:44:04 -04002026 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002027 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04002028 return;
2029 }
2030
Clarence Ip730e7192016-06-26 22:45:09 -04002031 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04002032 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04002033
Clarence Ipae4e60c2016-06-26 22:44:04 -04002034 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04002035 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04002036 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04002037 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04002038 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002039
Clarence Ipaa0faf42016-05-30 12:07:48 -04002040 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04002041 if (!pstate) {
2042 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002043 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04002044 }
Clarence Ip730e7192016-06-26 22:45:09 -04002045
Clarence Ipaa0faf42016-05-30 12:07:48 -04002046 /* reset value helper */
2047 msm_property_reset_state(&psde->property_info, pstate,
2048 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002049
2050 pstate->base.plane = plane;
2051
2052 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002053}
2054
2055static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002056 .update_plane = drm_atomic_helper_update_plane,
2057 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002058 .destroy = sde_plane_destroy,
2059 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002060 .atomic_set_property = sde_plane_atomic_set_property,
2061 .atomic_get_property = sde_plane_atomic_get_property,
2062 .reset = sde_plane_reset,
2063 .atomic_duplicate_state = sde_plane_duplicate_state,
2064 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002065};
2066
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002067static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
2068 .prepare_fb = sde_plane_prepare_fb,
2069 .cleanup_fb = sde_plane_cleanup_fb,
2070 .atomic_check = sde_plane_atomic_check,
2071 .atomic_update = sde_plane_atomic_update,
2072};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002073
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002074enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002075{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002076 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002077}
2078
Clarence Ip4ce59322016-06-26 22:27:51 -04002079static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
2080{
2081 const struct sde_sspp_sub_blks *sblk = 0;
2082 const struct sde_sspp_cfg *cfg = 0;
2083
2084 if (psde && psde->pipe_hw)
2085 cfg = psde->pipe_hw->cap;
2086 if (cfg)
2087 sblk = cfg->sblk;
2088
2089 if (kms && sblk) {
2090 /* create overall sub-directory for the pipe */
2091 psde->debugfs_root =
2092 debugfs_create_dir(psde->pipe_name,
2093 sde_debugfs_get_root(kms));
2094 if (psde->debugfs_root) {
2095 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04002096 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04002097 psde->debugfs_root, &psde->features);
2098
2099 /* add register dump support */
2100 sde_debugfs_setup_regset32(&psde->debugfs_src,
2101 sblk->src_blk.base + cfg->base,
2102 sblk->src_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04002103 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04002104 sde_debugfs_create_regset32("src_blk", 0444,
2105 psde->debugfs_root, &psde->debugfs_src);
2106
2107 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
2108 sblk->scaler_blk.base + cfg->base,
2109 sblk->scaler_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04002110 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04002111 sde_debugfs_create_regset32("scaler_blk", 0444,
2112 psde->debugfs_root,
2113 &psde->debugfs_scaler);
2114
2115 sde_debugfs_setup_regset32(&psde->debugfs_csc,
2116 sblk->csc_blk.base + cfg->base,
2117 sblk->csc_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04002118 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04002119 sde_debugfs_create_regset32("csc_blk", 0444,
2120 psde->debugfs_root, &psde->debugfs_csc);
2121 }
2122 }
2123}
2124
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002125/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04002126struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip2bbf7b32016-09-23 15:07:16 -04002127 uint32_t pipe, bool primary_plane,
2128 unsigned long possible_crtcs)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002129{
2130 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002131 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002132 struct msm_drm_private *priv;
2133 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002134 enum drm_plane_type type;
Clarence Ipc47a0692016-10-11 10:54:17 -04002135 int ret = -EINVAL;
Clarence Ip4c1d9772016-06-26 09:35:38 -04002136
2137 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002138 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002139 goto exit;
2140 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002141
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002142 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04002143 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002144 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04002145 goto exit;
2146 }
2147
2148 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002149 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04002150 goto exit;
2151 }
2152 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002153
Clarence Ip4c1d9772016-06-26 09:35:38 -04002154 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002155 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002156 goto exit;
2157 }
2158
Clarence Ip4ce59322016-06-26 22:27:51 -04002159 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002160 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
2161 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002162 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002163 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04002164 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002165 }
2166
Clarence Ip4c1d9772016-06-26 09:35:38 -04002167 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002168 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002169 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04002170 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002171
Clarence Ip4c1d9772016-06-26 09:35:38 -04002172 /* initialize underlying h/w driver */
2173 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
2174 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002175 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002176 ret = PTR_ERR(psde->pipe_hw);
2177 goto clean_plane;
2178 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002179 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002180 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002181 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04002182
2183 /* cache features mask for later */
2184 psde->features = psde->pipe_hw->cap->features;
2185 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04002186 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002187 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04002188 goto clean_sspp;
2189 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04002190
abeykun48f407a2016-08-25 12:06:44 -04002191 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
2192 psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
2193 GFP_KERNEL);
2194 if (!psde->scaler3_cfg) {
2195 SDE_ERROR("[%u]failed to allocate scale struct\n",
2196 pipe);
2197 ret = -ENOMEM;
2198 goto clean_sspp;
2199 }
2200 }
2201
Clarence Ip4c1d9772016-06-26 09:35:38 -04002202 /* add plane to DRM framework */
Clarence Ipea3d6262016-07-15 16:20:11 -04002203 psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
2204 psde->formats,
2205 0,
2206 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002207
Clarence Ip4c1d9772016-06-26 09:35:38 -04002208 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002209 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002210 goto clean_sspp;
2211 }
2212
2213 if (psde->features & BIT(SDE_SSPP_CURSOR))
2214 type = DRM_PLANE_TYPE_CURSOR;
2215 else if (primary_plane)
2216 type = DRM_PLANE_TYPE_PRIMARY;
2217 else
2218 type = DRM_PLANE_TYPE_OVERLAY;
Clarence Ip2bbf7b32016-09-23 15:07:16 -04002219 ret = drm_universal_plane_init(dev, plane, possible_crtcs,
2220 &sde_plane_funcs, psde->formats, psde->nformats, type);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002221 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04002222 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002223
Clarence Ip4c1d9772016-06-26 09:35:38 -04002224 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002225 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002226
Clarence Ipaa0faf42016-05-30 12:07:48 -04002227 msm_property_init(&psde->property_info, &plane->base, dev,
2228 priv->plane_property, psde->property_data,
2229 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
2230 sizeof(struct sde_plane_state));
2231
Clarence Ipc47a0692016-10-11 10:54:17 -04002232 _sde_plane_install_properties(plane, kms->catalog);
Clarence Ip5e2a9222016-06-26 22:38:24 -04002233
Clarence Ip4ce59322016-06-26 22:27:51 -04002234 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04002235 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04002236
Clarence Ip730e7192016-06-26 22:45:09 -04002237 mutex_init(&psde->lock);
2238
Clarence Ip4ce59322016-06-26 22:27:51 -04002239 _sde_plane_init_debugfs(psde, kms);
2240
Clarence Ip13a8cf42016-09-29 17:27:47 -04002241 DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002242 return plane;
2243
Clarence Ip4c1d9772016-06-26 09:35:38 -04002244clean_sspp:
2245 if (psde && psde->pipe_hw)
2246 sde_hw_sspp_destroy(psde->pipe_hw);
abeykun48f407a2016-08-25 12:06:44 -04002247
2248 if (psde && psde->scaler3_cfg)
2249 kfree(psde->scaler3_cfg);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002250clean_plane:
2251 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04002252exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002253 return ERR_PTR(ret);
2254}