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Clarence Ipaac9f332016-08-31 15:46:35 -04001/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040012
13#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
Clarence Ip4ce59322016-06-26 22:27:51 -040015#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040016#include <uapi/drm/sde_drm.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040017
18#include "msm_prop.h"
19
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070020#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040021#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040022#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040023#include "sde_hw_sspp.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040024#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070025#include "sde_crtc.h"
Lloyd Atkinson8772e202016-09-26 17:52:16 -040026#include "sde_vbif.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040027
Clarence Ip13a8cf42016-09-29 17:27:47 -040028#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
29 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
30
31#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
33
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040034#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
35#define PHASE_STEP_SHIFT 21
36#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
37#define PHASE_RESIDUAL 15
38
Clarence Ipe78efb72016-06-24 18:35:21 -040039#define SHARP_STRENGTH_DEFAULT 32
40#define SHARP_EDGE_THR_DEFAULT 112
41#define SHARP_SMOOTH_THR_DEFAULT 8
42#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040043
Clarence Ip5e2a9222016-06-26 22:38:24 -040044#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070045
Clarence Ipcae1bb62016-07-07 12:07:13 -040046#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
47
Clarence Ip282dad62016-09-27 17:07:35 -040048/* dirty bits for update function */
49#define SDE_PLANE_DIRTY_RECTS 0x1
50#define SDE_PLANE_DIRTY_FORMAT 0x2
51#define SDE_PLANE_DIRTY_SHARPEN 0x4
52#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
53
Alan Kwong1a00e4d2016-07-18 09:42:30 -040054/**
55 * enum sde_plane_qos - Different qos configurations for each pipe
56 *
57 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
58 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
59 * this configuration is mutually exclusive from VBLANK_CTRL.
60 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
61 */
62enum sde_plane_qos {
63 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
64 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
65 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
66};
67
Clarence Ip5fc00c52016-09-23 15:03:34 -040068/*
69 * struct sde_plane - local sde plane structure
70 * @csc_cfg: Decoded user configuration for csc
71 * @csc_usr_ptr: Points to csc_cfg if valid user config available
72 * @csc_ptr: Points to sde_csc_cfg structure to use for current
73 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070074struct sde_plane {
75 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040076
77 int mmu_id;
78
Clarence Ip730e7192016-06-26 22:45:09 -040079 struct mutex lock;
80
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040081 enum sde_sspp pipe;
82 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070083 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -040084 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040085
86 struct sde_hw_pipe *pipe_hw;
87 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -040088 struct sde_hw_sharp_cfg sharp_cfg;
abeykun48f407a2016-08-25 12:06:44 -040089 struct sde_hw_scaler3_cfg *scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040090 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -040091 uint32_t color_fill;
92 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040093 bool is_rt_pipe;
Clarence Ip4ce59322016-06-26 22:27:51 -040094
Clarence Ipb43d4592016-09-08 14:21:35 -040095 struct sde_hw_pixel_ext pixel_ext;
96 bool pixel_ext_usr;
97
Clarence Ip373f8592016-05-26 00:58:42 -040098 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -040099 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -0400100 struct sde_csc_cfg *csc_ptr;
101
Clarence Ip4c1d9772016-06-26 09:35:38 -0400102 const struct sde_sspp_sub_blks *pipe_sblk;
103
Clarence Ip5e2a9222016-06-26 22:38:24 -0400104 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400105
Clarence Ipaa0faf42016-05-30 12:07:48 -0400106 struct msm_property_info property_info;
107 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700108 struct drm_property_blob *blob_info;
Clarence Ip730e7192016-06-26 22:45:09 -0400109
Clarence Ip4ce59322016-06-26 22:27:51 -0400110 /* debugfs related stuff */
111 struct dentry *debugfs_root;
112 struct sde_debugfs_regset32 debugfs_src;
113 struct sde_debugfs_regset32 debugfs_scaler;
114 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700115};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700116
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700117#define to_sde_plane(x) container_of(x, struct sde_plane, base)
118
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400119static bool sde_plane_enabled(struct drm_plane_state *state)
120{
Clarence Ipdbde9832016-06-26 09:48:36 -0400121 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400122}
123
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400124/**
125 * _sde_plane_calc_fill_level - calculate fill level of the given source format
126 * @plane: Pointer to drm plane
127 * @fmt: Pointer to source buffer format
128 * @src_wdith: width of source buffer
129 * Return: fill level corresponding to the source buffer/format or 0 if error
130 */
131static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
132 const struct sde_format *fmt, u32 src_width)
133{
134 struct sde_plane *psde;
135 u32 fixed_buff_size;
136 u32 total_fl;
137
138 if (!plane || !fmt) {
139 SDE_ERROR("invalid arguments\n");
140 return 0;
141 }
142
143 psde = to_sde_plane(plane);
144 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
145
146 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
147 if (fmt->chroma_sample == SDE_CHROMA_420) {
148 /* NV12 */
149 total_fl = (fixed_buff_size / 2) /
150 ((src_width + 32) * fmt->bpp);
151 } else {
152 /* non NV12 */
153 total_fl = (fixed_buff_size) /
154 ((src_width + 32) * fmt->bpp);
155 }
156 } else {
157 total_fl = (fixed_buff_size * 2) /
158 ((src_width + 32) * fmt->bpp);
159 }
160
161 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
162 plane->base.id, psde->pipe - SSPP_VIG0,
163 fmt->base.pixel_format, src_width, total_fl);
164
165 return total_fl;
166}
167
168/**
169 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
170 * @total_fl: fill level
171 * Return: LUT setting corresponding to the fill level
172 */
173static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
174{
175 u32 qos_lut;
176
177 if (total_fl <= 4)
178 qos_lut = 0x1B;
179 else if (total_fl <= 5)
180 qos_lut = 0x5B;
181 else if (total_fl <= 6)
182 qos_lut = 0x15B;
183 else if (total_fl <= 7)
184 qos_lut = 0x55B;
185 else if (total_fl <= 8)
186 qos_lut = 0x155B;
187 else if (total_fl <= 9)
188 qos_lut = 0x555B;
189 else if (total_fl <= 10)
190 qos_lut = 0x1555B;
191 else if (total_fl <= 11)
192 qos_lut = 0x5555B;
193 else if (total_fl <= 12)
194 qos_lut = 0x15555B;
195 else
196 qos_lut = 0x55555B;
197
198 return qos_lut;
199}
200
201/**
202 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
203 * @total_fl: fill level
204 * Return: LUT setting corresponding to the fill level
205 */
206static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
207{
208 u32 qos_lut;
209
210 if (total_fl <= 10)
211 qos_lut = 0x1AAff;
212 else if (total_fl <= 11)
213 qos_lut = 0x5AAFF;
214 else if (total_fl <= 12)
215 qos_lut = 0x15AAFF;
216 else
217 qos_lut = 0x55AAFF;
218
219 return qos_lut;
220}
221
222/**
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400223 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
224 * @plane: Pointer to drm plane
225 * @fb: Pointer to framebuffer associated with the given plane
226 */
227static void _sde_plane_set_qos_lut(struct drm_plane *plane,
228 struct drm_framebuffer *fb)
229{
230 struct sde_plane *psde;
231 const struct sde_format *fmt = NULL;
232 u32 qos_lut;
233 u32 total_fl = 0;
234
235 if (!plane || !fb) {
236 SDE_ERROR("invalid arguments plane %d fb %d\n",
237 plane != 0, fb != 0);
238 return;
239 }
240
241 psde = to_sde_plane(plane);
242
243 if (!psde->pipe_hw || !psde->pipe_sblk) {
244 SDE_ERROR("invalid arguments\n");
245 return;
246 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
247 return;
248 }
249
250 if (!psde->is_rt_pipe) {
251 qos_lut = psde->pipe_sblk->creq_lut_nrt;
252 } else {
253 fmt = sde_get_sde_format_ext(
254 fb->pixel_format,
255 fb->modifier,
256 drm_format_num_planes(fb->pixel_format));
257 total_fl = _sde_plane_calc_fill_level(plane, fmt,
258 psde->pipe_cfg.src_rect.w);
259
260 if (SDE_FORMAT_IS_LINEAR(fmt))
261 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
262 else
263 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
264 }
265
266 psde->pipe_qos_cfg.creq_lut = qos_lut;
267
268 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
269 (fmt) ? fmt->base.pixel_format : 0,
270 psde->is_rt_pipe, total_fl, qos_lut,
271 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
272
273 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
274 plane->base.id,
275 psde->pipe - SSPP_VIG0,
276 (fmt) ? fmt->base.pixel_format : 0,
277 psde->is_rt_pipe, total_fl, qos_lut);
278
279 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
280}
281
282/**
283 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
284 * @plane: Pointer to drm plane
285 * @fb: Pointer to framebuffer associated with the given plane
286 */
287static void _sde_plane_set_danger_lut(struct drm_plane *plane,
288 struct drm_framebuffer *fb)
289{
290 struct sde_plane *psde;
291 const struct sde_format *fmt = NULL;
292 u32 danger_lut, safe_lut;
293
294 if (!plane || !fb) {
295 SDE_ERROR("invalid arguments\n");
296 return;
297 }
298
299 psde = to_sde_plane(plane);
300
301 if (!psde->pipe_hw || !psde->pipe_sblk) {
302 SDE_ERROR("invalid arguments\n");
303 return;
304 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
305 return;
306 }
307
308 if (!psde->is_rt_pipe) {
309 danger_lut = psde->pipe_sblk->danger_lut_nrt;
310 safe_lut = psde->pipe_sblk->safe_lut_nrt;
311 } else {
312 fmt = sde_get_sde_format_ext(
313 fb->pixel_format,
314 fb->modifier,
315 drm_format_num_planes(fb->pixel_format));
316
317 if (SDE_FORMAT_IS_LINEAR(fmt)) {
318 danger_lut = psde->pipe_sblk->danger_lut_linear;
319 safe_lut = psde->pipe_sblk->safe_lut_linear;
320 } else {
321 danger_lut = psde->pipe_sblk->danger_lut_tile;
322 safe_lut = psde->pipe_sblk->safe_lut_tile;
323 }
324 }
325
326 psde->pipe_qos_cfg.danger_lut = danger_lut;
327 psde->pipe_qos_cfg.safe_lut = safe_lut;
328
329 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
330 (fmt) ? fmt->base.pixel_format : 0,
331 (fmt) ? fmt->fetch_mode : 0,
332 psde->pipe_qos_cfg.danger_lut,
333 psde->pipe_qos_cfg.safe_lut);
334
335 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
336 plane->base.id,
337 psde->pipe - SSPP_VIG0,
338 fmt ? fmt->base.pixel_format : 0,
339 fmt ? fmt->fetch_mode : -1,
340 psde->pipe_qos_cfg.danger_lut,
341 psde->pipe_qos_cfg.safe_lut);
342
343 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
344 &psde->pipe_qos_cfg);
345}
346
347/**
348 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
349 * @plane: Pointer to drm plane
350 * @enable: true to enable QoS control
351 * @flags: QoS control mode (enum sde_plane_qos)
352 */
353static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
354 bool enable, u32 flags)
355{
356 struct sde_plane *psde;
357
358 if (!plane) {
359 SDE_ERROR("invalid arguments\n");
360 return;
361 }
362
363 psde = to_sde_plane(plane);
364
365 if (!psde->pipe_hw || !psde->pipe_sblk) {
366 SDE_ERROR("invalid arguments\n");
367 return;
368 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
369 return;
370 }
371
372 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
373 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
374 psde->pipe_qos_cfg.danger_vblank =
375 psde->pipe_sblk->danger_vblank;
376 psde->pipe_qos_cfg.vblank_en = enable;
377 }
378
379 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
380 /* this feature overrules previous VBLANK_CTRL */
381 psde->pipe_qos_cfg.vblank_en = false;
382 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
383 }
384
385 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
386 psde->pipe_qos_cfg.danger_safe_en = enable;
387
388 if (!psde->is_rt_pipe) {
389 psde->pipe_qos_cfg.vblank_en = false;
390 psde->pipe_qos_cfg.danger_safe_en = false;
391 }
392
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400393 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400394 plane->base.id,
395 psde->pipe - SSPP_VIG0,
396 psde->pipe_qos_cfg.danger_safe_en,
397 psde->pipe_qos_cfg.vblank_en,
398 psde->pipe_qos_cfg.creq_vblank,
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400399 psde->pipe_qos_cfg.danger_vblank,
400 psde->is_rt_pipe);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400401
402 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
403 &psde->pipe_qos_cfg);
404}
405
Alan Kwong5d324e42016-07-28 22:56:18 -0400406/**
407 * _sde_plane_set_ot_limit - set OT limit for the given plane
408 * @plane: Pointer to drm plane
409 * @crtc: Pointer to drm crtc
410 */
411static void _sde_plane_set_ot_limit(struct drm_plane *plane,
412 struct drm_crtc *crtc)
413{
414 struct sde_plane *psde;
415 struct sde_vbif_set_ot_params ot_params;
416 struct msm_drm_private *priv;
417 struct sde_kms *sde_kms;
418
419 if (!plane || !plane->dev || !crtc) {
420 SDE_ERROR("invalid arguments plane %d crtc %d\n",
421 plane != 0, crtc != 0);
422 return;
423 }
424
425 priv = plane->dev->dev_private;
426 if (!priv || !priv->kms) {
427 SDE_ERROR("invalid KMS reference\n");
428 return;
429 }
430
431 sde_kms = to_sde_kms(priv->kms);
432 psde = to_sde_plane(plane);
433 if (!psde->pipe_hw) {
434 SDE_ERROR("invalid pipe reference\n");
435 return;
436 }
437
438 memset(&ot_params, 0, sizeof(ot_params));
439 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
440 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
441 ot_params.width = psde->pipe_cfg.src_rect.w;
442 ot_params.height = psde->pipe_cfg.src_rect.h;
443 ot_params.is_wfd = !psde->is_rt_pipe;
444 ot_params.frame_rate = crtc->mode.vrefresh;
445 ot_params.vbif_idx = VBIF_RT;
446 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
447 ot_params.rd = true;
448
449 sde_vbif_set_ot_limit(sde_kms, &ot_params);
450}
451
Clarence Ipcae1bb62016-07-07 12:07:13 -0400452/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400453static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400454 struct sde_plane_state *pstate, uint64_t fd)
455{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400456 if (!psde || !pstate) {
457 SDE_ERROR("invalid arg(s), plane %d state %d\n",
458 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400459 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400460 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400461
462 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400463 if (pstate->input_fence)
464 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400465
466 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400467 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400468
Clarence Ip13a8cf42016-09-29 17:27:47 -0400469 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400470}
471
Clarence Ipcae1bb62016-07-07 12:07:13 -0400472int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400473{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400474 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400475 struct sde_plane_state *pstate;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400476 uint32_t prefix;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400477 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400478 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400479
480 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700481 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400482 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400483 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400484 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400485 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400486 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400487 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400488
Clarence Ipcae1bb62016-07-07 12:07:13 -0400489 if (input_fence) {
Clarence Ip78a04ed2016-10-04 15:57:45 -0400490 prefix = sde_sync_get_name_prefix(input_fence);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400491 ret = sde_sync_wait(input_fence, wait_ms);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400492
493 MSM_EVT(plane->dev,
494 plane->base.id,
495 (uint64_t)-ret << (sizeof(uint32_t) * CHAR_BIT)
496 | prefix);
497
Clarence Ipcae1bb62016-07-07 12:07:13 -0400498 switch (ret) {
499 case 0:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400500 SDE_DEBUG_PLANE(psde, "signaled\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400501 break;
502 case -ETIME:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400503 SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
504 wait_ms, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400505 psde->is_error = true;
506 break;
507 default:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400508 SDE_ERROR_PLANE(psde, "error %d on %08X\n",
509 ret, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400510 psde->is_error = true;
511 break;
512 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400513 } else {
514 ret = 0;
515 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400516 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400517 return ret;
518}
519
Clarence Ip282dad62016-09-27 17:07:35 -0400520static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400521 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400522 struct sde_hw_pipe_cfg *pipe_cfg,
523 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400524{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400525 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400526 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400527
Clarence Ip13a8cf42016-09-29 17:27:47 -0400528 if (!plane || !pstate || !pipe_cfg || !fb) {
529 SDE_ERROR(
530 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
531 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400532 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400533 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400534
535 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400536 if (!psde->pipe_hw) {
537 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400538 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400539 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400540
Clarence Ipb6eb2362016-09-08 16:18:13 -0400541 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
542 if (ret == -EAGAIN)
543 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
544 else if (ret)
545 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
546 else if (psde->pipe_hw->ops.setup_sourceaddress)
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400547 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400548}
549
abeykun48f407a2016-08-25 12:06:44 -0400550static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
551 struct sde_plane_state *pstate)
552{
553 struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg;
554 int ret = 0;
555
556 cfg->dir_lut = msm_property_get_blob(
557 &psde->property_info,
558 pstate->property_blobs, &cfg->dir_len,
559 PLANE_PROP_SCALER_LUT_ED);
560 cfg->cir_lut = msm_property_get_blob(
561 &psde->property_info,
562 pstate->property_blobs, &cfg->cir_len,
563 PLANE_PROP_SCALER_LUT_CIR);
564 cfg->sep_lut = msm_property_get_blob(
565 &psde->property_info,
566 pstate->property_blobs, &cfg->sep_len,
567 PLANE_PROP_SCALER_LUT_SEP);
568 if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
569 ret = -ENODATA;
570 return ret;
571}
572
Clarence Ipcb410d42016-06-26 22:52:33 -0400573static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400574 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
575 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400576 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400577 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
578{
579}
580
Clarence Ipcb410d42016-06-26 22:52:33 -0400581/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400582 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400583 * @psde: Pointer to SDE plane object
584 * @src: Source size
585 * @dst: Destination size
586 * @phase_steps: Pointer to output array for phase steps
587 * @filter: Pointer to output array for filter type
588 * @fmt: Pointer to format definition
589 * @chroma_subsampling: Subsampling amount for chroma channel
590 *
591 * Returns: 0 on success
592 */
593static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400594 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400595 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400596 uint32_t chroma_subsampling)
597{
Clarence Ipcb410d42016-06-26 22:52:33 -0400598 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400599 SDE_ERROR(
600 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
601 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400602 return -EINVAL;
603 }
604
Clarence Ip4c1d9772016-06-26 09:35:38 -0400605 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400606 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400607 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400608 phase_steps[SDE_SSPP_COMP_1_2] =
609 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
610 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
611 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400612
613 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400614 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400615 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400616 (src <= dst) ? SDE_SCALE_FILTER_BIL :
617 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400618
Clarence Ipdbde9832016-06-26 09:48:36 -0400619 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400620 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400621 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
622 } else {
623 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
624 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400625 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400626 }
627 } else {
628 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400629 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
630 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
631 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400632 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400633 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400634}
635
Clarence Ipcb410d42016-06-26 22:52:33 -0400636/**
637 * _sde_plane_setup_pixel_ext - determine default pixel extension values
638 * @psde: Pointer to SDE plane object
639 * @src: Source size
640 * @dst: Destination size
641 * @decimated_src: Source size after decimation, if any
642 * @phase_steps: Pointer to output array for phase steps
643 * @out_src: Output array for pixel extension values
644 * @out_edge1: Output array for pixel extension first edge
645 * @out_edge2: Output array for pixel extension second edge
646 * @filter: Pointer to array for filter type
647 * @fmt: Pointer to format definition
648 * @chroma_subsampling: Subsampling amount for chroma channel
649 * @post_compare: Whether to chroma subsampled source size for comparisions
650 */
651static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400652 uint32_t src, uint32_t dst, uint32_t decimated_src,
653 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400654 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400655 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400656 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400657{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400658 int64_t edge1, edge2, caf;
659 uint32_t src_work;
660 int i, tmp;
661
Clarence Ipcb410d42016-06-26 22:52:33 -0400662 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400663 out_edge2 && filter && fmt) {
664 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400665 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400666 caf = PHASE_STEP_UNIT_SCALE;
667 else
668 caf = 0;
669
670 for (i = 0; i < SDE_MAX_PLANES; i++) {
671 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400672 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400673 src_work /= chroma_subsampling;
674 if (post_compare)
675 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400676 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400677 /* unity */
678 edge1 = 0;
679 edge2 = 0;
680 } else if (dst >= src) {
681 /* upscale */
682 edge1 = (1 << PHASE_RESIDUAL);
683 edge1 -= caf;
684 edge2 = (1 << PHASE_RESIDUAL);
685 edge2 += (dst - 1) * *(phase_steps + i);
686 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
687 edge2 += caf;
688 edge2 = -(edge2);
689 } else {
690 /* downscale */
691 edge1 = 0;
692 edge2 = (dst - 1) * *(phase_steps + i);
693 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
694 edge2 += *(phase_steps + i);
695 edge2 = -(edge2);
696 }
697
698 /* only enable CAF for luma plane */
699 caf = 0;
700
701 /* populate output arrays */
702 *(out_src + i) = src_work;
703
704 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400705 if (edge1 >= 0) {
706 tmp = (uint32_t)edge1;
707 tmp >>= PHASE_STEP_SHIFT;
708 *(out_edge1 + i) = -tmp;
709 } else {
710 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400711 *(out_edge1 + i) =
712 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
713 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400714 }
715 if (edge2 >= 0) {
716 tmp = (uint32_t)edge2;
717 tmp >>= PHASE_STEP_SHIFT;
718 *(out_edge2 + i) = -tmp;
719 } else {
720 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400721 *(out_edge2 + i) =
722 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
723 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400724 }
725 }
726 }
727}
728
Clarence Ip5fc00c52016-09-23 15:03:34 -0400729static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400730{
731 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
732 {
Clarence Ip373f8592016-05-26 00:58:42 -0400733 /* S15.16 format */
734 0x00012A00, 0x00000000, 0x00019880,
735 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
736 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400737 },
Clarence Ip373f8592016-05-26 00:58:42 -0400738 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400739 { 0xfff0, 0xff80, 0xff80,},
740 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400741 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400742 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400743 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400744 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400745
Clarence Ip5fc00c52016-09-23 15:03:34 -0400746 if (!psde) {
747 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400748 return;
749 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400750
Clarence Ipcae1bb62016-07-07 12:07:13 -0400751 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400752 if (psde->csc_usr_ptr)
753 psde->csc_ptr = psde->csc_usr_ptr;
754 else
Clarence Ip373f8592016-05-26 00:58:42 -0400755 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400756
Clarence Ip13a8cf42016-09-29 17:27:47 -0400757 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400758 psde->csc_ptr->csc_mv[0],
759 psde->csc_ptr->csc_mv[1],
760 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400761}
762
Clarence Ipcb410d42016-06-26 22:52:33 -0400763static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400764 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400765 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700766{
Clarence Ipb43d4592016-09-08 14:21:35 -0400767 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -0400768 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Clarence Ipb43d4592016-09-08 14:21:35 -0400769 uint32_t tmp, i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400770
Clarence Ipb43d4592016-09-08 14:21:35 -0400771 if (!psde || !fmt) {
772 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
773 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400774 return;
Clarence Ipb43d4592016-09-08 14:21:35 -0400775 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400776
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400777 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400778
Clarence Ipdedbba92016-09-27 17:43:10 -0400779 psde->pipe_cfg.horz_decimation =
780 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
781 psde->pipe_cfg.vert_decimation =
782 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400783
784 /* don't chroma subsample if decimating */
785 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400786 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400787 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400788 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400789
Clarence Ip5e2a9222016-06-26 22:38:24 -0400790 /* update scaler */
791 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
abeykun48f407a2016-08-25 12:06:44 -0400792 int error;
793
794 error = _sde_plane_setup_scaler3_lut(psde, pstate);
795 if (error || !psde->pixel_ext_usr) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400796 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -0400797 _sde_plane_setup_scaler3(psde,
798 psde->pipe_cfg.src_rect.w,
799 psde->pipe_cfg.src_rect.h,
800 psde->pipe_cfg.dst_rect.w,
801 psde->pipe_cfg.dst_rect.h,
abeykun48f407a2016-08-25 12:06:44 -0400802 psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400803 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400804 }
Clarence Ipb43d4592016-09-08 14:21:35 -0400805 } else if (!psde->pixel_ext_usr) {
806 /* calculate default configuration for QSEED2 */
807 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400808
Clarence Ip13a8cf42016-09-29 17:27:47 -0400809 SDE_DEBUG_PLANE(psde, "default config\n");
Clarence Ipb43d4592016-09-08 14:21:35 -0400810 _sde_plane_setup_scaler2(psde,
811 psde->pipe_cfg.src_rect.w,
812 psde->pipe_cfg.dst_rect.w,
813 pe->phase_step_x,
814 pe->horz_filter, fmt, chroma_subsmpl_h);
815 _sde_plane_setup_scaler2(psde,
816 psde->pipe_cfg.src_rect.h,
817 psde->pipe_cfg.dst_rect.h,
818 pe->phase_step_y,
819 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400820
Clarence Ip5e2a9222016-06-26 22:38:24 -0400821 /* calculate left/right/top/bottom pixel extensions */
Clarence Ipcb410d42016-06-26 22:52:33 -0400822 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400823 psde->pipe_cfg.horz_decimation);
Clarence Ipdbde9832016-06-26 09:48:36 -0400824 if (SDE_FORMAT_IS_YUV(fmt))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400825 tmp &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400826 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
827 psde->pipe_cfg.dst_rect.w, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400828 pe->phase_step_x,
829 pe->roi_w,
830 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400831 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400832 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400833
Clarence Ipcb410d42016-06-26 22:52:33 -0400834 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400835 psde->pipe_cfg.vert_decimation);
Clarence Ipcb410d42016-06-26 22:52:33 -0400836 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
837 psde->pipe_cfg.dst_rect.h, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400838 pe->phase_step_y,
839 pe->roi_h,
840 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400841 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400842 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400843
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400844 for (i = 0; i < SDE_MAX_PLANES; i++) {
845 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400846 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400847 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400848 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400849
850 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400851 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400852 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400853 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400854
855 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400856 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400857 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400858 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400859
860 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400861 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400862 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400863 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400864 }
865 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400866}
867
Clarence Ipcae1bb62016-07-07 12:07:13 -0400868/**
869 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -0400870 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -0400871 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
872 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
873 * Returns: 0 on success
874 */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400875static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -0400876 uint32_t color, uint32_t alpha)
877{
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400878 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400879
Clarence Ip13a8cf42016-09-29 17:27:47 -0400880 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700881 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400882 return -EINVAL;
883 }
884
Clarence Ipcb410d42016-06-26 22:52:33 -0400885 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400886 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400887 return -EINVAL;
888 }
889
Clarence Ip13a8cf42016-09-29 17:27:47 -0400890 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400891
Clarence Ipcb410d42016-06-26 22:52:33 -0400892 /*
893 * select fill format to match user property expectation,
894 * h/w only supports RGB variants
895 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400896 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400897
898 /* update sspp */
899 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
900 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
901 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
902
903 /* override scaler/decimation if solid fill */
904 psde->pipe_cfg.src_rect.x = 0;
905 psde->pipe_cfg.src_rect.y = 0;
906 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
907 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
908
909 _sde_plane_setup_scaler(psde, fmt, 0);
910
911 if (psde->pipe_hw->ops.setup_format)
912 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
913 fmt, SDE_SSPP_SOLID_FILL);
914
915 if (psde->pipe_hw->ops.setup_rects)
916 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
abeykun48f407a2016-08-25 12:06:44 -0400917 &psde->pipe_cfg, &psde->pixel_ext,
918 psde->scaler3_cfg);
Clarence Ipcb410d42016-06-26 22:52:33 -0400919 }
920
921 return 0;
922}
923
924static int _sde_plane_mode_set(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -0700925 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -0400926{
Clarence Ipc47a0692016-10-11 10:54:17 -0400927 uint32_t nplanes, src_flags;
Clarence Ipcb410d42016-06-26 22:52:33 -0400928 struct sde_plane *psde;
929 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400930 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -0700931 struct drm_crtc *crtc;
932 struct drm_framebuffer *fb;
933 struct sde_rect src, dst;
934 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -0400935 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -0400936
Clarence Ip13a8cf42016-09-29 17:27:47 -0400937 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -0400938 SDE_ERROR("invalid plane\n");
939 return -EINVAL;
940 } else if (!plane->state) {
941 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400942 return -EINVAL;
943 }
944
945 psde = to_sde_plane(plane);
946 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -0400947
Dhaval Patel47302cf2016-08-18 15:04:28 -0700948 crtc = state->crtc;
949 fb = state->fb;
950 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400951 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
952 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -0700953 return -EINVAL;
954 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400955 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400956 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -0400957
Clarence Ip282dad62016-09-27 17:07:35 -0400958 /* determine what needs to be refreshed */
959 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
960 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400961 case PLANE_PROP_SCALER_V1:
abeykun48f407a2016-08-25 12:06:44 -0400962 case PLANE_PROP_SCALER_V2:
Clarence Ipdedbba92016-09-27 17:43:10 -0400963 case PLANE_PROP_H_DECIMATE:
964 case PLANE_PROP_V_DECIMATE:
965 case PLANE_PROP_SRC_CONFIG:
966 case PLANE_PROP_ZPOS:
Clarence Ip282dad62016-09-27 17:07:35 -0400967 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
968 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400969 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -0400970 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
971 break;
972 case PLANE_PROP_COLOR_FILL:
973 /* potentially need to refresh everything */
974 pstate->dirty = SDE_PLANE_DIRTY_ALL;
975 break;
976 case PLANE_PROP_ROTATION:
977 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
978 break;
Clarence Ip282dad62016-09-27 17:07:35 -0400979 case PLANE_PROP_INFO:
980 case PLANE_PROP_ALPHA:
981 case PLANE_PROP_INPUT_FENCE:
982 case PLANE_PROP_BLEND_OP:
983 /* no special action required */
984 break;
985 default:
986 /* unknown property, refresh everything */
987 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
988 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
989 break;
990 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400991 }
992
Clarence Ip282dad62016-09-27 17:07:35 -0400993 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
994 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -0400995
996 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
997
Clarence Ip282dad62016-09-27 17:07:35 -0400998 /* early out if nothing dirty */
999 if (!pstate->dirty)
1000 return 0;
1001 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001002
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001003 psde->is_rt_pipe = sde_crtc_is_rt(crtc);
Clarence Ip282dad62016-09-27 17:07:35 -04001004 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1005
1006 /* update roi config */
1007 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
1008 POPULATE_RECT(&src, state->src_x, state->src_y,
1009 state->src_w, state->src_h, q16_data);
1010 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
1011 state->crtc_w, state->crtc_h, !q16_data);
1012
Clarence Ip13a8cf42016-09-29 17:27:47 -04001013 SDE_DEBUG_PLANE(psde,
1014 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001015 fb->base.id, src.x, src.y, src.w, src.h,
1016 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
1017 drm_get_format_name(fmt->base.pixel_format),
1018 SDE_FORMAT_IS_UBWC(fmt));
1019
1020 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
1021 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001022 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001023 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
1024 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
1025 src.h /= 2;
1026 src.y = DIV_ROUND_UP(src.y, 2);
1027 src.y &= ~0x1;
1028 }
1029
1030 psde->pipe_cfg.src_rect = src;
1031 psde->pipe_cfg.dst_rect = dst;
1032
1033 /* check for color fill */
1034 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
1035 PLANE_PROP_COLOR_FILL);
1036 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
1037 /* skip remaining processing on color fill */
1038 pstate->dirty = 0x0;
1039 } else if (psde->pipe_hw->ops.setup_rects) {
1040 _sde_plane_setup_scaler(psde, fmt, pstate);
1041
Clarence Ip282dad62016-09-27 17:07:35 -04001042 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
abeykun48f407a2016-08-25 12:06:44 -04001043 &psde->pipe_cfg, &psde->pixel_ext,
1044 psde->scaler3_cfg);
Clarence Ip282dad62016-09-27 17:07:35 -04001045 }
Dhaval Patel48c76022016-09-01 17:51:23 -07001046 }
1047
Clarence Ip282dad62016-09-27 17:07:35 -04001048 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
1049 psde->pipe_hw->ops.setup_format) {
1050 src_flags = 0x0;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001051 SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001052 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
1053 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1054 BIT(DRM_REFLECT_X))
1055 src_flags |= SDE_SSPP_FLIP_LR;
1056 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1057 BIT(DRM_REFLECT_Y))
1058 src_flags |= SDE_SSPP_FLIP_UD;
1059
1060 /* update format */
1061 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags);
1062
1063 /* update csc */
1064 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04001065 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04001066 else
1067 psde->csc_ptr = 0;
1068 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001069
Clarence Ipe78efb72016-06-24 18:35:21 -04001070 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04001071 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
1072 psde->pipe_hw->ops.setup_sharpening) {
1073 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
1074 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
1075 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
1076 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04001077
Clarence Ipe78efb72016-06-24 18:35:21 -04001078 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04001079 &psde->sharp_cfg);
1080 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001081
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001082 _sde_plane_set_qos_lut(plane, fb);
1083 _sde_plane_set_danger_lut(plane, fb);
1084
Alan Kwong5d324e42016-07-28 22:56:18 -04001085 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001086 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04001087 _sde_plane_set_ot_limit(plane, crtc);
1088 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001089
Clarence Ip282dad62016-09-27 17:07:35 -04001090 /* clear dirty */
1091 pstate->dirty = 0x0;
1092
Clarence Ip5e2a9222016-06-26 22:38:24 -04001093 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001094}
1095
1096static int sde_plane_prepare_fb(struct drm_plane *plane,
1097 const struct drm_plane_state *new_state)
1098{
1099 struct drm_framebuffer *fb = new_state->fb;
1100 struct sde_plane *psde = to_sde_plane(plane);
1101
1102 if (!new_state->fb)
1103 return 0;
1104
Clarence Ip13a8cf42016-09-29 17:27:47 -04001105 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001106 return msm_framebuffer_prepare(fb, psde->mmu_id);
1107}
1108
1109static void sde_plane_cleanup_fb(struct drm_plane *plane,
1110 const struct drm_plane_state *old_state)
1111{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001112 struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
1113 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001114
1115 if (!fb)
1116 return;
1117
Clarence Ip13a8cf42016-09-29 17:27:47 -04001118 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001119 msm_framebuffer_cleanup(fb, psde->mmu_id);
1120}
1121
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001122static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
1123 struct drm_plane_state *state,
1124 struct drm_plane_state *old_state)
1125{
1126 struct sde_plane_state *pstate = to_sde_plane_state(state);
1127
Dhaval Patel47302cf2016-08-18 15:04:28 -07001128 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04001129 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001130 return;
1131
Clarence Ip282dad62016-09-27 17:07:35 -04001132 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
1133 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001134 SDE_DEBUG_PLANE(psde,
1135 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001136 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001137 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001138 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001139 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001140 } else if (state->src_w != old_state->src_w ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07001141 state->src_h != old_state->src_h ||
1142 state->src_x != old_state->src_x ||
1143 state->src_y != old_state->src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001144 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001145 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001146 } else if (state->crtc_w != old_state->crtc_w ||
1147 state->crtc_h != old_state->crtc_h ||
1148 state->crtc_x != old_state->crtc_x ||
1149 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001150 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001151 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1152 }
1153
1154 if (!state->fb || !old_state->fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001155 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001156 } else if (state->fb->pixel_format != old_state->fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001157 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001158 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001159 } else {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001160 uint64_t *new_mods = state->fb->modifier;
1161 uint64_t *old_mods = old_state->fb->modifier;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001162 uint32_t *new_pitches = state->fb->pitches;
1163 uint32_t *old_pitches = old_state->fb->pitches;
1164 uint32_t *new_offset = state->fb->offsets;
1165 uint32_t *old_offset = old_state->fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001166 int i;
1167
1168 for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
1169 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001170 SDE_DEBUG_PLANE(psde,
1171 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001172 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001173 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001174 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1175 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001176 break;
1177 }
1178 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001179 for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
1180 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001181 SDE_DEBUG_PLANE(psde,
1182 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001183 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001184 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001185 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001186 break;
1187 }
1188 }
Dhaval Patel47302cf2016-08-18 15:04:28 -07001189 for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
1190 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001191 SDE_DEBUG_PLANE(psde,
1192 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001193 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001194 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001195 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1196 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001197 break;
1198 }
1199 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001200 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001201}
1202
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001203static int sde_plane_atomic_check(struct drm_plane *plane,
1204 struct drm_plane_state *state)
1205{
Clarence Ipdedbba92016-09-27 17:43:10 -04001206 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04001207 struct sde_plane *psde;
1208 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001209 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001210 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04001211 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001212 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
1213 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04001214
1215 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001216 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1217 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04001218 ret = -EINVAL;
1219 goto exit;
1220 }
1221
1222 psde = to_sde_plane(plane);
1223 pstate = to_sde_plane_state(state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001224
1225 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001226 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001227 ret = -EINVAL;
1228 goto exit;
1229 }
1230
Clarence Ipdedbba92016-09-27 17:43:10 -04001231 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1232 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04001233
1234 /* src values are in Q16 fixed point, convert to integer */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001235 POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
1236 state->src_h, q16_data);
1237 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
1238 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04001239
Dhaval Patel47302cf2016-08-18 15:04:28 -07001240 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
1241 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04001242
Dhaval Patel47302cf2016-08-18 15:04:28 -07001243 max_upscale = psde->pipe_sblk->maxupscale;
1244 max_downscale = psde->pipe_sblk->maxdwnscale;
1245 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04001246
Clarence Ip13a8cf42016-09-29 17:27:47 -04001247 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001248 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001249
Dhaval Patel47302cf2016-08-18 15:04:28 -07001250 if (!sde_plane_enabled(state))
1251 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04001252
Dhaval Patel47302cf2016-08-18 15:04:28 -07001253 fmt = to_sde_format(msm_framebuffer_format(state->fb));
1254
1255 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
1256
1257 if (SDE_FORMAT_IS_YUV(fmt) &&
1258 (!(psde->features & SDE_SSPP_SCALER) ||
1259 !(psde->features & BIT(SDE_SSPP_CSC)))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001260 SDE_ERROR_PLANE(psde,
1261 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07001262 ret = -EINVAL;
1263
1264 /* check src bounds */
1265 } else if (state->fb->width > MAX_IMG_WIDTH ||
1266 state->fb->height > MAX_IMG_HEIGHT ||
1267 src.w < min_src_size || src.h < min_src_size ||
1268 CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
1269 CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001270 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001271 src.x, src.y, src.w, src.h);
1272 ret = -E2BIG;
1273
1274 /* valid yuv image */
1275 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
1276 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001277 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001278 src.x, src.y, src.w, src.h);
1279 ret = -EINVAL;
1280
1281 /* min dst support */
1282 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001283 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001284 dst.x, dst.y, dst.w, dst.h);
1285 ret = -EINVAL;
1286
1287 /* decimation validation */
1288 } else if (deci_w || deci_h) {
1289 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
1290 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001291 SDE_ERROR_PLANE(psde,
1292 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001293 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001294 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001295 SDE_ERROR_PLANE(psde,
1296 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001297 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001298 }
1299
Dhaval Patel47302cf2016-08-18 15:04:28 -07001300 } else if (!(psde->features & SDE_SSPP_SCALER) &&
1301 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001302 SDE_ERROR_PLANE(psde,
1303 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001304 src.w, src.h, dst.w, dst.h);
1305 ret = -EINVAL;
1306
1307 /* check decimated source width */
1308 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001309 SDE_ERROR_PLANE(psde,
1310 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001311 src.w, src_deci_w, max_linewidth);
1312 ret = -E2BIG;
1313
1314 /* check max scaler capability */
1315 } else if (((src_deci_w * max_upscale) < dst.w) ||
1316 ((src_deci_h * max_upscale) < dst.h) ||
1317 ((dst.w * max_downscale) < src_deci_w) ||
1318 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001319 SDE_ERROR_PLANE(psde,
1320 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001321 src_deci_w, src_deci_h, dst.w, dst.h);
1322 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001323 }
1324
Dhaval Patel47302cf2016-08-18 15:04:28 -07001325modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001326 if (!ret)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001327 _sde_plane_atomic_check_mode_changed(psde, state, plane->state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001328exit:
1329 return ret;
1330}
1331
Clarence Ipcae1bb62016-07-07 12:07:13 -04001332/**
1333 * sde_plane_flush - final plane operations before commit flush
1334 * @plane: Pointer to drm plane structure
1335 */
1336void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04001337{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001338 struct sde_plane *psde;
1339
Clarence Ip13a8cf42016-09-29 17:27:47 -04001340 if (!plane) {
1341 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001342 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001343 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04001344
1345 psde = to_sde_plane(plane);
1346
1347 /*
1348 * These updates have to be done immediately before the plane flush
1349 * timing, and may not be moved to the atomic_update/mode_set functions.
1350 */
1351 if (psde->is_error)
1352 /* force white frame with 0% alpha pipe output on error */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001353 _sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001354 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
1355 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001356 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001357 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
1358 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
1359
1360 /* flag h/w flush complete */
1361 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04001362 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001363}
1364
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001365static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001366 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001367{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001368 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001369 struct drm_plane_state *state;
1370 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001371
Clarence Ip13a8cf42016-09-29 17:27:47 -04001372 if (!plane) {
1373 SDE_ERROR("invalid plane\n");
1374 return;
1375 } else if (!plane->state) {
1376 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001377 return;
1378 }
1379
Clarence Ip13a8cf42016-09-29 17:27:47 -04001380 psde = to_sde_plane(plane);
1381 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001382 state = plane->state;
1383 pstate = to_sde_plane_state(state);
1384
Clarence Ip13a8cf42016-09-29 17:27:47 -04001385 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001386
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001387 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001388 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001389 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001390 int ret;
1391
Dhaval Patel47302cf2016-08-18 15:04:28 -07001392 ret = _sde_plane_mode_set(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001393 /* atomic_check should have ensured that this doesn't fail */
1394 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001395 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001396}
1397
Dhaval Patel47302cf2016-08-18 15:04:28 -07001398
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001399/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001400static void _sde_plane_install_properties(struct drm_plane *plane,
Clarence Ipc47a0692016-10-11 10:54:17 -04001401 struct sde_mdss_cfg *catalog)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001402{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001403 static const struct drm_prop_enum_list e_blend_op[] = {
1404 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1405 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1406 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1407 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1408 };
1409 static const struct drm_prop_enum_list e_src_config[] = {
1410 {SDE_DRM_DEINTERLACE, "deinterlace"}
1411 };
Clarence Ipea3d6262016-07-15 16:20:11 -04001412 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07001413 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001414 struct sde_plane *psde = to_sde_plane(plane);
Clarence Ipc47a0692016-10-11 10:54:17 -04001415 int zpos_max = 255;
1416 int zpos_def = 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001417
Clarence Ip13a8cf42016-09-29 17:27:47 -04001418 if (!plane || !psde) {
1419 SDE_ERROR("invalid plane\n");
1420 return;
1421 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
1422 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
1423 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001424 return;
Clarence Ipc47a0692016-10-11 10:54:17 -04001425 } else if (!catalog) {
1426 SDE_ERROR("invalid catalog\n");
1427 return;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001428 }
1429
Clarence Ipc47a0692016-10-11 10:54:17 -04001430 if (sde_is_custom_client()) {
1431 if (catalog->mixer_count && catalog->mixer)
1432 zpos_max = catalog->mixer[0].sblk->maxblendstages;
1433 } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
1434 /* reserve zpos == 0 for primary planes */
1435 zpos_def = drm_plane_index(plane) + 1;
1436 }
1437
1438 msm_property_install_range(&psde->property_info, "zpos",
1439 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001440
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001441 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001442 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001443
Dhaval Patel47302cf2016-08-18 15:04:28 -07001444 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001445 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07001446 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001447
Clarence Ipdedbba92016-09-27 17:43:10 -04001448 if (psde->pipe_sblk->maxhdeciexp) {
1449 msm_property_install_range(&psde->property_info, "h_decimate",
1450 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0,
1451 PLANE_PROP_H_DECIMATE);
1452 }
1453
1454 if (psde->pipe_sblk->maxvdeciexp) {
1455 msm_property_install_range(&psde->property_info, "v_decimate",
1456 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0,
1457 PLANE_PROP_V_DECIMATE);
1458 }
1459
abeykun48f407a2016-08-25 12:06:44 -04001460 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
1461 msm_property_install_volatile_range(&psde->property_info,
1462 "scaler_v2", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
1463 msm_property_install_blob(&psde->property_info, "lut_ed", 0,
1464 PLANE_PROP_SCALER_LUT_ED);
1465 msm_property_install_blob(&psde->property_info, "lut_cir", 0,
1466 PLANE_PROP_SCALER_LUT_CIR);
1467 msm_property_install_blob(&psde->property_info, "lut_sep", 0,
1468 PLANE_PROP_SCALER_LUT_SEP);
1469 } else if (psde->features & SDE_SSPP_SCALER) {
Clarence Ipb43d4592016-09-08 14:21:35 -04001470 msm_property_install_volatile_range(&psde->property_info,
1471 "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
1472 }
1473
Clarence Ip5fc00c52016-09-23 15:03:34 -04001474 if (psde->features & BIT(SDE_SSPP_CSC)) {
1475 msm_property_install_volatile_range(&psde->property_info,
1476 "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1);
1477 }
1478
Clarence Ip5e2a9222016-06-26 22:38:24 -04001479 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001480 msm_property_install_rotation(&psde->property_info,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001481 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001482
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001483 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001484 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001485
Dhaval Patel47302cf2016-08-18 15:04:28 -07001486 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
1487 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
1488
1489 if (psde->pipe_hw->ops.setup_solidfill)
1490 msm_property_install_range(&psde->property_info, "color_fill",
1491 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
1492
Dhaval Patel4e574842016-08-23 15:11:37 -07001493 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001494 if (!info) {
1495 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07001496 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001497 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001498
1499 msm_property_install_blob(&psde->property_info, "capabilities",
1500 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
1501 sde_kms_info_reset(info);
1502
Clarence Ipea3d6262016-07-15 16:20:11 -04001503 format_list = psde->pipe_sblk->format_list;
1504 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04001505 sde_kms_info_start(info, "pixel_formats");
1506 while (format_list->fourcc_format) {
1507 sde_kms_info_append_format(info,
1508 format_list->fourcc_format,
1509 format_list->modifier);
1510 ++format_list;
1511 }
1512 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04001513 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001514
1515 sde_kms_info_add_keyint(info, "max_linewidth",
1516 psde->pipe_sblk->maxlinewidth);
1517 sde_kms_info_add_keyint(info, "max_upscale",
1518 psde->pipe_sblk->maxupscale);
1519 sde_kms_info_add_keyint(info, "max_downscale",
1520 psde->pipe_sblk->maxdwnscale);
1521 sde_kms_info_add_keyint(info, "max_horizontal_deci",
1522 psde->pipe_sblk->maxhdeciexp);
1523 sde_kms_info_add_keyint(info, "max_vertical_deci",
1524 psde->pipe_sblk->maxvdeciexp);
1525 msm_property_set_blob(&psde->property_info, &psde->blob_info,
1526 info->data, info->len, PLANE_PROP_INFO);
1527
1528 kfree(info);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001529}
1530
Clarence Ip5fc00c52016-09-23 15:03:34 -04001531static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
1532{
1533 struct sde_drm_csc_v1 csc_v1;
1534 int i;
1535
1536 if (!psde) {
1537 SDE_ERROR("invalid plane\n");
1538 return;
1539 }
1540
1541 psde->csc_usr_ptr = NULL;
1542 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001543 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001544 return;
1545 }
1546
1547 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001548 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001549 return;
1550 }
1551
Clarence Ipb43d4592016-09-08 14:21:35 -04001552 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04001553 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
1554 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
1555 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
1556 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
1557 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
1558 }
1559 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
1560 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
1561 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
1562 }
1563 psde->csc_usr_ptr = &psde->csc_cfg;
1564}
1565
Clarence Ipb43d4592016-09-08 14:21:35 -04001566static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
1567{
1568 struct sde_drm_scaler_v1 scale_v1;
1569 struct sde_hw_pixel_ext *pe;
1570 int i;
1571
1572 if (!psde) {
1573 SDE_ERROR("invalid plane\n");
1574 return;
1575 }
1576
1577 psde->pixel_ext_usr = false;
1578 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001579 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001580 return;
1581 }
1582
1583 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001584 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001585 return;
1586 }
1587
1588 /* populate from user space */
1589 pe = &(psde->pixel_ext);
1590 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1591 for (i = 0; i < SDE_MAX_PLANES; i++) {
1592 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
1593 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
1594 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
1595 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
1596
1597 pe->horz_filter[i] = scale_v1.horz_filter[i];
1598 pe->vert_filter[i] = scale_v1.vert_filter[i];
1599 }
1600 for (i = 0; i < SDE_MAX_PLANES; i++) {
1601 pe->num_ext_pxls_left[i] = scale_v1.lr.num_pxls_start[i];
1602 pe->num_ext_pxls_right[i] = scale_v1.lr.num_pxls_end[i];
1603 pe->left_ftch[i] = scale_v1.lr.ftch_start[i];
1604 pe->right_ftch[i] = scale_v1.lr.ftch_end[i];
1605 pe->left_rpt[i] = scale_v1.lr.rpt_start[i];
1606 pe->right_rpt[i] = scale_v1.lr.rpt_end[i];
1607 pe->roi_w[i] = scale_v1.lr.roi[i];
1608
1609 pe->num_ext_pxls_top[i] = scale_v1.tb.num_pxls_start[i];
1610 pe->num_ext_pxls_btm[i] = scale_v1.tb.num_pxls_end[i];
1611 pe->top_ftch[i] = scale_v1.tb.ftch_start[i];
1612 pe->btm_ftch[i] = scale_v1.tb.ftch_end[i];
1613 pe->top_rpt[i] = scale_v1.tb.rpt_start[i];
1614 pe->btm_rpt[i] = scale_v1.tb.rpt_end[i];
1615 pe->roi_h[i] = scale_v1.tb.roi[i];
1616 }
1617 psde->pixel_ext_usr = true;
1618
Clarence Ip13a8cf42016-09-29 17:27:47 -04001619 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001620}
1621
abeykun48f407a2016-08-25 12:06:44 -04001622static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
1623 struct sde_plane_state *pstate, void *usr)
1624{
1625 struct sde_drm_scaler_v2 scale_v2;
1626 struct sde_hw_pixel_ext *pe;
1627 int i;
1628 struct sde_hw_scaler3_cfg *cfg;
1629
1630 if (!psde) {
1631 SDE_ERROR("invalid plane\n");
1632 return;
1633 }
1634
1635 cfg = psde->scaler3_cfg;
1636 psde->pixel_ext_usr = false;
1637 if (!usr) {
1638 SDE_DEBUG_PLANE(psde, "scale data removed\n");
1639 return;
1640 }
1641
1642 if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
1643 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
1644 return;
1645 }
1646
1647 /* populate from user space */
1648 pe = &(psde->pixel_ext);
1649 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1650 cfg->enable = scale_v2.enable;
1651 cfg->dir_en = scale_v2.dir_en;
1652 for (i = 0; i < SDE_MAX_PLANES; i++) {
1653 cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
1654 cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
1655 cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
1656 cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
1657
1658 cfg->preload_x[i] = scale_v2.preload_x[i];
1659 cfg->preload_y[i] = scale_v2.preload_y[i];
1660 cfg->src_width[i] = scale_v2.src_width[i];
1661 cfg->src_height[i] = scale_v2.src_height[i];
1662 }
1663 cfg->dst_width = scale_v2.dst_width;
1664 cfg->dst_height = scale_v2.dst_height;
1665
1666 cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
1667 cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
1668 cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
1669 cfg->blend_cfg = scale_v2.blend_cfg;
1670
1671 cfg->lut_flag = scale_v2.lut_flag;
1672 cfg->dir_lut_idx = scale_v2.dir_lut_idx;
1673 cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
1674 cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
1675 cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
1676 cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
1677
1678 cfg->de.enable = scale_v2.de.enable;
1679 cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
1680 cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
1681 cfg->de.clip = scale_v2.de.clip;
1682 cfg->de.limit = scale_v2.de.limit;
1683 cfg->de.thr_quiet = scale_v2.de.thr_quiet;
1684 cfg->de.thr_dieout = scale_v2.de.thr_dieout;
1685 cfg->de.thr_low = scale_v2.de.thr_low;
1686 cfg->de.thr_high = scale_v2.de.thr_high;
1687 cfg->de.prec_shift = scale_v2.de.prec_shift;
1688 for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
1689 cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
1690 cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
1691 cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
1692 }
1693 for (i = 0; i < SDE_MAX_PLANES; i++) {
1694 pe->num_ext_pxls_left[i] = scale_v2.lr.num_pxls_start[i];
1695 pe->num_ext_pxls_right[i] = scale_v2.lr.num_pxls_end[i];
1696 pe->left_ftch[i] = scale_v2.lr.ftch_start[i];
1697 pe->right_ftch[i] = scale_v2.lr.ftch_end[i];
1698 pe->left_rpt[i] = scale_v2.lr.rpt_start[i];
1699 pe->right_rpt[i] = scale_v2.lr.rpt_end[i];
1700 pe->roi_w[i] = scale_v2.lr.roi[i];
1701
1702 pe->num_ext_pxls_top[i] = scale_v2.tb.num_pxls_start[i];
1703 pe->num_ext_pxls_btm[i] = scale_v2.tb.num_pxls_end[i];
1704 pe->top_ftch[i] = scale_v2.tb.ftch_start[i];
1705 pe->btm_ftch[i] = scale_v2.tb.ftch_end[i];
1706 pe->top_rpt[i] = scale_v2.tb.rpt_start[i];
1707 pe->btm_rpt[i] = scale_v2.tb.rpt_end[i];
1708 pe->roi_h[i] = scale_v2.tb.roi[i];
1709 }
1710 psde->pixel_ext_usr = true;
1711
1712 SDE_DEBUG_PLANE(psde, "user property data copied\n");
1713}
1714
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001715static int sde_plane_atomic_set_property(struct drm_plane *plane,
1716 struct drm_plane_state *state, struct drm_property *property,
1717 uint64_t val)
1718{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001719 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001720 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001721 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001722
Clarence Ip13a8cf42016-09-29 17:27:47 -04001723 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001724
1725 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001726 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001727 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001728 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001729 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001730 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001731 ret = msm_property_atomic_set(&psde->property_info,
1732 pstate->property_values, pstate->property_blobs,
1733 property, val);
1734 if (!ret) {
1735 idx = msm_property_index(&psde->property_info,
1736 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001737 switch (idx) {
1738 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04001739 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001740 break;
1741 case PLANE_PROP_CSC_V1:
1742 _sde_plane_set_csc_v1(psde, (void *)val);
1743 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04001744 case PLANE_PROP_SCALER_V1:
1745 _sde_plane_set_scaler_v1(psde, (void *)val);
1746 break;
abeykun48f407a2016-08-25 12:06:44 -04001747 case PLANE_PROP_SCALER_V2:
1748 _sde_plane_set_scaler_v2(psde, pstate,
1749 (void *)val);
1750 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001751 default:
1752 /* nothing to do */
1753 break;
1754 }
Clarence Ipe78efb72016-06-24 18:35:21 -04001755 }
1756 }
1757
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001758 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001759}
1760
1761static int sde_plane_set_property(struct drm_plane *plane,
1762 struct drm_property *property, uint64_t val)
1763{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001764 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001765
Clarence Ipae4e60c2016-06-26 22:44:04 -04001766 return sde_plane_atomic_set_property(plane,
1767 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001768}
1769
1770static int sde_plane_atomic_get_property(struct drm_plane *plane,
1771 const struct drm_plane_state *state,
1772 struct drm_property *property, uint64_t *val)
1773{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001774 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001775 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001776 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001777
Clarence Ipaa0faf42016-05-30 12:07:48 -04001778 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001779 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001780 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001781 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001782 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001783 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001784 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001785 ret = msm_property_atomic_get(&psde->property_info,
1786 pstate->property_values, pstate->property_blobs,
1787 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001788 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001789
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001790 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001791}
1792
1793static void sde_plane_destroy(struct drm_plane *plane)
1794{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001795 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001796
Clarence Ip13a8cf42016-09-29 17:27:47 -04001797 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001798
Clarence Ip13a8cf42016-09-29 17:27:47 -04001799 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001800 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1801
Clarence Ip4ce59322016-06-26 22:27:51 -04001802 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001803
Dhaval Patel4e574842016-08-23 15:11:37 -07001804 if (psde->blob_info)
1805 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001806 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001807 mutex_destroy(&psde->lock);
1808
Clarence Ip4ce59322016-06-26 22:27:51 -04001809 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001810
Clarence Ip4ce59322016-06-26 22:27:51 -04001811 /* this will destroy the states as well */
1812 drm_plane_cleanup(plane);
1813
Clarence Ip4c1d9772016-06-26 09:35:38 -04001814 if (psde->pipe_hw)
1815 sde_hw_sspp_destroy(psde->pipe_hw);
1816
Clarence Ip4ce59322016-06-26 22:27:51 -04001817 kfree(psde);
1818 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001819}
1820
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001821static void sde_plane_destroy_state(struct drm_plane *plane,
1822 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001823{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001824 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001825 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001826
Clarence Ipae4e60c2016-06-26 22:44:04 -04001827 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001828 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1829 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001830 return;
1831 }
1832
Clarence Ipaa0faf42016-05-30 12:07:48 -04001833 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001834 pstate = to_sde_plane_state(state);
1835
Clarence Ip13a8cf42016-09-29 17:27:47 -04001836 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001837
Clarence Ipe78efb72016-06-24 18:35:21 -04001838 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001839 if (state->fb)
1840 drm_framebuffer_unreference(state->fb);
1841
Clarence Ipae4e60c2016-06-26 22:44:04 -04001842 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001843 if (pstate->input_fence)
1844 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001845
Clarence Ipaa0faf42016-05-30 12:07:48 -04001846 /* destroy value helper */
1847 msm_property_destroy_state(&psde->property_info, pstate,
1848 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001849}
1850
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001851static struct drm_plane_state *
1852sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001853{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001854 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001855 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001856 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04001857 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001858
Clarence Ip13a8cf42016-09-29 17:27:47 -04001859 if (!plane) {
1860 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001861 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001862 } else if (!plane->state) {
1863 SDE_ERROR("invalid plane state\n");
1864 return NULL;
1865 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001866
Clarence Ip730e7192016-06-26 22:45:09 -04001867 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001868 psde = to_sde_plane(plane);
1869 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001870 if (!pstate) {
1871 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001872 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001873 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001874
Clarence Ip13a8cf42016-09-29 17:27:47 -04001875 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001876
1877 /* duplicate value helper */
1878 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
1879 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001880
Clarence Ip730e7192016-06-26 22:45:09 -04001881 /* add ref count for frame buffer */
1882 if (pstate->base.fb)
1883 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001884
Clarence Ip17e908b2016-09-29 15:58:00 -04001885 /* clear out any input fence */
1886 pstate->input_fence = 0;
1887 input_fence_default = msm_property_get_default(
1888 &psde->property_info, PLANE_PROP_INPUT_FENCE);
1889 msm_property_set_property(&psde->property_info, pstate->property_values,
1890 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001891
Clarence Ip282dad62016-09-27 17:07:35 -04001892 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04001893 pstate->pending = false;
1894
1895 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001896}
1897
1898static void sde_plane_reset(struct drm_plane *plane)
1899{
Clarence Ipae4e60c2016-06-26 22:44:04 -04001900 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001901 struct sde_plane_state *pstate;
1902
Clarence Ipae4e60c2016-06-26 22:44:04 -04001903 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001904 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001905 return;
1906 }
1907
Clarence Ip730e7192016-06-26 22:45:09 -04001908 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001909 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001910
Clarence Ipae4e60c2016-06-26 22:44:04 -04001911 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001912 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04001913 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001914 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04001915 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001916
Clarence Ipaa0faf42016-05-30 12:07:48 -04001917 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001918 if (!pstate) {
1919 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001920 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001921 }
Clarence Ip730e7192016-06-26 22:45:09 -04001922
Clarence Ipaa0faf42016-05-30 12:07:48 -04001923 /* reset value helper */
1924 msm_property_reset_state(&psde->property_info, pstate,
1925 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001926
1927 pstate->base.plane = plane;
1928
1929 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001930}
1931
1932static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001933 .update_plane = drm_atomic_helper_update_plane,
1934 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001935 .destroy = sde_plane_destroy,
1936 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001937 .atomic_set_property = sde_plane_atomic_set_property,
1938 .atomic_get_property = sde_plane_atomic_get_property,
1939 .reset = sde_plane_reset,
1940 .atomic_duplicate_state = sde_plane_duplicate_state,
1941 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001942};
1943
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001944static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
1945 .prepare_fb = sde_plane_prepare_fb,
1946 .cleanup_fb = sde_plane_cleanup_fb,
1947 .atomic_check = sde_plane_atomic_check,
1948 .atomic_update = sde_plane_atomic_update,
1949};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001950
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001951enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001952{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001953 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001954}
1955
Clarence Ip4ce59322016-06-26 22:27:51 -04001956static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
1957{
1958 const struct sde_sspp_sub_blks *sblk = 0;
1959 const struct sde_sspp_cfg *cfg = 0;
1960
1961 if (psde && psde->pipe_hw)
1962 cfg = psde->pipe_hw->cap;
1963 if (cfg)
1964 sblk = cfg->sblk;
1965
1966 if (kms && sblk) {
1967 /* create overall sub-directory for the pipe */
1968 psde->debugfs_root =
1969 debugfs_create_dir(psde->pipe_name,
1970 sde_debugfs_get_root(kms));
1971 if (psde->debugfs_root) {
1972 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001973 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04001974 psde->debugfs_root, &psde->features);
1975
1976 /* add register dump support */
1977 sde_debugfs_setup_regset32(&psde->debugfs_src,
1978 sblk->src_blk.base + cfg->base,
1979 sblk->src_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001980 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001981 sde_debugfs_create_regset32("src_blk", 0444,
1982 psde->debugfs_root, &psde->debugfs_src);
1983
1984 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
1985 sblk->scaler_blk.base + cfg->base,
1986 sblk->scaler_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001987 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001988 sde_debugfs_create_regset32("scaler_blk", 0444,
1989 psde->debugfs_root,
1990 &psde->debugfs_scaler);
1991
1992 sde_debugfs_setup_regset32(&psde->debugfs_csc,
1993 sblk->csc_blk.base + cfg->base,
1994 sblk->csc_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001995 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001996 sde_debugfs_create_regset32("csc_blk", 0444,
1997 psde->debugfs_root, &psde->debugfs_csc);
1998 }
1999 }
2000}
2001
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002002/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04002003struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip2bbf7b32016-09-23 15:07:16 -04002004 uint32_t pipe, bool primary_plane,
2005 unsigned long possible_crtcs)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002006{
2007 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002008 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002009 struct msm_drm_private *priv;
2010 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002011 enum drm_plane_type type;
Clarence Ipc47a0692016-10-11 10:54:17 -04002012 int ret = -EINVAL;
Clarence Ip4c1d9772016-06-26 09:35:38 -04002013
2014 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002015 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002016 goto exit;
2017 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002018
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002019 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04002020 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002021 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04002022 goto exit;
2023 }
2024
2025 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002026 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04002027 goto exit;
2028 }
2029 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002030
Clarence Ip4c1d9772016-06-26 09:35:38 -04002031 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002032 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002033 goto exit;
2034 }
2035
Clarence Ip4ce59322016-06-26 22:27:51 -04002036 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002037 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
2038 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002039 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002040 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04002041 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002042 }
2043
Clarence Ip4c1d9772016-06-26 09:35:38 -04002044 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002045 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002046 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04002047 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002048
Clarence Ip4c1d9772016-06-26 09:35:38 -04002049 /* initialize underlying h/w driver */
2050 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
2051 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002052 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002053 ret = PTR_ERR(psde->pipe_hw);
2054 goto clean_plane;
2055 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002056 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002057 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002058 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04002059
2060 /* cache features mask for later */
2061 psde->features = psde->pipe_hw->cap->features;
2062 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04002063 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002064 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04002065 goto clean_sspp;
2066 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04002067
abeykun48f407a2016-08-25 12:06:44 -04002068 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
2069 psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
2070 GFP_KERNEL);
2071 if (!psde->scaler3_cfg) {
2072 SDE_ERROR("[%u]failed to allocate scale struct\n",
2073 pipe);
2074 ret = -ENOMEM;
2075 goto clean_sspp;
2076 }
2077 }
2078
Clarence Ip4c1d9772016-06-26 09:35:38 -04002079 /* add plane to DRM framework */
Clarence Ipea3d6262016-07-15 16:20:11 -04002080 psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
2081 psde->formats,
2082 0,
2083 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002084
Clarence Ip4c1d9772016-06-26 09:35:38 -04002085 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002086 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002087 goto clean_sspp;
2088 }
2089
2090 if (psde->features & BIT(SDE_SSPP_CURSOR))
2091 type = DRM_PLANE_TYPE_CURSOR;
2092 else if (primary_plane)
2093 type = DRM_PLANE_TYPE_PRIMARY;
2094 else
2095 type = DRM_PLANE_TYPE_OVERLAY;
Clarence Ip2bbf7b32016-09-23 15:07:16 -04002096 ret = drm_universal_plane_init(dev, plane, possible_crtcs,
2097 &sde_plane_funcs, psde->formats, psde->nformats, type);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002098 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04002099 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002100
Clarence Ip4c1d9772016-06-26 09:35:38 -04002101 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002102 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002103
Clarence Ipaa0faf42016-05-30 12:07:48 -04002104 msm_property_init(&psde->property_info, &plane->base, dev,
2105 priv->plane_property, psde->property_data,
2106 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
2107 sizeof(struct sde_plane_state));
2108
Clarence Ipc47a0692016-10-11 10:54:17 -04002109 _sde_plane_install_properties(plane, kms->catalog);
Clarence Ip5e2a9222016-06-26 22:38:24 -04002110
Clarence Ip4ce59322016-06-26 22:27:51 -04002111 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04002112 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04002113
Clarence Ip730e7192016-06-26 22:45:09 -04002114 mutex_init(&psde->lock);
2115
Clarence Ip4ce59322016-06-26 22:27:51 -04002116 _sde_plane_init_debugfs(psde, kms);
2117
Clarence Ip13a8cf42016-09-29 17:27:47 -04002118 DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002119 return plane;
2120
Clarence Ip4c1d9772016-06-26 09:35:38 -04002121clean_sspp:
2122 if (psde && psde->pipe_hw)
2123 sde_hw_sspp_destroy(psde->pipe_hw);
abeykun48f407a2016-08-25 12:06:44 -04002124
2125 if (psde && psde->scaler3_cfg)
2126 kfree(psde->scaler3_cfg);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002127clean_plane:
2128 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04002129exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002130 return ERR_PTR(ret);
2131}