blob: 6ae7ce4ac63eb9b6a65ecf8ae0a49093579ae597 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
Ralf Baechle010b8532006-01-29 18:42:08 +00005 * Copyright (C) 1994 - 2006 Ralf Baechle
Ralf Baechle41943182005-05-05 16:45:59 +00006 * Copyright (C) 2003, 2004 Maciej W. Rozycki
Ralf Baechle41943182005-05-05 16:45:59 +00007 * Copyright (C) 2001, 2004 MIPS Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010017#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/stddef.h>
Paul Gortmaker73bc2562011-07-23 16:30:40 -040019#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechle57599062007-02-18 19:07:31 +000021#include <asm/bugs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
David Daney654f57b2008-09-23 00:07:16 -070025#include <asm/watch.h>
Paul Gortmaker06372a62011-07-23 16:26:41 -040026#include <asm/elf.h>
Chris Dearmana074f0e2009-07-10 01:51:27 -070027#include <asm/spram.h>
David Daney949e51b2010-10-14 11:32:33 -070028#include <asm/uaccess.h>
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
Ralf Baechle982f6ff2009-09-17 02:25:07 +020037void (*cpu_wait)(void);
Wu Zhangjinf8ede0f2009-11-17 01:32:59 +080038EXPORT_SYMBOL(cpu_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090048 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -070052}
53
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090054extern void r4k_wait(void);
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090055
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
Kevin D. Kissell8531a352008-09-09 21:48:52 +020063void r4k_wait_irqoff(void)
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090064{
65 local_irq_disable();
66 if (!need_resched())
Kevin D. Kissell8531a352008-09-09 21:48:52 +020067 __asm__(" .set push \n"
68 " .set mips3 \n"
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090069 " wait \n"
Kevin D. Kissell8531a352008-09-09 21:48:52 +020070 " .set pop \n");
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090071 local_irq_enable();
Kevin D. Kissell8531a352008-09-09 21:48:52 +020072 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070074}
75
Ralf Baechle5a812992007-07-17 18:49:48 +010076/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
Manuel Lauss2882b0c2009-08-22 18:09:27 +020097/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
Pete Popov494900a2005-04-07 00:42:10 +0000102static void au1k_wait(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103{
Atsushi Nemoto60a6c372006-06-08 01:09:01 +0900104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
Ralf Baechle10f650d2005-05-25 13:32:49 +0000115 : : "r" (au1k_wait));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116}
117
Ralf Baechle982f6ff2009-09-17 02:25:07 +0200118static int __initdata nowait;
Ralf Baechle55d04df2005-07-13 19:22:45 +0000119
Atsushi Nemotof49a7472007-02-18 01:02:14 +0900120static int __init wait_disable(char *s)
Ralf Baechle55d04df2005-07-13 19:22:45 +0000121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
Kevin Cernekee0103d232010-05-02 14:43:52 -0700129static int __cpuinitdata mips_fpu_disabled;
130
131static int __init fpu_disable(char *s)
132{
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137}
138
139__setup("nofpu", fpu_disable);
140
141int __cpuinitdata mips_dsp_disabled;
142
143static int __init dsp_disable(char *s)
144{
145 cpu_data[0].ases &= ~MIPS_ASE_DSP;
146 mips_dsp_disabled = 1;
147
148 return 1;
149}
150
151__setup("nodsp", dsp_disable);
152
Atsushi Nemotoc65a5482007-11-12 02:05:18 +0900153void __init check_wait(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154{
155 struct cpuinfo_mips *c = &current_cpu_data;
156
Ralf Baechle55d04df2005-07-13 19:22:45 +0000157 if (nowait) {
Ralf Baechlec2379232006-11-30 01:14:44 +0000158 printk("Wait instruction disabled.\n");
Ralf Baechle55d04df2005-07-13 19:22:45 +0000159 return;
160 }
161
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
Shinya Kuribayashia644b272009-03-03 18:05:51 +0900177 case CPU_R5500:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 case CPU_NEVADA:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 case CPU_25KF:
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100184 case CPU_PR4450:
Kevin Cernekee602977b2010-10-16 14:22:30 -0700185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
David Daney0dd47812008-12-11 15:33:26 -0800189 case CPU_CAVIUM_OCTEON:
David Daney6f329462010-02-10 15:12:48 -0800190 case CPU_CAVIUM_OCTEON_PLUS:
David Daney0e56b382010-10-07 16:03:45 -0700191 case CPU_CAVIUM_OCTEON2:
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +0000192 case CPU_JZRISC:
Jayachandran C11d48aa2011-08-23 13:35:30 +0530193 case CPU_XLR:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +0000194 case CPU_XLP:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 cpu_wait = r4k_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 break;
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100197
Ralf Baechle5a812992007-07-17 18:49:48 +0100198 case CPU_RM7000:
199 cpu_wait = rm7k_wait_irqoff;
200 break;
201
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100202 case CPU_24K:
203 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +0100204 case CPU_1004K:
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100205 cpu_wait = r4k_wait;
206 if (read_c0_config7() & MIPS_CONF7_WII)
207 cpu_wait = r4k_wait_irqoff;
208 break;
209
210 case CPU_74K:
211 cpu_wait = r4k_wait;
212 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
213 cpu_wait = r4k_wait_irqoff;
214 break;
215
Atsushi Nemoto60a6c372006-06-08 01:09:01 +0900216 case CPU_TX49XX:
217 cpu_wait = r4k_wait_irqoff;
Atsushi Nemoto60a6c372006-06-08 01:09:01 +0900218 break;
Manuel Lauss270717a2009-03-25 17:49:28 +0100219 case CPU_ALCHEMY:
Manuel Lauss0c694de2008-12-21 09:26:23 +0100220 cpu_wait = au1k_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 break;
Ralf Baechlec8eae712007-06-12 13:04:09 +0100222 case CPU_20KC:
223 /*
224 * WAIT on Rev1.0 has E1, E2, E3 and E16.
225 * WAIT on Rev2.0 and Rev3.0 has E16.
226 * Rev3.1 WAIT is nop, why bother
227 */
228 if ((c->processor_id & 0xff) <= 0x64)
229 break;
230
Ralf Baechle50da4692007-09-14 19:08:43 +0100231 /*
232 * Another rev is incremeting c0_count at a reduced clock
233 * rate while in WAIT mode. So we basically have the choice
234 * between using the cp0 timer as clocksource or avoiding
235 * the WAIT instruction. Until more details are known,
236 * disable the use of WAIT for 20Kc entirely.
237 cpu_wait = r4k_wait;
238 */
Ralf Baechlec8eae712007-06-12 13:04:09 +0100239 break;
Ralf Baechle441ee342006-06-02 11:48:11 +0100240 case CPU_RM9000:
Ralf Baechlec2379232006-11-30 01:14:44 +0000241 if ((c->processor_id & 0x00ff) >= 0x40)
Ralf Baechle441ee342006-06-02 11:48:11 +0100242 cpu_wait = r4k_wait;
Ralf Baechle441ee342006-06-02 11:48:11 +0100243 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 default:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 break;
246 }
247}
248
Marc St-Jean9267a302007-06-14 15:55:31 -0600249static inline void check_errata(void)
250{
251 struct cpuinfo_mips *c = &current_cpu_data;
252
253 switch (c->cputype) {
254 case CPU_34K:
255 /*
256 * Erratum "RPS May Cause Incorrect Instruction Execution"
257 * This code only handles VPE0, any SMP/SMTC/RTOS code
258 * making use of VPE1 will be responsable for that VPE.
259 */
260 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
261 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
262 break;
263 default:
264 break;
265 }
266}
267
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268void __init check_bugs32(void)
269{
Marc St-Jean9267a302007-06-14 15:55:31 -0600270 check_errata();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271}
272
273/*
274 * Probe whether cpu has config register by trying to play with
275 * alternate cache bit and see whether it matters.
276 * It's used by cpu_probe to distinguish between R3000A and R3081.
277 */
278static inline int cpu_has_confreg(void)
279{
280#ifdef CONFIG_CPU_R3000
281 extern unsigned long r3k_cache_size(unsigned long);
282 unsigned long size1, size2;
283 unsigned long cfg = read_c0_conf();
284
285 size1 = r3k_cache_size(ST0_ISC);
286 write_c0_conf(cfg ^ R30XX_CONF_AC);
287 size2 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg);
289 return size1 != size2;
290#else
291 return 0;
292#endif
293}
294
Robert Millanc094c992011-04-18 11:37:55 -0700295static inline void set_elf_platform(int cpu, const char *plat)
296{
297 if (cpu == 0)
298 __elf_platform = plat;
299}
300
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301/*
302 * Get the FPU Implementation/Revision.
303 */
304static inline unsigned long cpu_get_fpu_id(void)
305{
306 unsigned long tmp, fpu_id;
307
308 tmp = read_c0_status();
309 __enable_fpu();
310 fpu_id = read_32bit_cp1_register(CP1_REVISION);
311 write_c0_status(tmp);
312 return fpu_id;
313}
314
315/*
316 * Check the CPU has an FPU the official way.
317 */
318static inline int __cpu_has_fpu(void)
319{
320 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
321}
322
Guenter Roeck91dfc422010-02-02 08:52:20 -0800323static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
324{
325#ifdef __NEED_VMBITS_PROBE
David Daney5b7efa82010-02-08 12:27:00 -0800326 write_c0_entryhi(0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800327 back_to_back_c0_hazard();
David Daney5b7efa82010-02-08 12:27:00 -0800328 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800329#endif
330}
331
Ralf Baechle02cf2112005-10-01 13:06:32 +0100332#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 | MIPS_CPU_COUNTER)
334
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000335static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336{
337 switch (c->processor_id & 0xff00) {
338 case PRID_IMP_R2000:
339 c->cputype = CPU_R2000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000340 __cpu_name[cpu] = "R2000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341 c->isa_level = MIPS_CPU_ISA_I;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100342 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500343 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 if (__cpu_has_fpu())
345 c->options |= MIPS_CPU_FPU;
346 c->tlbsize = 64;
347 break;
348 case PRID_IMP_R3000:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000349 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
350 if (cpu_has_confreg()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 c->cputype = CPU_R3081E;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000352 __cpu_name[cpu] = "R3081";
353 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354 c->cputype = CPU_R3000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000355 __cpu_name[cpu] = "R3000A";
356 }
357 break;
358 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 c->cputype = CPU_R3000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000360 __cpu_name[cpu] = "R3000";
361 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 c->isa_level = MIPS_CPU_ISA_I;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100363 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500364 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 if (__cpu_has_fpu())
366 c->options |= MIPS_CPU_FPU;
367 c->tlbsize = 64;
368 break;
369 case PRID_IMP_R4000:
370 if (read_c0_config() & CONF_SC) {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000371 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 c->cputype = CPU_R4400PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000373 __cpu_name[cpu] = "R4400PC";
374 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 c->cputype = CPU_R4000PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000376 __cpu_name[cpu] = "R4000PC";
377 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 } else {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000379 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 c->cputype = CPU_R4400SC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000381 __cpu_name[cpu] = "R4400SC";
382 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383 c->cputype = CPU_R4000SC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000384 __cpu_name[cpu] = "R4000SC";
385 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 }
387
388 c->isa_level = MIPS_CPU_ISA_III;
389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500390 MIPS_CPU_WATCH | MIPS_CPU_VCE |
391 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 c->tlbsize = 48;
393 break;
394 case PRID_IMP_VR41XX:
395 switch (c->processor_id & 0xf0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 case PRID_REV_VR4111:
397 c->cputype = CPU_VR4111;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000398 __cpu_name[cpu] = "NEC VR4111";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 case PRID_REV_VR4121:
401 c->cputype = CPU_VR4121;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000402 __cpu_name[cpu] = "NEC VR4121";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 break;
404 case PRID_REV_VR4122:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000405 if ((c->processor_id & 0xf) < 0x3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406 c->cputype = CPU_VR4122;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000407 __cpu_name[cpu] = "NEC VR4122";
408 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 c->cputype = CPU_VR4181A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000410 __cpu_name[cpu] = "NEC VR4181A";
411 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 break;
413 case PRID_REV_VR4130:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000414 if ((c->processor_id & 0xf) < 0x4) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 c->cputype = CPU_VR4131;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000416 __cpu_name[cpu] = "NEC VR4131";
417 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 c->cputype = CPU_VR4133;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000419 __cpu_name[cpu] = "NEC VR4133";
420 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 break;
422 default:
423 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
424 c->cputype = CPU_VR41XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000425 __cpu_name[cpu] = "NEC Vr41xx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 break;
427 }
428 c->isa_level = MIPS_CPU_ISA_III;
429 c->options = R4K_OPTS;
430 c->tlbsize = 32;
431 break;
432 case PRID_IMP_R4300:
433 c->cputype = CPU_R4300;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000434 __cpu_name[cpu] = "R4300";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 c->isa_level = MIPS_CPU_ISA_III;
436 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500437 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 c->tlbsize = 32;
439 break;
440 case PRID_IMP_R4600:
441 c->cputype = CPU_R4600;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000442 __cpu_name[cpu] = "R4600";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 c->isa_level = MIPS_CPU_ISA_III;
Thiemo Seufer075e7502005-07-27 21:48:12 +0000444 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
445 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 c->tlbsize = 48;
447 break;
448 #if 0
Steven J. Hill03751e72012-05-10 23:21:18 -0500449 case PRID_IMP_R4650:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 /*
451 * This processor doesn't have an MMU, so it's not
452 * "real easy" to run Linux on it. It is left purely
453 * for documentation. Commented out because it shares
454 * it's c0_prid id number with the TX3900.
455 */
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000456 c->cputype = CPU_R4650;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000457 __cpu_name[cpu] = "R4650";
Steven J. Hill03751e72012-05-10 23:21:18 -0500458 c->isa_level = MIPS_CPU_ISA_III;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
Steven J. Hill03751e72012-05-10 23:21:18 -0500460 c->tlbsize = 48;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461 break;
462 #endif
463 case PRID_IMP_TX39:
464 c->isa_level = MIPS_CPU_ISA_I;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100465 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466
467 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
468 c->cputype = CPU_TX3927;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000469 __cpu_name[cpu] = "TX3927";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 c->tlbsize = 64;
471 } else {
472 switch (c->processor_id & 0xff) {
473 case PRID_REV_TX3912:
474 c->cputype = CPU_TX3912;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000475 __cpu_name[cpu] = "TX3912";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476 c->tlbsize = 32;
477 break;
478 case PRID_REV_TX3922:
479 c->cputype = CPU_TX3922;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000480 __cpu_name[cpu] = "TX3922";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 c->tlbsize = 64;
482 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483 }
484 }
485 break;
486 case PRID_IMP_R4700:
487 c->cputype = CPU_R4700;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000488 __cpu_name[cpu] = "R4700";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 c->isa_level = MIPS_CPU_ISA_III;
490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500491 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 c->tlbsize = 48;
493 break;
494 case PRID_IMP_TX49:
495 c->cputype = CPU_TX49XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000496 __cpu_name[cpu] = "R49XX";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 c->isa_level = MIPS_CPU_ISA_III;
498 c->options = R4K_OPTS | MIPS_CPU_LLSC;
499 if (!(c->processor_id & 0x08))
500 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
501 c->tlbsize = 48;
502 break;
503 case PRID_IMP_R5000:
504 c->cputype = CPU_R5000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000505 __cpu_name[cpu] = "R5000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 c->isa_level = MIPS_CPU_ISA_IV;
507 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500508 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 c->tlbsize = 48;
510 break;
511 case PRID_IMP_R5432:
512 c->cputype = CPU_R5432;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000513 __cpu_name[cpu] = "R5432";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 c->isa_level = MIPS_CPU_ISA_IV;
515 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500516 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 c->tlbsize = 48;
518 break;
519 case PRID_IMP_R5500:
520 c->cputype = CPU_R5500;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000521 __cpu_name[cpu] = "R5500";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522 c->isa_level = MIPS_CPU_ISA_IV;
523 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500524 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 c->tlbsize = 48;
526 break;
527 case PRID_IMP_NEVADA:
528 c->cputype = CPU_NEVADA;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000529 __cpu_name[cpu] = "Nevada";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 c->isa_level = MIPS_CPU_ISA_IV;
531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500532 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 c->tlbsize = 48;
534 break;
535 case PRID_IMP_R6000:
536 c->cputype = CPU_R6000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000537 __cpu_name[cpu] = "R6000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 c->isa_level = MIPS_CPU_ISA_II;
539 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500540 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 c->tlbsize = 32;
542 break;
543 case PRID_IMP_R6000A:
544 c->cputype = CPU_R6000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000545 __cpu_name[cpu] = "R6000A";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546 c->isa_level = MIPS_CPU_ISA_II;
547 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500548 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 c->tlbsize = 32;
550 break;
551 case PRID_IMP_RM7000:
552 c->cputype = CPU_RM7000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000553 __cpu_name[cpu] = "RM7000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 c->isa_level = MIPS_CPU_ISA_IV;
555 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500556 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557 /*
558 * Undocumented RM7000: Bit 29 in the info register of
559 * the RM7000 v2.0 indicates if the TLB has 48 or 64
560 * entries.
561 *
562 * 29 1 => 64 entry JTLB
563 * 0 => 48 entry JTLB
564 */
565 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
566 break;
567 case PRID_IMP_RM9000:
568 c->cputype = CPU_RM9000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000569 __cpu_name[cpu] = "RM9000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570 c->isa_level = MIPS_CPU_ISA_IV;
571 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500572 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 /*
574 * Bit 29 in the info register of the RM9000
575 * indicates if the TLB has 48 or 64 entries.
576 *
577 * 29 1 => 64 entry JTLB
578 * 0 => 48 entry JTLB
579 */
580 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
581 break;
582 case PRID_IMP_R8000:
583 c->cputype = CPU_R8000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000584 __cpu_name[cpu] = "RM8000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585 c->isa_level = MIPS_CPU_ISA_IV;
586 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500587 MIPS_CPU_FPU | MIPS_CPU_32FPR |
588 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
590 break;
591 case PRID_IMP_R10000:
592 c->cputype = CPU_R10000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000593 __cpu_name[cpu] = "R10000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 c->isa_level = MIPS_CPU_ISA_IV;
Ralf Baechle8b366122005-11-22 17:53:59 +0000595 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500596 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500598 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 c->tlbsize = 64;
600 break;
601 case PRID_IMP_R12000:
602 c->cputype = CPU_R12000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000603 __cpu_name[cpu] = "R12000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 c->isa_level = MIPS_CPU_ISA_IV;
Ralf Baechle8b366122005-11-22 17:53:59 +0000605 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500606 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500608 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 c->tlbsize = 64;
610 break;
Kumba44d921b2006-05-16 22:23:59 -0400611 case PRID_IMP_R14000:
612 c->cputype = CPU_R14000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000613 __cpu_name[cpu] = "R14000";
Kumba44d921b2006-05-16 22:23:59 -0400614 c->isa_level = MIPS_CPU_ISA_IV;
615 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500616 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Kumba44d921b2006-05-16 22:23:59 -0400617 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500618 MIPS_CPU_LLSC;
Kumba44d921b2006-05-16 22:23:59 -0400619 c->tlbsize = 64;
620 break;
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800621 case PRID_IMP_LOONGSON2:
622 c->cputype = CPU_LOONGSON2;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000623 __cpu_name[cpu] = "ICT Loongson-2";
Robert Millan5aac1e82011-04-16 11:29:29 -0700624
625 switch (c->processor_id & PRID_REV_MASK) {
626 case PRID_REV_LOONGSON2E:
627 set_elf_platform(cpu, "loongson2e");
628 break;
629 case PRID_REV_LOONGSON2F:
630 set_elf_platform(cpu, "loongson2f");
631 break;
632 }
633
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800634 c->isa_level = MIPS_CPU_ISA_III;
635 c->options = R4K_OPTS |
636 MIPS_CPU_FPU | MIPS_CPU_LLSC |
637 MIPS_CPU_32FPR;
638 c->tlbsize = 64;
639 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640 }
641}
642
Ralf Baechle234fcd12008-03-08 09:56:28 +0000643static char unknown_isa[] __cpuinitdata = KERN_ERR \
Ralf Baechleb4672d32005-12-08 14:04:24 +0000644 "Unsupported ISA type, c0.config0: %d.";
645
Ralf Baechle41943182005-05-05 16:45:59 +0000646static inline unsigned int decode_config0(struct cpuinfo_mips *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647{
Ralf Baechle41943182005-05-05 16:45:59 +0000648 unsigned int config0;
649 int isa;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
Ralf Baechle41943182005-05-05 16:45:59 +0000651 config0 = read_c0_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652
Ralf Baechle41943182005-05-05 16:45:59 +0000653 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
Ralf Baechle02cf2112005-10-01 13:06:32 +0100654 c->options |= MIPS_CPU_TLB;
Ralf Baechle41943182005-05-05 16:45:59 +0000655 isa = (config0 & MIPS_CONF_AT) >> 13;
656 switch (isa) {
657 case 0:
Thiemo Seufer3a01c492006-07-03 13:30:01 +0100658 switch ((config0 & MIPS_CONF_AR) >> 10) {
Ralf Baechleb4672d32005-12-08 14:04:24 +0000659 case 0:
660 c->isa_level = MIPS_CPU_ISA_M32R1;
661 break;
662 case 1:
663 c->isa_level = MIPS_CPU_ISA_M32R2;
664 break;
665 default:
666 goto unknown;
667 }
Ralf Baechle41943182005-05-05 16:45:59 +0000668 break;
669 case 2:
Thiemo Seufer3a01c492006-07-03 13:30:01 +0100670 switch ((config0 & MIPS_CONF_AR) >> 10) {
Ralf Baechleb4672d32005-12-08 14:04:24 +0000671 case 0:
672 c->isa_level = MIPS_CPU_ISA_M64R1;
673 break;
674 case 1:
675 c->isa_level = MIPS_CPU_ISA_M64R2;
676 break;
677 default:
678 goto unknown;
679 }
Ralf Baechle41943182005-05-05 16:45:59 +0000680 break;
681 default:
Ralf Baechleb4672d32005-12-08 14:04:24 +0000682 goto unknown;
Ralf Baechle41943182005-05-05 16:45:59 +0000683 }
684
685 return config0 & MIPS_CONF_M;
Ralf Baechleb4672d32005-12-08 14:04:24 +0000686
687unknown:
688 panic(unknown_isa, config0);
Ralf Baechle41943182005-05-05 16:45:59 +0000689}
690
691static inline unsigned int decode_config1(struct cpuinfo_mips *c)
692{
693 unsigned int config1;
694
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 config1 = read_c0_config1();
Ralf Baechle41943182005-05-05 16:45:59 +0000696
697 if (config1 & MIPS_CONF1_MD)
698 c->ases |= MIPS_ASE_MDMX;
699 if (config1 & MIPS_CONF1_WR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 c->options |= MIPS_CPU_WATCH;
Ralf Baechle41943182005-05-05 16:45:59 +0000701 if (config1 & MIPS_CONF1_CA)
702 c->ases |= MIPS_ASE_MIPS16;
703 if (config1 & MIPS_CONF1_EP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 c->options |= MIPS_CPU_EJTAG;
Ralf Baechle41943182005-05-05 16:45:59 +0000705 if (config1 & MIPS_CONF1_FP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 c->options |= MIPS_CPU_FPU;
707 c->options |= MIPS_CPU_32FPR;
708 }
Ralf Baechle41943182005-05-05 16:45:59 +0000709 if (cpu_has_tlb)
710 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
711
712 return config1 & MIPS_CONF_M;
713}
714
715static inline unsigned int decode_config2(struct cpuinfo_mips *c)
716{
717 unsigned int config2;
718
719 config2 = read_c0_config2();
720
721 if (config2 & MIPS_CONF2_SL)
722 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
723
724 return config2 & MIPS_CONF_M;
725}
726
727static inline unsigned int decode_config3(struct cpuinfo_mips *c)
728{
729 unsigned int config3;
730
731 config3 = read_c0_config3();
732
733 if (config3 & MIPS_CONF3_SM)
734 c->ases |= MIPS_ASE_SMARTMIPS;
Ralf Baechlee50c0a82005-05-31 11:49:19 +0000735 if (config3 & MIPS_CONF3_DSP)
736 c->ases |= MIPS_ASE_DSP;
Ralf Baechle8f406112005-07-14 07:34:18 +0000737 if (config3 & MIPS_CONF3_VINT)
738 c->options |= MIPS_CPU_VINT;
739 if (config3 & MIPS_CONF3_VEIC)
740 c->options |= MIPS_CPU_VEIC;
741 if (config3 & MIPS_CONF3_MT)
Steven J. Hill03751e72012-05-10 23:21:18 -0500742 c->ases |= MIPS_ASE_MIPSMT;
Ralf Baechlea3692022007-07-10 17:33:02 +0100743 if (config3 & MIPS_CONF3_ULRI)
744 c->options |= MIPS_CPU_ULRI;
Ralf Baechle41943182005-05-05 16:45:59 +0000745
746 return config3 & MIPS_CONF_M;
747}
748
David Daney1b362e32010-01-22 14:41:15 -0800749static inline unsigned int decode_config4(struct cpuinfo_mips *c)
750{
751 unsigned int config4;
752
753 config4 = read_c0_config4();
754
755 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
756 && cpu_has_tlb)
757 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
758
David Daneye77c32f2010-12-21 14:19:09 -0800759 c->kscratch_mask = (config4 >> 16) & 0xff;
760
David Daney1b362e32010-01-22 14:41:15 -0800761 return config4 & MIPS_CONF_M;
762}
763
Ralf Baechle234fcd12008-03-08 09:56:28 +0000764static void __cpuinit decode_configs(struct cpuinfo_mips *c)
Ralf Baechle41943182005-05-05 16:45:59 +0000765{
Ralf Baechle558ce122008-10-29 12:33:34 +0000766 int ok;
767
Ralf Baechle41943182005-05-05 16:45:59 +0000768 /* MIPS32 or MIPS64 compliant CPU. */
Ralf Baechle02cf2112005-10-01 13:06:32 +0100769 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
Steven J. Hill03751e72012-05-10 23:21:18 -0500770 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
Ralf Baechle41943182005-05-05 16:45:59 +0000771
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
773
Ralf Baechle558ce122008-10-29 12:33:34 +0000774 ok = decode_config0(c); /* Read Config registers. */
775 BUG_ON(!ok); /* Arch spec violation! */
776 if (ok)
777 ok = decode_config1(c);
778 if (ok)
779 ok = decode_config2(c);
780 if (ok)
781 ok = decode_config3(c);
David Daney1b362e32010-01-22 14:41:15 -0800782 if (ok)
783 ok = decode_config4(c);
Ralf Baechle558ce122008-10-29 12:33:34 +0000784
785 mips_probe_watch_registers(c);
David Daney0c2f4552010-07-26 14:29:37 -0700786
787 if (cpu_has_mips_r2)
788 c->core = read_c0_ebase() & 0x3ff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789}
790
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000791static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792{
Ralf Baechle41943182005-05-05 16:45:59 +0000793 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 switch (c->processor_id & 0xff00) {
795 case PRID_IMP_4KC:
796 c->cputype = CPU_4KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000797 __cpu_name[cpu] = "MIPS 4Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 break;
799 case PRID_IMP_4KEC:
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000800 case PRID_IMP_4KECR2:
801 c->cputype = CPU_4KEC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000802 __cpu_name[cpu] = "MIPS 4KEc";
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000803 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 case PRID_IMP_4KSC:
Ralf Baechle8afcb5d2005-10-04 15:01:26 +0100805 case PRID_IMP_4KSD:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806 c->cputype = CPU_4KSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000807 __cpu_name[cpu] = "MIPS 4KSc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 break;
809 case PRID_IMP_5KC:
810 c->cputype = CPU_5KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000811 __cpu_name[cpu] = "MIPS 5Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812 break;
813 case PRID_IMP_20KC:
814 c->cputype = CPU_20KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000815 __cpu_name[cpu] = "MIPS 20Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 break;
817 case PRID_IMP_24K:
Ralf Baechlee50c0a82005-05-31 11:49:19 +0000818 case PRID_IMP_24KE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 c->cputype = CPU_24K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000820 __cpu_name[cpu] = "MIPS 24Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821 break;
822 case PRID_IMP_25KF:
823 c->cputype = CPU_25KF;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000824 __cpu_name[cpu] = "MIPS 25Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 break;
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000826 case PRID_IMP_34K:
827 c->cputype = CPU_34K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000828 __cpu_name[cpu] = "MIPS 34Kc";
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000829 break;
Chris Dearmanc6209532006-05-02 14:08:46 +0100830 case PRID_IMP_74K:
831 c->cputype = CPU_74K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000832 __cpu_name[cpu] = "MIPS 74Kc";
Chris Dearmanc6209532006-05-02 14:08:46 +0100833 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100834 case PRID_IMP_1004K:
835 c->cputype = CPU_1004K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000836 __cpu_name[cpu] = "MIPS 1004Kc";
Ralf Baechle39b8d522008-04-28 17:14:26 +0100837 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 }
Chris Dearman0b6d4972007-09-13 12:32:02 +0100839
840 spram_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841}
842
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000843static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844{
Ralf Baechle41943182005-05-05 16:45:59 +0000845 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 switch (c->processor_id & 0xff00) {
847 case PRID_IMP_AU1_REV1:
848 case PRID_IMP_AU1_REV2:
Manuel Lauss270717a2009-03-25 17:49:28 +0100849 c->cputype = CPU_ALCHEMY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 switch ((c->processor_id >> 24) & 0xff) {
851 case 0:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000852 __cpu_name[cpu] = "Au1000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 break;
854 case 1:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000855 __cpu_name[cpu] = "Au1500";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 break;
857 case 2:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000858 __cpu_name[cpu] = "Au1100";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 break;
860 case 3:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000861 __cpu_name[cpu] = "Au1550";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 break;
Pete Popove3ad1c22005-03-01 06:33:16 +0000863 case 4:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000864 __cpu_name[cpu] = "Au1200";
Manuel Lauss270717a2009-03-25 17:49:28 +0100865 if ((c->processor_id & 0xff) == 2)
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000866 __cpu_name[cpu] = "Au1250";
Manuel Lauss237cfee2007-12-06 09:07:55 +0100867 break;
868 case 5:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000869 __cpu_name[cpu] = "Au1210";
Pete Popove3ad1c22005-03-01 06:33:16 +0000870 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 default:
Manuel Lauss270717a2009-03-25 17:49:28 +0100872 __cpu_name[cpu] = "Au1xxx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873 break;
874 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 break;
876 }
877}
878
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000879static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880{
Ralf Baechle41943182005-05-05 16:45:59 +0000881 decode_configs(c);
Ralf Baechle02cf2112005-10-01 13:06:32 +0100882
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 switch (c->processor_id & 0xff00) {
884 case PRID_IMP_SB1:
885 c->cputype = CPU_SB1;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000886 __cpu_name[cpu] = "SiByte SB1";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887 /* FPU in pass1 is known to have issues. */
Ralf Baechleaa323742006-05-29 00:02:12 +0100888 if ((c->processor_id & 0xff) < 0x02)
Ralf Baechle010b8532006-01-29 18:42:08 +0000889 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 break;
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700891 case PRID_IMP_SB1A:
892 c->cputype = CPU_SB1A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000893 __cpu_name[cpu] = "SiByte SB1A";
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700894 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895 }
896}
897
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000898static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899{
Ralf Baechle41943182005-05-05 16:45:59 +0000900 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 switch (c->processor_id & 0xff00) {
902 case PRID_IMP_SR71000:
903 c->cputype = CPU_SR71000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000904 __cpu_name[cpu] = "Sandcraft SR71000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 c->scache.ways = 8;
906 c->tlbsize = 64;
907 break;
908 }
909}
910
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000911static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
Pete Popovbdf21b12005-07-14 17:47:57 +0000912{
913 decode_configs(c);
914 switch (c->processor_id & 0xff00) {
915 case PRID_IMP_PR4450:
916 c->cputype = CPU_PR4450;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000917 __cpu_name[cpu] = "Philips PR4450";
Ralf Baechlee7958bb2005-12-08 13:00:20 +0000918 c->isa_level = MIPS_CPU_ISA_M32R1;
Pete Popovbdf21b12005-07-14 17:47:57 +0000919 break;
Pete Popovbdf21b12005-07-14 17:47:57 +0000920 }
921}
922
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000923static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200924{
925 decode_configs(c);
926 switch (c->processor_id & 0xff00) {
Kevin Cernekee190fca32010-11-23 10:26:45 -0800927 case PRID_IMP_BMIPS32_REV4:
928 case PRID_IMP_BMIPS32_REV8:
Kevin Cernekee602977b2010-10-16 14:22:30 -0700929 c->cputype = CPU_BMIPS32;
930 __cpu_name[cpu] = "Broadcom BMIPS32";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700931 set_elf_platform(cpu, "bmips32");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200932 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700933 case PRID_IMP_BMIPS3300:
934 case PRID_IMP_BMIPS3300_ALT:
935 case PRID_IMP_BMIPS3300_BUG:
936 c->cputype = CPU_BMIPS3300;
937 __cpu_name[cpu] = "Broadcom BMIPS3300";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700938 set_elf_platform(cpu, "bmips3300");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200939 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700940 case PRID_IMP_BMIPS43XX: {
941 int rev = c->processor_id & 0xff;
942
943 if (rev >= PRID_REV_BMIPS4380_LO &&
944 rev <= PRID_REV_BMIPS4380_HI) {
945 c->cputype = CPU_BMIPS4380;
946 __cpu_name[cpu] = "Broadcom BMIPS4380";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700947 set_elf_platform(cpu, "bmips4380");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700948 } else {
949 c->cputype = CPU_BMIPS4350;
950 __cpu_name[cpu] = "Broadcom BMIPS4350";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700951 set_elf_platform(cpu, "bmips4350");
Maxime Bizon0de663e2009-08-18 13:23:37 +0100952 }
953 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200954 }
Kevin Cernekee602977b2010-10-16 14:22:30 -0700955 case PRID_IMP_BMIPS5000:
956 c->cputype = CPU_BMIPS5000;
957 __cpu_name[cpu] = "Broadcom BMIPS5000";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700958 set_elf_platform(cpu, "bmips5000");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700959 c->options |= MIPS_CPU_ULRI;
960 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700961 }
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200962}
963
David Daney0dd47812008-12-11 15:33:26 -0800964static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
965{
966 decode_configs(c);
967 switch (c->processor_id & 0xff00) {
968 case PRID_IMP_CAVIUM_CN38XX:
969 case PRID_IMP_CAVIUM_CN31XX:
970 case PRID_IMP_CAVIUM_CN30XX:
David Daney6f329462010-02-10 15:12:48 -0800971 c->cputype = CPU_CAVIUM_OCTEON;
972 __cpu_name[cpu] = "Cavium Octeon";
973 goto platform;
David Daney0dd47812008-12-11 15:33:26 -0800974 case PRID_IMP_CAVIUM_CN58XX:
975 case PRID_IMP_CAVIUM_CN56XX:
976 case PRID_IMP_CAVIUM_CN50XX:
977 case PRID_IMP_CAVIUM_CN52XX:
David Daney6f329462010-02-10 15:12:48 -0800978 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
979 __cpu_name[cpu] = "Cavium Octeon+";
980platform:
Robert Millanc094c992011-04-18 11:37:55 -0700981 set_elf_platform(cpu, "octeon");
David Daney0dd47812008-12-11 15:33:26 -0800982 break;
David Daneya1431b62011-09-24 02:29:54 +0200983 case PRID_IMP_CAVIUM_CN61XX:
David Daney0e56b382010-10-07 16:03:45 -0700984 case PRID_IMP_CAVIUM_CN63XX:
David Daneya1431b62011-09-24 02:29:54 +0200985 case PRID_IMP_CAVIUM_CN66XX:
986 case PRID_IMP_CAVIUM_CN68XX:
David Daney0e56b382010-10-07 16:03:45 -0700987 c->cputype = CPU_CAVIUM_OCTEON2;
988 __cpu_name[cpu] = "Cavium Octeon II";
Robert Millanc094c992011-04-18 11:37:55 -0700989 set_elf_platform(cpu, "octeon2");
David Daney0e56b382010-10-07 16:03:45 -0700990 break;
David Daney0dd47812008-12-11 15:33:26 -0800991 default:
992 printk(KERN_INFO "Unknown Octeon chip!\n");
993 c->cputype = CPU_UNKNOWN;
994 break;
995 }
996}
997
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +0000998static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
999{
1000 decode_configs(c);
1001 /* JZRISC does not implement the CP0 counter. */
1002 c->options &= ~MIPS_CPU_COUNTER;
1003 switch (c->processor_id & 0xff00) {
1004 case PRID_IMP_JZRISC:
1005 c->cputype = CPU_JZRISC;
1006 __cpu_name[cpu] = "Ingenic JZRISC";
1007 break;
1008 default:
1009 panic("Unknown Ingenic Processor ID!");
1010 break;
1011 }
1012}
1013
Jayachandran Ca7117c62011-05-11 12:04:58 +05301014static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1015{
1016 decode_configs(c);
1017
Manuel Lauss809f36c2011-11-01 20:03:30 +01001018 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1019 c->cputype = CPU_ALCHEMY;
1020 __cpu_name[cpu] = "Au1300";
1021 /* following stuff is not for Alchemy */
1022 return;
1023 }
1024
Jayachandran Ca7117c62011-05-11 12:04:58 +05301025 c->options = (MIPS_CPU_TLB |
1026 MIPS_CPU_4KEX |
1027 MIPS_CPU_COUNTER |
1028 MIPS_CPU_DIVEC |
1029 MIPS_CPU_WATCH |
1030 MIPS_CPU_EJTAG |
1031 MIPS_CPU_LLSC);
1032
1033 switch (c->processor_id & 0xff00) {
Jayachandran C2aa54b22011-11-16 00:21:29 +00001034 case PRID_IMP_NETLOGIC_XLP8XX:
1035 case PRID_IMP_NETLOGIC_XLP3XX:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001036 c->cputype = CPU_XLP;
1037 __cpu_name[cpu] = "Netlogic XLP";
1038 break;
1039
Jayachandran Ca7117c62011-05-11 12:04:58 +05301040 case PRID_IMP_NETLOGIC_XLR732:
1041 case PRID_IMP_NETLOGIC_XLR716:
1042 case PRID_IMP_NETLOGIC_XLR532:
1043 case PRID_IMP_NETLOGIC_XLR308:
1044 case PRID_IMP_NETLOGIC_XLR532C:
1045 case PRID_IMP_NETLOGIC_XLR516C:
1046 case PRID_IMP_NETLOGIC_XLR508C:
1047 case PRID_IMP_NETLOGIC_XLR308C:
1048 c->cputype = CPU_XLR;
1049 __cpu_name[cpu] = "Netlogic XLR";
1050 break;
1051
1052 case PRID_IMP_NETLOGIC_XLS608:
1053 case PRID_IMP_NETLOGIC_XLS408:
1054 case PRID_IMP_NETLOGIC_XLS404:
1055 case PRID_IMP_NETLOGIC_XLS208:
1056 case PRID_IMP_NETLOGIC_XLS204:
1057 case PRID_IMP_NETLOGIC_XLS108:
1058 case PRID_IMP_NETLOGIC_XLS104:
1059 case PRID_IMP_NETLOGIC_XLS616B:
1060 case PRID_IMP_NETLOGIC_XLS608B:
1061 case PRID_IMP_NETLOGIC_XLS416B:
1062 case PRID_IMP_NETLOGIC_XLS412B:
1063 case PRID_IMP_NETLOGIC_XLS408B:
1064 case PRID_IMP_NETLOGIC_XLS404B:
1065 c->cputype = CPU_XLR;
1066 __cpu_name[cpu] = "Netlogic XLS";
1067 break;
1068
1069 default:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001070 pr_info("Unknown Netlogic chip id [%02x]!\n",
Jayachandran Ca7117c62011-05-11 12:04:58 +05301071 c->processor_id);
1072 c->cputype = CPU_XLR;
1073 break;
1074 }
1075
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001076 if (c->cputype == CPU_XLP) {
1077 c->isa_level = MIPS_CPU_ISA_M64R2;
1078 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1079 /* This will be updated again after all threads are woken up */
1080 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1081 } else {
1082 c->isa_level = MIPS_CPU_ISA_M64R1;
1083 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1084 }
Jayachandran Ca7117c62011-05-11 12:04:58 +05301085}
1086
David Daney949e51b2010-10-14 11:32:33 -07001087#ifdef CONFIG_64BIT
1088/* For use by uaccess.h */
1089u64 __ua_limit;
1090EXPORT_SYMBOL(__ua_limit);
1091#endif
1092
Ralf Baechle9966db252007-10-11 23:46:17 +01001093const char *__cpu_name[NR_CPUS];
David Daney874fd3b2010-01-28 16:52:12 -08001094const char *__elf_platform;
Ralf Baechle9966db252007-10-11 23:46:17 +01001095
Ralf Baechle234fcd12008-03-08 09:56:28 +00001096__cpuinit void cpu_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097{
1098 struct cpuinfo_mips *c = &current_cpu_data;
Ralf Baechle9966db252007-10-11 23:46:17 +01001099 unsigned int cpu = smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100
1101 c->processor_id = PRID_IMP_UNKNOWN;
1102 c->fpu_id = FPIR_IMP_NONE;
1103 c->cputype = CPU_UNKNOWN;
1104
1105 c->processor_id = read_c0_prid();
1106 switch (c->processor_id & 0xff0000) {
1107 case PRID_COMP_LEGACY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001108 cpu_probe_legacy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 break;
1110 case PRID_COMP_MIPS:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001111 cpu_probe_mips(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112 break;
1113 case PRID_COMP_ALCHEMY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001114 cpu_probe_alchemy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115 break;
1116 case PRID_COMP_SIBYTE:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001117 cpu_probe_sibyte(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001119 case PRID_COMP_BROADCOM:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001120 cpu_probe_broadcom(c, cpu);
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001121 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122 case PRID_COMP_SANDCRAFT:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001123 cpu_probe_sandcraft(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 break;
Daniel Lairda92b0582008-03-06 09:07:18 +00001125 case PRID_COMP_NXP:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001126 cpu_probe_nxp(c, cpu);
Ralf Baechlea3dddd52006-03-11 08:18:41 +00001127 break;
David Daney0dd47812008-12-11 15:33:26 -08001128 case PRID_COMP_CAVIUM:
1129 cpu_probe_cavium(c, cpu);
1130 break;
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001131 case PRID_COMP_INGENIC:
1132 cpu_probe_ingenic(c, cpu);
1133 break;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301134 case PRID_COMP_NETLOGIC:
1135 cpu_probe_netlogic(c, cpu);
1136 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137 }
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001138
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001139 BUG_ON(!__cpu_name[cpu]);
1140 BUG_ON(c->cputype == CPU_UNKNOWN);
1141
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001142 /*
1143 * Platform code can force the cpu type to optimize code
1144 * generation. In that case be sure the cpu type is correctly
1145 * manually setup otherwise it could trigger some nasty bugs.
1146 */
1147 BUG_ON(current_cpu_type() != c->cputype);
1148
Kevin Cernekee0103d232010-05-02 14:43:52 -07001149 if (mips_fpu_disabled)
1150 c->options &= ~MIPS_CPU_FPU;
1151
1152 if (mips_dsp_disabled)
1153 c->ases &= ~MIPS_ASE_DSP;
1154
Ralf Baechle41943182005-05-05 16:45:59 +00001155 if (c->options & MIPS_CPU_FPU) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 c->fpu_id = cpu_get_fpu_id();
Ralf Baechle41943182005-05-05 16:45:59 +00001157
Ralf Baechlee7958bb2005-12-08 13:00:20 +00001158 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
Ralf Baechleb4672d32005-12-08 14:04:24 +00001159 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1160 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1161 c->isa_level == MIPS_CPU_ISA_M64R2) {
Ralf Baechle41943182005-05-05 16:45:59 +00001162 if (c->fpu_id & MIPS_FPIR_3D)
1163 c->ases |= MIPS_ASE_MIPS3D;
1164 }
1165 }
Ralf Baechle9966db252007-10-11 23:46:17 +01001166
Ralf Baechlef6771db2007-11-08 18:02:29 +00001167 if (cpu_has_mips_r2)
1168 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1169 else
1170 c->srsets = 1;
Guenter Roeck91dfc422010-02-02 08:52:20 -08001171
1172 cpu_probe_vmbits(c);
David Daney949e51b2010-10-14 11:32:33 -07001173
1174#ifdef CONFIG_64BIT
1175 if (cpu == 0)
1176 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1177#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178}
1179
Ralf Baechle234fcd12008-03-08 09:56:28 +00001180__cpuinit void cpu_report(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181{
1182 struct cpuinfo_mips *c = &current_cpu_data;
1183
Ralf Baechle9966db252007-10-11 23:46:17 +01001184 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1185 c->processor_id, cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186 if (c->options & MIPS_CPU_FPU)
Ralf Baechle9966db252007-10-11 23:46:17 +01001187 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188}