Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 12 | |
| 13 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
| 14 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 15 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 16 | #include <uapi/drm/sde_drm.h> |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 17 | #include <uapi/drm/msm_drm_pp.h> |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 18 | |
| 19 | #include "msm_prop.h" |
| 20 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 21 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 22 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 23 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 24 | #include "sde_hw_sspp.h" |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 25 | #include "sde_trace.h" |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 26 | #include "sde_crtc.h" |
Lloyd Atkinson | 8772e20 | 2016-09-26 17:52:16 -0400 | [diff] [blame] | 27 | #include "sde_vbif.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 28 | #include "sde_plane.h" |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 29 | #include "sde_color_processing.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 30 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 31 | #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\ |
| 32 | (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) |
| 33 | |
| 34 | #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\ |
| 35 | (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) |
| 36 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 37 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 38 | #define PHASE_STEP_SHIFT 21 |
| 39 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 40 | #define PHASE_RESIDUAL 15 |
| 41 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 42 | #define SHARP_STRENGTH_DEFAULT 32 |
| 43 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 44 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 45 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 46 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 47 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 48 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 49 | #define SDE_PLANE_COLOR_FILL_FLAG BIT(31) |
| 50 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 51 | /* dirty bits for update function */ |
| 52 | #define SDE_PLANE_DIRTY_RECTS 0x1 |
| 53 | #define SDE_PLANE_DIRTY_FORMAT 0x2 |
| 54 | #define SDE_PLANE_DIRTY_SHARPEN 0x4 |
| 55 | #define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF |
| 56 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 57 | /** |
| 58 | * enum sde_plane_qos - Different qos configurations for each pipe |
| 59 | * |
| 60 | * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. |
| 61 | * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. |
| 62 | * this configuration is mutually exclusive from VBLANK_CTRL. |
| 63 | * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. |
| 64 | */ |
| 65 | enum sde_plane_qos { |
| 66 | SDE_PLANE_QOS_VBLANK_CTRL = BIT(0), |
| 67 | SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), |
| 68 | SDE_PLANE_QOS_PANIC_CTRL = BIT(2), |
| 69 | }; |
| 70 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 71 | /* |
| 72 | * struct sde_plane - local sde plane structure |
| 73 | * @csc_cfg: Decoded user configuration for csc |
| 74 | * @csc_usr_ptr: Points to csc_cfg if valid user config available |
| 75 | * @csc_ptr: Points to sde_csc_cfg structure to use for current |
| 76 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 77 | struct sde_plane { |
| 78 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 79 | |
| 80 | int mmu_id; |
| 81 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 82 | struct mutex lock; |
| 83 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 84 | enum sde_sspp pipe; |
| 85 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 86 | uint32_t nformats; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 87 | uint32_t formats[64]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 88 | |
| 89 | struct sde_hw_pipe *pipe_hw; |
| 90 | struct sde_hw_pipe_cfg pipe_cfg; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 91 | struct sde_hw_sharp_cfg sharp_cfg; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 92 | struct sde_hw_scaler3_cfg *scaler3_cfg; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 93 | struct sde_hw_pipe_qos_cfg pipe_qos_cfg; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 94 | uint32_t color_fill; |
| 95 | bool is_error; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 96 | bool is_rt_pipe; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 97 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 98 | struct sde_hw_pixel_ext pixel_ext; |
| 99 | bool pixel_ext_usr; |
| 100 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 101 | struct sde_csc_cfg csc_cfg; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 102 | struct sde_csc_cfg *csc_usr_ptr; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 103 | struct sde_csc_cfg *csc_ptr; |
| 104 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 105 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 106 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 107 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 108 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 109 | struct msm_property_info property_info; |
| 110 | struct msm_property_data property_data[PLANE_PROP_COUNT]; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 111 | struct drm_property_blob *blob_info; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 112 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 113 | /* debugfs related stuff */ |
| 114 | struct dentry *debugfs_root; |
| 115 | struct sde_debugfs_regset32 debugfs_src; |
| 116 | struct sde_debugfs_regset32 debugfs_scaler; |
| 117 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 118 | }; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 119 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 120 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 121 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 122 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 123 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 124 | return state && state->fb && state->crtc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 125 | } |
| 126 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 127 | /** |
| 128 | * _sde_plane_calc_fill_level - calculate fill level of the given source format |
| 129 | * @plane: Pointer to drm plane |
| 130 | * @fmt: Pointer to source buffer format |
| 131 | * @src_wdith: width of source buffer |
| 132 | * Return: fill level corresponding to the source buffer/format or 0 if error |
| 133 | */ |
| 134 | static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, |
| 135 | const struct sde_format *fmt, u32 src_width) |
| 136 | { |
| 137 | struct sde_plane *psde; |
| 138 | u32 fixed_buff_size; |
| 139 | u32 total_fl; |
| 140 | |
| 141 | if (!plane || !fmt) { |
| 142 | SDE_ERROR("invalid arguments\n"); |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | psde = to_sde_plane(plane); |
| 147 | fixed_buff_size = psde->pipe_sblk->pixel_ram_size; |
| 148 | |
| 149 | if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) { |
| 150 | if (fmt->chroma_sample == SDE_CHROMA_420) { |
| 151 | /* NV12 */ |
| 152 | total_fl = (fixed_buff_size / 2) / |
| 153 | ((src_width + 32) * fmt->bpp); |
| 154 | } else { |
| 155 | /* non NV12 */ |
| 156 | total_fl = (fixed_buff_size) / |
| 157 | ((src_width + 32) * fmt->bpp); |
| 158 | } |
| 159 | } else { |
| 160 | total_fl = (fixed_buff_size * 2) / |
| 161 | ((src_width + 32) * fmt->bpp); |
| 162 | } |
| 163 | |
| 164 | SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n", |
| 165 | plane->base.id, psde->pipe - SSPP_VIG0, |
| 166 | fmt->base.pixel_format, src_width, total_fl); |
| 167 | |
| 168 | return total_fl; |
| 169 | } |
| 170 | |
| 171 | /** |
| 172 | * _sde_plane_get_qos_lut_linear - get linear LUT mapping |
| 173 | * @total_fl: fill level |
| 174 | * Return: LUT setting corresponding to the fill level |
| 175 | */ |
| 176 | static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl) |
| 177 | { |
| 178 | u32 qos_lut; |
| 179 | |
| 180 | if (total_fl <= 4) |
| 181 | qos_lut = 0x1B; |
| 182 | else if (total_fl <= 5) |
| 183 | qos_lut = 0x5B; |
| 184 | else if (total_fl <= 6) |
| 185 | qos_lut = 0x15B; |
| 186 | else if (total_fl <= 7) |
| 187 | qos_lut = 0x55B; |
| 188 | else if (total_fl <= 8) |
| 189 | qos_lut = 0x155B; |
| 190 | else if (total_fl <= 9) |
| 191 | qos_lut = 0x555B; |
| 192 | else if (total_fl <= 10) |
| 193 | qos_lut = 0x1555B; |
| 194 | else if (total_fl <= 11) |
| 195 | qos_lut = 0x5555B; |
| 196 | else if (total_fl <= 12) |
| 197 | qos_lut = 0x15555B; |
| 198 | else |
| 199 | qos_lut = 0x55555B; |
| 200 | |
| 201 | return qos_lut; |
| 202 | } |
| 203 | |
| 204 | /** |
| 205 | * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping |
| 206 | * @total_fl: fill level |
| 207 | * Return: LUT setting corresponding to the fill level |
| 208 | */ |
| 209 | static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl) |
| 210 | { |
| 211 | u32 qos_lut; |
| 212 | |
| 213 | if (total_fl <= 10) |
| 214 | qos_lut = 0x1AAff; |
| 215 | else if (total_fl <= 11) |
| 216 | qos_lut = 0x5AAFF; |
| 217 | else if (total_fl <= 12) |
| 218 | qos_lut = 0x15AAFF; |
| 219 | else |
| 220 | qos_lut = 0x55AAFF; |
| 221 | |
| 222 | return qos_lut; |
| 223 | } |
| 224 | |
| 225 | /** |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 226 | * _sde_plane_set_qos_lut - set QoS LUT of the given plane |
| 227 | * @plane: Pointer to drm plane |
| 228 | * @fb: Pointer to framebuffer associated with the given plane |
| 229 | */ |
| 230 | static void _sde_plane_set_qos_lut(struct drm_plane *plane, |
| 231 | struct drm_framebuffer *fb) |
| 232 | { |
| 233 | struct sde_plane *psde; |
| 234 | const struct sde_format *fmt = NULL; |
| 235 | u32 qos_lut; |
| 236 | u32 total_fl = 0; |
| 237 | |
| 238 | if (!plane || !fb) { |
| 239 | SDE_ERROR("invalid arguments plane %d fb %d\n", |
| 240 | plane != 0, fb != 0); |
| 241 | return; |
| 242 | } |
| 243 | |
| 244 | psde = to_sde_plane(plane); |
| 245 | |
| 246 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 247 | SDE_ERROR("invalid arguments\n"); |
| 248 | return; |
| 249 | } else if (!psde->pipe_hw->ops.setup_creq_lut) { |
| 250 | return; |
| 251 | } |
| 252 | |
| 253 | if (!psde->is_rt_pipe) { |
| 254 | qos_lut = psde->pipe_sblk->creq_lut_nrt; |
| 255 | } else { |
| 256 | fmt = sde_get_sde_format_ext( |
| 257 | fb->pixel_format, |
| 258 | fb->modifier, |
| 259 | drm_format_num_planes(fb->pixel_format)); |
| 260 | total_fl = _sde_plane_calc_fill_level(plane, fmt, |
| 261 | psde->pipe_cfg.src_rect.w); |
| 262 | |
| 263 | if (SDE_FORMAT_IS_LINEAR(fmt)) |
| 264 | qos_lut = _sde_plane_get_qos_lut_linear(total_fl); |
| 265 | else |
| 266 | qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl); |
| 267 | } |
| 268 | |
| 269 | psde->pipe_qos_cfg.creq_lut = qos_lut; |
| 270 | |
| 271 | trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, |
| 272 | (fmt) ? fmt->base.pixel_format : 0, |
| 273 | psde->is_rt_pipe, total_fl, qos_lut, |
| 274 | (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0); |
| 275 | |
| 276 | SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n", |
| 277 | plane->base.id, |
| 278 | psde->pipe - SSPP_VIG0, |
| 279 | (fmt) ? fmt->base.pixel_format : 0, |
| 280 | psde->is_rt_pipe, total_fl, qos_lut); |
| 281 | |
| 282 | psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg); |
| 283 | } |
| 284 | |
| 285 | /** |
| 286 | * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane |
| 287 | * @plane: Pointer to drm plane |
| 288 | * @fb: Pointer to framebuffer associated with the given plane |
| 289 | */ |
| 290 | static void _sde_plane_set_danger_lut(struct drm_plane *plane, |
| 291 | struct drm_framebuffer *fb) |
| 292 | { |
| 293 | struct sde_plane *psde; |
| 294 | const struct sde_format *fmt = NULL; |
| 295 | u32 danger_lut, safe_lut; |
| 296 | |
| 297 | if (!plane || !fb) { |
| 298 | SDE_ERROR("invalid arguments\n"); |
| 299 | return; |
| 300 | } |
| 301 | |
| 302 | psde = to_sde_plane(plane); |
| 303 | |
| 304 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 305 | SDE_ERROR("invalid arguments\n"); |
| 306 | return; |
| 307 | } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) { |
| 308 | return; |
| 309 | } |
| 310 | |
| 311 | if (!psde->is_rt_pipe) { |
| 312 | danger_lut = psde->pipe_sblk->danger_lut_nrt; |
| 313 | safe_lut = psde->pipe_sblk->safe_lut_nrt; |
| 314 | } else { |
| 315 | fmt = sde_get_sde_format_ext( |
| 316 | fb->pixel_format, |
| 317 | fb->modifier, |
| 318 | drm_format_num_planes(fb->pixel_format)); |
| 319 | |
| 320 | if (SDE_FORMAT_IS_LINEAR(fmt)) { |
| 321 | danger_lut = psde->pipe_sblk->danger_lut_linear; |
| 322 | safe_lut = psde->pipe_sblk->safe_lut_linear; |
| 323 | } else { |
| 324 | danger_lut = psde->pipe_sblk->danger_lut_tile; |
| 325 | safe_lut = psde->pipe_sblk->safe_lut_tile; |
| 326 | } |
| 327 | } |
| 328 | |
| 329 | psde->pipe_qos_cfg.danger_lut = danger_lut; |
| 330 | psde->pipe_qos_cfg.safe_lut = safe_lut; |
| 331 | |
| 332 | trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0, |
| 333 | (fmt) ? fmt->base.pixel_format : 0, |
| 334 | (fmt) ? fmt->fetch_mode : 0, |
| 335 | psde->pipe_qos_cfg.danger_lut, |
| 336 | psde->pipe_qos_cfg.safe_lut); |
| 337 | |
| 338 | SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n", |
| 339 | plane->base.id, |
| 340 | psde->pipe - SSPP_VIG0, |
| 341 | fmt ? fmt->base.pixel_format : 0, |
| 342 | fmt ? fmt->fetch_mode : -1, |
| 343 | psde->pipe_qos_cfg.danger_lut, |
| 344 | psde->pipe_qos_cfg.safe_lut); |
| 345 | |
| 346 | psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw, |
| 347 | &psde->pipe_qos_cfg); |
| 348 | } |
| 349 | |
| 350 | /** |
| 351 | * _sde_plane_set_qos_ctrl - set QoS control of the given plane |
| 352 | * @plane: Pointer to drm plane |
| 353 | * @enable: true to enable QoS control |
| 354 | * @flags: QoS control mode (enum sde_plane_qos) |
| 355 | */ |
| 356 | static void _sde_plane_set_qos_ctrl(struct drm_plane *plane, |
| 357 | bool enable, u32 flags) |
| 358 | { |
| 359 | struct sde_plane *psde; |
| 360 | |
| 361 | if (!plane) { |
| 362 | SDE_ERROR("invalid arguments\n"); |
| 363 | return; |
| 364 | } |
| 365 | |
| 366 | psde = to_sde_plane(plane); |
| 367 | |
| 368 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 369 | SDE_ERROR("invalid arguments\n"); |
| 370 | return; |
| 371 | } else if (!psde->pipe_hw->ops.setup_qos_ctrl) { |
| 372 | return; |
| 373 | } |
| 374 | |
| 375 | if (flags & SDE_PLANE_QOS_VBLANK_CTRL) { |
| 376 | psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank; |
| 377 | psde->pipe_qos_cfg.danger_vblank = |
| 378 | psde->pipe_sblk->danger_vblank; |
| 379 | psde->pipe_qos_cfg.vblank_en = enable; |
| 380 | } |
| 381 | |
| 382 | if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) { |
| 383 | /* this feature overrules previous VBLANK_CTRL */ |
| 384 | psde->pipe_qos_cfg.vblank_en = false; |
| 385 | psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ |
| 386 | } |
| 387 | |
| 388 | if (flags & SDE_PLANE_QOS_PANIC_CTRL) |
| 389 | psde->pipe_qos_cfg.danger_safe_en = enable; |
| 390 | |
| 391 | if (!psde->is_rt_pipe) { |
| 392 | psde->pipe_qos_cfg.vblank_en = false; |
| 393 | psde->pipe_qos_cfg.danger_safe_en = false; |
| 394 | } |
| 395 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 396 | SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 397 | plane->base.id, |
| 398 | psde->pipe - SSPP_VIG0, |
| 399 | psde->pipe_qos_cfg.danger_safe_en, |
| 400 | psde->pipe_qos_cfg.vblank_en, |
| 401 | psde->pipe_qos_cfg.creq_vblank, |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 402 | psde->pipe_qos_cfg.danger_vblank, |
| 403 | psde->is_rt_pipe); |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 404 | |
| 405 | psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw, |
| 406 | &psde->pipe_qos_cfg); |
| 407 | } |
| 408 | |
Alan Kwong | f0fd851 | 2016-10-24 21:39:26 -0400 | [diff] [blame] | 409 | int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) |
| 410 | { |
| 411 | struct sde_plane *psde; |
| 412 | struct msm_drm_private *priv; |
| 413 | struct sde_kms *sde_kms; |
| 414 | |
| 415 | if (!plane || !plane->dev) { |
| 416 | SDE_ERROR("invalid arguments\n"); |
| 417 | return -EINVAL; |
| 418 | } |
| 419 | |
| 420 | priv = plane->dev->dev_private; |
| 421 | if (!priv || !priv->kms) { |
| 422 | SDE_ERROR("invalid KMS reference\n"); |
| 423 | return -EINVAL; |
| 424 | } |
| 425 | |
| 426 | sde_kms = to_sde_kms(priv->kms); |
| 427 | psde = to_sde_plane(plane); |
| 428 | |
| 429 | if (!psde->is_rt_pipe) |
| 430 | goto end; |
| 431 | |
| 432 | sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true); |
| 433 | |
| 434 | _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL); |
| 435 | |
| 436 | sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false); |
| 437 | |
| 438 | end: |
| 439 | return 0; |
| 440 | } |
| 441 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 442 | /** |
| 443 | * _sde_plane_set_ot_limit - set OT limit for the given plane |
| 444 | * @plane: Pointer to drm plane |
| 445 | * @crtc: Pointer to drm crtc |
| 446 | */ |
| 447 | static void _sde_plane_set_ot_limit(struct drm_plane *plane, |
| 448 | struct drm_crtc *crtc) |
| 449 | { |
| 450 | struct sde_plane *psde; |
| 451 | struct sde_vbif_set_ot_params ot_params; |
| 452 | struct msm_drm_private *priv; |
| 453 | struct sde_kms *sde_kms; |
| 454 | |
| 455 | if (!plane || !plane->dev || !crtc) { |
| 456 | SDE_ERROR("invalid arguments plane %d crtc %d\n", |
| 457 | plane != 0, crtc != 0); |
| 458 | return; |
| 459 | } |
| 460 | |
| 461 | priv = plane->dev->dev_private; |
| 462 | if (!priv || !priv->kms) { |
| 463 | SDE_ERROR("invalid KMS reference\n"); |
| 464 | return; |
| 465 | } |
| 466 | |
| 467 | sde_kms = to_sde_kms(priv->kms); |
| 468 | psde = to_sde_plane(plane); |
| 469 | if (!psde->pipe_hw) { |
| 470 | SDE_ERROR("invalid pipe reference\n"); |
| 471 | return; |
| 472 | } |
| 473 | |
| 474 | memset(&ot_params, 0, sizeof(ot_params)); |
| 475 | ot_params.xin_id = psde->pipe_hw->cap->xin_id; |
| 476 | ot_params.num = psde->pipe_hw->idx - SSPP_NONE; |
| 477 | ot_params.width = psde->pipe_cfg.src_rect.w; |
| 478 | ot_params.height = psde->pipe_cfg.src_rect.h; |
| 479 | ot_params.is_wfd = !psde->is_rt_pipe; |
| 480 | ot_params.frame_rate = crtc->mode.vrefresh; |
| 481 | ot_params.vbif_idx = VBIF_RT; |
| 482 | ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl; |
| 483 | ot_params.rd = true; |
| 484 | |
| 485 | sde_vbif_set_ot_limit(sde_kms, &ot_params); |
| 486 | } |
| 487 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 488 | /* helper to update a state's input fence pointer from the property */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 489 | static void _sde_plane_set_input_fence(struct sde_plane *psde, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 490 | struct sde_plane_state *pstate, uint64_t fd) |
| 491 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 492 | if (!psde || !pstate) { |
| 493 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 494 | psde != 0, pstate != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 495 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 496 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 497 | |
| 498 | /* clear previous reference */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 499 | if (pstate->input_fence) |
| 500 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 501 | |
| 502 | /* get fence pointer for later */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 503 | pstate->input_fence = sde_sync_get(fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 504 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 505 | SDE_DEBUG_PLANE(psde, "0x%llX\n", fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 506 | } |
| 507 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 508 | int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 509 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 510 | struct sde_plane *psde; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 511 | struct sde_plane_state *pstate; |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 512 | uint32_t prefix; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 513 | void *input_fence; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 514 | int ret = -EINVAL; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 515 | |
| 516 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 517 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 518 | } else if (!plane->state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 519 | SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 520 | } else { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 521 | psde = to_sde_plane(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 522 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 523 | input_fence = pstate->input_fence; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 524 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 525 | if (input_fence) { |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 526 | prefix = sde_sync_get_name_prefix(input_fence); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 527 | ret = sde_sync_wait(input_fence, wait_ms); |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 528 | |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 529 | SDE_EVT32(DRMID(plane), -ret, prefix); |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 530 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 531 | switch (ret) { |
| 532 | case 0: |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 533 | SDE_DEBUG_PLANE(psde, "signaled\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 534 | break; |
| 535 | case -ETIME: |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 536 | SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n", |
| 537 | wait_ms, prefix); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 538 | psde->is_error = true; |
| 539 | break; |
| 540 | default: |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 541 | SDE_ERROR_PLANE(psde, "error %d on %08X\n", |
| 542 | ret, prefix); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 543 | psde->is_error = true; |
| 544 | break; |
| 545 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 546 | } else { |
| 547 | ret = 0; |
| 548 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 549 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 550 | return ret; |
| 551 | } |
| 552 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 553 | static inline void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 554 | struct sde_plane_state *pstate, |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 555 | struct sde_hw_pipe_cfg *pipe_cfg, |
| 556 | struct drm_framebuffer *fb) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 557 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 558 | struct sde_plane *psde; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 559 | int ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 560 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 561 | if (!plane || !pstate || !pipe_cfg || !fb) { |
| 562 | SDE_ERROR( |
| 563 | "invalid arg(s), plane %d state %d cfg %d fb %d\n", |
| 564 | plane != 0, pstate != 0, pipe_cfg != 0, fb != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 565 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 566 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 567 | |
| 568 | psde = to_sde_plane(plane); |
Clarence Ip | b6eb236 | 2016-09-08 16:18:13 -0400 | [diff] [blame] | 569 | if (!psde->pipe_hw) { |
| 570 | SDE_ERROR_PLANE(psde, "invalid pipe_hw\n"); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 571 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 572 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 573 | |
Clarence Ip | b6eb236 | 2016-09-08 16:18:13 -0400 | [diff] [blame] | 574 | ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout); |
| 575 | if (ret == -EAGAIN) |
| 576 | SDE_DEBUG_PLANE(psde, "not updating same src addrs\n"); |
| 577 | else if (ret) |
| 578 | SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret); |
| 579 | else if (psde->pipe_hw->ops.setup_sourceaddress) |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 580 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 581 | } |
| 582 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 583 | static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde, |
| 584 | struct sde_plane_state *pstate) |
| 585 | { |
| 586 | struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg; |
| 587 | int ret = 0; |
| 588 | |
| 589 | cfg->dir_lut = msm_property_get_blob( |
| 590 | &psde->property_info, |
| 591 | pstate->property_blobs, &cfg->dir_len, |
| 592 | PLANE_PROP_SCALER_LUT_ED); |
| 593 | cfg->cir_lut = msm_property_get_blob( |
| 594 | &psde->property_info, |
| 595 | pstate->property_blobs, &cfg->cir_len, |
| 596 | PLANE_PROP_SCALER_LUT_CIR); |
| 597 | cfg->sep_lut = msm_property_get_blob( |
| 598 | &psde->property_info, |
| 599 | pstate->property_blobs, &cfg->sep_len, |
| 600 | PLANE_PROP_SCALER_LUT_SEP); |
| 601 | if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut) |
| 602 | ret = -ENODATA; |
| 603 | return ret; |
| 604 | } |
| 605 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 606 | static void _sde_plane_setup_scaler3(struct sde_plane *psde, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 607 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 608 | struct sde_hw_scaler3_cfg *scale_cfg, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 609 | const struct sde_format *fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 610 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 611 | { |
| 612 | } |
| 613 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 614 | /** |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 615 | * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 616 | * @psde: Pointer to SDE plane object |
| 617 | * @src: Source size |
| 618 | * @dst: Destination size |
| 619 | * @phase_steps: Pointer to output array for phase steps |
| 620 | * @filter: Pointer to output array for filter type |
| 621 | * @fmt: Pointer to format definition |
| 622 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 623 | * |
| 624 | * Returns: 0 on success |
| 625 | */ |
| 626 | static int _sde_plane_setup_scaler2(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 627 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 628 | enum sde_hw_filter *filter, const struct sde_format *fmt, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 629 | uint32_t chroma_subsampling) |
| 630 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 631 | if (!psde || !phase_steps || !filter || !fmt) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 632 | SDE_ERROR( |
| 633 | "invalid arg(s), plane %d phase %d filter %d fmt %d\n", |
| 634 | psde != 0, phase_steps != 0, filter != 0, fmt != 0); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 635 | return -EINVAL; |
| 636 | } |
| 637 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 638 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 639 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 640 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 641 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 642 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 643 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 644 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 645 | |
| 646 | /* calculate scaler config, if necessary */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 647 | if (SDE_FORMAT_IS_YUV(fmt) || src != dst) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 648 | filter[SDE_SSPP_COMP_3] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 649 | (src <= dst) ? SDE_SCALE_FILTER_BIL : |
| 650 | SDE_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 651 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 652 | if (SDE_FORMAT_IS_YUV(fmt)) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 653 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 654 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 655 | } else { |
| 656 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 657 | filter[SDE_SSPP_COMP_1_2] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 658 | SDE_SCALE_FILTER_NEAREST; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 659 | } |
| 660 | } else { |
| 661 | /* disable scaler */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 662 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX; |
| 663 | filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX; |
| 664 | filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 665 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 666 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 667 | } |
| 668 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 669 | /** |
| 670 | * _sde_plane_setup_pixel_ext - determine default pixel extension values |
| 671 | * @psde: Pointer to SDE plane object |
| 672 | * @src: Source size |
| 673 | * @dst: Destination size |
| 674 | * @decimated_src: Source size after decimation, if any |
| 675 | * @phase_steps: Pointer to output array for phase steps |
| 676 | * @out_src: Output array for pixel extension values |
| 677 | * @out_edge1: Output array for pixel extension first edge |
| 678 | * @out_edge2: Output array for pixel extension second edge |
| 679 | * @filter: Pointer to array for filter type |
| 680 | * @fmt: Pointer to format definition |
| 681 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 682 | * @post_compare: Whether to chroma subsampled source size for comparisions |
| 683 | */ |
| 684 | static void _sde_plane_setup_pixel_ext(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 685 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 686 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 687 | int *out_edge2, enum sde_hw_filter *filter, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 688 | const struct sde_format *fmt, uint32_t chroma_subsampling, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 689 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 690 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 691 | int64_t edge1, edge2, caf; |
| 692 | uint32_t src_work; |
| 693 | int i, tmp; |
| 694 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 695 | if (psde && phase_steps && out_src && out_edge1 && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 696 | out_edge2 && filter && fmt) { |
| 697 | /* handle CAF for YUV formats */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 698 | if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 699 | caf = PHASE_STEP_UNIT_SCALE; |
| 700 | else |
| 701 | caf = 0; |
| 702 | |
| 703 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 704 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 705 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 706 | src_work /= chroma_subsampling; |
| 707 | if (post_compare) |
| 708 | src = src_work; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 709 | if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 710 | /* unity */ |
| 711 | edge1 = 0; |
| 712 | edge2 = 0; |
| 713 | } else if (dst >= src) { |
| 714 | /* upscale */ |
| 715 | edge1 = (1 << PHASE_RESIDUAL); |
| 716 | edge1 -= caf; |
| 717 | edge2 = (1 << PHASE_RESIDUAL); |
| 718 | edge2 += (dst - 1) * *(phase_steps + i); |
| 719 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 720 | edge2 += caf; |
| 721 | edge2 = -(edge2); |
| 722 | } else { |
| 723 | /* downscale */ |
| 724 | edge1 = 0; |
| 725 | edge2 = (dst - 1) * *(phase_steps + i); |
| 726 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 727 | edge2 += *(phase_steps + i); |
| 728 | edge2 = -(edge2); |
| 729 | } |
| 730 | |
| 731 | /* only enable CAF for luma plane */ |
| 732 | caf = 0; |
| 733 | |
| 734 | /* populate output arrays */ |
| 735 | *(out_src + i) = src_work; |
| 736 | |
| 737 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 738 | if (edge1 >= 0) { |
| 739 | tmp = (uint32_t)edge1; |
| 740 | tmp >>= PHASE_STEP_SHIFT; |
| 741 | *(out_edge1 + i) = -tmp; |
| 742 | } else { |
| 743 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 744 | *(out_edge1 + i) = |
| 745 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 746 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 747 | } |
| 748 | if (edge2 >= 0) { |
| 749 | tmp = (uint32_t)edge2; |
| 750 | tmp >>= PHASE_STEP_SHIFT; |
| 751 | *(out_edge2 + i) = -tmp; |
| 752 | } else { |
| 753 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 754 | *(out_edge2 + i) = |
| 755 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 756 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 757 | } |
| 758 | } |
| 759 | } |
| 760 | } |
| 761 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 762 | static inline void _sde_plane_setup_csc(struct sde_plane *psde) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 763 | { |
| 764 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 765 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 766 | /* S15.16 format */ |
| 767 | 0x00012A00, 0x00000000, 0x00019880, |
| 768 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 769 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 770 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 771 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 772 | { 0xfff0, 0xff80, 0xff80,}, |
| 773 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 774 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 775 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 776 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 777 | }; |
abeykun | 1c312f6 | 2016-08-26 09:47:12 -0400 | [diff] [blame] | 778 | static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = { |
| 779 | { |
| 780 | /* S15.16 format */ |
| 781 | 0x00012A00, 0x00000000, 0x00019880, |
| 782 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 783 | 0x00012A00, 0x00020480, 0x00000000, |
| 784 | }, |
| 785 | /* signed bias */ |
| 786 | { 0xffc0, 0xfe00, 0xfe00,}, |
| 787 | { 0x0, 0x0, 0x0,}, |
| 788 | /* unsigned clamp */ |
| 789 | { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, |
| 790 | { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, |
| 791 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 792 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 793 | if (!psde) { |
| 794 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 795 | return; |
| 796 | } |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 797 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 798 | /* revert to kernel default if override not available */ |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 799 | if (psde->csc_usr_ptr) |
| 800 | psde->csc_ptr = psde->csc_usr_ptr; |
abeykun | 1c312f6 | 2016-08-26 09:47:12 -0400 | [diff] [blame] | 801 | else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features) |
| 802 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 803 | else |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 804 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 805 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 806 | SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n", |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 807 | psde->csc_ptr->csc_mv[0], |
| 808 | psde->csc_ptr->csc_mv[1], |
| 809 | psde->csc_ptr->csc_mv[2]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 810 | } |
| 811 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 812 | static void sde_color_process_plane_setup(struct drm_plane *plane) |
| 813 | { |
| 814 | struct sde_plane *psde; |
| 815 | struct sde_plane_state *pstate; |
| 816 | uint32_t hue, saturation, value, contrast; |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 817 | struct drm_msm_memcol *memcol = NULL; |
| 818 | size_t memcol_sz = 0; |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 819 | |
| 820 | psde = to_sde_plane(plane); |
| 821 | pstate = to_sde_plane_state(plane->state); |
| 822 | |
| 823 | hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST); |
| 824 | if (psde->pipe_hw->ops.setup_pa_hue) |
| 825 | psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue); |
| 826 | saturation = (uint32_t) sde_plane_get_property(pstate, |
| 827 | PLANE_PROP_SATURATION_ADJUST); |
| 828 | if (psde->pipe_hw->ops.setup_pa_sat) |
| 829 | psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation); |
| 830 | value = (uint32_t) sde_plane_get_property(pstate, |
| 831 | PLANE_PROP_VALUE_ADJUST); |
| 832 | if (psde->pipe_hw->ops.setup_pa_val) |
| 833 | psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value); |
| 834 | contrast = (uint32_t) sde_plane_get_property(pstate, |
| 835 | PLANE_PROP_CONTRAST_ADJUST); |
| 836 | if (psde->pipe_hw->ops.setup_pa_cont) |
| 837 | psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast); |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 838 | |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 839 | if (psde->pipe_hw->ops.setup_pa_memcolor) { |
| 840 | /* Skin memory color setup */ |
| 841 | memcol = msm_property_get_blob(&psde->property_info, |
| 842 | pstate->property_blobs, |
| 843 | &memcol_sz, |
| 844 | PLANE_PROP_SKIN_COLOR); |
| 845 | psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw, |
| 846 | MEMCOLOR_SKIN, memcol); |
| 847 | |
| 848 | /* Sky memory color setup */ |
| 849 | memcol = msm_property_get_blob(&psde->property_info, |
| 850 | pstate->property_blobs, |
| 851 | &memcol_sz, |
| 852 | PLANE_PROP_SKY_COLOR); |
| 853 | psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw, |
| 854 | MEMCOLOR_SKY, memcol); |
| 855 | |
| 856 | /* Foliage memory color setup */ |
| 857 | memcol = msm_property_get_blob(&psde->property_info, |
| 858 | pstate->property_blobs, |
| 859 | &memcol_sz, |
| 860 | PLANE_PROP_FOLIAGE_COLOR); |
| 861 | psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw, |
| 862 | MEMCOLOR_FOLIAGE, memcol); |
| 863 | } |
| 864 | } |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 865 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 866 | static void _sde_plane_setup_scaler(struct sde_plane *psde, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 867 | const struct sde_format *fmt, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 868 | struct sde_plane_state *pstate) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 869 | { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 870 | struct sde_hw_pixel_ext *pe; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 871 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 872 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 873 | if (!psde || !fmt) { |
| 874 | SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n", |
| 875 | psde != 0, fmt != 0, pstate != 0); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 876 | return; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 877 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 878 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 879 | pe = &(psde->pixel_ext); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 880 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 881 | psde->pipe_cfg.horz_decimation = |
| 882 | sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE); |
| 883 | psde->pipe_cfg.vert_decimation = |
| 884 | sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 885 | |
| 886 | /* don't chroma subsample if decimating */ |
| 887 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 888 | drm_format_horz_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 889 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 890 | drm_format_vert_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 891 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 892 | /* update scaler */ |
| 893 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 894 | int error; |
| 895 | |
| 896 | error = _sde_plane_setup_scaler3_lut(psde, pstate); |
| 897 | if (error || !psde->pixel_ext_usr) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 898 | /* calculate default config for QSEED3 */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 899 | _sde_plane_setup_scaler3(psde, |
| 900 | psde->pipe_cfg.src_rect.w, |
| 901 | psde->pipe_cfg.src_rect.h, |
| 902 | psde->pipe_cfg.dst_rect.w, |
| 903 | psde->pipe_cfg.dst_rect.h, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 904 | psde->scaler3_cfg, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 905 | chroma_subsmpl_h, chroma_subsmpl_v); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 906 | } |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 907 | } else if (!psde->pixel_ext_usr) { |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 908 | uint32_t deci_dim, i; |
| 909 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 910 | /* calculate default configuration for QSEED2 */ |
| 911 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 912 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 913 | SDE_DEBUG_PLANE(psde, "default config\n"); |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 914 | deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w, |
| 915 | psde->pipe_cfg.horz_decimation); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 916 | _sde_plane_setup_scaler2(psde, |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 917 | deci_dim, |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 918 | psde->pipe_cfg.dst_rect.w, |
| 919 | pe->phase_step_x, |
| 920 | pe->horz_filter, fmt, chroma_subsmpl_h); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 921 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 922 | if (SDE_FORMAT_IS_YUV(fmt)) |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 923 | deci_dim &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 924 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w, |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 925 | psde->pipe_cfg.dst_rect.w, deci_dim, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 926 | pe->phase_step_x, |
| 927 | pe->roi_w, |
| 928 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 929 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 930 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 931 | |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 932 | deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 933 | psde->pipe_cfg.vert_decimation); |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 934 | _sde_plane_setup_scaler2(psde, |
| 935 | deci_dim, |
| 936 | psde->pipe_cfg.dst_rect.h, |
| 937 | pe->phase_step_y, |
| 938 | pe->vert_filter, fmt, chroma_subsmpl_v); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 939 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h, |
Lloyd Atkinson | cd43ca6 | 2016-11-29 14:13:11 -0500 | [diff] [blame] | 940 | psde->pipe_cfg.dst_rect.h, deci_dim, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 941 | pe->phase_step_y, |
| 942 | pe->roi_h, |
| 943 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 944 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 945 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 946 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 947 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 948 | if (pe->num_ext_pxls_left[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 949 | pe->left_rpt[i] = pe->num_ext_pxls_left[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 950 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 951 | pe->left_ftch[i] = pe->num_ext_pxls_left[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 952 | |
| 953 | if (pe->num_ext_pxls_right[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 954 | pe->right_rpt[i] = pe->num_ext_pxls_right[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 955 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 956 | pe->right_ftch[i] = pe->num_ext_pxls_right[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 957 | |
| 958 | if (pe->num_ext_pxls_top[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 959 | pe->top_rpt[i] = pe->num_ext_pxls_top[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 960 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 961 | pe->top_ftch[i] = pe->num_ext_pxls_top[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 962 | |
| 963 | if (pe->num_ext_pxls_btm[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 964 | pe->btm_rpt[i] = pe->num_ext_pxls_btm[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 965 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 966 | pe->btm_ftch[i] = pe->num_ext_pxls_btm[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 967 | } |
| 968 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 969 | } |
| 970 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 971 | /** |
| 972 | * _sde_plane_color_fill - enables color fill on plane |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 973 | * @psde: Pointer to SDE plane object |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 974 | * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red |
| 975 | * @alpha: 8-bit fill alpha value, 255 selects 100% alpha |
| 976 | * Returns: 0 on success |
| 977 | */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 978 | static int _sde_plane_color_fill(struct sde_plane *psde, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 979 | uint32_t color, uint32_t alpha) |
| 980 | { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 981 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 982 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 983 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 984 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 985 | return -EINVAL; |
| 986 | } |
| 987 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 988 | if (!psde->pipe_hw) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 989 | SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 990 | return -EINVAL; |
| 991 | } |
| 992 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 993 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 994 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 995 | /* |
| 996 | * select fill format to match user property expectation, |
| 997 | * h/w only supports RGB variants |
| 998 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 999 | fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1000 | |
| 1001 | /* update sspp */ |
| 1002 | if (fmt && psde->pipe_hw->ops.setup_solidfill) { |
| 1003 | psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw, |
| 1004 | (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); |
| 1005 | |
| 1006 | /* override scaler/decimation if solid fill */ |
| 1007 | psde->pipe_cfg.src_rect.x = 0; |
| 1008 | psde->pipe_cfg.src_rect.y = 0; |
| 1009 | psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w; |
| 1010 | psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h; |
| 1011 | |
| 1012 | _sde_plane_setup_scaler(psde, fmt, 0); |
| 1013 | |
| 1014 | if (psde->pipe_hw->ops.setup_format) |
| 1015 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
| 1016 | fmt, SDE_SSPP_SOLID_FILL); |
| 1017 | |
| 1018 | if (psde->pipe_hw->ops.setup_rects) |
| 1019 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1020 | &psde->pipe_cfg, &psde->pixel_ext, |
| 1021 | psde->scaler3_cfg); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1022 | } |
| 1023 | |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
| 1027 | static int _sde_plane_mode_set(struct drm_plane *plane, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1028 | struct drm_plane_state *state) |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1029 | { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1030 | uint32_t nplanes, src_flags; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1031 | struct sde_plane *psde; |
| 1032 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1033 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1034 | struct drm_crtc *crtc; |
| 1035 | struct drm_framebuffer *fb; |
| 1036 | struct sde_rect src, dst; |
| 1037 | bool q16_data = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1038 | int idx; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1039 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1040 | if (!plane) { |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1041 | SDE_ERROR("invalid plane\n"); |
| 1042 | return -EINVAL; |
| 1043 | } else if (!plane->state) { |
| 1044 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1045 | return -EINVAL; |
| 1046 | } |
| 1047 | |
| 1048 | psde = to_sde_plane(plane); |
| 1049 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1050 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1051 | crtc = state->crtc; |
| 1052 | fb = state->fb; |
| 1053 | if (!crtc || !fb) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1054 | SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n", |
| 1055 | crtc != 0, fb != 0); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1056 | return -EINVAL; |
| 1057 | } |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1058 | fmt = to_sde_format(msm_framebuffer_format(fb)); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1059 | nplanes = fmt->num_planes; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1060 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1061 | /* determine what needs to be refreshed */ |
| 1062 | while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) { |
| 1063 | switch (idx) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1064 | case PLANE_PROP_SCALER_V1: |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1065 | case PLANE_PROP_SCALER_V2: |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1066 | case PLANE_PROP_H_DECIMATE: |
| 1067 | case PLANE_PROP_V_DECIMATE: |
| 1068 | case PLANE_PROP_SRC_CONFIG: |
| 1069 | case PLANE_PROP_ZPOS: |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1070 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1071 | break; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1072 | case PLANE_PROP_CSC_V1: |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1073 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 1074 | break; |
| 1075 | case PLANE_PROP_COLOR_FILL: |
| 1076 | /* potentially need to refresh everything */ |
| 1077 | pstate->dirty = SDE_PLANE_DIRTY_ALL; |
| 1078 | break; |
| 1079 | case PLANE_PROP_ROTATION: |
| 1080 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 1081 | break; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1082 | case PLANE_PROP_INFO: |
| 1083 | case PLANE_PROP_ALPHA: |
| 1084 | case PLANE_PROP_INPUT_FENCE: |
| 1085 | case PLANE_PROP_BLEND_OP: |
| 1086 | /* no special action required */ |
| 1087 | break; |
| 1088 | default: |
| 1089 | /* unknown property, refresh everything */ |
| 1090 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
| 1091 | SDE_ERROR("executing full mode set, prp_idx %d\n", idx); |
| 1092 | break; |
| 1093 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1094 | } |
| 1095 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1096 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) |
| 1097 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1098 | |
| 1099 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 1100 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1101 | /* early out if nothing dirty */ |
| 1102 | if (!pstate->dirty) |
| 1103 | return 0; |
| 1104 | pstate->pending = true; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1105 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1106 | psde->is_rt_pipe = sde_crtc_is_rt(crtc); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1107 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1108 | |
| 1109 | /* update roi config */ |
| 1110 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) { |
| 1111 | POPULATE_RECT(&src, state->src_x, state->src_y, |
| 1112 | state->src_w, state->src_h, q16_data); |
| 1113 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, |
| 1114 | state->crtc_w, state->crtc_h, !q16_data); |
| 1115 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1116 | SDE_DEBUG_PLANE(psde, |
| 1117 | "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n", |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1118 | fb->base.id, src.x, src.y, src.w, src.h, |
| 1119 | crtc->base.id, dst.x, dst.y, dst.w, dst.h, |
| 1120 | drm_get_format_name(fmt->base.pixel_format), |
| 1121 | SDE_FORMAT_IS_UBWC(fmt)); |
| 1122 | |
| 1123 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 1124 | BIT(SDE_DRM_DEINTERLACE)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1125 | SDE_DEBUG_PLANE(psde, "deinterlace\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1126 | for (idx = 0; idx < SDE_MAX_PLANES; ++idx) |
| 1127 | psde->pipe_cfg.layout.plane_pitch[idx] <<= 1; |
| 1128 | src.h /= 2; |
| 1129 | src.y = DIV_ROUND_UP(src.y, 2); |
| 1130 | src.y &= ~0x1; |
| 1131 | } |
| 1132 | |
| 1133 | psde->pipe_cfg.src_rect = src; |
| 1134 | psde->pipe_cfg.dst_rect = dst; |
| 1135 | |
| 1136 | /* check for color fill */ |
| 1137 | psde->color_fill = (uint32_t)sde_plane_get_property(pstate, |
| 1138 | PLANE_PROP_COLOR_FILL); |
| 1139 | if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) { |
| 1140 | /* skip remaining processing on color fill */ |
| 1141 | pstate->dirty = 0x0; |
| 1142 | } else if (psde->pipe_hw->ops.setup_rects) { |
| 1143 | _sde_plane_setup_scaler(psde, fmt, pstate); |
| 1144 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1145 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1146 | &psde->pipe_cfg, &psde->pixel_ext, |
| 1147 | psde->scaler3_cfg); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1148 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1149 | } |
| 1150 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1151 | if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) && |
| 1152 | psde->pipe_hw->ops.setup_format) { |
| 1153 | src_flags = 0x0; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1154 | SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n", |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1155 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 1156 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1157 | BIT(DRM_REFLECT_X)) |
| 1158 | src_flags |= SDE_SSPP_FLIP_LR; |
| 1159 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1160 | BIT(DRM_REFLECT_Y)) |
| 1161 | src_flags |= SDE_SSPP_FLIP_UD; |
| 1162 | |
| 1163 | /* update format */ |
| 1164 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags); |
| 1165 | |
| 1166 | /* update csc */ |
| 1167 | if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1168 | _sde_plane_setup_csc(psde); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1169 | else |
| 1170 | psde->csc_ptr = 0; |
| 1171 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1172 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1173 | sde_color_process_plane_setup(plane); |
| 1174 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1175 | /* update sharpening */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1176 | if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) && |
| 1177 | psde->pipe_hw->ops.setup_sharpening) { |
| 1178 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 1179 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 1180 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 1181 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1182 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1183 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1184 | &psde->sharp_cfg); |
| 1185 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1186 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1187 | _sde_plane_set_qos_lut(plane, fb); |
| 1188 | _sde_plane_set_danger_lut(plane, fb); |
| 1189 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1190 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1191 | _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL); |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1192 | _sde_plane_set_ot_limit(plane, crtc); |
| 1193 | } |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1194 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1195 | /* clear dirty */ |
| 1196 | pstate->dirty = 0x0; |
| 1197 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1198 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
| 1202 | const struct drm_plane_state *new_state) |
| 1203 | { |
| 1204 | struct drm_framebuffer *fb = new_state->fb; |
| 1205 | struct sde_plane *psde = to_sde_plane(plane); |
| 1206 | |
| 1207 | if (!new_state->fb) |
| 1208 | return 0; |
| 1209 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1210 | SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1211 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 1212 | } |
| 1213 | |
| 1214 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
| 1215 | const struct drm_plane_state *old_state) |
| 1216 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1217 | struct drm_framebuffer *fb = old_state ? old_state->fb : NULL; |
| 1218 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1219 | |
| 1220 | if (!fb) |
| 1221 | return; |
| 1222 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1223 | SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1224 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 1225 | } |
| 1226 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1227 | static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde, |
| 1228 | struct drm_plane_state *state, |
| 1229 | struct drm_plane_state *old_state) |
| 1230 | { |
| 1231 | struct sde_plane_state *pstate = to_sde_plane_state(state); |
| 1232 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1233 | /* no need to check it again */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1234 | if (pstate->dirty == SDE_PLANE_DIRTY_ALL) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1235 | return; |
| 1236 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1237 | if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state) |
| 1238 | || psde->is_error) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1239 | SDE_DEBUG_PLANE(psde, |
| 1240 | "enabling/disabling full modeset required\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1241 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1242 | } else if (to_sde_plane_state(old_state)->pending) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1243 | SDE_DEBUG_PLANE(psde, "still pending\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1244 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1245 | } else if (state->src_w != old_state->src_w || |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1246 | state->src_h != old_state->src_h || |
| 1247 | state->src_x != old_state->src_x || |
| 1248 | state->src_y != old_state->src_y) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1249 | SDE_DEBUG_PLANE(psde, "src rect updated\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1250 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1251 | } else if (state->crtc_w != old_state->crtc_w || |
| 1252 | state->crtc_h != old_state->crtc_h || |
| 1253 | state->crtc_x != old_state->crtc_x || |
| 1254 | state->crtc_y != old_state->crtc_y) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1255 | SDE_DEBUG_PLANE(psde, "crtc rect updated\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1256 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1257 | } |
| 1258 | |
| 1259 | if (!state->fb || !old_state->fb) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1260 | SDE_DEBUG_PLANE(psde, "can't compare fb handles\n"); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1261 | } else if (state->fb->pixel_format != old_state->fb->pixel_format) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1262 | SDE_DEBUG_PLANE(psde, "format change\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1263 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1264 | } else { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1265 | uint64_t *new_mods = state->fb->modifier; |
| 1266 | uint64_t *old_mods = old_state->fb->modifier; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1267 | uint32_t *new_pitches = state->fb->pitches; |
| 1268 | uint32_t *old_pitches = old_state->fb->pitches; |
| 1269 | uint32_t *new_offset = state->fb->offsets; |
| 1270 | uint32_t *old_offset = old_state->fb->offsets; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1271 | int i; |
| 1272 | |
| 1273 | for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) { |
| 1274 | if (new_mods[i] != old_mods[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1275 | SDE_DEBUG_PLANE(psde, |
| 1276 | "format modifiers change\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1277 | plane:%d new_mode:%llu old_mode:%llu\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1278 | i, new_mods[i], old_mods[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1279 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1280 | SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1281 | break; |
| 1282 | } |
| 1283 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1284 | for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) { |
| 1285 | if (new_pitches[i] != old_pitches[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1286 | SDE_DEBUG_PLANE(psde, |
| 1287 | "pitches change plane:%d\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1288 | old_pitches:%u new_pitches:%u\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1289 | i, old_pitches[i], new_pitches[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1290 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1291 | break; |
| 1292 | } |
| 1293 | } |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1294 | for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) { |
| 1295 | if (new_offset[i] != old_offset[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1296 | SDE_DEBUG_PLANE(psde, |
| 1297 | "offset change plane:%d\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1298 | old_offset:%u new_offset:%u\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1299 | i, old_offset[i], new_offset[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1300 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1301 | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1302 | break; |
| 1303 | } |
| 1304 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1305 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1306 | } |
| 1307 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1308 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 1309 | struct drm_plane_state *state) |
| 1310 | { |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1311 | int ret = 0; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1312 | struct sde_plane *psde; |
| 1313 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1314 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1315 | struct sde_rect src, dst; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1316 | uint32_t deci_w, deci_h, src_deci_w, src_deci_h; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1317 | uint32_t max_upscale, max_downscale, min_src_size, max_linewidth; |
| 1318 | bool q16_data = true; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1319 | |
| 1320 | if (!plane || !state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1321 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 1322 | plane != 0, state != 0); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1323 | ret = -EINVAL; |
| 1324 | goto exit; |
| 1325 | } |
| 1326 | |
| 1327 | psde = to_sde_plane(plane); |
| 1328 | pstate = to_sde_plane_state(state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1329 | |
| 1330 | if (!psde->pipe_sblk) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1331 | SDE_ERROR_PLANE(psde, "invalid catalog\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1332 | ret = -EINVAL; |
| 1333 | goto exit; |
| 1334 | } |
| 1335 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1336 | deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE); |
| 1337 | deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1338 | |
| 1339 | /* src values are in Q16 fixed point, convert to integer */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1340 | POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w, |
| 1341 | state->src_h, q16_data); |
| 1342 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w, |
| 1343 | state->crtc_h, !q16_data); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1344 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1345 | src_deci_w = DECIMATED_DIMENSION(src.w, deci_w); |
| 1346 | src_deci_h = DECIMATED_DIMENSION(src.h, deci_h); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1347 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1348 | max_upscale = psde->pipe_sblk->maxupscale; |
| 1349 | max_downscale = psde->pipe_sblk->maxdwnscale; |
| 1350 | max_linewidth = psde->pipe_sblk->maxlinewidth; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1351 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1352 | SDE_DEBUG_PLANE(psde, "check %d -> %d\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1353 | sde_plane_enabled(plane->state), sde_plane_enabled(state)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1354 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1355 | if (!sde_plane_enabled(state)) |
| 1356 | goto modeset_update; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1357 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1358 | fmt = to_sde_format(msm_framebuffer_format(state->fb)); |
| 1359 | |
| 1360 | min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1; |
| 1361 | |
| 1362 | if (SDE_FORMAT_IS_YUV(fmt) && |
| 1363 | (!(psde->features & SDE_SSPP_SCALER) || |
abeykun | 1c312f6 | 2016-08-26 09:47:12 -0400 | [diff] [blame] | 1364 | !(psde->features & (BIT(SDE_SSPP_CSC) |
| 1365 | | BIT(SDE_SSPP_CSC_10BIT))))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1366 | SDE_ERROR_PLANE(psde, |
| 1367 | "plane doesn't have scaler/csc for yuv\n"); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1368 | ret = -EINVAL; |
| 1369 | |
| 1370 | /* check src bounds */ |
| 1371 | } else if (state->fb->width > MAX_IMG_WIDTH || |
| 1372 | state->fb->height > MAX_IMG_HEIGHT || |
| 1373 | src.w < min_src_size || src.h < min_src_size || |
| 1374 | CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) || |
| 1375 | CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1376 | SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1377 | src.x, src.y, src.w, src.h); |
| 1378 | ret = -E2BIG; |
| 1379 | |
| 1380 | /* valid yuv image */ |
| 1381 | } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) || |
| 1382 | (src.w & 0x1) || (src.h & 0x1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1383 | SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1384 | src.x, src.y, src.w, src.h); |
| 1385 | ret = -EINVAL; |
| 1386 | |
| 1387 | /* min dst support */ |
| 1388 | } else if (dst.w < 0x1 || dst.h < 0x1) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1389 | SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1390 | dst.x, dst.y, dst.w, dst.h); |
| 1391 | ret = -EINVAL; |
| 1392 | |
| 1393 | /* decimation validation */ |
| 1394 | } else if (deci_w || deci_h) { |
| 1395 | if ((deci_w > psde->pipe_sblk->maxhdeciexp) || |
| 1396 | (deci_h > psde->pipe_sblk->maxvdeciexp)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1397 | SDE_ERROR_PLANE(psde, |
| 1398 | "too much decimation requested\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1399 | ret = -EINVAL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1400 | } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1401 | SDE_ERROR_PLANE(psde, |
| 1402 | "decimation requires linear fetch\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1403 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1404 | } |
| 1405 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1406 | } else if (!(psde->features & SDE_SSPP_SCALER) && |
| 1407 | ((src.w != dst.w) || (src.h != dst.h))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1408 | SDE_ERROR_PLANE(psde, |
| 1409 | "pipe doesn't support scaling %ux%u->%ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1410 | src.w, src.h, dst.w, dst.h); |
| 1411 | ret = -EINVAL; |
| 1412 | |
| 1413 | /* check decimated source width */ |
| 1414 | } else if (src_deci_w > max_linewidth) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1415 | SDE_ERROR_PLANE(psde, |
| 1416 | "invalid src w:%u, deci w:%u, line w:%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1417 | src.w, src_deci_w, max_linewidth); |
| 1418 | ret = -E2BIG; |
| 1419 | |
| 1420 | /* check max scaler capability */ |
| 1421 | } else if (((src_deci_w * max_upscale) < dst.w) || |
| 1422 | ((src_deci_h * max_upscale) < dst.h) || |
| 1423 | ((dst.w * max_downscale) < src_deci_w) || |
| 1424 | ((dst.h * max_downscale) < src_deci_h)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1425 | SDE_ERROR_PLANE(psde, |
| 1426 | "too much scaling requested %ux%u->%ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1427 | src_deci_w, src_deci_h, dst.w, dst.h); |
| 1428 | ret = -E2BIG; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1429 | } |
| 1430 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1431 | modeset_update: |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1432 | if (!ret) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1433 | _sde_plane_atomic_check_mode_changed(psde, state, plane->state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1434 | exit: |
| 1435 | return ret; |
| 1436 | } |
| 1437 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1438 | /** |
| 1439 | * sde_plane_flush - final plane operations before commit flush |
| 1440 | * @plane: Pointer to drm plane structure |
| 1441 | */ |
| 1442 | void sde_plane_flush(struct drm_plane *plane) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1443 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1444 | struct sde_plane *psde; |
| 1445 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1446 | if (!plane) { |
| 1447 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1448 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1449 | } |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1450 | |
| 1451 | psde = to_sde_plane(plane); |
| 1452 | |
| 1453 | /* |
| 1454 | * These updates have to be done immediately before the plane flush |
| 1455 | * timing, and may not be moved to the atomic_update/mode_set functions. |
| 1456 | */ |
| 1457 | if (psde->is_error) |
| 1458 | /* force white frame with 0% alpha pipe output on error */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1459 | _sde_plane_color_fill(psde, 0xFFFFFF, 0x0); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1460 | else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) |
| 1461 | /* force 100% alpha */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1462 | _sde_plane_color_fill(psde, psde->color_fill, 0xFF); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1463 | else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc) |
| 1464 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
| 1465 | |
| 1466 | /* flag h/w flush complete */ |
| 1467 | if (plane->state) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1468 | to_sde_plane_state(plane->state)->pending = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1469 | } |
| 1470 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1471 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1472 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1473 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1474 | struct sde_plane *psde; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1475 | struct drm_plane_state *state; |
| 1476 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1477 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1478 | if (!plane) { |
| 1479 | SDE_ERROR("invalid plane\n"); |
| 1480 | return; |
| 1481 | } else if (!plane->state) { |
| 1482 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1483 | return; |
| 1484 | } |
| 1485 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1486 | psde = to_sde_plane(plane); |
| 1487 | psde->is_error = false; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1488 | state = plane->state; |
| 1489 | pstate = to_sde_plane_state(state); |
| 1490 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1491 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1492 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1493 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1494 | pstate->pending = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1495 | } else { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1496 | int ret; |
| 1497 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1498 | ret = _sde_plane_mode_set(plane, state); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1499 | /* atomic_check should have ensured that this doesn't fail */ |
| 1500 | WARN_ON(ret < 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1501 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1502 | } |
| 1503 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1504 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1505 | /* helper to install properties which are common to planes and crtcs */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1506 | static void _sde_plane_install_properties(struct drm_plane *plane, |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1507 | struct sde_mdss_cfg *catalog) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1508 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1509 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 1510 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 1511 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 1512 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 1513 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 1514 | }; |
| 1515 | static const struct drm_prop_enum_list e_src_config[] = { |
| 1516 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 1517 | }; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1518 | const struct sde_format_extended *format_list; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1519 | struct sde_kms_info *info; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1520 | struct sde_plane *psde = to_sde_plane(plane); |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1521 | int zpos_max = 255; |
| 1522 | int zpos_def = 0; |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1523 | char feature_name[256]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1524 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1525 | if (!plane || !psde) { |
| 1526 | SDE_ERROR("invalid plane\n"); |
| 1527 | return; |
| 1528 | } else if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 1529 | SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n", |
| 1530 | psde->pipe_hw != 0, psde->pipe_sblk != 0); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1531 | return; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1532 | } else if (!catalog) { |
| 1533 | SDE_ERROR("invalid catalog\n"); |
| 1534 | return; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1535 | } |
| 1536 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1537 | if (sde_is_custom_client()) { |
Clarence Ip | 649989a | 2016-10-21 14:28:34 -0400 | [diff] [blame] | 1538 | if (catalog->mixer_count && catalog->mixer && |
| 1539 | catalog->mixer[0].sblk->maxblendstages) { |
| 1540 | zpos_max = catalog->mixer[0].sblk->maxblendstages - 1; |
| 1541 | if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1) |
| 1542 | zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1; |
| 1543 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1544 | } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) { |
| 1545 | /* reserve zpos == 0 for primary planes */ |
| 1546 | zpos_def = drm_plane_index(plane) + 1; |
| 1547 | } |
| 1548 | |
| 1549 | msm_property_install_range(&psde->property_info, "zpos", |
| 1550 | 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1551 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1552 | msm_property_install_range(&psde->property_info, "alpha", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1553 | 0x0, 0, 255, 255, PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1554 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1555 | /* linux default file descriptor range on each process */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1556 | msm_property_install_range(&psde->property_info, "input_fence", |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1557 | 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1558 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1559 | if (psde->pipe_sblk->maxhdeciexp) { |
| 1560 | msm_property_install_range(&psde->property_info, "h_decimate", |
| 1561 | 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0, |
| 1562 | PLANE_PROP_H_DECIMATE); |
| 1563 | } |
| 1564 | |
| 1565 | if (psde->pipe_sblk->maxvdeciexp) { |
| 1566 | msm_property_install_range(&psde->property_info, "v_decimate", |
| 1567 | 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0, |
| 1568 | PLANE_PROP_V_DECIMATE); |
| 1569 | } |
| 1570 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1571 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 1572 | msm_property_install_volatile_range(&psde->property_info, |
| 1573 | "scaler_v2", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2); |
| 1574 | msm_property_install_blob(&psde->property_info, "lut_ed", 0, |
| 1575 | PLANE_PROP_SCALER_LUT_ED); |
| 1576 | msm_property_install_blob(&psde->property_info, "lut_cir", 0, |
| 1577 | PLANE_PROP_SCALER_LUT_CIR); |
| 1578 | msm_property_install_blob(&psde->property_info, "lut_sep", 0, |
| 1579 | PLANE_PROP_SCALER_LUT_SEP); |
| 1580 | } else if (psde->features & SDE_SSPP_SCALER) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1581 | msm_property_install_volatile_range(&psde->property_info, |
| 1582 | "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1); |
| 1583 | } |
| 1584 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1585 | if (psde->features & BIT(SDE_SSPP_CSC)) { |
| 1586 | msm_property_install_volatile_range(&psde->property_info, |
| 1587 | "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1); |
| 1588 | } |
| 1589 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1590 | if (psde->features & BIT(SDE_SSPP_HSIC)) { |
| 1591 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1592 | "SDE_SSPP_HUE_V", |
| 1593 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1594 | msm_property_install_range(&psde->property_info, |
| 1595 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1596 | PLANE_PROP_HUE_ADJUST); |
| 1597 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1598 | "SDE_SSPP_SATURATION_V", |
| 1599 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1600 | msm_property_install_range(&psde->property_info, |
| 1601 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1602 | PLANE_PROP_SATURATION_ADJUST); |
| 1603 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1604 | "SDE_SSPP_VALUE_V", |
| 1605 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1606 | msm_property_install_range(&psde->property_info, |
| 1607 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1608 | PLANE_PROP_VALUE_ADJUST); |
| 1609 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1610 | "SDE_SSPP_CONTRAST_V", |
| 1611 | psde->pipe_sblk->hsic_blk.version >> 16); |
| 1612 | msm_property_install_range(&psde->property_info, |
| 1613 | feature_name, 0, 0, 0xFFFFFFFF, 0, |
| 1614 | PLANE_PROP_CONTRAST_ADJUST); |
| 1615 | } |
| 1616 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1617 | /* standard properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1618 | msm_property_install_rotation(&psde->property_info, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1619 | BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1620 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1621 | msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1622 | e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1623 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1624 | msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1, |
| 1625 | e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG); |
| 1626 | |
| 1627 | if (psde->pipe_hw->ops.setup_solidfill) |
| 1628 | msm_property_install_range(&psde->property_info, "color_fill", |
| 1629 | 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL); |
| 1630 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1631 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1632 | if (!info) { |
| 1633 | SDE_ERROR("failed to allocate info memory\n"); |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1634 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1635 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1636 | |
| 1637 | msm_property_install_blob(&psde->property_info, "capabilities", |
| 1638 | DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO); |
| 1639 | sde_kms_info_reset(info); |
| 1640 | |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1641 | format_list = psde->pipe_sblk->format_list; |
| 1642 | if (format_list) { |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1643 | sde_kms_info_start(info, "pixel_formats"); |
| 1644 | while (format_list->fourcc_format) { |
| 1645 | sde_kms_info_append_format(info, |
| 1646 | format_list->fourcc_format, |
| 1647 | format_list->modifier); |
| 1648 | ++format_list; |
| 1649 | } |
| 1650 | sde_kms_info_stop(info); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1651 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1652 | |
| 1653 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 1654 | psde->pipe_sblk->maxlinewidth); |
| 1655 | sde_kms_info_add_keyint(info, "max_upscale", |
| 1656 | psde->pipe_sblk->maxupscale); |
| 1657 | sde_kms_info_add_keyint(info, "max_downscale", |
| 1658 | psde->pipe_sblk->maxdwnscale); |
| 1659 | sde_kms_info_add_keyint(info, "max_horizontal_deci", |
| 1660 | psde->pipe_sblk->maxhdeciexp); |
| 1661 | sde_kms_info_add_keyint(info, "max_vertical_deci", |
| 1662 | psde->pipe_sblk->maxvdeciexp); |
| 1663 | msm_property_set_blob(&psde->property_info, &psde->blob_info, |
| 1664 | info->data, info->len, PLANE_PROP_INFO); |
| 1665 | |
| 1666 | kfree(info); |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 1667 | |
| 1668 | if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) { |
| 1669 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1670 | "SDE_SSPP_SKIN_COLOR_V", |
| 1671 | psde->pipe_sblk->memcolor_blk.version >> 16); |
| 1672 | msm_property_install_blob(&psde->property_info, feature_name, 0, |
| 1673 | PLANE_PROP_SKIN_COLOR); |
| 1674 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1675 | "SDE_SSPP_SKY_COLOR_V", |
| 1676 | psde->pipe_sblk->memcolor_blk.version >> 16); |
| 1677 | msm_property_install_blob(&psde->property_info, feature_name, 0, |
| 1678 | PLANE_PROP_SKY_COLOR); |
| 1679 | snprintf(feature_name, sizeof(feature_name), "%s%d", |
| 1680 | "SDE_SSPP_FOLIAGE_COLOR_V", |
| 1681 | psde->pipe_sblk->memcolor_blk.version >> 16); |
| 1682 | msm_property_install_blob(&psde->property_info, feature_name, 0, |
| 1683 | PLANE_PROP_FOLIAGE_COLOR); |
| 1684 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1685 | } |
| 1686 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1687 | static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr) |
| 1688 | { |
| 1689 | struct sde_drm_csc_v1 csc_v1; |
| 1690 | int i; |
| 1691 | |
| 1692 | if (!psde) { |
| 1693 | SDE_ERROR("invalid plane\n"); |
| 1694 | return; |
| 1695 | } |
| 1696 | |
| 1697 | psde->csc_usr_ptr = NULL; |
| 1698 | if (!usr_ptr) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1699 | SDE_DEBUG_PLANE(psde, "csc data removed\n"); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1700 | return; |
| 1701 | } |
| 1702 | |
| 1703 | if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1704 | SDE_ERROR_PLANE(psde, "failed to copy csc data\n"); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1705 | return; |
| 1706 | } |
| 1707 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1708 | /* populate from user space */ |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1709 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
| 1710 | psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16; |
| 1711 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
| 1712 | psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i]; |
| 1713 | psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i]; |
| 1714 | } |
| 1715 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
| 1716 | psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i]; |
| 1717 | psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i]; |
| 1718 | } |
| 1719 | psde->csc_usr_ptr = &psde->csc_cfg; |
| 1720 | } |
| 1721 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1722 | static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr) |
| 1723 | { |
| 1724 | struct sde_drm_scaler_v1 scale_v1; |
| 1725 | struct sde_hw_pixel_ext *pe; |
| 1726 | int i; |
| 1727 | |
| 1728 | if (!psde) { |
| 1729 | SDE_ERROR("invalid plane\n"); |
| 1730 | return; |
| 1731 | } |
| 1732 | |
| 1733 | psde->pixel_ext_usr = false; |
| 1734 | if (!usr) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1735 | SDE_DEBUG_PLANE(psde, "scale data removed\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1736 | return; |
| 1737 | } |
| 1738 | |
| 1739 | if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1740 | SDE_ERROR_PLANE(psde, "failed to copy scale data\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1741 | return; |
| 1742 | } |
| 1743 | |
| 1744 | /* populate from user space */ |
| 1745 | pe = &(psde->pixel_ext); |
| 1746 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
| 1747 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 1748 | pe->init_phase_x[i] = scale_v1.init_phase_x[i]; |
| 1749 | pe->phase_step_x[i] = scale_v1.phase_step_x[i]; |
| 1750 | pe->init_phase_y[i] = scale_v1.init_phase_y[i]; |
| 1751 | pe->phase_step_y[i] = scale_v1.phase_step_y[i]; |
| 1752 | |
| 1753 | pe->horz_filter[i] = scale_v1.horz_filter[i]; |
| 1754 | pe->vert_filter[i] = scale_v1.vert_filter[i]; |
| 1755 | } |
| 1756 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1757 | pe->left_ftch[i] = scale_v1.pe.left_ftch[i]; |
| 1758 | pe->right_ftch[i] = scale_v1.pe.right_ftch[i]; |
| 1759 | pe->left_rpt[i] = scale_v1.pe.left_rpt[i]; |
| 1760 | pe->right_rpt[i] = scale_v1.pe.right_rpt[i]; |
| 1761 | pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i]; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1762 | |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1763 | pe->top_ftch[i] = scale_v1.pe.top_ftch[i]; |
| 1764 | pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i]; |
| 1765 | pe->top_rpt[i] = scale_v1.pe.top_rpt[i]; |
| 1766 | pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i]; |
| 1767 | pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i]; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1768 | } |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1769 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1770 | psde->pixel_ext_usr = true; |
| 1771 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1772 | SDE_DEBUG_PLANE(psde, "user property data copied\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1773 | } |
| 1774 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1775 | static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde, |
| 1776 | struct sde_plane_state *pstate, void *usr) |
| 1777 | { |
| 1778 | struct sde_drm_scaler_v2 scale_v2; |
| 1779 | struct sde_hw_pixel_ext *pe; |
| 1780 | int i; |
| 1781 | struct sde_hw_scaler3_cfg *cfg; |
| 1782 | |
| 1783 | if (!psde) { |
| 1784 | SDE_ERROR("invalid plane\n"); |
| 1785 | return; |
| 1786 | } |
| 1787 | |
| 1788 | cfg = psde->scaler3_cfg; |
| 1789 | psde->pixel_ext_usr = false; |
| 1790 | if (!usr) { |
| 1791 | SDE_DEBUG_PLANE(psde, "scale data removed\n"); |
| 1792 | return; |
| 1793 | } |
| 1794 | |
| 1795 | if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) { |
| 1796 | SDE_ERROR_PLANE(psde, "failed to copy scale data\n"); |
| 1797 | return; |
| 1798 | } |
| 1799 | |
| 1800 | /* populate from user space */ |
| 1801 | pe = &(psde->pixel_ext); |
| 1802 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
| 1803 | cfg->enable = scale_v2.enable; |
| 1804 | cfg->dir_en = scale_v2.dir_en; |
| 1805 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 1806 | cfg->init_phase_x[i] = scale_v2.init_phase_x[i]; |
| 1807 | cfg->phase_step_x[i] = scale_v2.phase_step_x[i]; |
| 1808 | cfg->init_phase_y[i] = scale_v2.init_phase_y[i]; |
| 1809 | cfg->phase_step_y[i] = scale_v2.phase_step_y[i]; |
| 1810 | |
| 1811 | cfg->preload_x[i] = scale_v2.preload_x[i]; |
| 1812 | cfg->preload_y[i] = scale_v2.preload_y[i]; |
| 1813 | cfg->src_width[i] = scale_v2.src_width[i]; |
| 1814 | cfg->src_height[i] = scale_v2.src_height[i]; |
| 1815 | } |
| 1816 | cfg->dst_width = scale_v2.dst_width; |
| 1817 | cfg->dst_height = scale_v2.dst_height; |
| 1818 | |
| 1819 | cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg; |
| 1820 | cfg->uv_filter_cfg = scale_v2.uv_filter_cfg; |
| 1821 | cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg; |
| 1822 | cfg->blend_cfg = scale_v2.blend_cfg; |
| 1823 | |
| 1824 | cfg->lut_flag = scale_v2.lut_flag; |
| 1825 | cfg->dir_lut_idx = scale_v2.dir_lut_idx; |
| 1826 | cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx; |
| 1827 | cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx; |
| 1828 | cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx; |
| 1829 | cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx; |
| 1830 | |
| 1831 | cfg->de.enable = scale_v2.de.enable; |
| 1832 | cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1; |
| 1833 | cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2; |
| 1834 | cfg->de.clip = scale_v2.de.clip; |
| 1835 | cfg->de.limit = scale_v2.de.limit; |
| 1836 | cfg->de.thr_quiet = scale_v2.de.thr_quiet; |
| 1837 | cfg->de.thr_dieout = scale_v2.de.thr_dieout; |
| 1838 | cfg->de.thr_low = scale_v2.de.thr_low; |
| 1839 | cfg->de.thr_high = scale_v2.de.thr_high; |
| 1840 | cfg->de.prec_shift = scale_v2.de.prec_shift; |
| 1841 | for (i = 0; i < SDE_MAX_DE_CURVES; i++) { |
| 1842 | cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i]; |
| 1843 | cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i]; |
| 1844 | cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i]; |
| 1845 | } |
| 1846 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1847 | pe->left_ftch[i] = scale_v2.pe.left_ftch[i]; |
| 1848 | pe->right_ftch[i] = scale_v2.pe.right_ftch[i]; |
| 1849 | pe->left_rpt[i] = scale_v2.pe.left_rpt[i]; |
| 1850 | pe->right_rpt[i] = scale_v2.pe.right_rpt[i]; |
| 1851 | pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i]; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1852 | |
abeykun | 4106012 | 2016-11-28 13:02:01 -0500 | [diff] [blame] | 1853 | pe->top_ftch[i] = scale_v2.pe.top_ftch[i]; |
| 1854 | pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i]; |
| 1855 | pe->top_rpt[i] = scale_v2.pe.top_rpt[i]; |
| 1856 | pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i]; |
| 1857 | pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i]; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1858 | } |
| 1859 | psde->pixel_ext_usr = true; |
| 1860 | |
| 1861 | SDE_DEBUG_PLANE(psde, "user property data copied\n"); |
| 1862 | } |
| 1863 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1864 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1865 | struct drm_plane_state *state, struct drm_property *property, |
| 1866 | uint64_t val) |
| 1867 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1868 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1869 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1870 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1871 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1872 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1873 | |
| 1874 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1875 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1876 | } else if (!state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1877 | SDE_ERROR_PLANE(psde, "invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1878 | } else { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1879 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1880 | ret = msm_property_atomic_set(&psde->property_info, |
| 1881 | pstate->property_values, pstate->property_blobs, |
| 1882 | property, val); |
| 1883 | if (!ret) { |
| 1884 | idx = msm_property_index(&psde->property_info, |
| 1885 | property); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1886 | switch (idx) { |
| 1887 | case PLANE_PROP_INPUT_FENCE: |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1888 | _sde_plane_set_input_fence(psde, pstate, val); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1889 | break; |
| 1890 | case PLANE_PROP_CSC_V1: |
| 1891 | _sde_plane_set_csc_v1(psde, (void *)val); |
| 1892 | break; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1893 | case PLANE_PROP_SCALER_V1: |
| 1894 | _sde_plane_set_scaler_v1(psde, (void *)val); |
| 1895 | break; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1896 | case PLANE_PROP_SCALER_V2: |
| 1897 | _sde_plane_set_scaler_v2(psde, pstate, |
| 1898 | (void *)val); |
| 1899 | break; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1900 | default: |
| 1901 | /* nothing to do */ |
| 1902 | break; |
| 1903 | } |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1904 | } |
| 1905 | } |
| 1906 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1907 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1908 | } |
| 1909 | |
| 1910 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1911 | struct drm_property *property, uint64_t val) |
| 1912 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1913 | SDE_DEBUG("\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1914 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1915 | return sde_plane_atomic_set_property(plane, |
| 1916 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1917 | } |
| 1918 | |
| 1919 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1920 | const struct drm_plane_state *state, |
| 1921 | struct drm_property *property, uint64_t *val) |
| 1922 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1923 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1924 | struct sde_plane_state *pstate; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1925 | int ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1926 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1927 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1928 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1929 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1930 | SDE_ERROR("invalid state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1931 | } else { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1932 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1933 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1934 | ret = msm_property_atomic_get(&psde->property_info, |
| 1935 | pstate->property_values, pstate->property_blobs, |
| 1936 | property, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1937 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1938 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1939 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1940 | } |
| 1941 | |
| 1942 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1943 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1944 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1945 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1946 | SDE_DEBUG_PLANE(psde, "\n"); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1947 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1948 | if (psde) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1949 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1950 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1951 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1952 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1953 | if (psde->blob_info) |
| 1954 | drm_property_unreference_blob(psde->blob_info); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1955 | msm_property_destroy(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1956 | mutex_destroy(&psde->lock); |
| 1957 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1958 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1959 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1960 | /* this will destroy the states as well */ |
| 1961 | drm_plane_cleanup(plane); |
| 1962 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1963 | if (psde->pipe_hw) |
| 1964 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1965 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1966 | kfree(psde); |
| 1967 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1968 | } |
| 1969 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1970 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1971 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1972 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1973 | struct sde_plane *psde; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1974 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1975 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1976 | if (!plane || !state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1977 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 1978 | plane != 0, state != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1979 | return; |
| 1980 | } |
| 1981 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1982 | psde = to_sde_plane(plane); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1983 | pstate = to_sde_plane_state(state); |
| 1984 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1985 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1986 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1987 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1988 | if (state->fb) |
| 1989 | drm_framebuffer_unreference(state->fb); |
| 1990 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1991 | /* remove ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1992 | if (pstate->input_fence) |
| 1993 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1994 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1995 | /* destroy value helper */ |
| 1996 | msm_property_destroy_state(&psde->property_info, pstate, |
| 1997 | pstate->property_values, pstate->property_blobs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1998 | } |
| 1999 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2000 | static struct drm_plane_state * |
| 2001 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2002 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2003 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2004 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2005 | struct sde_plane_state *old_state; |
Clarence Ip | 17e908b | 2016-09-29 15:58:00 -0400 | [diff] [blame] | 2006 | uint64_t input_fence_default; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2007 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2008 | if (!plane) { |
| 2009 | SDE_ERROR("invalid plane\n"); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2010 | return NULL; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2011 | } else if (!plane->state) { |
| 2012 | SDE_ERROR("invalid plane state\n"); |
| 2013 | return NULL; |
| 2014 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2015 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2016 | old_state = to_sde_plane_state(plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2017 | psde = to_sde_plane(plane); |
| 2018 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2019 | if (!pstate) { |
| 2020 | SDE_ERROR_PLANE(psde, "failed to allocate state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2021 | return NULL; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2022 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2023 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2024 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2025 | |
| 2026 | /* duplicate value helper */ |
| 2027 | msm_property_duplicate_state(&psde->property_info, old_state, pstate, |
| 2028 | pstate->property_values, pstate->property_blobs); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2029 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2030 | /* add ref count for frame buffer */ |
| 2031 | if (pstate->base.fb) |
| 2032 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2033 | |
Clarence Ip | 17e908b | 2016-09-29 15:58:00 -0400 | [diff] [blame] | 2034 | /* clear out any input fence */ |
| 2035 | pstate->input_fence = 0; |
| 2036 | input_fence_default = msm_property_get_default( |
| 2037 | &psde->property_info, PLANE_PROP_INPUT_FENCE); |
| 2038 | msm_property_set_property(&psde->property_info, pstate->property_values, |
| 2039 | PLANE_PROP_INPUT_FENCE, input_fence_default); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2040 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 2041 | pstate->dirty = 0x0; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2042 | pstate->pending = false; |
| 2043 | |
| 2044 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2045 | } |
| 2046 | |
| 2047 | static void sde_plane_reset(struct drm_plane *plane) |
| 2048 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2049 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2050 | struct sde_plane_state *pstate; |
| 2051 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2052 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2053 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2054 | return; |
| 2055 | } |
| 2056 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2057 | psde = to_sde_plane(plane); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2058 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2059 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2060 | /* remove previous state, if present */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2061 | if (plane->state) { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2062 | sde_plane_destroy_state(plane, plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2063 | plane->state = 0; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 2064 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2065 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2066 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2067 | if (!pstate) { |
| 2068 | SDE_ERROR_PLANE(psde, "failed to allocate state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2069 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2070 | } |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2071 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2072 | /* reset value helper */ |
| 2073 | msm_property_reset_state(&psde->property_info, pstate, |
| 2074 | pstate->property_values, pstate->property_blobs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2075 | |
| 2076 | pstate->base.plane = plane; |
| 2077 | |
| 2078 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2079 | } |
| 2080 | |
| 2081 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2082 | .update_plane = drm_atomic_helper_update_plane, |
| 2083 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2084 | .destroy = sde_plane_destroy, |
| 2085 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2086 | .atomic_set_property = sde_plane_atomic_set_property, |
| 2087 | .atomic_get_property = sde_plane_atomic_get_property, |
| 2088 | .reset = sde_plane_reset, |
| 2089 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 2090 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2091 | }; |
| 2092 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2093 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 2094 | .prepare_fb = sde_plane_prepare_fb, |
| 2095 | .cleanup_fb = sde_plane_cleanup_fb, |
| 2096 | .atomic_check = sde_plane_atomic_check, |
| 2097 | .atomic_update = sde_plane_atomic_update, |
| 2098 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2099 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2100 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2101 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2102 | return plane ? to_sde_plane(plane)->pipe : SSPP_NONE; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2103 | } |
| 2104 | |
Alan Kwong | f0fd851 | 2016-10-24 21:39:26 -0400 | [diff] [blame] | 2105 | static ssize_t _sde_plane_danger_read(struct file *file, |
| 2106 | char __user *buff, size_t count, loff_t *ppos) |
| 2107 | { |
| 2108 | struct sde_kms *kms = file->private_data; |
| 2109 | struct sde_mdss_cfg *cfg = kms->catalog; |
| 2110 | int len = 0; |
| 2111 | char buf[40] = {'\0'}; |
| 2112 | |
| 2113 | if (!cfg) |
| 2114 | return -ENODEV; |
| 2115 | |
| 2116 | if (*ppos) |
| 2117 | return 0; /* the end */ |
| 2118 | |
| 2119 | len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); |
| 2120 | if (len < 0 || len >= sizeof(buf)) |
| 2121 | return 0; |
| 2122 | |
| 2123 | if ((count < sizeof(buf)) || copy_to_user(buff, buf, len)) |
| 2124 | return -EFAULT; |
| 2125 | |
| 2126 | *ppos += len; /* increase offset */ |
| 2127 | |
| 2128 | return len; |
| 2129 | } |
| 2130 | |
| 2131 | static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable) |
| 2132 | { |
| 2133 | struct drm_plane *plane; |
| 2134 | |
| 2135 | drm_for_each_plane(plane, kms->dev) { |
| 2136 | if (plane->fb && plane->state) { |
| 2137 | sde_plane_danger_signal_ctrl(plane, enable); |
| 2138 | SDE_DEBUG("plane:%d img:%dx%d ", |
| 2139 | plane->base.id, plane->fb->width, |
| 2140 | plane->fb->height); |
| 2141 | SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", |
| 2142 | plane->state->src_x >> 16, |
| 2143 | plane->state->src_y >> 16, |
| 2144 | plane->state->src_w >> 16, |
| 2145 | plane->state->src_h >> 16, |
| 2146 | plane->state->crtc_x, plane->state->crtc_y, |
| 2147 | plane->state->crtc_w, plane->state->crtc_h); |
| 2148 | } else { |
| 2149 | SDE_DEBUG("Inactive plane:%d\n", plane->base.id); |
| 2150 | } |
| 2151 | } |
| 2152 | } |
| 2153 | |
| 2154 | static ssize_t _sde_plane_danger_write(struct file *file, |
| 2155 | const char __user *user_buf, size_t count, loff_t *ppos) |
| 2156 | { |
| 2157 | struct sde_kms *kms = file->private_data; |
| 2158 | struct sde_mdss_cfg *cfg = kms->catalog; |
| 2159 | int disable_panic; |
| 2160 | char buf[10]; |
| 2161 | |
| 2162 | if (!cfg) |
| 2163 | return -EFAULT; |
| 2164 | |
| 2165 | if (count >= sizeof(buf)) |
| 2166 | return -EFAULT; |
| 2167 | |
| 2168 | if (copy_from_user(buf, user_buf, count)) |
| 2169 | return -EFAULT; |
| 2170 | |
| 2171 | buf[count] = 0; /* end of string */ |
| 2172 | |
| 2173 | if (kstrtoint(buf, 0, &disable_panic)) |
| 2174 | return -EFAULT; |
| 2175 | |
| 2176 | if (disable_panic) { |
| 2177 | /* Disable panic signal for all active pipes */ |
| 2178 | SDE_DEBUG("Disabling danger:\n"); |
| 2179 | _sde_plane_set_danger_state(kms, false); |
| 2180 | kms->has_danger_ctrl = false; |
| 2181 | } else { |
| 2182 | /* Enable panic signal for all active pipes */ |
| 2183 | SDE_DEBUG("Enabling danger:\n"); |
| 2184 | kms->has_danger_ctrl = true; |
| 2185 | _sde_plane_set_danger_state(kms, true); |
| 2186 | } |
| 2187 | |
| 2188 | return count; |
| 2189 | } |
| 2190 | |
| 2191 | static const struct file_operations sde_plane_danger_enable = { |
| 2192 | .open = simple_open, |
| 2193 | .read = _sde_plane_danger_read, |
| 2194 | .write = _sde_plane_danger_write, |
| 2195 | }; |
| 2196 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2197 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 2198 | { |
| 2199 | const struct sde_sspp_sub_blks *sblk = 0; |
| 2200 | const struct sde_sspp_cfg *cfg = 0; |
| 2201 | |
| 2202 | if (psde && psde->pipe_hw) |
| 2203 | cfg = psde->pipe_hw->cap; |
| 2204 | if (cfg) |
| 2205 | sblk = cfg->sblk; |
| 2206 | |
| 2207 | if (kms && sblk) { |
| 2208 | /* create overall sub-directory for the pipe */ |
| 2209 | psde->debugfs_root = |
| 2210 | debugfs_create_dir(psde->pipe_name, |
| 2211 | sde_debugfs_get_root(kms)); |
| 2212 | if (psde->debugfs_root) { |
| 2213 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2214 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2215 | psde->debugfs_root, &psde->features); |
| 2216 | |
| 2217 | /* add register dump support */ |
| 2218 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 2219 | sblk->src_blk.base + cfg->base, |
| 2220 | sblk->src_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 2221 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2222 | sde_debugfs_create_regset32("src_blk", 0444, |
| 2223 | psde->debugfs_root, &psde->debugfs_src); |
| 2224 | |
| 2225 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 2226 | sblk->scaler_blk.base + cfg->base, |
| 2227 | sblk->scaler_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 2228 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2229 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 2230 | psde->debugfs_root, |
| 2231 | &psde->debugfs_scaler); |
| 2232 | |
| 2233 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 2234 | sblk->csc_blk.base + cfg->base, |
| 2235 | sblk->csc_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 2236 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2237 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 2238 | psde->debugfs_root, &psde->debugfs_csc); |
Alan Kwong | f0fd851 | 2016-10-24 21:39:26 -0400 | [diff] [blame] | 2239 | |
| 2240 | debugfs_create_u32("xin_id", |
| 2241 | 0444, |
| 2242 | psde->debugfs_root, |
| 2243 | (u32 *) &cfg->xin_id); |
| 2244 | debugfs_create_u32("clk_ctrl", |
| 2245 | 0444, |
| 2246 | psde->debugfs_root, |
| 2247 | (u32 *) &cfg->clk_ctrl); |
| 2248 | debugfs_create_x32("creq_vblank", |
| 2249 | 0644, |
| 2250 | psde->debugfs_root, |
| 2251 | (u32 *) &sblk->creq_vblank); |
| 2252 | debugfs_create_x32("danger_vblank", |
| 2253 | 0644, |
| 2254 | psde->debugfs_root, |
| 2255 | (u32 *) &sblk->danger_vblank); |
| 2256 | |
| 2257 | debugfs_create_file("disable_danger", |
| 2258 | 0644, |
| 2259 | psde->debugfs_root, |
| 2260 | kms, &sde_plane_danger_enable); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2261 | } |
| 2262 | } |
| 2263 | } |
| 2264 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2265 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 2266 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 2bbf7b3 | 2016-09-23 15:07:16 -0400 | [diff] [blame] | 2267 | uint32_t pipe, bool primary_plane, |
| 2268 | unsigned long possible_crtcs) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2269 | { |
| 2270 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2271 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2272 | struct msm_drm_private *priv; |
| 2273 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2274 | enum drm_plane_type type; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2275 | int ret = -EINVAL; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2276 | |
| 2277 | if (!dev) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2278 | SDE_ERROR("[%u]device is NULL\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2279 | goto exit; |
| 2280 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2281 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2282 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2283 | if (!priv) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2284 | SDE_ERROR("[%u]private data is NULL\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2285 | goto exit; |
| 2286 | } |
| 2287 | |
| 2288 | if (!priv->kms) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2289 | SDE_ERROR("[%u]invalid KMS reference\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2290 | goto exit; |
| 2291 | } |
| 2292 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2293 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2294 | if (!kms->catalog) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2295 | SDE_ERROR("[%u]invalid catalog reference\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2296 | goto exit; |
| 2297 | } |
| 2298 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2299 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2300 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 2301 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2302 | SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2303 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2304 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2305 | } |
| 2306 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2307 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2308 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2309 | psde->pipe = pipe; |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 2310 | psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2311 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2312 | /* initialize underlying h/w driver */ |
| 2313 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 2314 | if (IS_ERR(psde->pipe_hw)) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2315 | SDE_ERROR("[%u]SSPP init failed\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2316 | ret = PTR_ERR(psde->pipe_hw); |
| 2317 | goto clean_plane; |
| 2318 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2319 | SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2320 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2321 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2322 | |
| 2323 | /* cache features mask for later */ |
| 2324 | psde->features = psde->pipe_hw->cap->features; |
| 2325 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 2326 | if (!psde->pipe_sblk) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2327 | SDE_ERROR("[%u]invalid sblk\n", pipe); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 2328 | goto clean_sspp; |
| 2329 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2330 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 2331 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 2332 | psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg), |
| 2333 | GFP_KERNEL); |
| 2334 | if (!psde->scaler3_cfg) { |
| 2335 | SDE_ERROR("[%u]failed to allocate scale struct\n", |
| 2336 | pipe); |
| 2337 | ret = -ENOMEM; |
| 2338 | goto clean_sspp; |
| 2339 | } |
| 2340 | } |
| 2341 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2342 | /* add plane to DRM framework */ |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 2343 | psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list, |
| 2344 | psde->formats, |
| 2345 | 0, |
| 2346 | ARRAY_SIZE(psde->formats)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2347 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2348 | if (!psde->nformats) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2349 | SDE_ERROR("[%u]no valid formats for plane\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2350 | goto clean_sspp; |
| 2351 | } |
| 2352 | |
| 2353 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 2354 | type = DRM_PLANE_TYPE_CURSOR; |
| 2355 | else if (primary_plane) |
| 2356 | type = DRM_PLANE_TYPE_PRIMARY; |
| 2357 | else |
| 2358 | type = DRM_PLANE_TYPE_OVERLAY; |
Clarence Ip | 2bbf7b3 | 2016-09-23 15:07:16 -0400 | [diff] [blame] | 2359 | ret = drm_universal_plane_init(dev, plane, possible_crtcs, |
| 2360 | &sde_plane_funcs, psde->formats, psde->nformats, type); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2361 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2362 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2363 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2364 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2365 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2366 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2367 | msm_property_init(&psde->property_info, &plane->base, dev, |
| 2368 | priv->plane_property, psde->property_data, |
| 2369 | PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT, |
| 2370 | sizeof(struct sde_plane_state)); |
| 2371 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2372 | _sde_plane_install_properties(plane, kms->catalog); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 2373 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2374 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 2375 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2376 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2377 | mutex_init(&psde->lock); |
| 2378 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2379 | _sde_plane_init_debugfs(psde, kms); |
| 2380 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 2381 | DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2382 | return plane; |
| 2383 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2384 | clean_sspp: |
| 2385 | if (psde && psde->pipe_hw) |
| 2386 | sde_hw_sspp_destroy(psde->pipe_hw); |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 2387 | |
| 2388 | if (psde && psde->scaler3_cfg) |
| 2389 | kfree(psde->scaler3_cfg); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2390 | clean_plane: |
| 2391 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2392 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2393 | return ERR_PTR(ret); |
| 2394 | } |