Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-integrator/integrator_cp.c |
| 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License. |
| 9 | */ |
| 10 | #include <linux/types.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/list.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 14 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/dma-mapping.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <linux/string.h> |
Kay Sievers | edbaa60 | 2011-12-21 16:26:03 -0800 | [diff] [blame] | 17 | #include <linux/device.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 18 | #include <linux/amba/bus.h> |
| 19 | #include <linux/amba/kmi.h> |
| 20 | #include <linux/amba/clcd.h> |
Linus Walleij | 11c32d7 | 2014-05-22 23:25:14 +0200 | [diff] [blame] | 21 | #include <linux/platform_data/video-clcd-versatile.h> |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 22 | #include <linux/amba/mmci.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Rob Herring | 44fa72d | 2014-05-29 16:44:27 -0500 | [diff] [blame] | 24 | #include <linux/irqchip.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 25 | #include <linux/gfp.h> |
Marc Zyngier | 046dfa0 | 2011-05-18 10:51:53 +0100 | [diff] [blame] | 26 | #include <linux/mtd/physmap.h> |
Linus Walleij | 4980f9b | 2012-09-06 09:08:24 +0100 | [diff] [blame] | 27 | #include <linux/of_irq.h> |
| 28 | #include <linux/of_address.h> |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 29 | #include <linux/of_platform.h> |
Linus Walleij | a79528e | 2014-02-13 21:35:07 +0100 | [diff] [blame] | 30 | #include <linux/sched_clock.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <asm/setup.h> |
| 33 | #include <asm/mach-types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <asm/mach/arch.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/mach/irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <asm/mach/map.h> |
| 37 | #include <asm/mach/time.h> |
| 38 | |
Linus Walleij | 1b1ef75 | 2014-02-13 21:26:24 +0100 | [diff] [blame] | 39 | #include "hardware.h" |
Linus Walleij | bb4dbef | 2013-06-16 02:44:27 +0200 | [diff] [blame] | 40 | #include "cm.h" |
Russell King | 98c672c | 2010-05-22 18:18:57 +0100 | [diff] [blame] | 41 | #include "common.h" |
| 42 | |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 43 | /* Base address to the CP controller */ |
| 44 | static void __iomem *intcp_con_base; |
| 45 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #define INTCP_PA_FLASH_BASE 0x24000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
| 48 | #define INTCP_PA_CLCD_BASE 0xc0000000 |
| 49 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | #define INTCP_FLASHPROG 0x04 |
| 51 | #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) |
| 52 | #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) |
| 53 | |
| 54 | /* |
| 55 | * Logical Physical |
Linus Walleij | 608914b | 2014-01-24 14:04:28 +0100 | [diff] [blame] | 56 | * f1000000 10000000 Core module registers |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | * f1300000 13000000 Counter/Timer |
| 58 | * f1400000 14000000 Interrupt controller |
| 59 | * f1600000 16000000 UART 0 |
| 60 | * f1700000 17000000 UART 1 |
| 61 | * f1a00000 1a000000 Debug LEDs |
Russell King | da7ba95 | 2010-01-17 19:59:58 +0000 | [diff] [blame] | 62 | * fc900000 c9000000 GPIO |
| 63 | * fca00000 ca000000 SIC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | */ |
| 65 | |
Arnd Bergmann | 060fd1b | 2013-02-14 13:50:57 +0100 | [diff] [blame] | 66 | static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 67 | { |
Linus Walleij | 608914b | 2014-01-24 14:04:28 +0100 | [diff] [blame] | 68 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), |
| 69 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), |
| 70 | .length = SZ_4K, |
| 71 | .type = MT_DEVICE |
| 72 | }, { |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 73 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), |
| 74 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), |
| 75 | .length = SZ_4K, |
| 76 | .type = MT_DEVICE |
| 77 | }, { |
| 78 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), |
| 79 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), |
| 80 | .length = SZ_4K, |
| 81 | .type = MT_DEVICE |
| 82 | }, { |
| 83 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), |
| 84 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), |
| 85 | .length = SZ_4K, |
| 86 | .type = MT_DEVICE |
| 87 | }, { |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 88 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), |
| 89 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), |
| 90 | .length = SZ_4K, |
| 91 | .type = MT_DEVICE |
| 92 | }, { |
Russell King | da7ba95 | 2010-01-17 19:59:58 +0000 | [diff] [blame] | 93 | .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE), |
| 94 | .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE), |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 95 | .length = SZ_4K, |
| 96 | .type = MT_DEVICE |
| 97 | }, { |
Russell King | da7ba95 | 2010-01-17 19:59:58 +0000 | [diff] [blame] | 98 | .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), |
| 99 | .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 100 | .length = SZ_4K, |
| 101 | .type = MT_DEVICE |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 102 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | static void __init intcp_map_io(void) |
| 106 | { |
| 107 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); |
| 108 | } |
| 109 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | * Flash handling. |
| 112 | */ |
Marc Zyngier | 046dfa0 | 2011-05-18 10:51:53 +0100 | [diff] [blame] | 113 | static int intcp_flash_init(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | { |
| 115 | u32 val; |
| 116 | |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 117 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | val |= CINTEGRATOR_FLASHPROG_FLWREN; |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 119 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | |
Marc Zyngier | 046dfa0 | 2011-05-18 10:51:53 +0100 | [diff] [blame] | 124 | static void intcp_flash_exit(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | { |
| 126 | u32 val; |
| 127 | |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 128 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 130 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Marc Zyngier | 667f390 | 2011-05-18 10:51:55 +0100 | [diff] [blame] | 133 | static void intcp_flash_set_vpp(struct platform_device *pdev, int on) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | { |
| 135 | u32 val; |
| 136 | |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 137 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | if (on) |
| 139 | val |= CINTEGRATOR_FLASHPROG_FLVPPEN; |
| 140 | else |
| 141 | val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 142 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Marc Zyngier | 046dfa0 | 2011-05-18 10:51:53 +0100 | [diff] [blame] | 145 | static struct physmap_flash_data intcp_flash_data = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | .width = 4, |
| 147 | .init = intcp_flash_init, |
| 148 | .exit = intcp_flash_exit, |
| 149 | .set_vpp = intcp_flash_set_vpp, |
| 150 | }; |
| 151 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | /* |
| 153 | * It seems that the card insertion interrupt remains active after |
| 154 | * we've acknowledged it. We therefore ignore the interrupt, and |
| 155 | * rely on reading it from the SIC. This also means that we must |
| 156 | * clear the latched interrupt. |
| 157 | */ |
| 158 | static unsigned int mmc_status(struct device *dev) |
| 159 | { |
Arnd Bergmann | b7a3f8d | 2012-09-14 20:16:39 +0000 | [diff] [blame] | 160 | unsigned int status = readl(__io_address(0xca000000 + 4)); |
Linus Walleij | e6fae08 | 2012-11-04 21:03:02 +0100 | [diff] [blame] | 161 | writel(8, intcp_con_base + 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | |
| 163 | return status & 8; |
| 164 | } |
| 165 | |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 166 | static struct mmci_platform_data mmc_data = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 168 | .status = mmc_status, |
Russell King | 7fb2bbf | 2009-07-09 15:15:12 +0100 | [diff] [blame] | 169 | .gpio_wp = -1, |
| 170 | .gpio_cd = -1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | }; |
| 172 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | /* |
| 174 | * CLCD support |
| 175 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 176 | /* |
| 177 | * Ensure VGA is selected. |
| 178 | */ |
| 179 | static void cp_clcd_enable(struct clcd_fb *fb) |
| 180 | { |
Russell King | e6b9c1f | 2011-01-22 11:02:10 +0000 | [diff] [blame] | 181 | struct fb_var_screeninfo *var = &fb->fb.var; |
Jonathan Austin | 30aeadd | 2013-08-29 18:41:11 +0100 | [diff] [blame] | 182 | u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2 |
| 183 | | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1; |
Russell King | 4774e22 | 2005-04-30 23:32:38 +0100 | [diff] [blame] | 184 | |
Russell King | e6b9c1f | 2011-01-22 11:02:10 +0000 | [diff] [blame] | 185 | if (var->bits_per_pixel <= 8 || |
| 186 | (var->bits_per_pixel == 16 && var->green.length == 5)) |
| 187 | /* Pseudocolor, RGB555, BGR555 */ |
| 188 | val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555; |
Russell King | 4774e22 | 2005-04-30 23:32:38 +0100 | [diff] [blame] | 189 | else if (fb->fb.var.bits_per_pixel <= 16) |
Russell King | e6b9c1f | 2011-01-22 11:02:10 +0000 | [diff] [blame] | 190 | /* truecolor RGB565 */ |
| 191 | val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555; |
Russell King | 4774e22 | 2005-04-30 23:32:38 +0100 | [diff] [blame] | 192 | else |
| 193 | val = 0; /* no idea for this, don't trust the docs */ |
| 194 | |
| 195 | cm_control(CM_CTRL_LCDMUXSEL_MASK| |
| 196 | CM_CTRL_LCDEN0| |
| 197 | CM_CTRL_LCDEN1| |
| 198 | CM_CTRL_STATIC1| |
| 199 | CM_CTRL_STATIC2| |
| 200 | CM_CTRL_STATIC| |
| 201 | CM_CTRL_n24BITEN, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | } |
| 203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | static int cp_clcd_setup(struct clcd_fb *fb) |
| 205 | { |
Russell King | 9dfec4f | 2011-01-18 20:10:10 +0000 | [diff] [blame] | 206 | fb->panel = versatile_clcd_get_panel("VGA"); |
| 207 | if (!fb->panel) |
| 208 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | |
Russell King | 9dfec4f | 2011-01-18 20:10:10 +0000 | [diff] [blame] | 210 | return versatile_clcd_setup_dma(fb, SZ_1M); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | static struct clcd_board clcd_data = { |
| 214 | .name = "Integrator/CP", |
Russell King | 9dfec4f | 2011-01-18 20:10:10 +0000 | [diff] [blame] | 215 | .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | .check = clcdfb_check, |
| 217 | .decode = clcdfb_decode, |
| 218 | .enable = cp_clcd_enable, |
| 219 | .setup = cp_clcd_setup, |
Russell King | 9dfec4f | 2011-01-18 20:10:10 +0000 | [diff] [blame] | 220 | .mmap = versatile_clcd_mmap_dma, |
| 221 | .remove = versatile_clcd_remove_dma, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | }; |
| 223 | |
Russell King | d77e270 | 2011-01-22 11:37:54 +0000 | [diff] [blame] | 224 | #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) |
| 225 | |
Linus Walleij | a79528e | 2014-02-13 21:35:07 +0100 | [diff] [blame] | 226 | static u64 notrace intcp_read_sched_clock(void) |
| 227 | { |
| 228 | return readl(REFCOUNTER); |
| 229 | } |
| 230 | |
Russell King | c735c98 | 2011-01-11 13:00:04 +0000 | [diff] [blame] | 231 | static void __init intcp_init_early(void) |
| 232 | { |
Linus Walleij | a79528e | 2014-02-13 21:35:07 +0100 | [diff] [blame] | 233 | sched_clock_register(intcp_read_sched_clock, 32, 24000000); |
Russell King | c735c98 | 2011-01-11 13:00:04 +0000 | [diff] [blame] | 234 | } |
| 235 | |
Linus Walleij | 4980f9b | 2012-09-06 09:08:24 +0100 | [diff] [blame] | 236 | static void __init intcp_init_irq_of(void) |
| 237 | { |
Linus Walleij | bb4dbef | 2013-06-16 02:44:27 +0200 | [diff] [blame] | 238 | cm_init(); |
Rob Herring | 44fa72d | 2014-05-29 16:44:27 -0500 | [diff] [blame] | 239 | irqchip_init(); |
Linus Walleij | 4980f9b | 2012-09-06 09:08:24 +0100 | [diff] [blame] | 240 | } |
| 241 | |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 242 | /* |
| 243 | * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA |
| 244 | * and enforce the bus names since these are used for clock lookups. |
| 245 | */ |
| 246 | static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { |
| 247 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, |
| 248 | "rtc", NULL), |
| 249 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 250 | "uart0", NULL), |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 251 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 252 | "uart1", NULL), |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 253 | OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, |
| 254 | "kmi0", NULL), |
| 255 | OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, |
| 256 | "kmi1", NULL), |
| 257 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE, |
| 258 | "mmci", &mmc_data), |
| 259 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE, |
| 260 | "aaci", &mmc_data), |
| 261 | OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE, |
| 262 | "clcd", &clcd_data), |
Linus Walleij | 73efd53 | 2012-09-06 09:09:11 +0100 | [diff] [blame] | 263 | OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE, |
| 264 | "physmap-flash", &intcp_flash_data), |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 265 | { /* sentinel */ }, |
| 266 | }; |
| 267 | |
Linus Walleij | df36680 | 2013-10-10 18:24:58 +0200 | [diff] [blame] | 268 | static const struct of_device_id intcp_syscon_match[] = { |
| 269 | { .compatible = "arm,integrator-cp-syscon"}, |
| 270 | { }, |
| 271 | }; |
| 272 | |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 273 | static void __init intcp_init_of(void) |
| 274 | { |
Linus Walleij | 64100a0 | 2012-11-02 01:20:43 +0100 | [diff] [blame] | 275 | struct device_node *cpcon; |
Linus Walleij | 64100a0 | 2012-11-02 01:20:43 +0100 | [diff] [blame] | 276 | |
Linus Walleij | 11f9323 | 2014-06-24 14:08:07 +0200 | [diff] [blame] | 277 | cpcon = of_find_matching_node(NULL, intcp_syscon_match); |
Linus Walleij | 64100a0 | 2012-11-02 01:20:43 +0100 | [diff] [blame] | 278 | if (!cpcon) |
| 279 | return; |
| 280 | |
| 281 | intcp_con_base = of_iomap(cpcon, 0); |
| 282 | if (!intcp_con_base) |
| 283 | return; |
| 284 | |
Linus Walleij | 11f9323 | 2014-06-24 14:08:07 +0200 | [diff] [blame] | 285 | of_platform_populate(NULL, of_default_bus_match_table, |
| 286 | intcp_auxdata_lookup, NULL); |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 287 | } |
| 288 | |
Linus Walleij | 4980f9b | 2012-09-06 09:08:24 +0100 | [diff] [blame] | 289 | static const char * intcp_dt_board_compat[] = { |
| 290 | "arm,integrator-cp", |
| 291 | NULL, |
| 292 | }; |
| 293 | |
| 294 | DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") |
| 295 | .reserve = integrator_reserve, |
| 296 | .map_io = intcp_map_io, |
Linus Walleij | 4980f9b | 2012-09-06 09:08:24 +0100 | [diff] [blame] | 297 | .init_early = intcp_init_early, |
| 298 | .init_irq = intcp_init_irq_of, |
Linus Walleij | 4672cdd | 2012-09-06 09:08:47 +0100 | [diff] [blame] | 299 | .init_machine = intcp_init_of, |
Linus Walleij | 4980f9b | 2012-09-06 09:08:24 +0100 | [diff] [blame] | 300 | .dt_compat = intcp_dt_board_compat, |
| 301 | MACHINE_END |