Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2 | * Performance events x86 architecture code |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 3 | * |
Ingo Molnar | 9814451 | 2009-04-29 14:52:50 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
Peter Zijlstra | 90eec10 | 2015-11-16 11:08:45 +0100 | [diff] [blame] | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 11 | * |
| 12 | * For licencing details see kernel-base/COPYING |
| 13 | */ |
| 14 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 15 | #include <linux/perf_event.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 16 | #include <linux/capability.h> |
| 17 | #include <linux/notifier.h> |
| 18 | #include <linux/hardirq.h> |
| 19 | #include <linux/kprobes.h> |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 21 | #include <linux/kdebug.h> |
| 22 | #include <linux/sched.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 23 | #include <linux/uaccess.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 24 | #include <linux/slab.h> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 25 | #include <linux/cpu.h> |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 26 | #include <linux/bitops.h> |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 27 | #include <linux/device.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 28 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 29 | #include <asm/apic.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 30 | #include <asm/stacktrace.h> |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 31 | #include <asm/nmi.h> |
Lin Ming | 6909262 | 2011-03-03 10:34:50 +0800 | [diff] [blame] | 32 | #include <asm/smp.h> |
Robert Richter | c8e5910 | 2011-04-16 02:27:55 +0200 | [diff] [blame] | 33 | #include <asm/alternative.h> |
Andy Lutomirski | 7911d3f | 2014-10-24 15:58:12 -0700 | [diff] [blame] | 34 | #include <asm/mmu_context.h> |
Andy Lutomirski | 375074c | 2014-10-24 15:58:07 -0700 | [diff] [blame] | 35 | #include <asm/tlbflush.h> |
Peter Zijlstra | e3f3541 | 2011-11-21 11:43:53 +0100 | [diff] [blame] | 36 | #include <asm/timer.h> |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 37 | #include <asm/desc.h> |
| 38 | #include <asm/ldt.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 39 | |
Borislav Petkov | 27f6d22 | 2016-02-10 10:55:23 +0100 | [diff] [blame] | 40 | #include "perf_event.h" |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 41 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 42 | struct x86_pmu x86_pmu __read_mostly; |
Stephane Eranian | efc9f05 | 2011-06-06 16:57:03 +0200 | [diff] [blame] | 43 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 44 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 45 | .enabled = 1, |
| 46 | }; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 47 | |
Andy Lutomirski | a667342 | 2014-10-24 15:58:13 -0700 | [diff] [blame] | 48 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
| 49 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 50 | u64 __read_mostly hw_cache_event_ids |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 51 | [PERF_COUNT_HW_CACHE_MAX] |
| 52 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 54 | u64 __read_mostly hw_cache_extra_regs |
Andi Kleen | e994d7d | 2011-03-03 10:34:48 +0800 | [diff] [blame] | 55 | [PERF_COUNT_HW_CACHE_MAX] |
| 56 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 58 | |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 59 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 60 | * Propagate event elapsed time into the generic event. |
| 61 | * Can only be executed on the CPU where the event is active. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 62 | * Returns the delta events processed. |
| 63 | */ |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 64 | u64 x86_perf_event_update(struct perf_event *event) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 65 | { |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 66 | struct hw_perf_event *hwc = &event->hw; |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 67 | int shift = 64 - x86_pmu.cntval_bits; |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 68 | u64 prev_raw_count, new_raw_count; |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 69 | int idx = hwc->idx; |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 70 | s64 delta; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 71 | |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 72 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 73 | return 0; |
| 74 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 75 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 76 | * Careful: an NMI might modify the previous event value. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 77 | * |
| 78 | * Our tactic to handle this is to first atomically read and |
| 79 | * exchange a new raw count - then add that new-prev delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 80 | * count to the generic event atomically: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 81 | */ |
| 82 | again: |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 83 | prev_raw_count = local64_read(&hwc->prev_count); |
Vince Weaver | c48b605 | 2012-03-01 17:28:14 -0500 | [diff] [blame] | 84 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 85 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 86 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 87 | new_raw_count) != prev_raw_count) |
| 88 | goto again; |
| 89 | |
| 90 | /* |
| 91 | * Now we have the new raw value and have updated the prev |
| 92 | * timestamp already. We can now calculate the elapsed delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 93 | * (event-)time and add that to the generic event. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 94 | * |
| 95 | * Careful, not all hw sign-extends above the physical width |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 96 | * of the count. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 97 | */ |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 98 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 99 | delta >>= shift; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 100 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 101 | local64_add(delta, &event->count); |
| 102 | local64_sub(delta, &hwc->period_left); |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 103 | |
| 104 | return new_raw_count; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 105 | } |
| 106 | |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 107 | /* |
| 108 | * Find and validate any extra registers to set up. |
| 109 | */ |
| 110 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) |
| 111 | { |
Stephane Eranian | efc9f05 | 2011-06-06 16:57:03 +0200 | [diff] [blame] | 112 | struct hw_perf_event_extra *reg; |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 113 | struct extra_reg *er; |
| 114 | |
Stephane Eranian | efc9f05 | 2011-06-06 16:57:03 +0200 | [diff] [blame] | 115 | reg = &event->hw.extra_reg; |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 116 | |
| 117 | if (!x86_pmu.extra_regs) |
| 118 | return 0; |
| 119 | |
| 120 | for (er = x86_pmu.extra_regs; er->msr; er++) { |
| 121 | if (er->event != (config & er->config_mask)) |
| 122 | continue; |
| 123 | if (event->attr.config1 & ~er->valid_mask) |
| 124 | return -EINVAL; |
Kan Liang | 338b522 | 2014-07-14 12:25:56 -0700 | [diff] [blame] | 125 | /* Check if the extra msrs can be safely accessed*/ |
| 126 | if (!er->extra_msr_access) |
| 127 | return -ENXIO; |
Stephane Eranian | efc9f05 | 2011-06-06 16:57:03 +0200 | [diff] [blame] | 128 | |
| 129 | reg->idx = er->idx; |
| 130 | reg->config = event->attr.config1; |
| 131 | reg->reg = er->msr; |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 132 | break; |
| 133 | } |
| 134 | return 0; |
| 135 | } |
| 136 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 137 | static atomic_t active_events; |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 138 | static atomic_t pmc_refcount; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 139 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 140 | |
Robert Richter | b27ea29 | 2010-03-17 12:49:10 +0100 | [diff] [blame] | 141 | #ifdef CONFIG_X86_LOCAL_APIC |
| 142 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 143 | static bool reserve_pmc_hardware(void) |
| 144 | { |
| 145 | int i; |
| 146 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 148 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 149 | goto perfctr_fail; |
| 150 | } |
| 151 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 152 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 153 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 154 | goto eventsel_fail; |
| 155 | } |
| 156 | |
| 157 | return true; |
| 158 | |
| 159 | eventsel_fail: |
| 160 | for (i--; i >= 0; i--) |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 161 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 162 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 163 | i = x86_pmu.num_counters; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 164 | |
| 165 | perfctr_fail: |
| 166 | for (i--; i >= 0; i--) |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 168 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 169 | return false; |
| 170 | } |
| 171 | |
| 172 | static void release_pmc_hardware(void) |
| 173 | { |
| 174 | int i; |
| 175 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 176 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 177 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
| 178 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 179 | } |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 180 | } |
| 181 | |
Robert Richter | b27ea29 | 2010-03-17 12:49:10 +0100 | [diff] [blame] | 182 | #else |
| 183 | |
| 184 | static bool reserve_pmc_hardware(void) { return true; } |
| 185 | static void release_pmc_hardware(void) {} |
| 186 | |
| 187 | #endif |
| 188 | |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 189 | static bool check_hw_exists(void) |
| 190 | { |
George Dunlap | a5ebe0b | 2013-04-03 15:46:28 +0100 | [diff] [blame] | 191 | u64 val, val_fail, val_new= ~0; |
| 192 | int i, reg, reg_fail, ret = 0; |
| 193 | int bios_fail = 0; |
Don Zickus | 68ab747 | 2015-05-18 15:16:48 -0400 | [diff] [blame] | 194 | int reg_safe = -1; |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 195 | |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 196 | /* |
| 197 | * Check to see if the BIOS enabled any of the counters, if so |
| 198 | * complain and bail. |
| 199 | */ |
| 200 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 201 | reg = x86_pmu_config_addr(i); |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 202 | ret = rdmsrl_safe(reg, &val); |
| 203 | if (ret) |
| 204 | goto msr_fail; |
George Dunlap | a5ebe0b | 2013-04-03 15:46:28 +0100 | [diff] [blame] | 205 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
| 206 | bios_fail = 1; |
| 207 | val_fail = val; |
| 208 | reg_fail = reg; |
Don Zickus | 68ab747 | 2015-05-18 15:16:48 -0400 | [diff] [blame] | 209 | } else { |
| 210 | reg_safe = i; |
George Dunlap | a5ebe0b | 2013-04-03 15:46:28 +0100 | [diff] [blame] | 211 | } |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | if (x86_pmu.num_counters_fixed) { |
| 215 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 216 | ret = rdmsrl_safe(reg, &val); |
| 217 | if (ret) |
| 218 | goto msr_fail; |
| 219 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { |
George Dunlap | a5ebe0b | 2013-04-03 15:46:28 +0100 | [diff] [blame] | 220 | if (val & (0x03 << i*4)) { |
| 221 | bios_fail = 1; |
| 222 | val_fail = val; |
| 223 | reg_fail = reg; |
| 224 | } |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 225 | } |
| 226 | } |
| 227 | |
| 228 | /* |
Don Zickus | 68ab747 | 2015-05-18 15:16:48 -0400 | [diff] [blame] | 229 | * If all the counters are enabled, the below test will always |
| 230 | * fail. The tools will also become useless in this scenario. |
| 231 | * Just fail and disable the hardware counters. |
| 232 | */ |
| 233 | |
| 234 | if (reg_safe == -1) { |
| 235 | reg = reg_safe; |
| 236 | goto msr_fail; |
| 237 | } |
| 238 | |
| 239 | /* |
Andre Przywara | bffd5fc | 2012-10-09 17:38:35 +0200 | [diff] [blame] | 240 | * Read the current value, change it and read it back to see if it |
| 241 | * matches, this is needed to detect certain hardware emulators |
| 242 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 243 | */ |
Don Zickus | 68ab747 | 2015-05-18 15:16:48 -0400 | [diff] [blame] | 244 | reg = x86_pmu_event_addr(reg_safe); |
Andre Przywara | bffd5fc | 2012-10-09 17:38:35 +0200 | [diff] [blame] | 245 | if (rdmsrl_safe(reg, &val)) |
| 246 | goto msr_fail; |
| 247 | val ^= 0xffffUL; |
Robert Richter | f285f92 | 2012-06-20 20:46:36 +0200 | [diff] [blame] | 248 | ret = wrmsrl_safe(reg, val); |
| 249 | ret |= rdmsrl_safe(reg, &val_new); |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 250 | if (ret || val != val_new) |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 251 | goto msr_fail; |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 252 | |
Ingo Molnar | 45daae5 | 2011-03-25 10:24:23 +0100 | [diff] [blame] | 253 | /* |
| 254 | * We still allow the PMU driver to operate: |
| 255 | */ |
George Dunlap | a5ebe0b | 2013-04-03 15:46:28 +0100 | [diff] [blame] | 256 | if (bios_fail) { |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 257 | pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); |
| 258 | pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", |
| 259 | reg_fail, val_fail); |
George Dunlap | a5ebe0b | 2013-04-03 15:46:28 +0100 | [diff] [blame] | 260 | } |
Ingo Molnar | 45daae5 | 2011-03-25 10:24:23 +0100 | [diff] [blame] | 261 | |
| 262 | return true; |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 263 | |
| 264 | msr_fail: |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 265 | pr_cont("Broken PMU hardware detected, using software events only.\n"); |
| 266 | pr_info("%sFailed to access perfctr msr (MSR %x is %Lx)\n", |
Peter Zijlstra (Intel) | 65d71fe | 2014-10-07 19:07:33 +0200 | [diff] [blame] | 267 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, |
| 268 | reg, val_new); |
Ingo Molnar | 45daae5 | 2011-03-25 10:24:23 +0100 | [diff] [blame] | 269 | |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 270 | return false; |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 271 | } |
| 272 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 273 | static void hw_perf_event_destroy(struct perf_event *event) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 274 | { |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 275 | x86_release_hardware(); |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 276 | atomic_dec(&active_events); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 277 | } |
| 278 | |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 279 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
| 280 | { |
| 281 | hw_perf_event_destroy(event); |
| 282 | |
| 283 | /* undo the lbr/bts event accounting */ |
| 284 | x86_del_exclusive(x86_lbr_exclusive_lbr); |
| 285 | } |
| 286 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 287 | static inline int x86_pmu_initialized(void) |
| 288 | { |
| 289 | return x86_pmu.handle_irq != NULL; |
| 290 | } |
| 291 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 292 | static inline int |
Andi Kleen | e994d7d | 2011-03-03 10:34:48 +0800 | [diff] [blame] | 293 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 294 | { |
Andi Kleen | e994d7d | 2011-03-03 10:34:48 +0800 | [diff] [blame] | 295 | struct perf_event_attr *attr = &event->attr; |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 296 | unsigned int cache_type, cache_op, cache_result; |
| 297 | u64 config, val; |
| 298 | |
| 299 | config = attr->config; |
| 300 | |
| 301 | cache_type = (config >> 0) & 0xff; |
| 302 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 303 | return -EINVAL; |
| 304 | |
| 305 | cache_op = (config >> 8) & 0xff; |
| 306 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 307 | return -EINVAL; |
| 308 | |
| 309 | cache_result = (config >> 16) & 0xff; |
| 310 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 311 | return -EINVAL; |
| 312 | |
| 313 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; |
| 314 | |
| 315 | if (val == 0) |
| 316 | return -ENOENT; |
| 317 | |
| 318 | if (val == -1) |
| 319 | return -EINVAL; |
| 320 | |
| 321 | hwc->config |= val; |
Andi Kleen | e994d7d | 2011-03-03 10:34:48 +0800 | [diff] [blame] | 322 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
| 323 | return x86_pmu_extra_regs(val, event); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 324 | } |
| 325 | |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 326 | int x86_reserve_hardware(void) |
| 327 | { |
| 328 | int err = 0; |
| 329 | |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 330 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 331 | mutex_lock(&pmc_reserve_mutex); |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 332 | if (atomic_read(&pmc_refcount) == 0) { |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 333 | if (!reserve_pmc_hardware()) |
| 334 | err = -EBUSY; |
| 335 | else |
| 336 | reserve_ds_buffers(); |
| 337 | } |
| 338 | if (!err) |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 339 | atomic_inc(&pmc_refcount); |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 340 | mutex_unlock(&pmc_reserve_mutex); |
| 341 | } |
| 342 | |
| 343 | return err; |
| 344 | } |
| 345 | |
| 346 | void x86_release_hardware(void) |
| 347 | { |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 348 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 349 | release_pmc_hardware(); |
| 350 | release_ds_buffers(); |
| 351 | mutex_unlock(&pmc_reserve_mutex); |
| 352 | } |
| 353 | } |
| 354 | |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 355 | /* |
| 356 | * Check if we can create event of a certain type (that no conflicting events |
| 357 | * are present). |
| 358 | */ |
| 359 | int x86_add_exclusive(unsigned int what) |
| 360 | { |
Peter Zijlstra | 93472af | 2015-06-24 16:47:50 +0200 | [diff] [blame] | 361 | int i; |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 362 | |
Peter Zijlstra | 93472af | 2015-06-24 16:47:50 +0200 | [diff] [blame] | 363 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
| 364 | mutex_lock(&pmc_reserve_mutex); |
| 365 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { |
| 366 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) |
| 367 | goto fail_unlock; |
| 368 | } |
| 369 | atomic_inc(&x86_pmu.lbr_exclusive[what]); |
| 370 | mutex_unlock(&pmc_reserve_mutex); |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 371 | } |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 372 | |
Peter Zijlstra | 93472af | 2015-06-24 16:47:50 +0200 | [diff] [blame] | 373 | atomic_inc(&active_events); |
| 374 | return 0; |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 375 | |
Peter Zijlstra | 93472af | 2015-06-24 16:47:50 +0200 | [diff] [blame] | 376 | fail_unlock: |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 377 | mutex_unlock(&pmc_reserve_mutex); |
Peter Zijlstra | 93472af | 2015-06-24 16:47:50 +0200 | [diff] [blame] | 378 | return -EBUSY; |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | void x86_del_exclusive(unsigned int what) |
| 382 | { |
| 383 | atomic_dec(&x86_pmu.lbr_exclusive[what]); |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 384 | atomic_dec(&active_events); |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 385 | } |
| 386 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 387 | int x86_setup_perfctr(struct perf_event *event) |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 388 | { |
| 389 | struct perf_event_attr *attr = &event->attr; |
| 390 | struct hw_perf_event *hwc = &event->hw; |
| 391 | u64 config; |
| 392 | |
Franck Bui-Huu | 6c7e550 | 2010-11-23 16:21:43 +0100 | [diff] [blame] | 393 | if (!is_sampling_event(event)) { |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 394 | hwc->sample_period = x86_pmu.max_period; |
| 395 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 396 | local64_set(&hwc->period_left, hwc->sample_period); |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | if (attr->type == PERF_TYPE_RAW) |
Peter Zijlstra | ed13ec5 | 2011-11-14 10:03:25 +0100 | [diff] [blame] | 400 | return x86_pmu_extra_regs(event->attr.config, event); |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 401 | |
| 402 | if (attr->type == PERF_TYPE_HW_CACHE) |
Andi Kleen | e994d7d | 2011-03-03 10:34:48 +0800 | [diff] [blame] | 403 | return set_ext_hw_attr(hwc, event); |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 404 | |
| 405 | if (attr->config >= x86_pmu.max_events) |
| 406 | return -EINVAL; |
| 407 | |
| 408 | /* |
| 409 | * The generic map: |
| 410 | */ |
| 411 | config = x86_pmu.event_map(attr->config); |
| 412 | |
| 413 | if (config == 0) |
| 414 | return -ENOENT; |
| 415 | |
| 416 | if (config == -1LL) |
| 417 | return -EINVAL; |
| 418 | |
| 419 | /* |
| 420 | * Branch tracing: |
| 421 | */ |
Peter Zijlstra | 18a073a | 2011-04-26 13:24:33 +0200 | [diff] [blame] | 422 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
| 423 | !attr->freq && hwc->sample_period == 1) { |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 424 | /* BTS is not supported by this architecture. */ |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 425 | if (!x86_pmu.bts_active) |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 426 | return -EOPNOTSUPP; |
| 427 | |
| 428 | /* BTS is currently only allowed for user-mode. */ |
| 429 | if (!attr->exclude_kernel) |
| 430 | return -EOPNOTSUPP; |
Alexander Shishkin | 4807034 | 2015-01-14 14:18:20 +0200 | [diff] [blame] | 431 | |
| 432 | /* disallow bts if conflicting events are present */ |
| 433 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) |
| 434 | return -EBUSY; |
| 435 | |
| 436 | event->destroy = hw_perf_lbr_event_destroy; |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | hwc->config |= config; |
| 440 | |
| 441 | return 0; |
| 442 | } |
Robert Richter | 4261e0e | 2010-04-13 22:23:10 +0200 | [diff] [blame] | 443 | |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 444 | /* |
| 445 | * check that branch_sample_type is compatible with |
| 446 | * settings needed for precise_ip > 1 which implies |
| 447 | * using the LBR to capture ALL taken branches at the |
| 448 | * priv levels of the measurement |
| 449 | */ |
| 450 | static inline int precise_br_compat(struct perf_event *event) |
| 451 | { |
| 452 | u64 m = event->attr.branch_sample_type; |
| 453 | u64 b = 0; |
| 454 | |
| 455 | /* must capture all branches */ |
| 456 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) |
| 457 | return 0; |
| 458 | |
| 459 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; |
| 460 | |
| 461 | if (!event->attr.exclude_user) |
| 462 | b |= PERF_SAMPLE_BRANCH_USER; |
| 463 | |
| 464 | if (!event->attr.exclude_kernel) |
| 465 | b |= PERF_SAMPLE_BRANCH_KERNEL; |
| 466 | |
| 467 | /* |
| 468 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 |
| 469 | */ |
| 470 | |
| 471 | return m == b; |
| 472 | } |
| 473 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 474 | int x86_pmu_hw_config(struct perf_event *event) |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 475 | { |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 476 | if (event->attr.precise_ip) { |
| 477 | int precise = 0; |
| 478 | |
| 479 | /* Support for constant skid */ |
Peter Zijlstra | c93dc84 | 2012-06-08 14:50:50 +0200 | [diff] [blame] | 480 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 481 | precise++; |
| 482 | |
Peter Zijlstra | 5553be2 | 2010-10-19 14:38:11 +0200 | [diff] [blame] | 483 | /* Support for IP fixup */ |
Andi Kleen | 03de874 | 2014-08-07 17:08:54 -0700 | [diff] [blame] | 484 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
Peter Zijlstra | 5553be2 | 2010-10-19 14:38:11 +0200 | [diff] [blame] | 485 | precise++; |
Andi Kleen | 7246976 | 2015-12-04 03:50:52 -0800 | [diff] [blame] | 486 | |
| 487 | if (x86_pmu.pebs_prec_dist) |
| 488 | precise++; |
Peter Zijlstra | 5553be2 | 2010-10-19 14:38:11 +0200 | [diff] [blame] | 489 | } |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 490 | |
| 491 | if (event->attr.precise_ip > precise) |
| 492 | return -EOPNOTSUPP; |
Yan, Zheng | 4b85490 | 2014-11-04 21:56:08 -0500 | [diff] [blame] | 493 | } |
| 494 | /* |
| 495 | * check that PEBS LBR correction does not conflict with |
| 496 | * whatever the user is asking with attr->branch_sample_type |
| 497 | */ |
| 498 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { |
| 499 | u64 *br_type = &event->attr.branch_sample_type; |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 500 | |
Yan, Zheng | 4b85490 | 2014-11-04 21:56:08 -0500 | [diff] [blame] | 501 | if (has_branch_stack(event)) { |
| 502 | if (!precise_br_compat(event)) |
| 503 | return -EOPNOTSUPP; |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 504 | |
Yan, Zheng | 4b85490 | 2014-11-04 21:56:08 -0500 | [diff] [blame] | 505 | /* branch_sample_type is compatible */ |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 506 | |
Yan, Zheng | 4b85490 | 2014-11-04 21:56:08 -0500 | [diff] [blame] | 507 | } else { |
| 508 | /* |
| 509 | * user did not specify branch_sample_type |
| 510 | * |
| 511 | * For PEBS fixups, we capture all |
| 512 | * the branches at the priv level of the |
| 513 | * event. |
| 514 | */ |
| 515 | *br_type = PERF_SAMPLE_BRANCH_ANY; |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 516 | |
Yan, Zheng | 4b85490 | 2014-11-04 21:56:08 -0500 | [diff] [blame] | 517 | if (!event->attr.exclude_user) |
| 518 | *br_type |= PERF_SAMPLE_BRANCH_USER; |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 519 | |
Yan, Zheng | 4b85490 | 2014-11-04 21:56:08 -0500 | [diff] [blame] | 520 | if (!event->attr.exclude_kernel) |
| 521 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; |
Stephane Eranian | ff3fb51 | 2012-02-09 23:20:54 +0100 | [diff] [blame] | 522 | } |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 523 | } |
| 524 | |
Yan, Zheng | e18bf52 | 2014-11-04 21:56:03 -0500 | [diff] [blame] | 525 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
| 526 | event->attach_state |= PERF_ATTACH_TASK_DATA; |
| 527 | |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 528 | /* |
| 529 | * Generate PMC IRQs: |
| 530 | * (keep 'enabled' bit clear for now) |
| 531 | */ |
Peter Zijlstra | b4cdc5c | 2010-03-30 17:00:06 +0200 | [diff] [blame] | 532 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 533 | |
| 534 | /* |
| 535 | * Count user and OS events unless requested not to |
| 536 | */ |
Peter Zijlstra | b4cdc5c | 2010-03-30 17:00:06 +0200 | [diff] [blame] | 537 | if (!event->attr.exclude_user) |
| 538 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; |
| 539 | if (!event->attr.exclude_kernel) |
| 540 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; |
| 541 | |
| 542 | if (event->attr.type == PERF_TYPE_RAW) |
| 543 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 544 | |
Andi Kleen | 294fe0f | 2015-02-17 18:18:06 -0800 | [diff] [blame] | 545 | if (event->attr.sample_period && x86_pmu.limit_period) { |
| 546 | if (x86_pmu.limit_period(event, event->attr.sample_period) > |
| 547 | event->attr.sample_period) |
| 548 | return -EINVAL; |
| 549 | } |
| 550 | |
Robert Richter | 9d0fcba6 | 2010-04-13 22:23:12 +0200 | [diff] [blame] | 551 | return x86_setup_perfctr(event); |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 552 | } |
| 553 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 554 | /* |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 555 | * Setup the hardware configuration for a given attr_type |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 556 | */ |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 557 | static int __x86_pmu_event_init(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 558 | { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 559 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 560 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 561 | if (!x86_pmu_initialized()) |
| 562 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 563 | |
Alexander Shishkin | 6b099d9 | 2015-06-11 15:13:56 +0300 | [diff] [blame] | 564 | err = x86_reserve_hardware(); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 565 | if (err) |
| 566 | return err; |
| 567 | |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 568 | atomic_inc(&active_events); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 569 | event->destroy = hw_perf_event_destroy; |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 570 | |
Robert Richter | 4261e0e | 2010-04-13 22:23:10 +0200 | [diff] [blame] | 571 | event->hw.idx = -1; |
| 572 | event->hw.last_cpu = -1; |
| 573 | event->hw.last_tag = ~0ULL; |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 574 | |
Stephane Eranian | efc9f05 | 2011-06-06 16:57:03 +0200 | [diff] [blame] | 575 | /* mark unused */ |
| 576 | event->hw.extra_reg.idx = EXTRA_REG_NONE; |
Stephane Eranian | b36817e | 2012-02-09 23:20:53 +0100 | [diff] [blame] | 577 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
| 578 | |
Robert Richter | 9d0fcba6 | 2010-04-13 22:23:12 +0200 | [diff] [blame] | 579 | return x86_pmu.hw_config(event); |
Robert Richter | 4261e0e | 2010-04-13 22:23:10 +0200 | [diff] [blame] | 580 | } |
| 581 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 582 | void x86_pmu_disable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 583 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 584 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 585 | int idx; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 586 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 587 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 588 | u64 val; |
| 589 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 590 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 591 | continue; |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 592 | rdmsrl(x86_pmu_config_addr(idx), val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 593 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 594 | continue; |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 595 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 596 | wrmsrl(x86_pmu_config_addr(idx), val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 597 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 598 | } |
| 599 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 600 | static void x86_pmu_disable(struct pmu *pmu) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 601 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 602 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 603 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 604 | if (!x86_pmu_initialized()) |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 605 | return; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 606 | |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 607 | if (!cpuc->enabled) |
| 608 | return; |
| 609 | |
| 610 | cpuc->n_added = 0; |
| 611 | cpuc->enabled = 0; |
| 612 | barrier(); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 613 | |
| 614 | x86_pmu.disable_all(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 615 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 616 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 617 | void x86_pmu_enable_all(int added) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 618 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 619 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 620 | int idx; |
| 621 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 622 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | d45dd92 | 2011-02-02 17:40:56 +0100 | [diff] [blame] | 623 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 624 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 625 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 626 | continue; |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 627 | |
Robert Richter | d45dd92 | 2011-02-02 17:40:56 +0100 | [diff] [blame] | 628 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 629 | } |
| 630 | } |
| 631 | |
Peter Zijlstra | 51b0fe3 | 2010-06-11 13:35:57 +0200 | [diff] [blame] | 632 | static struct pmu pmu; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 633 | |
| 634 | static inline int is_x86_event(struct perf_event *event) |
| 635 | { |
| 636 | return event->pmu == &pmu; |
| 637 | } |
| 638 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 639 | /* |
| 640 | * Event scheduler state: |
| 641 | * |
| 642 | * Assign events iterating over all events and counters, beginning |
| 643 | * with events with least weights first. Keep the current iterator |
| 644 | * state in struct sched_state. |
| 645 | */ |
| 646 | struct sched_state { |
| 647 | int weight; |
| 648 | int event; /* event index */ |
| 649 | int counter; /* counter index */ |
| 650 | int unassigned; /* number of events to be assigned left */ |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 651 | int nr_gp; /* number of GP counters used */ |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 652 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 653 | }; |
| 654 | |
Robert Richter | bc1738f | 2011-11-18 12:35:22 +0100 | [diff] [blame] | 655 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
| 656 | #define SCHED_STATES_MAX 2 |
| 657 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 658 | struct perf_sched { |
| 659 | int max_weight; |
| 660 | int max_events; |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 661 | int max_gp; |
| 662 | int saved_states; |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 663 | struct event_constraint **constraints; |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 664 | struct sched_state state; |
Robert Richter | bc1738f | 2011-11-18 12:35:22 +0100 | [diff] [blame] | 665 | struct sched_state saved[SCHED_STATES_MAX]; |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 666 | }; |
| 667 | |
| 668 | /* |
| 669 | * Initialize interator that runs through all events and counters. |
| 670 | */ |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 671 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 672 | int num, int wmin, int wmax, int gpmax) |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 673 | { |
| 674 | int idx; |
| 675 | |
| 676 | memset(sched, 0, sizeof(*sched)); |
| 677 | sched->max_events = num; |
| 678 | sched->max_weight = wmax; |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 679 | sched->max_gp = gpmax; |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 680 | sched->constraints = constraints; |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 681 | |
| 682 | for (idx = 0; idx < num; idx++) { |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 683 | if (constraints[idx]->weight == wmin) |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 684 | break; |
| 685 | } |
| 686 | |
| 687 | sched->state.event = idx; /* start with min weight */ |
| 688 | sched->state.weight = wmin; |
| 689 | sched->state.unassigned = num; |
| 690 | } |
| 691 | |
Robert Richter | bc1738f | 2011-11-18 12:35:22 +0100 | [diff] [blame] | 692 | static void perf_sched_save_state(struct perf_sched *sched) |
| 693 | { |
| 694 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) |
| 695 | return; |
| 696 | |
| 697 | sched->saved[sched->saved_states] = sched->state; |
| 698 | sched->saved_states++; |
| 699 | } |
| 700 | |
| 701 | static bool perf_sched_restore_state(struct perf_sched *sched) |
| 702 | { |
| 703 | if (!sched->saved_states) |
| 704 | return false; |
| 705 | |
| 706 | sched->saved_states--; |
| 707 | sched->state = sched->saved[sched->saved_states]; |
| 708 | |
| 709 | /* continue with next counter: */ |
| 710 | clear_bit(sched->state.counter++, sched->state.used); |
| 711 | |
| 712 | return true; |
| 713 | } |
| 714 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 715 | /* |
| 716 | * Select a counter for the current event to schedule. Return true on |
| 717 | * success. |
| 718 | */ |
Robert Richter | bc1738f | 2011-11-18 12:35:22 +0100 | [diff] [blame] | 719 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 720 | { |
| 721 | struct event_constraint *c; |
| 722 | int idx; |
| 723 | |
| 724 | if (!sched->state.unassigned) |
| 725 | return false; |
| 726 | |
| 727 | if (sched->state.event >= sched->max_events) |
| 728 | return false; |
| 729 | |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 730 | c = sched->constraints[sched->state.event]; |
Peter Zijlstra | 4defea8 | 2011-11-10 15:15:42 +0100 | [diff] [blame] | 731 | /* Prefer fixed purpose counters */ |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 732 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
| 733 | idx = INTEL_PMC_IDX_FIXED; |
Akinobu Mita | 307b1cd | 2012-03-23 15:02:03 -0700 | [diff] [blame] | 734 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
Peter Zijlstra | 4defea8 | 2011-11-10 15:15:42 +0100 | [diff] [blame] | 735 | if (!__test_and_set_bit(idx, sched->state.used)) |
| 736 | goto done; |
| 737 | } |
| 738 | } |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 739 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 740 | /* Grab the first unused counter starting with idx */ |
| 741 | idx = sched->state.counter; |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 742 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 743 | if (!__test_and_set_bit(idx, sched->state.used)) { |
| 744 | if (sched->state.nr_gp++ >= sched->max_gp) |
| 745 | return false; |
| 746 | |
Peter Zijlstra | 4defea8 | 2011-11-10 15:15:42 +0100 | [diff] [blame] | 747 | goto done; |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 748 | } |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 749 | } |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 750 | |
Peter Zijlstra | 4defea8 | 2011-11-10 15:15:42 +0100 | [diff] [blame] | 751 | return false; |
| 752 | |
| 753 | done: |
| 754 | sched->state.counter = idx; |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 755 | |
Robert Richter | bc1738f | 2011-11-18 12:35:22 +0100 | [diff] [blame] | 756 | if (c->overlap) |
| 757 | perf_sched_save_state(sched); |
| 758 | |
| 759 | return true; |
| 760 | } |
| 761 | |
| 762 | static bool perf_sched_find_counter(struct perf_sched *sched) |
| 763 | { |
| 764 | while (!__perf_sched_find_counter(sched)) { |
| 765 | if (!perf_sched_restore_state(sched)) |
| 766 | return false; |
| 767 | } |
| 768 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 769 | return true; |
| 770 | } |
| 771 | |
| 772 | /* |
| 773 | * Go through all unassigned events and find the next one to schedule. |
| 774 | * Take events with the least weight first. Return true on success. |
| 775 | */ |
| 776 | static bool perf_sched_next_event(struct perf_sched *sched) |
| 777 | { |
| 778 | struct event_constraint *c; |
| 779 | |
| 780 | if (!sched->state.unassigned || !--sched->state.unassigned) |
| 781 | return false; |
| 782 | |
| 783 | do { |
| 784 | /* next event */ |
| 785 | sched->state.event++; |
| 786 | if (sched->state.event >= sched->max_events) { |
| 787 | /* next weight */ |
| 788 | sched->state.event = 0; |
| 789 | sched->state.weight++; |
| 790 | if (sched->state.weight > sched->max_weight) |
| 791 | return false; |
| 792 | } |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 793 | c = sched->constraints[sched->state.event]; |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 794 | } while (c->weight != sched->state.weight); |
| 795 | |
| 796 | sched->state.counter = 0; /* start with first counter */ |
| 797 | |
| 798 | return true; |
| 799 | } |
| 800 | |
| 801 | /* |
| 802 | * Assign a counter for each event. |
| 803 | */ |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 804 | int perf_assign_events(struct event_constraint **constraints, int n, |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 805 | int wmin, int wmax, int gpmax, int *assign) |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 806 | { |
| 807 | struct perf_sched sched; |
| 808 | |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 809 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 810 | |
| 811 | do { |
| 812 | if (!perf_sched_find_counter(&sched)) |
| 813 | break; /* failed */ |
| 814 | if (assign) |
| 815 | assign[sched.state.event] = sched.state.counter; |
| 816 | } while (perf_sched_next_event(&sched)); |
| 817 | |
| 818 | return sched.state.unassigned; |
| 819 | } |
Yan, Zheng | 4a3dc12 | 2014-03-18 16:56:43 +0800 | [diff] [blame] | 820 | EXPORT_SYMBOL_GPL(perf_assign_events); |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 821 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 822 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 823 | { |
Andrew Hunter | 43b45780 | 2013-05-23 11:07:03 -0700 | [diff] [blame] | 824 | struct event_constraint *c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 825 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 826 | struct perf_event *e; |
Maria Dimakopoulou | e979121 | 2014-11-17 20:06:58 +0100 | [diff] [blame] | 827 | int i, wmin, wmax, unsched = 0; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 828 | struct hw_perf_event *hwc; |
| 829 | |
| 830 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 831 | |
Maria Dimakopoulou | c5362c0 | 2014-11-17 20:06:55 +0100 | [diff] [blame] | 832 | if (x86_pmu.start_scheduling) |
| 833 | x86_pmu.start_scheduling(cpuc); |
| 834 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 835 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 836 | cpuc->event_constraint[i] = NULL; |
Stephane Eranian | 79cba82 | 2014-11-17 20:06:56 +0100 | [diff] [blame] | 837 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 838 | cpuc->event_constraint[i] = c; |
Andrew Hunter | 43b45780 | 2013-05-23 11:07:03 -0700 | [diff] [blame] | 839 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 840 | wmin = min(wmin, c->weight); |
| 841 | wmax = max(wmax, c->weight); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 842 | } |
| 843 | |
| 844 | /* |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 845 | * fastpath, try to reuse previous register |
| 846 | */ |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 847 | for (i = 0; i < n; i++) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 848 | hwc = &cpuc->event_list[i]->hw; |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 849 | c = cpuc->event_constraint[i]; |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 850 | |
| 851 | /* never assigned */ |
| 852 | if (hwc->idx == -1) |
| 853 | break; |
| 854 | |
| 855 | /* constraint still honored */ |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 856 | if (!test_bit(hwc->idx, c->idxmsk)) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 857 | break; |
| 858 | |
| 859 | /* not already used */ |
| 860 | if (test_bit(hwc->idx, used_mask)) |
| 861 | break; |
| 862 | |
Peter Zijlstra | 34538ee | 2010-03-02 21:16:55 +0100 | [diff] [blame] | 863 | __set_bit(hwc->idx, used_mask); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 864 | if (assign) |
| 865 | assign[i] = hwc->idx; |
| 866 | } |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 867 | |
Robert Richter | 1e2ad28 | 2011-11-18 12:35:21 +0100 | [diff] [blame] | 868 | /* slow path */ |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 869 | if (i != n) { |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 870 | int gpmax = x86_pmu.num_counters; |
| 871 | |
| 872 | /* |
| 873 | * Do not allow scheduling of more than half the available |
| 874 | * generic counters. |
| 875 | * |
| 876 | * This helps avoid counter starvation of sibling thread by |
| 877 | * ensuring at most half the counters cannot be in exclusive |
| 878 | * mode. There is no designated counters for the limits. Any |
| 879 | * N/2 counters can be used. This helps with events with |
| 880 | * specific counter constraints. |
| 881 | */ |
| 882 | if (is_ht_workaround_enabled() && !cpuc->is_fake && |
| 883 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) |
| 884 | gpmax /= 2; |
| 885 | |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 886 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
Peter Zijlstra | cc1790c | 2015-05-21 10:57:17 +0200 | [diff] [blame] | 887 | wmax, gpmax, assign); |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 888 | } |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 889 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 890 | /* |
Maria Dimakopoulou | e979121 | 2014-11-17 20:06:58 +0100 | [diff] [blame] | 891 | * In case of success (unsched = 0), mark events as committed, |
| 892 | * so we do not put_constraint() in case new events are added |
| 893 | * and fail to be scheduled |
| 894 | * |
| 895 | * We invoke the lower level commit callback to lock the resource |
| 896 | * |
| 897 | * We do not need to do all of this in case we are called to |
| 898 | * validate an event group (assign == NULL) |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 899 | */ |
Maria Dimakopoulou | e979121 | 2014-11-17 20:06:58 +0100 | [diff] [blame] | 900 | if (!unsched && assign) { |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 901 | for (i = 0; i < n; i++) { |
| 902 | e = cpuc->event_list[i]; |
| 903 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; |
Maria Dimakopoulou | c5362c0 | 2014-11-17 20:06:55 +0100 | [diff] [blame] | 904 | if (x86_pmu.commit_scheduling) |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 905 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 906 | } |
Peter Zijlstra | 8736e54 | 2015-05-21 10:57:43 +0200 | [diff] [blame] | 907 | } else { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 908 | for (i = 0; i < n; i++) { |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 909 | e = cpuc->event_list[i]; |
| 910 | /* |
| 911 | * do not put_constraint() on comitted events, |
| 912 | * because they are good to go |
| 913 | */ |
| 914 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) |
| 915 | continue; |
| 916 | |
Maria Dimakopoulou | e979121 | 2014-11-17 20:06:58 +0100 | [diff] [blame] | 917 | /* |
| 918 | * release events that failed scheduling |
| 919 | */ |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 920 | if (x86_pmu.put_event_constraints) |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 921 | x86_pmu.put_event_constraints(cpuc, e); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 922 | } |
| 923 | } |
Maria Dimakopoulou | c5362c0 | 2014-11-17 20:06:55 +0100 | [diff] [blame] | 924 | |
| 925 | if (x86_pmu.stop_scheduling) |
| 926 | x86_pmu.stop_scheduling(cpuc); |
| 927 | |
Maria Dimakopoulou | e979121 | 2014-11-17 20:06:58 +0100 | [diff] [blame] | 928 | return unsched ? -EINVAL : 0; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | /* |
| 932 | * dogrp: true if must collect siblings events (group) |
| 933 | * returns total number of events and error code |
| 934 | */ |
| 935 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) |
| 936 | { |
| 937 | struct perf_event *event; |
| 938 | int n, max_count; |
| 939 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 940 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 941 | |
| 942 | /* current number of events already accepted */ |
| 943 | n = cpuc->n_events; |
| 944 | |
| 945 | if (is_x86_event(leader)) { |
| 946 | if (n >= max_count) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 947 | return -EINVAL; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 948 | cpuc->event_list[n] = leader; |
| 949 | n++; |
| 950 | } |
| 951 | if (!dogrp) |
| 952 | return n; |
| 953 | |
| 954 | list_for_each_entry(event, &leader->sibling_list, group_entry) { |
| 955 | if (!is_x86_event(event) || |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 956 | event->state <= PERF_EVENT_STATE_OFF) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 957 | continue; |
| 958 | |
| 959 | if (n >= max_count) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 960 | return -EINVAL; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 961 | |
| 962 | cpuc->event_list[n] = event; |
| 963 | n++; |
| 964 | } |
| 965 | return n; |
| 966 | } |
| 967 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 968 | static inline void x86_assign_hw_event(struct perf_event *event, |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 969 | struct cpu_hw_events *cpuc, int i) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 970 | { |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 971 | struct hw_perf_event *hwc = &event->hw; |
| 972 | |
| 973 | hwc->idx = cpuc->assign[i]; |
| 974 | hwc->last_cpu = smp_processor_id(); |
| 975 | hwc->last_tag = ++cpuc->tags[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 976 | |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 977 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 978 | hwc->config_base = 0; |
| 979 | hwc->event_base = 0; |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 980 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 981 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 982 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
| 983 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 984 | } else { |
Robert Richter | 73d6e52 | 2011-02-02 17:40:59 +0100 | [diff] [blame] | 985 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
| 986 | hwc->event_base = x86_pmu_event_addr(hwc->idx); |
Jacob Shin | 0fbdad0 | 2013-02-06 11:26:28 -0600 | [diff] [blame] | 987 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 988 | } |
| 989 | } |
| 990 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 991 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
| 992 | struct cpu_hw_events *cpuc, |
| 993 | int i) |
| 994 | { |
| 995 | return hwc->idx == cpuc->assign[i] && |
| 996 | hwc->last_cpu == smp_processor_id() && |
| 997 | hwc->last_tag == cpuc->tags[i]; |
| 998 | } |
| 999 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1000 | static void x86_pmu_start(struct perf_event *event, int flags); |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1001 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1002 | static void x86_pmu_enable(struct pmu *pmu) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1003 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1004 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1005 | struct perf_event *event; |
| 1006 | struct hw_perf_event *hwc; |
Peter Zijlstra | 11164cd | 2010-03-26 14:08:44 +0100 | [diff] [blame] | 1007 | int i, added = cpuc->n_added; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1008 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1009 | if (!x86_pmu_initialized()) |
Ingo Molnar | 2b9ff0d | 2008-12-14 18:36:30 +0100 | [diff] [blame] | 1010 | return; |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 1011 | |
| 1012 | if (cpuc->enabled) |
| 1013 | return; |
| 1014 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1015 | if (cpuc->n_added) { |
Peter Zijlstra | 19925ce | 2010-03-06 13:20:40 +0100 | [diff] [blame] | 1016 | int n_running = cpuc->n_events - cpuc->n_added; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1017 | /* |
| 1018 | * apply assignment obtained either from |
| 1019 | * hw_perf_group_sched_in() or x86_pmu_enable() |
| 1020 | * |
| 1021 | * step1: save events moving to new counters |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1022 | */ |
Peter Zijlstra | 19925ce | 2010-03-06 13:20:40 +0100 | [diff] [blame] | 1023 | for (i = 0; i < n_running; i++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1024 | event = cpuc->event_list[i]; |
| 1025 | hwc = &event->hw; |
| 1026 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1027 | /* |
| 1028 | * we can avoid reprogramming counter if: |
| 1029 | * - assigned same counter as last time |
| 1030 | * - running on same CPU as last time |
| 1031 | * - no other event has used the counter since |
| 1032 | */ |
| 1033 | if (hwc->idx == -1 || |
| 1034 | match_prev_assignment(hwc, cpuc, i)) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1035 | continue; |
| 1036 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1037 | /* |
| 1038 | * Ensure we don't accidentally enable a stopped |
| 1039 | * counter simply because we rescheduled. |
| 1040 | */ |
| 1041 | if (hwc->state & PERF_HES_STOPPED) |
| 1042 | hwc->state |= PERF_HES_ARCH; |
| 1043 | |
| 1044 | x86_pmu_stop(event, PERF_EF_UPDATE); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1045 | } |
| 1046 | |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1047 | /* |
| 1048 | * step2: reprogram moved events into new counters |
| 1049 | */ |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1050 | for (i = 0; i < cpuc->n_events; i++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1051 | event = cpuc->event_list[i]; |
| 1052 | hwc = &event->hw; |
| 1053 | |
Peter Zijlstra | 45e16a6 | 2010-03-11 13:40:30 +0100 | [diff] [blame] | 1054 | if (!match_prev_assignment(hwc, cpuc, i)) |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1055 | x86_assign_hw_event(event, cpuc, i); |
Peter Zijlstra | 45e16a6 | 2010-03-11 13:40:30 +0100 | [diff] [blame] | 1056 | else if (i < n_running) |
| 1057 | continue; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1058 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1059 | if (hwc->state & PERF_HES_ARCH) |
| 1060 | continue; |
| 1061 | |
| 1062 | x86_pmu_start(event, PERF_EF_RELOAD); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1063 | } |
| 1064 | cpuc->n_added = 0; |
| 1065 | perf_events_lapic_init(); |
| 1066 | } |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 1067 | |
| 1068 | cpuc->enabled = 1; |
| 1069 | barrier(); |
| 1070 | |
Peter Zijlstra | 11164cd | 2010-03-26 14:08:44 +0100 | [diff] [blame] | 1071 | x86_pmu.enable_all(added); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1072 | } |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1073 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1074 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1075 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1076 | /* |
| 1077 | * Set the next IRQ period, based on the hwc->period_left value. |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1078 | * To be called with the event disabled in hw: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1079 | */ |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 1080 | int x86_perf_event_set_period(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1081 | { |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 1082 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 1083 | s64 left = local64_read(&hwc->period_left); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1084 | s64 period = hwc->sample_period; |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 1085 | int ret = 0, idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1086 | |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 1087 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1088 | return 0; |
| 1089 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1090 | /* |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1091 | * If we are way outside a reasonable range then just skip forward: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1092 | */ |
| 1093 | if (unlikely(left <= -period)) { |
| 1094 | left = period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 1095 | local64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1096 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1097 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1098 | } |
| 1099 | |
| 1100 | if (unlikely(left <= 0)) { |
| 1101 | left += period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 1102 | local64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1103 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1104 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1105 | } |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 1106 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 1107 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 1108 | */ |
| 1109 | if (unlikely(left < 2)) |
| 1110 | left = 2; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1111 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1112 | if (left > x86_pmu.max_period) |
| 1113 | left = x86_pmu.max_period; |
| 1114 | |
Andi Kleen | 294fe0f | 2015-02-17 18:18:06 -0800 | [diff] [blame] | 1115 | if (x86_pmu.limit_period) |
| 1116 | left = x86_pmu.limit_period(event, left); |
| 1117 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1118 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1119 | |
Yan, Zheng | 851559e | 2015-05-06 15:33:47 -0400 | [diff] [blame] | 1120 | if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) || |
| 1121 | local64_read(&hwc->prev_count) != (u64)-left) { |
| 1122 | /* |
| 1123 | * The hw event starts counting from this event offset, |
| 1124 | * mark it to be able to extra future deltas: |
| 1125 | */ |
| 1126 | local64_set(&hwc->prev_count, (u64)-left); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1127 | |
Yan, Zheng | 851559e | 2015-05-06 15:33:47 -0400 | [diff] [blame] | 1128 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
| 1129 | } |
Cyrill Gorcunov | 68aa00a | 2010-06-03 01:23:04 +0400 | [diff] [blame] | 1130 | |
| 1131 | /* |
| 1132 | * Due to erratum on certan cpu we need |
| 1133 | * a second write to be sure the register |
| 1134 | * is updated properly |
| 1135 | */ |
| 1136 | if (x86_pmu.perfctr_second_write) { |
Robert Richter | 73d6e52 | 2011-02-02 17:40:59 +0100 | [diff] [blame] | 1137 | wrmsrl(hwc->event_base, |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1138 | (u64)(-left) & x86_pmu.cntval_mask); |
Cyrill Gorcunov | 68aa00a | 2010-06-03 01:23:04 +0400 | [diff] [blame] | 1139 | } |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1140 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1141 | perf_event_update_userpage(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 1142 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1143 | return ret; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1144 | } |
| 1145 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 1146 | void x86_pmu_enable_event(struct perf_event *event) |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1147 | { |
Tejun Heo | 0a3aee0 | 2010-12-18 16:28:55 +0100 | [diff] [blame] | 1148 | if (__this_cpu_read(cpu_hw_events.enabled)) |
Robert Richter | 31fa58a | 2010-04-13 22:23:14 +0200 | [diff] [blame] | 1149 | __x86_pmu_enable_event(&event->hw, |
| 1150 | ARCH_PERFMON_EVENTSEL_ENABLE); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1151 | } |
| 1152 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1153 | /* |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1154 | * Add a single event to the PMU. |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1155 | * |
| 1156 | * The event is added to the group of enabled events |
| 1157 | * but only if it can be scehduled with existing events. |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1158 | */ |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1159 | static int x86_pmu_add(struct perf_event *event, int flags) |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1160 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1161 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1162 | struct hw_perf_event *hwc; |
| 1163 | int assign[X86_PMC_IDX_MAX]; |
| 1164 | int n, n0, ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1165 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1166 | hwc = &event->hw; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1167 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1168 | n0 = cpuc->n_events; |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 1169 | ret = n = collect_events(cpuc, event, false); |
| 1170 | if (ret < 0) |
| 1171 | goto out; |
Ingo Molnar | 53b441a | 2009-05-25 21:41:28 +0200 | [diff] [blame] | 1172 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1173 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
| 1174 | if (!(flags & PERF_EF_START)) |
| 1175 | hwc->state |= PERF_HES_ARCH; |
| 1176 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1177 | /* |
| 1178 | * If group events scheduling transaction was started, |
Lucas De Marchi | 0d2eb44 | 2011-03-17 16:24:16 -0300 | [diff] [blame] | 1179 | * skip the schedulability test here, it will be performed |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1180 | * at commit time (->commit_txn) as a whole. |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1181 | */ |
Sukadev Bhattiprolu | 8f3e568 | 2015-09-03 20:07:53 -0700 | [diff] [blame] | 1182 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 1183 | goto done_collect; |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1184 | |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 1185 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1186 | if (ret) |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 1187 | goto out; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1188 | /* |
| 1189 | * copy new assignment, now we know it is possible |
| 1190 | * will be used by hw_perf_enable() |
| 1191 | */ |
| 1192 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1193 | |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 1194 | done_collect: |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1195 | /* |
| 1196 | * Commit the collect_events() state. See x86_pmu_del() and |
| 1197 | * x86_pmu_*_txn(). |
| 1198 | */ |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1199 | cpuc->n_events = n; |
Peter Zijlstra | 356e1f2 | 2010-03-06 13:49:56 +0100 | [diff] [blame] | 1200 | cpuc->n_added += n - n0; |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1201 | cpuc->n_txn += n - n0; |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1202 | |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 1203 | ret = 0; |
| 1204 | out: |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 1205 | return ret; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1206 | } |
| 1207 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1208 | static void x86_pmu_start(struct perf_event *event, int flags) |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1209 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1210 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 1211 | int idx = event->hw.idx; |
| 1212 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1213 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
| 1214 | return; |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1215 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1216 | if (WARN_ON_ONCE(idx == -1)) |
| 1217 | return; |
| 1218 | |
| 1219 | if (flags & PERF_EF_RELOAD) { |
| 1220 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); |
| 1221 | x86_perf_event_set_period(event); |
| 1222 | } |
| 1223 | |
| 1224 | event->hw.state = 0; |
| 1225 | |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 1226 | cpuc->events[idx] = event; |
| 1227 | __set_bit(idx, cpuc->active_mask); |
Robert Richter | 63e6be6 | 2010-09-15 18:20:34 +0200 | [diff] [blame] | 1228 | __set_bit(idx, cpuc->running); |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 1229 | x86_pmu.enable(event); |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 1230 | perf_event_update_userpage(event); |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1231 | } |
| 1232 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1233 | void perf_event_print_debug(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1234 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1235 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
Andi Kleen | da3e606 | 2015-02-27 09:48:31 -0800 | [diff] [blame] | 1236 | u64 pebs, debugctl; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1237 | struct cpu_hw_events *cpuc; |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1238 | unsigned long flags; |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1239 | int cpu, idx; |
| 1240 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1241 | if (!x86_pmu.num_counters) |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1242 | return; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1243 | |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1244 | local_irq_save(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1245 | |
| 1246 | cpu = smp_processor_id(); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1247 | cpuc = &per_cpu(cpu_hw_events, cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1248 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1249 | if (x86_pmu.version >= 2) { |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1250 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 1251 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1252 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 1253 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1254 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1255 | pr_info("\n"); |
| 1256 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 1257 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 1258 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 1259 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
Andi Kleen | 15fde11 | 2015-02-27 09:48:32 -0800 | [diff] [blame] | 1260 | if (x86_pmu.pebs_constraints) { |
| 1261 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
| 1262 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
| 1263 | } |
Andi Kleen | da3e606 | 2015-02-27 09:48:31 -0800 | [diff] [blame] | 1264 | if (x86_pmu.lbr_nr) { |
| 1265 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
| 1266 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); |
| 1267 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1268 | } |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 1269 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1270 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1271 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 41bf498 | 2011-02-02 17:40:57 +0100 | [diff] [blame] | 1272 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
| 1273 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1274 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1275 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1276 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1277 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1278 | cpu, idx, pmc_ctrl); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1279 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1280 | cpu, idx, pmc_count); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1281 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1282 | cpu, idx, prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1283 | } |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1284 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1285 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 1286 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1287 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1288 | cpu, idx, pmc_count); |
| 1289 | } |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1290 | local_irq_restore(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1291 | } |
| 1292 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 1293 | void x86_pmu_stop(struct perf_event *event, int flags) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1294 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1295 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1296 | struct hw_perf_event *hwc = &event->hw; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1297 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1298 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
| 1299 | x86_pmu.disable(event); |
| 1300 | cpuc->events[hwc->idx] = NULL; |
| 1301 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); |
| 1302 | hwc->state |= PERF_HES_STOPPED; |
| 1303 | } |
Peter Zijlstra | 71e2d28 | 2010-03-08 17:51:33 +0100 | [diff] [blame] | 1304 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1305 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
| 1306 | /* |
| 1307 | * Drain the remaining delta count out of a event |
| 1308 | * that we are disabling: |
| 1309 | */ |
| 1310 | x86_perf_event_update(event); |
| 1311 | hwc->state |= PERF_HES_UPTODATE; |
| 1312 | } |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1313 | } |
| 1314 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1315 | static void x86_pmu_del(struct perf_event *event, int flags) |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1316 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1317 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1318 | int i; |
| 1319 | |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1320 | /* |
Stephane Eranian | 2f7f73a | 2013-06-20 18:42:54 +0200 | [diff] [blame] | 1321 | * event is descheduled |
| 1322 | */ |
| 1323 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; |
| 1324 | |
| 1325 | /* |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1326 | * If we're called during a txn, we don't need to do anything. |
| 1327 | * The events never got scheduled and ->cancel_txn will truncate |
| 1328 | * the event_list. |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1329 | * |
| 1330 | * XXX assumes any ->del() called during a TXN will only be on |
| 1331 | * an event added during that same TXN. |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1332 | */ |
Sukadev Bhattiprolu | 8f3e568 | 2015-09-03 20:07:53 -0700 | [diff] [blame] | 1333 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1334 | return; |
| 1335 | |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1336 | /* |
| 1337 | * Not a TXN, therefore cleanup properly. |
| 1338 | */ |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1339 | x86_pmu_stop(event, PERF_EF_UPDATE); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 1340 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1341 | for (i = 0; i < cpuc->n_events; i++) { |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1342 | if (event == cpuc->event_list[i]) |
Peter Zijlstra | 6c9687a | 2010-01-25 11:57:25 +0100 | [diff] [blame] | 1343 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1344 | } |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1345 | |
| 1346 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
| 1347 | return; |
| 1348 | |
| 1349 | /* If we have a newly added event; make sure to decrease n_added. */ |
| 1350 | if (i >= cpuc->n_events - cpuc->n_added) |
| 1351 | --cpuc->n_added; |
| 1352 | |
| 1353 | if (x86_pmu.put_event_constraints) |
| 1354 | x86_pmu.put_event_constraints(cpuc, event); |
| 1355 | |
| 1356 | /* Delete the array entry. */ |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 1357 | while (++i < cpuc->n_events) { |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1358 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 1359 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
| 1360 | } |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1361 | --cpuc->n_events; |
| 1362 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1363 | perf_event_update_userpage(event); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1364 | } |
| 1365 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 1366 | int x86_pmu_handle_irq(struct pt_regs *regs) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1367 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1368 | struct perf_sample_data data; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1369 | struct cpu_hw_events *cpuc; |
| 1370 | struct perf_event *event; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1371 | int idx, handled = 0; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1372 | u64 val; |
| 1373 | |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1374 | cpuc = this_cpu_ptr(&cpu_hw_events); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1375 | |
Don Zickus | 2bce5da | 2011-04-27 06:32:33 -0400 | [diff] [blame] | 1376 | /* |
| 1377 | * Some chipsets need to unmask the LVTPC in a particular spot |
| 1378 | * inside the nmi handler. As a result, the unmasking was pushed |
| 1379 | * into all the nmi handlers. |
| 1380 | * |
| 1381 | * This generic handler doesn't seem to have any issues where the |
| 1382 | * unmasking occurs so it was left at the top. |
| 1383 | */ |
| 1384 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 1385 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1386 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 63e6be6 | 2010-09-15 18:20:34 +0200 | [diff] [blame] | 1387 | if (!test_bit(idx, cpuc->active_mask)) { |
| 1388 | /* |
| 1389 | * Though we deactivated the counter some cpus |
| 1390 | * might still deliver spurious interrupts still |
| 1391 | * in flight. Catch them: |
| 1392 | */ |
| 1393 | if (__test_and_clear_bit(idx, cpuc->running)) |
| 1394 | handled++; |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1395 | continue; |
Robert Richter | 63e6be6 | 2010-09-15 18:20:34 +0200 | [diff] [blame] | 1396 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1397 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1398 | event = cpuc->events[idx]; |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1399 | |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 1400 | val = x86_perf_event_update(event); |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1401 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 1402 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1403 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1404 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1405 | * event overflow |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1406 | */ |
Robert Richter | 4177c42 | 2010-09-02 15:07:48 -0400 | [diff] [blame] | 1407 | handled++; |
Robert Richter | fd0d000 | 2012-04-02 20:19:08 +0200 | [diff] [blame] | 1408 | perf_sample_data_init(&data, 0, event->hw.last_period); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1409 | |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 1410 | if (!x86_perf_event_set_period(event)) |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1411 | continue; |
| 1412 | |
Peter Zijlstra | a8b0ca1 | 2011-06-27 14:41:57 +0200 | [diff] [blame] | 1413 | if (perf_event_overflow(event, &data, regs)) |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1414 | x86_pmu_stop(event, 0); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1415 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1416 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1417 | if (handled) |
| 1418 | inc_irq_stat(apic_perf_irqs); |
| 1419 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1420 | return handled; |
| 1421 | } |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 1422 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1423 | void perf_events_lapic_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1424 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1425 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1426 | return; |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1427 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1428 | /* |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1429 | * Always use NMI for PMU |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1430 | */ |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1431 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1432 | } |
| 1433 | |
Masami Hiramatsu | 9326638 | 2014-04-17 17:18:14 +0900 | [diff] [blame] | 1434 | static int |
Don Zickus | 9c48f1c | 2011-09-30 15:06:21 -0400 | [diff] [blame] | 1435 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1436 | { |
Dave Hansen | 14c63f1 | 2013-06-21 08:51:36 -0700 | [diff] [blame] | 1437 | u64 start_clock; |
| 1438 | u64 finish_clock; |
Peter Zijlstra | e8a923c | 2013-10-17 15:32:10 +0200 | [diff] [blame] | 1439 | int ret; |
Dave Hansen | 14c63f1 | 2013-06-21 08:51:36 -0700 | [diff] [blame] | 1440 | |
Alexander Shishkin | 1b7b938 | 2015-06-09 13:03:26 +0300 | [diff] [blame] | 1441 | /* |
| 1442 | * All PMUs/events that share this PMI handler should make sure to |
| 1443 | * increment active_events for their events. |
| 1444 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1445 | if (!atomic_read(&active_events)) |
Don Zickus | 9c48f1c | 2011-09-30 15:06:21 -0400 | [diff] [blame] | 1446 | return NMI_DONE; |
Peter Zijlstra | 63a809a | 2009-05-01 12:23:17 +0200 | [diff] [blame] | 1447 | |
Peter Zijlstra | e8a923c | 2013-10-17 15:32:10 +0200 | [diff] [blame] | 1448 | start_clock = sched_clock(); |
Dave Hansen | 14c63f1 | 2013-06-21 08:51:36 -0700 | [diff] [blame] | 1449 | ret = x86_pmu.handle_irq(regs); |
Peter Zijlstra | e8a923c | 2013-10-17 15:32:10 +0200 | [diff] [blame] | 1450 | finish_clock = sched_clock(); |
Dave Hansen | 14c63f1 | 2013-06-21 08:51:36 -0700 | [diff] [blame] | 1451 | |
| 1452 | perf_sample_event_took(finish_clock - start_clock); |
| 1453 | |
| 1454 | return ret; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1455 | } |
Masami Hiramatsu | 9326638 | 2014-04-17 17:18:14 +0900 | [diff] [blame] | 1456 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1457 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 1458 | struct event_constraint emptyconstraint; |
| 1459 | struct event_constraint unconstrained; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1460 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1461 | static int |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1462 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
| 1463 | { |
| 1464 | unsigned int cpu = (long)hcpu; |
Peter Zijlstra | 7fdba1c | 2011-07-22 13:41:54 +0200 | [diff] [blame] | 1465 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
Stephane Eranian | 9041346 | 2014-11-17 20:06:54 +0100 | [diff] [blame] | 1466 | int i, ret = NOTIFY_OK; |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1467 | |
| 1468 | switch (action & ~CPU_TASKS_FROZEN) { |
| 1469 | case CPU_UP_PREPARE: |
Stephane Eranian | 9041346 | 2014-11-17 20:06:54 +0100 | [diff] [blame] | 1470 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
| 1471 | cpuc->kfree_on_online[i] = NULL; |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1472 | if (x86_pmu.cpu_prepare) |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1473 | ret = x86_pmu.cpu_prepare(cpu); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1474 | break; |
| 1475 | |
| 1476 | case CPU_STARTING: |
| 1477 | if (x86_pmu.cpu_starting) |
| 1478 | x86_pmu.cpu_starting(cpu); |
| 1479 | break; |
| 1480 | |
Peter Zijlstra | 7fdba1c | 2011-07-22 13:41:54 +0200 | [diff] [blame] | 1481 | case CPU_ONLINE: |
Stephane Eranian | 9041346 | 2014-11-17 20:06:54 +0100 | [diff] [blame] | 1482 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
| 1483 | kfree(cpuc->kfree_on_online[i]); |
| 1484 | cpuc->kfree_on_online[i] = NULL; |
| 1485 | } |
Peter Zijlstra | 7fdba1c | 2011-07-22 13:41:54 +0200 | [diff] [blame] | 1486 | break; |
| 1487 | |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1488 | case CPU_DYING: |
| 1489 | if (x86_pmu.cpu_dying) |
| 1490 | x86_pmu.cpu_dying(cpu); |
| 1491 | break; |
| 1492 | |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1493 | case CPU_UP_CANCELED: |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1494 | case CPU_DEAD: |
| 1495 | if (x86_pmu.cpu_dead) |
| 1496 | x86_pmu.cpu_dead(cpu); |
| 1497 | break; |
| 1498 | |
| 1499 | default: |
| 1500 | break; |
| 1501 | } |
| 1502 | |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1503 | return ret; |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1504 | } |
| 1505 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1506 | static void __init pmu_check_apic(void) |
| 1507 | { |
| 1508 | if (cpu_has_apic) |
| 1509 | return; |
| 1510 | |
| 1511 | x86_pmu.apic = 0; |
| 1512 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
| 1513 | pr_info("no hardware sampling interrupt available.\n"); |
Vince Weaver | c184c98 | 2014-05-16 17:18:07 -0400 | [diff] [blame] | 1514 | |
| 1515 | /* |
| 1516 | * If we have a PMU initialized but no APIC |
| 1517 | * interrupts, we cannot sample hardware |
| 1518 | * events (user-space has to fall back and |
| 1519 | * sample via a hrtimer based software event): |
| 1520 | */ |
| 1521 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; |
| 1522 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1523 | } |
| 1524 | |
Jiri Olsa | 641cc93 | 2012-03-15 20:09:14 +0100 | [diff] [blame] | 1525 | static struct attribute_group x86_pmu_format_group = { |
| 1526 | .name = "format", |
| 1527 | .attrs = NULL, |
| 1528 | }; |
| 1529 | |
Jiri Olsa | 8300daa | 2012-10-10 14:53:12 +0200 | [diff] [blame] | 1530 | /* |
| 1531 | * Remove all undefined events (x86_pmu.event_map(id) == 0) |
| 1532 | * out of events_attr attributes. |
| 1533 | */ |
| 1534 | static void __init filter_events(struct attribute **attrs) |
| 1535 | { |
Stephane Eranian | 3a54aaa | 2013-01-24 16:10:26 +0100 | [diff] [blame] | 1536 | struct device_attribute *d; |
| 1537 | struct perf_pmu_events_attr *pmu_attr; |
Stephane Eranian | 61b87ca | 2015-12-07 20:33:25 +0100 | [diff] [blame] | 1538 | int offset = 0; |
Jiri Olsa | 8300daa | 2012-10-10 14:53:12 +0200 | [diff] [blame] | 1539 | int i, j; |
| 1540 | |
| 1541 | for (i = 0; attrs[i]; i++) { |
Stephane Eranian | 3a54aaa | 2013-01-24 16:10:26 +0100 | [diff] [blame] | 1542 | d = (struct device_attribute *)attrs[i]; |
| 1543 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); |
| 1544 | /* str trumps id */ |
| 1545 | if (pmu_attr->event_str) |
| 1546 | continue; |
Stephane Eranian | 61b87ca | 2015-12-07 20:33:25 +0100 | [diff] [blame] | 1547 | if (x86_pmu.event_map(i + offset)) |
Jiri Olsa | 8300daa | 2012-10-10 14:53:12 +0200 | [diff] [blame] | 1548 | continue; |
| 1549 | |
| 1550 | for (j = i; attrs[j]; j++) |
| 1551 | attrs[j] = attrs[j + 1]; |
| 1552 | |
| 1553 | /* Check the shifted attr. */ |
| 1554 | i--; |
Stephane Eranian | 61b87ca | 2015-12-07 20:33:25 +0100 | [diff] [blame] | 1555 | |
| 1556 | /* |
| 1557 | * event_map() is index based, the attrs array is organized |
| 1558 | * by increasing event index. If we shift the events, then |
| 1559 | * we need to compensate for the event_map(), otherwise |
| 1560 | * we are looking up the wrong event in the map |
| 1561 | */ |
| 1562 | offset++; |
Jiri Olsa | 8300daa | 2012-10-10 14:53:12 +0200 | [diff] [blame] | 1563 | } |
| 1564 | } |
| 1565 | |
Andi Kleen | 1a6461b | 2013-01-24 16:10:25 +0100 | [diff] [blame] | 1566 | /* Merge two pointer arrays */ |
Andi Kleen | 47732d8 | 2015-06-29 14:22:13 -0700 | [diff] [blame] | 1567 | __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) |
Andi Kleen | 1a6461b | 2013-01-24 16:10:25 +0100 | [diff] [blame] | 1568 | { |
| 1569 | struct attribute **new; |
| 1570 | int j, i; |
| 1571 | |
| 1572 | for (j = 0; a[j]; j++) |
| 1573 | ; |
| 1574 | for (i = 0; b[i]; i++) |
| 1575 | j++; |
| 1576 | j++; |
| 1577 | |
| 1578 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); |
| 1579 | if (!new) |
| 1580 | return NULL; |
| 1581 | |
| 1582 | j = 0; |
| 1583 | for (i = 0; a[i]; i++) |
| 1584 | new[j++] = a[i]; |
| 1585 | for (i = 0; b[i]; i++) |
| 1586 | new[j++] = b[i]; |
| 1587 | new[j] = NULL; |
| 1588 | |
| 1589 | return new; |
| 1590 | } |
| 1591 | |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1592 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1593 | char *page) |
| 1594 | { |
| 1595 | struct perf_pmu_events_attr *pmu_attr = \ |
| 1596 | container_of(attr, struct perf_pmu_events_attr, attr); |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1597 | u64 config = x86_pmu.event_map(pmu_attr->id); |
Stephane Eranian | 3a54aaa | 2013-01-24 16:10:26 +0100 | [diff] [blame] | 1598 | |
| 1599 | /* string trumps id */ |
| 1600 | if (pmu_attr->event_str) |
| 1601 | return sprintf(page, "%s", pmu_attr->event_str); |
| 1602 | |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1603 | return x86_pmu.events_sysfs_show(page, config); |
| 1604 | } |
| 1605 | |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1606 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); |
| 1607 | EVENT_ATTR(instructions, INSTRUCTIONS ); |
| 1608 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); |
| 1609 | EVENT_ATTR(cache-misses, CACHE_MISSES ); |
| 1610 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); |
| 1611 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); |
| 1612 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); |
| 1613 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); |
| 1614 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); |
| 1615 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); |
| 1616 | |
| 1617 | static struct attribute *empty_attrs; |
| 1618 | |
Peter Huewe | 95d18aa | 2012-10-29 21:48:17 +0100 | [diff] [blame] | 1619 | static struct attribute *events_attr[] = { |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1620 | EVENT_PTR(CPU_CYCLES), |
| 1621 | EVENT_PTR(INSTRUCTIONS), |
| 1622 | EVENT_PTR(CACHE_REFERENCES), |
| 1623 | EVENT_PTR(CACHE_MISSES), |
| 1624 | EVENT_PTR(BRANCH_INSTRUCTIONS), |
| 1625 | EVENT_PTR(BRANCH_MISSES), |
| 1626 | EVENT_PTR(BUS_CYCLES), |
| 1627 | EVENT_PTR(STALLED_CYCLES_FRONTEND), |
| 1628 | EVENT_PTR(STALLED_CYCLES_BACKEND), |
| 1629 | EVENT_PTR(REF_CPU_CYCLES), |
| 1630 | NULL, |
| 1631 | }; |
| 1632 | |
| 1633 | static struct attribute_group x86_pmu_events_group = { |
| 1634 | .name = "events", |
| 1635 | .attrs = events_attr, |
| 1636 | }; |
| 1637 | |
Jiri Olsa | 0bf79d4 | 2012-10-10 14:53:14 +0200 | [diff] [blame] | 1638 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
Jiri Olsa | 43c032f | 2012-10-10 14:53:13 +0200 | [diff] [blame] | 1639 | { |
Jiri Olsa | 43c032f | 2012-10-10 14:53:13 +0200 | [diff] [blame] | 1640 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
| 1641 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; |
| 1642 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); |
| 1643 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); |
| 1644 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); |
| 1645 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); |
| 1646 | ssize_t ret; |
| 1647 | |
| 1648 | /* |
| 1649 | * We have whole page size to spend and just little data |
| 1650 | * to write, so we can safely use sprintf. |
| 1651 | */ |
| 1652 | ret = sprintf(page, "event=0x%02llx", event); |
| 1653 | |
| 1654 | if (umask) |
| 1655 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); |
| 1656 | |
| 1657 | if (edge) |
| 1658 | ret += sprintf(page + ret, ",edge"); |
| 1659 | |
| 1660 | if (pc) |
| 1661 | ret += sprintf(page + ret, ",pc"); |
| 1662 | |
| 1663 | if (any) |
| 1664 | ret += sprintf(page + ret, ",any"); |
| 1665 | |
| 1666 | if (inv) |
| 1667 | ret += sprintf(page + ret, ",inv"); |
| 1668 | |
| 1669 | if (cmask) |
| 1670 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); |
| 1671 | |
| 1672 | ret += sprintf(page + ret, "\n"); |
| 1673 | |
| 1674 | return ret; |
| 1675 | } |
| 1676 | |
Yinghai Lu | dda9911 | 2011-01-21 15:30:01 -0800 | [diff] [blame] | 1677 | static int __init init_hw_perf_events(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1678 | { |
Peter Zijlstra | c1d6f42 | 2011-12-06 14:07:15 +0100 | [diff] [blame] | 1679 | struct x86_pmu_quirk *quirk; |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1680 | int err; |
| 1681 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1682 | pr_info("Performance Events: "); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1683 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1684 | switch (boot_cpu_data.x86_vendor) { |
| 1685 | case X86_VENDOR_INTEL: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1686 | err = intel_pmu_init(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1687 | break; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1688 | case X86_VENDOR_AMD: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1689 | err = amd_pmu_init(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1690 | break; |
Robert Richter | 4138960 | 2009-04-29 12:47:00 +0200 | [diff] [blame] | 1691 | default: |
Ingo Molnar | 8a3da6c7 | 2013-09-28 15:48:48 +0200 | [diff] [blame] | 1692 | err = -ENOTSUPP; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1693 | } |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1694 | if (err != 0) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1695 | pr_cont("no PMU driver, software events only.\n"); |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 1696 | return 0; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1697 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1698 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1699 | pmu_check_apic(); |
| 1700 | |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 1701 | /* sanity check that the hardware exists or is emulated */ |
Peter Zijlstra | 4407204 | 2010-12-08 15:56:23 +0100 | [diff] [blame] | 1702 | if (!check_hw_exists()) |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 1703 | return 0; |
Don Zickus | 33c6d6a | 2010-11-22 16:55:23 -0500 | [diff] [blame] | 1704 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1705 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1706 | |
Peter Zijlstra | e97df76 | 2014-02-05 20:48:51 +0100 | [diff] [blame] | 1707 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
| 1708 | |
Peter Zijlstra | c1d6f42 | 2011-12-06 14:07:15 +0100 | [diff] [blame] | 1709 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
| 1710 | quirk->func(); |
Peter Zijlstra | 3c44780 | 2010-03-04 21:49:01 +0100 | [diff] [blame] | 1711 | |
Robert Richter | a1eac7a | 2012-06-20 20:46:34 +0200 | [diff] [blame] | 1712 | if (!x86_pmu.intel_ctrl) |
| 1713 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1714 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1715 | perf_events_lapic_init(); |
Don Zickus | 9c48f1c | 2011-09-30 15:06:21 -0400 | [diff] [blame] | 1716 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1717 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1718 | unconstrained = (struct event_constraint) |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1719 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
Stephane Eranian | 9fac2cf | 2013-01-24 16:10:27 +0100 | [diff] [blame] | 1720 | 0, x86_pmu.num_counters, 0, 0); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1721 | |
Jiri Olsa | 641cc93 | 2012-03-15 20:09:14 +0100 | [diff] [blame] | 1722 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 1723 | |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1724 | if (x86_pmu.event_attrs) |
| 1725 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; |
| 1726 | |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1727 | if (!x86_pmu.events_sysfs_show) |
| 1728 | x86_pmu_events_group.attrs = &empty_attrs; |
Jiri Olsa | 8300daa | 2012-10-10 14:53:12 +0200 | [diff] [blame] | 1729 | else |
| 1730 | filter_events(x86_pmu_events_group.attrs); |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 1731 | |
Andi Kleen | 1a6461b | 2013-01-24 16:10:25 +0100 | [diff] [blame] | 1732 | if (x86_pmu.cpu_events) { |
| 1733 | struct attribute **tmp; |
| 1734 | |
| 1735 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); |
| 1736 | if (!WARN_ON(!tmp)) |
| 1737 | x86_pmu_events_group.attrs = tmp; |
| 1738 | } |
| 1739 | |
Ingo Molnar | 57c0c15 | 2009-09-21 12:20:38 +0200 | [diff] [blame] | 1740 | pr_info("... version: %d\n", x86_pmu.version); |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1741 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
| 1742 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); |
| 1743 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); |
Ingo Molnar | 57c0c15 | 2009-09-21 12:20:38 +0200 | [diff] [blame] | 1744 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1745 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
Robert Richter | d6dc0b4 | 2010-03-17 12:49:13 +0100 | [diff] [blame] | 1746 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1747 | |
Peter Zijlstra | 2e80a82 | 2010-11-17 23:17:36 +0100 | [diff] [blame] | 1748 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1749 | perf_cpu_notifier(x86_pmu_notifier); |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 1750 | |
| 1751 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1752 | } |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 1753 | early_initcall(init_hw_perf_events); |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1754 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1755 | static inline void x86_pmu_read(struct perf_event *event) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1756 | { |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 1757 | x86_perf_event_update(event); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1758 | } |
| 1759 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1760 | /* |
| 1761 | * Start group events scheduling transaction |
| 1762 | * Set the flag to make pmu::enable() not perform the |
| 1763 | * schedulability test, it will be performed at commit time |
Sukadev Bhattiprolu | fbbe070 | 2015-09-03 20:07:45 -0700 | [diff] [blame] | 1764 | * |
| 1765 | * We only support PERF_PMU_TXN_ADD transactions. Save the |
| 1766 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD |
| 1767 | * transactions. |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1768 | */ |
Sukadev Bhattiprolu | fbbe070 | 2015-09-03 20:07:45 -0700 | [diff] [blame] | 1769 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1770 | { |
Sukadev Bhattiprolu | fbbe070 | 2015-09-03 20:07:45 -0700 | [diff] [blame] | 1771 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| 1772 | |
| 1773 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ |
| 1774 | |
| 1775 | cpuc->txn_flags = txn_flags; |
| 1776 | if (txn_flags & ~PERF_PMU_TXN_ADD) |
| 1777 | return; |
| 1778 | |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 1779 | perf_pmu_disable(pmu); |
Tejun Heo | 0a3aee0 | 2010-12-18 16:28:55 +0100 | [diff] [blame] | 1780 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1781 | } |
| 1782 | |
| 1783 | /* |
| 1784 | * Stop group events scheduling transaction |
| 1785 | * Clear the flag and pmu::enable() will perform the |
| 1786 | * schedulability test. |
| 1787 | */ |
Peter Zijlstra | 51b0fe3 | 2010-06-11 13:35:57 +0200 | [diff] [blame] | 1788 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1789 | { |
Sukadev Bhattiprolu | fbbe070 | 2015-09-03 20:07:45 -0700 | [diff] [blame] | 1790 | unsigned int txn_flags; |
| 1791 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| 1792 | |
| 1793 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
| 1794 | |
| 1795 | txn_flags = cpuc->txn_flags; |
| 1796 | cpuc->txn_flags = 0; |
| 1797 | if (txn_flags & ~PERF_PMU_TXN_ADD) |
| 1798 | return; |
| 1799 | |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1800 | /* |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1801 | * Truncate collected array by the number of events added in this |
| 1802 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame] | 1803 | */ |
Tejun Heo | 0a3aee0 | 2010-12-18 16:28:55 +0100 | [diff] [blame] | 1804 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
| 1805 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 1806 | perf_pmu_enable(pmu); |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1807 | } |
| 1808 | |
| 1809 | /* |
| 1810 | * Commit group events scheduling transaction |
| 1811 | * Perform the group schedulability test as a whole |
| 1812 | * Return 0 if success |
Peter Zijlstra | c347a2f | 2014-02-24 12:26:21 +0100 | [diff] [blame] | 1813 | * |
| 1814 | * Does not cancel the transaction on failure; expects the caller to do this. |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1815 | */ |
Peter Zijlstra | 51b0fe3 | 2010-06-11 13:35:57 +0200 | [diff] [blame] | 1816 | static int x86_pmu_commit_txn(struct pmu *pmu) |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1817 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1818 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1819 | int assign[X86_PMC_IDX_MAX]; |
| 1820 | int n, ret; |
| 1821 | |
Sukadev Bhattiprolu | fbbe070 | 2015-09-03 20:07:45 -0700 | [diff] [blame] | 1822 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
| 1823 | |
| 1824 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { |
| 1825 | cpuc->txn_flags = 0; |
| 1826 | return 0; |
| 1827 | } |
| 1828 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1829 | n = cpuc->n_events; |
| 1830 | |
| 1831 | if (!x86_pmu_initialized()) |
| 1832 | return -EAGAIN; |
| 1833 | |
| 1834 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
| 1835 | if (ret) |
| 1836 | return ret; |
| 1837 | |
| 1838 | /* |
| 1839 | * copy new assignment, now we know it is possible |
| 1840 | * will be used by hw_perf_enable() |
| 1841 | */ |
| 1842 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
| 1843 | |
Sukadev Bhattiprolu | fbbe070 | 2015-09-03 20:07:45 -0700 | [diff] [blame] | 1844 | cpuc->txn_flags = 0; |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 1845 | perf_pmu_enable(pmu); |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1846 | return 0; |
| 1847 | } |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1848 | /* |
| 1849 | * a fake_cpuc is used to validate event groups. Due to |
| 1850 | * the extra reg logic, we need to also allocate a fake |
| 1851 | * per_core and per_cpu structure. Otherwise, group events |
| 1852 | * using extra reg may conflict without the kernel being |
| 1853 | * able to catch this when the last event gets added to |
| 1854 | * the group. |
| 1855 | */ |
| 1856 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) |
| 1857 | { |
| 1858 | kfree(cpuc->shared_regs); |
| 1859 | kfree(cpuc); |
| 1860 | } |
| 1861 | |
| 1862 | static struct cpu_hw_events *allocate_fake_cpuc(void) |
| 1863 | { |
| 1864 | struct cpu_hw_events *cpuc; |
| 1865 | int cpu = raw_smp_processor_id(); |
| 1866 | |
| 1867 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); |
| 1868 | if (!cpuc) |
| 1869 | return ERR_PTR(-ENOMEM); |
| 1870 | |
| 1871 | /* only needed, if we have extra_regs */ |
| 1872 | if (x86_pmu.extra_regs) { |
| 1873 | cpuc->shared_regs = allocate_shared_regs(cpu); |
| 1874 | if (!cpuc->shared_regs) |
| 1875 | goto error; |
| 1876 | } |
Peter Zijlstra | b430f7c | 2012-06-05 15:30:31 +0200 | [diff] [blame] | 1877 | cpuc->is_fake = 1; |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1878 | return cpuc; |
| 1879 | error: |
| 1880 | free_fake_cpuc(cpuc); |
| 1881 | return ERR_PTR(-ENOMEM); |
| 1882 | } |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1883 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1884 | /* |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1885 | * validate that we can schedule this event |
| 1886 | */ |
| 1887 | static int validate_event(struct perf_event *event) |
| 1888 | { |
| 1889 | struct cpu_hw_events *fake_cpuc; |
| 1890 | struct event_constraint *c; |
| 1891 | int ret = 0; |
| 1892 | |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1893 | fake_cpuc = allocate_fake_cpuc(); |
| 1894 | if (IS_ERR(fake_cpuc)) |
| 1895 | return PTR_ERR(fake_cpuc); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1896 | |
Stephane Eranian | 79cba82 | 2014-11-17 20:06:56 +0100 | [diff] [blame] | 1897 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1898 | |
| 1899 | if (!c || !c->weight) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 1900 | ret = -EINVAL; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1901 | |
| 1902 | if (x86_pmu.put_event_constraints) |
| 1903 | x86_pmu.put_event_constraints(fake_cpuc, event); |
| 1904 | |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1905 | free_fake_cpuc(fake_cpuc); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1906 | |
| 1907 | return ret; |
| 1908 | } |
| 1909 | |
| 1910 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1911 | * validate a single event group |
| 1912 | * |
| 1913 | * validation include: |
Ingo Molnar | 184f412 | 2010-01-27 08:39:39 +0100 | [diff] [blame] | 1914 | * - check events are compatible which each other |
| 1915 | * - events do not compete for the same counter |
| 1916 | * - number of events <= number of counters |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1917 | * |
| 1918 | * validation ensures the group can be loaded onto the |
| 1919 | * PMU if it was the only group available. |
| 1920 | */ |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1921 | static int validate_group(struct perf_event *event) |
| 1922 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1923 | struct perf_event *leader = event->group_leader; |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1924 | struct cpu_hw_events *fake_cpuc; |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 1925 | int ret = -EINVAL, n; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1926 | |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1927 | fake_cpuc = allocate_fake_cpuc(); |
| 1928 | if (IS_ERR(fake_cpuc)) |
| 1929 | return PTR_ERR(fake_cpuc); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1930 | /* |
| 1931 | * the event is not yet connected with its |
| 1932 | * siblings therefore we must first collect |
| 1933 | * existing siblings, then add the new event |
| 1934 | * before we can simulate the scheduling |
| 1935 | */ |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1936 | n = collect_events(fake_cpuc, leader, true); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1937 | if (n < 0) |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1938 | goto out; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1939 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1940 | fake_cpuc->n_events = n; |
| 1941 | n = collect_events(fake_cpuc, event, false); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1942 | if (n < 0) |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1943 | goto out; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1944 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1945 | fake_cpuc->n_events = n; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1946 | |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 1947 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1948 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1949 | out: |
Stephane Eranian | cd8a38d | 2011-06-06 16:57:08 +0200 | [diff] [blame] | 1950 | free_fake_cpuc(fake_cpuc); |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1951 | return ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1952 | } |
| 1953 | |
Yinghai Lu | dda9911 | 2011-01-21 15:30:01 -0800 | [diff] [blame] | 1954 | static int x86_pmu_event_init(struct perf_event *event) |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1955 | { |
Peter Zijlstra | 51b0fe3 | 2010-06-11 13:35:57 +0200 | [diff] [blame] | 1956 | struct pmu *tmp; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1957 | int err; |
| 1958 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 1959 | switch (event->attr.type) { |
| 1960 | case PERF_TYPE_RAW: |
| 1961 | case PERF_TYPE_HARDWARE: |
| 1962 | case PERF_TYPE_HW_CACHE: |
| 1963 | break; |
| 1964 | |
| 1965 | default: |
| 1966 | return -ENOENT; |
| 1967 | } |
| 1968 | |
| 1969 | err = __x86_pmu_event_init(event); |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1970 | if (!err) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1971 | /* |
| 1972 | * we temporarily connect event to its pmu |
| 1973 | * such that validate_group() can classify |
| 1974 | * it as an x86 event using is_x86_event() |
| 1975 | */ |
| 1976 | tmp = event->pmu; |
| 1977 | event->pmu = &pmu; |
| 1978 | |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1979 | if (event->group_leader != event) |
| 1980 | err = validate_group(event); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1981 | else |
| 1982 | err = validate_event(event); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1983 | |
| 1984 | event->pmu = tmp; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1985 | } |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1986 | if (err) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1987 | if (event->destroy) |
| 1988 | event->destroy(event); |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1989 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1990 | |
Andy Lutomirski | 7911d3f | 2014-10-24 15:58:12 -0700 | [diff] [blame] | 1991 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
| 1992 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; |
| 1993 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 1994 | return err; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1995 | } |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1996 | |
Andy Lutomirski | 7911d3f | 2014-10-24 15:58:12 -0700 | [diff] [blame] | 1997 | static void refresh_pce(void *ignored) |
| 1998 | { |
| 1999 | if (current->mm) |
| 2000 | load_mm_cr4(current->mm); |
| 2001 | } |
| 2002 | |
| 2003 | static void x86_pmu_event_mapped(struct perf_event *event) |
| 2004 | { |
| 2005 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
| 2006 | return; |
| 2007 | |
| 2008 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) |
| 2009 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); |
| 2010 | } |
| 2011 | |
| 2012 | static void x86_pmu_event_unmapped(struct perf_event *event) |
| 2013 | { |
| 2014 | if (!current->mm) |
| 2015 | return; |
| 2016 | |
| 2017 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
| 2018 | return; |
| 2019 | |
| 2020 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) |
| 2021 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); |
| 2022 | } |
| 2023 | |
Peter Zijlstra | fe4a330 | 2011-11-20 20:44:06 +0100 | [diff] [blame] | 2024 | static int x86_pmu_event_idx(struct perf_event *event) |
| 2025 | { |
| 2026 | int idx = event->hw.idx; |
| 2027 | |
Andy Lutomirski | 7911d3f | 2014-10-24 15:58:12 -0700 | [diff] [blame] | 2028 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
Peter Zijlstra | c720620 | 2012-03-22 17:26:36 +0100 | [diff] [blame] | 2029 | return 0; |
| 2030 | |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 2031 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
| 2032 | idx -= INTEL_PMC_IDX_FIXED; |
Peter Zijlstra | fe4a330 | 2011-11-20 20:44:06 +0100 | [diff] [blame] | 2033 | idx |= 1 << 30; |
| 2034 | } |
| 2035 | |
| 2036 | return idx + 1; |
| 2037 | } |
| 2038 | |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 2039 | static ssize_t get_attr_rdpmc(struct device *cdev, |
| 2040 | struct device_attribute *attr, |
| 2041 | char *buf) |
| 2042 | { |
| 2043 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); |
| 2044 | } |
| 2045 | |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 2046 | static ssize_t set_attr_rdpmc(struct device *cdev, |
| 2047 | struct device_attribute *attr, |
| 2048 | const char *buf, size_t count) |
| 2049 | { |
Shuah Khan | e2b297f | 2012-06-10 21:13:41 -0600 | [diff] [blame] | 2050 | unsigned long val; |
| 2051 | ssize_t ret; |
| 2052 | |
| 2053 | ret = kstrtoul(buf, 0, &val); |
| 2054 | if (ret) |
| 2055 | return ret; |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 2056 | |
Andy Lutomirski | a667342 | 2014-10-24 15:58:13 -0700 | [diff] [blame] | 2057 | if (val > 2) |
| 2058 | return -EINVAL; |
| 2059 | |
Peter Zijlstra | e97df76 | 2014-02-05 20:48:51 +0100 | [diff] [blame] | 2060 | if (x86_pmu.attr_rdpmc_broken) |
| 2061 | return -ENOTSUPP; |
| 2062 | |
Andy Lutomirski | a667342 | 2014-10-24 15:58:13 -0700 | [diff] [blame] | 2063 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
| 2064 | /* |
| 2065 | * Changing into or out of always available, aka |
| 2066 | * perf-event-bypassing mode. This path is extremely slow, |
| 2067 | * but only root can trigger it, so it's okay. |
| 2068 | */ |
| 2069 | if (val == 2) |
| 2070 | static_key_slow_inc(&rdpmc_always_available); |
| 2071 | else |
| 2072 | static_key_slow_dec(&rdpmc_always_available); |
| 2073 | on_each_cpu(refresh_pce, NULL, 1); |
| 2074 | } |
| 2075 | |
| 2076 | x86_pmu.attr_rdpmc = val; |
| 2077 | |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 2078 | return count; |
| 2079 | } |
| 2080 | |
| 2081 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); |
| 2082 | |
| 2083 | static struct attribute *x86_pmu_attrs[] = { |
| 2084 | &dev_attr_rdpmc.attr, |
| 2085 | NULL, |
| 2086 | }; |
| 2087 | |
| 2088 | static struct attribute_group x86_pmu_attr_group = { |
| 2089 | .attrs = x86_pmu_attrs, |
| 2090 | }; |
| 2091 | |
| 2092 | static const struct attribute_group *x86_pmu_attr_groups[] = { |
| 2093 | &x86_pmu_attr_group, |
Jiri Olsa | 641cc93 | 2012-03-15 20:09:14 +0100 | [diff] [blame] | 2094 | &x86_pmu_format_group, |
Jiri Olsa | a474739 | 2012-10-10 14:53:11 +0200 | [diff] [blame] | 2095 | &x86_pmu_events_group, |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 2096 | NULL, |
| 2097 | }; |
| 2098 | |
Yan, Zheng | ba53250 | 2014-11-04 21:55:58 -0500 | [diff] [blame] | 2099 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
Stephane Eranian | d010b33 | 2012-02-09 23:21:00 +0100 | [diff] [blame] | 2100 | { |
Yan, Zheng | ba53250 | 2014-11-04 21:55:58 -0500 | [diff] [blame] | 2101 | if (x86_pmu.sched_task) |
| 2102 | x86_pmu.sched_task(ctx, sched_in); |
Stephane Eranian | d010b33 | 2012-02-09 23:21:00 +0100 | [diff] [blame] | 2103 | } |
| 2104 | |
Peter Zijlstra | c93dc84 | 2012-06-08 14:50:50 +0200 | [diff] [blame] | 2105 | void perf_check_microcode(void) |
| 2106 | { |
| 2107 | if (x86_pmu.check_microcode) |
| 2108 | x86_pmu.check_microcode(); |
| 2109 | } |
| 2110 | EXPORT_SYMBOL_GPL(perf_check_microcode); |
| 2111 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 2112 | static struct pmu pmu = { |
Stephane Eranian | d010b33 | 2012-02-09 23:21:00 +0100 | [diff] [blame] | 2113 | .pmu_enable = x86_pmu_enable, |
| 2114 | .pmu_disable = x86_pmu_disable, |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 2115 | |
Peter Zijlstra | c93dc84 | 2012-06-08 14:50:50 +0200 | [diff] [blame] | 2116 | .attr_groups = x86_pmu_attr_groups, |
Peter Zijlstra | 0c9d42e | 2011-11-20 23:30:47 +0100 | [diff] [blame] | 2117 | |
Peter Zijlstra | c93dc84 | 2012-06-08 14:50:50 +0200 | [diff] [blame] | 2118 | .event_init = x86_pmu_event_init, |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 2119 | |
Andy Lutomirski | 7911d3f | 2014-10-24 15:58:12 -0700 | [diff] [blame] | 2120 | .event_mapped = x86_pmu_event_mapped, |
| 2121 | .event_unmapped = x86_pmu_event_unmapped, |
| 2122 | |
Stephane Eranian | d010b33 | 2012-02-09 23:21:00 +0100 | [diff] [blame] | 2123 | .add = x86_pmu_add, |
| 2124 | .del = x86_pmu_del, |
| 2125 | .start = x86_pmu_start, |
| 2126 | .stop = x86_pmu_stop, |
| 2127 | .read = x86_pmu_read, |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 2128 | |
Peter Zijlstra | c93dc84 | 2012-06-08 14:50:50 +0200 | [diff] [blame] | 2129 | .start_txn = x86_pmu_start_txn, |
| 2130 | .cancel_txn = x86_pmu_cancel_txn, |
| 2131 | .commit_txn = x86_pmu_commit_txn, |
Peter Zijlstra | fe4a330 | 2011-11-20 20:44:06 +0100 | [diff] [blame] | 2132 | |
Peter Zijlstra | c93dc84 | 2012-06-08 14:50:50 +0200 | [diff] [blame] | 2133 | .event_idx = x86_pmu_event_idx, |
Yan, Zheng | ba53250 | 2014-11-04 21:55:58 -0500 | [diff] [blame] | 2134 | .sched_task = x86_pmu_sched_task, |
Yan, Zheng | e18bf52 | 2014-11-04 21:56:03 -0500 | [diff] [blame] | 2135 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 2136 | }; |
| 2137 | |
Andy Lutomirski | c1317ec | 2014-10-24 15:58:11 -0700 | [diff] [blame] | 2138 | void arch_perf_update_userpage(struct perf_event *event, |
| 2139 | struct perf_event_mmap_page *userpg, u64 now) |
Peter Zijlstra | e3f3541 | 2011-11-21 11:43:53 +0100 | [diff] [blame] | 2140 | { |
Peter Zijlstra | 20d1c86 | 2013-11-29 15:40:29 +0100 | [diff] [blame] | 2141 | struct cyc2ns_data *data; |
| 2142 | |
Peter Zijlstra | fa73158 | 2013-09-19 10:16:42 +0200 | [diff] [blame] | 2143 | userpg->cap_user_time = 0; |
| 2144 | userpg->cap_user_time_zero = 0; |
Andy Lutomirski | 7911d3f | 2014-10-24 15:58:12 -0700 | [diff] [blame] | 2145 | userpg->cap_user_rdpmc = |
| 2146 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); |
Peter Zijlstra | c720620 | 2012-03-22 17:26:36 +0100 | [diff] [blame] | 2147 | userpg->pmc_width = x86_pmu.cntval_bits; |
| 2148 | |
Peter Zijlstra | 35af99e | 2013-11-28 19:38:42 +0100 | [diff] [blame] | 2149 | if (!sched_clock_stable()) |
Peter Zijlstra | e3f3541 | 2011-11-21 11:43:53 +0100 | [diff] [blame] | 2150 | return; |
| 2151 | |
Peter Zijlstra | 20d1c86 | 2013-11-29 15:40:29 +0100 | [diff] [blame] | 2152 | data = cyc2ns_read_begin(); |
| 2153 | |
Peter Zijlstra | 34f4392 | 2015-02-20 14:05:38 +0100 | [diff] [blame] | 2154 | /* |
| 2155 | * Internal timekeeping for enabled/running/stopped times |
| 2156 | * is always in the local_clock domain. |
| 2157 | */ |
Peter Zijlstra | fa73158 | 2013-09-19 10:16:42 +0200 | [diff] [blame] | 2158 | userpg->cap_user_time = 1; |
Peter Zijlstra | 20d1c86 | 2013-11-29 15:40:29 +0100 | [diff] [blame] | 2159 | userpg->time_mult = data->cyc2ns_mul; |
| 2160 | userpg->time_shift = data->cyc2ns_shift; |
| 2161 | userpg->time_offset = data->cyc2ns_offset - now; |
Adrian Hunter | c73deb6 | 2013-06-28 16:22:18 +0300 | [diff] [blame] | 2162 | |
Peter Zijlstra | 34f4392 | 2015-02-20 14:05:38 +0100 | [diff] [blame] | 2163 | /* |
| 2164 | * cap_user_time_zero doesn't make sense when we're using a different |
| 2165 | * time base for the records. |
| 2166 | */ |
| 2167 | if (event->clock == &local_clock) { |
| 2168 | userpg->cap_user_time_zero = 1; |
| 2169 | userpg->time_zero = data->cyc2ns_offset; |
| 2170 | } |
Peter Zijlstra | 20d1c86 | 2013-11-29 15:40:29 +0100 | [diff] [blame] | 2171 | |
| 2172 | cyc2ns_read_end(data); |
Peter Zijlstra | e3f3541 | 2011-11-21 11:43:53 +0100 | [diff] [blame] | 2173 | } |
| 2174 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2175 | /* |
| 2176 | * callchain support |
| 2177 | */ |
| 2178 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2179 | static int backtrace_stack(void *data, char *name) |
| 2180 | { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2181 | return 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2182 | } |
| 2183 | |
| 2184 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 2185 | { |
| 2186 | struct perf_callchain_entry *entry = data; |
| 2187 | |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 2188 | perf_callchain_store(entry, addr); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2189 | } |
| 2190 | |
| 2191 | static const struct stacktrace_ops backtrace_ops = { |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2192 | .stack = backtrace_stack, |
| 2193 | .address = backtrace_address, |
Frederic Weisbecker | 06d65bd | 2009-12-17 05:40:34 +0100 | [diff] [blame] | 2194 | .walk_stack = print_context_stack_bp, |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2195 | }; |
| 2196 | |
Frederic Weisbecker | 56962b4 | 2010-06-30 23:03:51 +0200 | [diff] [blame] | 2197 | void |
| 2198 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2199 | { |
Frederic Weisbecker | 927c7a9 | 2010-07-01 16:20:36 +0200 | [diff] [blame] | 2200 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 2201 | /* TODO: We don't support guest os callchain now */ |
Peter Zijlstra | ed80526 | 2010-08-20 14:30:41 +0200 | [diff] [blame] | 2202 | return; |
Frederic Weisbecker | 927c7a9 | 2010-07-01 16:20:36 +0200 | [diff] [blame] | 2203 | } |
| 2204 | |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 2205 | perf_callchain_store(entry, regs->ip); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2206 | |
Namhyung Kim | e8e999cf | 2011-03-18 11:40:06 +0900 | [diff] [blame] | 2207 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2208 | } |
| 2209 | |
Arun Sharma | bc6ca7b | 2012-04-20 15:41:35 -0700 | [diff] [blame] | 2210 | static inline int |
| 2211 | valid_user_frame(const void __user *fp, unsigned long size) |
| 2212 | { |
| 2213 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); |
| 2214 | } |
| 2215 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2216 | static unsigned long get_segment_base(unsigned int segment) |
| 2217 | { |
| 2218 | struct desc_struct *desc; |
| 2219 | int idx = segment >> 3; |
| 2220 | |
| 2221 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
Andy Lutomirski | a5b9e5a | 2015-07-30 14:31:34 -0700 | [diff] [blame] | 2222 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
Andy Lutomirski | 37868fe | 2015-07-30 14:31:32 -0700 | [diff] [blame] | 2223 | struct ldt_struct *ldt; |
| 2224 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2225 | if (idx > LDT_ENTRIES) |
| 2226 | return 0; |
| 2227 | |
Andy Lutomirski | 37868fe | 2015-07-30 14:31:32 -0700 | [diff] [blame] | 2228 | /* IRQs are off, so this synchronizes with smp_store_release */ |
| 2229 | ldt = lockless_dereference(current->active_mm->context.ldt); |
| 2230 | if (!ldt || idx > ldt->size) |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2231 | return 0; |
| 2232 | |
Andy Lutomirski | 37868fe | 2015-07-30 14:31:32 -0700 | [diff] [blame] | 2233 | desc = &ldt->entries[idx]; |
Andy Lutomirski | a5b9e5a | 2015-07-30 14:31:34 -0700 | [diff] [blame] | 2234 | #else |
| 2235 | return 0; |
| 2236 | #endif |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2237 | } else { |
| 2238 | if (idx > GDT_ENTRIES) |
| 2239 | return 0; |
| 2240 | |
Andy Lutomirski | 37868fe | 2015-07-30 14:31:32 -0700 | [diff] [blame] | 2241 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2242 | } |
| 2243 | |
Andy Lutomirski | 37868fe | 2015-07-30 14:31:32 -0700 | [diff] [blame] | 2244 | return get_desc_base(desc); |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2245 | } |
| 2246 | |
Brian Gerst | 10ed349 | 2015-06-22 07:55:17 -0400 | [diff] [blame] | 2247 | #ifdef CONFIG_IA32_EMULATION |
H. Peter Anvin | d1a797f | 2012-02-19 10:06:34 -0800 | [diff] [blame] | 2248 | |
| 2249 | #include <asm/compat.h> |
| 2250 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2251 | static inline int |
| 2252 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2253 | { |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2254 | /* 32-bit process in 64-bit kernel. */ |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2255 | unsigned long ss_base, cs_base; |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2256 | struct stack_frame_ia32 frame; |
| 2257 | const void __user *fp; |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2258 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2259 | if (!test_thread_flag(TIF_IA32)) |
| 2260 | return 0; |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2261 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2262 | cs_base = get_segment_base(regs->cs); |
| 2263 | ss_base = get_segment_base(regs->ss); |
| 2264 | |
| 2265 | fp = compat_ptr(ss_base + regs->bp); |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2266 | pagefault_disable(); |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2267 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
| 2268 | unsigned long bytes; |
| 2269 | frame.next_frame = 0; |
| 2270 | frame.return_address = 0; |
| 2271 | |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2272 | if (!access_ok(VERIFY_READ, fp, 8)) |
| 2273 | break; |
| 2274 | |
| 2275 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); |
| 2276 | if (bytes != 0) |
| 2277 | break; |
| 2278 | bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); |
Peter Zijlstra | 0a19684 | 2013-10-30 21:16:22 +0100 | [diff] [blame] | 2279 | if (bytes != 0) |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2280 | break; |
| 2281 | |
Arun Sharma | bc6ca7b | 2012-04-20 15:41:35 -0700 | [diff] [blame] | 2282 | if (!valid_user_frame(fp, sizeof(frame))) |
| 2283 | break; |
| 2284 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2285 | perf_callchain_store(entry, cs_base + frame.return_address); |
| 2286 | fp = compat_ptr(ss_base + frame.next_frame); |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2287 | } |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2288 | pagefault_enable(); |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2289 | return 1; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2290 | } |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2291 | #else |
| 2292 | static inline int |
| 2293 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 2294 | { |
| 2295 | return 0; |
| 2296 | } |
| 2297 | #endif |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2298 | |
Frederic Weisbecker | 56962b4 | 2010-06-30 23:03:51 +0200 | [diff] [blame] | 2299 | void |
| 2300 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2301 | { |
| 2302 | struct stack_frame frame; |
| 2303 | const void __user *fp; |
| 2304 | |
Frederic Weisbecker | 927c7a9 | 2010-07-01 16:20:36 +0200 | [diff] [blame] | 2305 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 2306 | /* TODO: We don't support guest os callchain now */ |
Peter Zijlstra | ed80526 | 2010-08-20 14:30:41 +0200 | [diff] [blame] | 2307 | return; |
Frederic Weisbecker | 927c7a9 | 2010-07-01 16:20:36 +0200 | [diff] [blame] | 2308 | } |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2309 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2310 | /* |
| 2311 | * We don't know what to do with VM86 stacks.. ignore them for now. |
| 2312 | */ |
| 2313 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) |
| 2314 | return; |
| 2315 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2316 | fp = (void __user *)regs->bp; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2317 | |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 2318 | perf_callchain_store(entry, regs->ip); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2319 | |
Andrey Vagin | 20afc60 | 2011-08-30 12:32:36 +0400 | [diff] [blame] | 2320 | if (!current->mm) |
| 2321 | return; |
| 2322 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2323 | if (perf_callchain_user32(regs, entry)) |
| 2324 | return; |
| 2325 | |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2326 | pagefault_disable(); |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 2327 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 2328 | unsigned long bytes; |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2329 | frame.next_frame = NULL; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2330 | frame.return_address = 0; |
| 2331 | |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2332 | if (!access_ok(VERIFY_READ, fp, 16)) |
| 2333 | break; |
| 2334 | |
| 2335 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8); |
| 2336 | if (bytes != 0) |
| 2337 | break; |
| 2338 | bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8); |
Peter Zijlstra | 0a19684 | 2013-10-30 21:16:22 +0100 | [diff] [blame] | 2339 | if (bytes != 0) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2340 | break; |
| 2341 | |
Arun Sharma | bc6ca7b | 2012-04-20 15:41:35 -0700 | [diff] [blame] | 2342 | if (!valid_user_frame(fp, sizeof(frame))) |
| 2343 | break; |
| 2344 | |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 2345 | perf_callchain_store(entry, frame.return_address); |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2346 | fp = (void __user *)frame.next_frame; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2347 | } |
Andi Kleen | 75925e1 | 2015-10-22 15:07:21 -0700 | [diff] [blame] | 2348 | pagefault_enable(); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2349 | } |
| 2350 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2351 | /* |
| 2352 | * Deal with code segment offsets for the various execution modes: |
| 2353 | * |
| 2354 | * VM86 - the good olde 16 bit days, where the linear address is |
| 2355 | * 20 bits and we use regs->ip + 0x10 * regs->cs. |
| 2356 | * |
| 2357 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables |
| 2358 | * to figure out what the 32bit base address is. |
| 2359 | * |
| 2360 | * X32 - has TIF_X32 set, but is running in x86_64 |
| 2361 | * |
| 2362 | * X86_64 - CS,DS,SS,ES are all zero based. |
| 2363 | */ |
| 2364 | static unsigned long code_segment_base(struct pt_regs *regs) |
| 2365 | { |
| 2366 | /* |
Andy Lutomirski | 383f3af | 2015-03-18 18:33:30 -0700 | [diff] [blame] | 2367 | * For IA32 we look at the GDT/LDT segment base to convert the |
| 2368 | * effective IP to a linear address. |
| 2369 | */ |
| 2370 | |
| 2371 | #ifdef CONFIG_X86_32 |
| 2372 | /* |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2373 | * If we are in VM86 mode, add the segment offset to convert to a |
| 2374 | * linear address. |
| 2375 | */ |
| 2376 | if (regs->flags & X86_VM_MASK) |
| 2377 | return 0x10 * regs->cs; |
| 2378 | |
Ingo Molnar | 55474c4 | 2015-03-29 11:02:34 +0200 | [diff] [blame] | 2379 | if (user_mode(regs) && regs->cs != __USER_CS) |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2380 | return get_segment_base(regs->cs); |
| 2381 | #else |
Andy Lutomirski | c56716a | 2015-03-18 18:33:28 -0700 | [diff] [blame] | 2382 | if (user_mode(regs) && !user_64bit_mode(regs) && |
| 2383 | regs->cs != __USER32_CS) |
| 2384 | return get_segment_base(regs->cs); |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2385 | #endif |
| 2386 | return 0; |
| 2387 | } |
| 2388 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 2389 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
| 2390 | { |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 2391 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2392 | return perf_guest_cbs->get_guest_ip(); |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 2393 | |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2394 | return regs->ip + code_segment_base(regs); |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 2395 | } |
| 2396 | |
| 2397 | unsigned long perf_misc_flags(struct pt_regs *regs) |
| 2398 | { |
| 2399 | int misc = 0; |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 2400 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 2401 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 2402 | if (perf_guest_cbs->is_user_mode()) |
| 2403 | misc |= PERF_RECORD_MISC_GUEST_USER; |
| 2404 | else |
| 2405 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; |
| 2406 | } else { |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 2407 | if (user_mode(regs)) |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 2408 | misc |= PERF_RECORD_MISC_USER; |
| 2409 | else |
| 2410 | misc |= PERF_RECORD_MISC_KERNEL; |
| 2411 | } |
| 2412 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 2413 | if (regs->flags & PERF_EFLAGS_EXACT) |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 2414 | misc |= PERF_RECORD_MISC_EXACT_IP; |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 2415 | |
| 2416 | return misc; |
| 2417 | } |
Gleb Natapov | b3d9468 | 2011-11-10 14:57:27 +0200 | [diff] [blame] | 2418 | |
| 2419 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) |
| 2420 | { |
| 2421 | cap->version = x86_pmu.version; |
| 2422 | cap->num_counters_gp = x86_pmu.num_counters; |
| 2423 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; |
| 2424 | cap->bit_width_gp = x86_pmu.cntval_bits; |
| 2425 | cap->bit_width_fixed = x86_pmu.cntval_bits; |
| 2426 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; |
| 2427 | cap->events_mask_len = x86_pmu.events_mask_len; |
| 2428 | } |
| 2429 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |