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gerrit-public.fairphone.software / kernel / msm-4.9 / 16b915e4389ba8f55df31b03d9de973a3d014cf7 / . / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
blob: 2c745368afa330d223a381d4c584fb953cdd65c4 [file] [log] [blame]
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]21#include <linux/io.h>
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]22#include <linux/kernel.h>
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]23#include <linux/pinctrl/pinconf-generic.h>
24
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]25#include <mach/r8a7740.h>
26#include <mach/irqs.h>
27
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]28#include "core.h"
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]29#include "sh_pfc.h"
30
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]31#define CPU_ALL_PORT(fn, pfx, sfx) \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame^]32 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
33 PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
34 PORT_10(200, fn, pfx##20, sfx), \
35 PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]36
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]37#define IRQC_PIN_MUX(irq, pin) \
38static const unsigned int intc_irq##irq##_pins[] = { \
39 pin, \
40}; \
41static const unsigned int intc_irq##irq##_mux[] = { \
42 IRQ##irq##_MARK, \
43}
44
45#define IRQC_PINS_MUX(irq, idx, pin) \
46static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
47 pin, \
48}; \
49static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
50 IRQ##irq##_PORT##pin##_MARK, \
51}
52
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]53enum {
54 PINMUX_RESERVED = 0,
55
56 /* PORT0_DATA -> PORT211_DATA */
57 PINMUX_DATA_BEGIN,
58 PORT_ALL(DATA),
59 PINMUX_DATA_END,
60
61 /* PORT0_IN -> PORT211_IN */
62 PINMUX_INPUT_BEGIN,
63 PORT_ALL(IN),
64 PINMUX_INPUT_END,
65
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]66 /* PORT0_OUT -> PORT211_OUT */
67 PINMUX_OUTPUT_BEGIN,
68 PORT_ALL(OUT),
69 PINMUX_OUTPUT_END,
70
71 PINMUX_FUNCTION_BEGIN,
72 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
73 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
74 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
75 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
76 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
77 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
78 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
79 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
80 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
81 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
82
83 MSEL1CR_31_0, MSEL1CR_31_1,
84 MSEL1CR_30_0, MSEL1CR_30_1,
85 MSEL1CR_29_0, MSEL1CR_29_1,
86 MSEL1CR_28_0, MSEL1CR_28_1,
87 MSEL1CR_27_0, MSEL1CR_27_1,
88 MSEL1CR_26_0, MSEL1CR_26_1,
89 MSEL1CR_16_0, MSEL1CR_16_1,
90 MSEL1CR_15_0, MSEL1CR_15_1,
91 MSEL1CR_14_0, MSEL1CR_14_1,
92 MSEL1CR_13_0, MSEL1CR_13_1,
93 MSEL1CR_12_0, MSEL1CR_12_1,
94 MSEL1CR_9_0, MSEL1CR_9_1,
95 MSEL1CR_7_0, MSEL1CR_7_1,
96 MSEL1CR_6_0, MSEL1CR_6_1,
97 MSEL1CR_5_0, MSEL1CR_5_1,
98 MSEL1CR_4_0, MSEL1CR_4_1,
99 MSEL1CR_3_0, MSEL1CR_3_1,
100 MSEL1CR_2_0, MSEL1CR_2_1,
101 MSEL1CR_0_0, MSEL1CR_0_1,
102
103 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
104 MSEL3CR_6_0, MSEL3CR_6_1,
105
106 MSEL4CR_19_0, MSEL4CR_19_1,
107 MSEL4CR_18_0, MSEL4CR_18_1,
108 MSEL4CR_15_0, MSEL4CR_15_1,
109 MSEL4CR_10_0, MSEL4CR_10_1,
110 MSEL4CR_6_0, MSEL4CR_6_1,
111 MSEL4CR_4_0, MSEL4CR_4_1,
112 MSEL4CR_1_0, MSEL4CR_1_1,
113
114 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
115 MSEL5CR_30_0, MSEL5CR_30_1,
116 MSEL5CR_29_0, MSEL5CR_29_1,
117 MSEL5CR_27_0, MSEL5CR_27_1,
118 MSEL5CR_25_0, MSEL5CR_25_1,
119 MSEL5CR_23_0, MSEL5CR_23_1,
120 MSEL5CR_21_0, MSEL5CR_21_1,
121 MSEL5CR_19_0, MSEL5CR_19_1,
122 MSEL5CR_17_0, MSEL5CR_17_1,
123 MSEL5CR_15_0, MSEL5CR_15_1,
124 MSEL5CR_14_0, MSEL5CR_14_1,
125 MSEL5CR_13_0, MSEL5CR_13_1,
126 MSEL5CR_12_0, MSEL5CR_12_1,
127 MSEL5CR_11_0, MSEL5CR_11_1,
128 MSEL5CR_10_0, MSEL5CR_10_1,
129 MSEL5CR_8_0, MSEL5CR_8_1,
130 MSEL5CR_7_0, MSEL5CR_7_1,
131 MSEL5CR_6_0, MSEL5CR_6_1,
132 MSEL5CR_5_0, MSEL5CR_5_1,
133 MSEL5CR_4_0, MSEL5CR_4_1,
134 MSEL5CR_3_0, MSEL5CR_3_1,
135 MSEL5CR_2_0, MSEL5CR_2_1,
136 MSEL5CR_0_0, MSEL5CR_0_1,
137 PINMUX_FUNCTION_END,
138
139 PINMUX_MARK_BEGIN,
140
141 /* IRQ */
142 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
143 IRQ1_MARK,
144 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
145 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
146 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
147 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
148 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
149 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
150 IRQ8_MARK,
151 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
152 IRQ10_MARK,
153 IRQ11_MARK,
154 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
155 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
156 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
157 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
158 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
159 IRQ17_MARK,
160 IRQ18_MARK,
161 IRQ19_MARK,
162 IRQ20_MARK,
163 IRQ21_MARK,
164 IRQ22_MARK,
165 IRQ23_MARK,
166 IRQ24_MARK,
167 IRQ25_MARK,
168 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
169 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
170 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
171 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
172 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
173 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
174
175 /* Function */
176
177 /* DBGT */
178 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
179 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
180 DBGMD21_MARK,
181
182 /* FSI-A */
183 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
184 FSIAISLD_PORT5_MARK,
185 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
186 FSIASPDIF_PORT18_MARK,
187 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
188 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
189 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
190
191 /* FSI-B */
192 FSIBCK_MARK,
193
194 /* FMSI */
195 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
196 FMSISLD_PORT6_MARK,
197 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
198 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
199 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
200
201 /* SCIFA0 */
202 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
203 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
204
205 /* SCIFA1 */
206 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
207 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
208
209 /* SCIFA2 */
210 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
211 SCIFA2_SCK_PORT199_MARK,
212 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
213 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
214
215 /* SCIFA3 */
216 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
217 SCIFA3_SCK_PORT116_MARK,
218 SCIFA3_CTS_PORT117_MARK,
219 SCIFA3_RXD_PORT174_MARK,
220 SCIFA3_TXD_PORT175_MARK,
221
222 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
223 SCIFA3_SCK_PORT158_MARK,
224 SCIFA3_CTS_PORT162_MARK,
225 SCIFA3_RXD_PORT159_MARK,
226 SCIFA3_TXD_PORT160_MARK,
227
228 /* SCIFA4 */
229 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
230 SCIFA4_TXD_PORT13_MARK,
231
232 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
233 SCIFA4_TXD_PORT203_MARK,
234
235 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
236 SCIFA4_TXD_PORT93_MARK,
237
238 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
239 SCIFA4_SCK_PORT205_MARK,
240
241 /* SCIFA5 */
242 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
243 SCIFA5_RXD_PORT10_MARK,
244
245 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
246 SCIFA5_TXD_PORT208_MARK,
247
248 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
249 SCIFA5_RXD_PORT92_MARK,
250
251 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
252 SCIFA5_SCK_PORT206_MARK,
253
254 /* SCIFA6 */
255 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
256
257 /* SCIFA7 */
258 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
259
260 /* SCIFAB */
261 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
262 SCIFB_RXD_PORT191_MARK,
263 SCIFB_TXD_PORT192_MARK,
264 SCIFB_RTS_PORT186_MARK,
265 SCIFB_CTS_PORT187_MARK,
266
267 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
268 SCIFB_RXD_PORT3_MARK,
269 SCIFB_TXD_PORT4_MARK,
270 SCIFB_RTS_PORT172_MARK,
271 SCIFB_CTS_PORT173_MARK,
272
273 /* LCD0 */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]274 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
275 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
276 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
277 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
278 LCD0_D16_MARK, LCD0_D17_MARK,
279 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
280 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
281 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
282 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
283 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
284
285 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
286 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
287 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
288 LCD0_LCLK_PORT165_MARK,
289
290 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
291 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
292 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
293 LCD0_LCLK_PORT102_MARK,
294
295 /* LCD1 */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]296 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
297 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
298 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
299 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
300 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
301 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
302 LCD1_DON_MARK, LCD1_VCPWC_MARK,
303 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
304
305 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
306 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
307 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
308 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
309
310 /* RSPI */
311 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
312 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
313 RSPI_MISO_A_MARK,
314
315 /* VIO CKO */
316 VIO_CKO1_MARK, /* needs fixup */
317 VIO_CKO2_MARK,
318 VIO_CKO_1_MARK,
319 VIO_CKO_MARK,
320
321 /* VIO0 */
322 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
323 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
324 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
325 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
326 VIO0_FIELD_MARK,
327
328 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
329 VIO0_D14_PORT25_MARK,
330 VIO0_D15_PORT24_MARK,
331
332 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
333 VIO0_D14_PORT95_MARK,
334 VIO0_D15_PORT96_MARK,
335
336 /* VIO1 */
337 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
338 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
339 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
340
341 /* TPU0 */
342 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
343 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
344 TPU0TO2_PORT202_MARK,
345
346 /* SSP1 0 */
347 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
348 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
349 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
350
351 /* SSP1 1 */
352 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
353 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
354 STP1_IPSYNC_MARK,
355
356 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
357 STP1_IPEN_PORT187_MARK,
358
359 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
360 STP1_IPEN_PORT193_MARK,
361
362 /* SIM */
363 SIM_RST_MARK, SIM_CLK_MARK,
364 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
365 SIM_D_PORT199_MARK,
366
367 /* SDHI0 */
368 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
369 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
370
371 /* SDHI1 */
372 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
373 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
374
375 /* SDHI2 */
376 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
377 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
378
379 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
380 SDHI2_WP_PORT25_MARK,
381
382 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
383 SDHI2_CD_PORT202_MARK,
384
385 /* MSIOF2 */
386 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
387 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
388 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
389 MSIOF2_RSCK_MARK,
390
391 /* KEYSC */
392 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
393 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
394 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
395
396 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
397 KEYIN1_PORT44_MARK,
398 KEYIN2_PORT45_MARK,
399 KEYIN3_PORT46_MARK,
400
401 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
402 KEYIN1_PORT57_MARK,
403 KEYIN2_PORT56_MARK,
404 KEYIN3_PORT55_MARK,
405
406 /* VOU */
407 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
408 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
409 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
410 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
411 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
412
413 /* MEMC */
414 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
415 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
416 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
417 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
418 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
419
420 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
421 MEMC_ADV_MARK,
422 MEMC_WAIT_MARK,
423 MEMC_BUSCLK_MARK,
424
425 MEMC_A1_MARK, /* MSEL4CR_6_1 */
426 MEMC_DREQ0_MARK,
427 MEMC_DREQ1_MARK,
428 MEMC_A0_MARK,
429
430 /* MMC */
431 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
432 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
433 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
434 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
435
436 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
437 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
438 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
439 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
440
441 /* MSIOF0 */
442 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
443 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
444 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
445 MSIOF0_TSYNC_MARK,
446
447 /* MSIOF1 */
448 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
449 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
450
451 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
452 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
453 MSIOF1_TSYNC_PORT120_MARK,
454 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
455
456 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
457 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
458 MSIOF1_RXD_PORT75_MARK,
459 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
460
461 /* GPIO */
462 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
463
464 /* USB0 */
465 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
466
467 /* USB1 */
468 USB1_OCI_MARK, USB1_PPON_MARK,
469
470 /* BBIF1 */
471 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
472 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
473 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
474
475 /* BBIF2 */
476 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
477 BBIF2_RXD2_PORT60_MARK,
478 BBIF2_TSYNC2_PORT6_MARK,
479 BBIF2_TSCK2_PORT59_MARK,
480
481 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
482 BBIF2_TXD2_PORT183_MARK,
483 BBIF2_TSCK2_PORT89_MARK,
484 BBIF2_TSYNC2_PORT184_MARK,
485
486 /* BSC / FLCTL / PCMCIA */
487 CS0_MARK, CS2_MARK, CS4_MARK,
488 CS5B_MARK, CS6A_MARK,
489 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
490 CS5A_PORT19_MARK,
491 IOIS16_MARK, /* ? */
492
493 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
494 A4_FOE_MARK, /* share with FLCTL */
495 A5_FCDE_MARK, /* share with FLCTL */
496 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
497 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
498 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
499 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
500 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
501 A26_MARK,
502
503 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
504 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
505 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
506 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
507 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
508 D15_NAF15_MARK, /* share with FLCTL */
509 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
510 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
511 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
512 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
513
514 WE0_FWE_MARK, /* share with FLCTL */
515 WE1_MARK,
516 WE2_ICIORD_MARK, /* share with PCMCIA */
517 WE3_ICIOWR_MARK, /* share with PCMCIA */
518 CKO_MARK, BS_MARK, RDWR_MARK,
519 RD_FSC_MARK, /* share with FLCTL */
520 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
521 WAIT_PORT90_MARK,
522
523 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
524
525 /* IRDA */
526 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
527
528 /* ATAPI */
529 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
530 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
531 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
532 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
533 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
534 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
535 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
536 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
537
538 /* RMII */
539 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
540 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
541 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
542 RMII_REF50CK_MARK, /* for RMII */
543 RMII_REF125CK_MARK, /* for GMII */
544
545 /* GEther */
546 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
547 ET_ETXD2_MARK, ET_ETXD3_MARK,
548 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
549 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
550 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
551 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
552 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
553 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
554 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
555 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
556
557 /* DMA0 */
558 DREQ0_MARK, DACK0_MARK,
559
560 /* DMA1 */
561 DREQ1_MARK, DACK1_MARK,
562
563 /* SYSC */
564 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
565
566 /* IRREM */
567 IROUT_MARK,
568
569 /* SDENC */
570 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
571
572 /* HDMI */
573 HDMI_HPD_MARK, HDMI_CEC_MARK,
574
575 /* DEBUG */
576 EDEBGREQ_PULLUP_MARK, /* for JTAG */
577 EDEBGREQ_PULLDOWN_MARK,
578
579 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
580 TRACEAUD_FROM_LCDC0_MARK,
581 TRACEAUD_FROM_MEMC_MARK,
582
583 PINMUX_MARK_END,
584};
585
Laurent Pinchart533743d2013-07-15 13:03:20 +0200[diff] [blame]586static const u16 pinmux_data[] = {
Laurent Pincharte3d93b42013-07-15 15:14:22 +0200[diff] [blame]587 PINMUX_DATA_ALL(),
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]588
589 /* Port0 */
590 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
591 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
592 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
593 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
594 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
595 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
596 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
597
598 /* Port1 */
599 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
600 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
601 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
602 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
603 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
604 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
605 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
606
607 /* Port2 */
608 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
609 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
610 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
611 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
612 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
613
614 /* Port3 */
615 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
616 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
617 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
618 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
619
620 /* Port4 */
621 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
622 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
623 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
624 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
625
626 /* Port5 */
627 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
628 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
629 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
630 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
631 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
632
633 /* Port6 */
634 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
635 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
636 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
637 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
638 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
639
640 /* Port7 */
641 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
642
643 /* Port8 */
644 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
645
646 /* Port9 */
647 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
648 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
649
650 /* Port10 */
651 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
652 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
653 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
654
655 /* Port11 */
656 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
657 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
658 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
659
660 /* Port12 */
661 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
662 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
663 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
664 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
665 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
666
667 /* Port13 */
668 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
669 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
670 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
671 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
672
673 /* Port14 */
674 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
675 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
676 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
677 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
678 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
679
680 /* Port15 */
681 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
682 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
683 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
684 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
685 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
686
687 /* Port16 */
688 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
689 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
690
691 /* Port17 */
692 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
693 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
694
695 /* Port18 */
696 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
697 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
698
699 /* Port19 */
700 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
701 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
702 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
703
704 /* Port20 */
705 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
706 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
707 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
708
709 /* Port21 */
710 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
711 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
712 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
713 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
714 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
715 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
716
717 /* Port22 */
718 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
719 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
720 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
721
722 /* Port23 */
723 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
724 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
725 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
726 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
727 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
728 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
729
730 /* Port24 */
731 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
732 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
733 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
734 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
735
736 /* Port25 */
737 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
738 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
739 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
740 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
741
742 /* Port26 */
743 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
744 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
745 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
746
747 /* Port27 - Port39 Function */
748 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
749 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
750 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
751 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
752 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
753 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
754 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
755 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
756 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
757 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
758 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
759 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
760 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
761
762 /* Port38 IRQ */
763 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
764
765 /* Port40 */
766 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
767 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
768 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
769
770 /* Port41 */
771 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
772 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
773 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
774
775 /* Port42 */
776 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
777 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
778 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
779
780 /* Port43 */
781 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
782 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
783 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
784 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
785
786 /* Port44 */
787 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
788 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
789 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
790 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
791
792 /* Port45 */
793 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
794 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
795 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
796 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
797
798 /* Port46 */
799 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
800 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
801 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
802
803 /* Port47 */
804 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
805 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
806 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
807
808 /* Port48 */
809 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
810 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
811 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
812
813 /* Port49 */
814 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
815 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
816 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
817 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
818
819 /* Port50 */
820 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
821 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
822 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
823 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
824
825 /* Port51 */
826 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
827 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
828 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
829
830 /* Port52 */
831 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
832 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
833 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
834
835 /* Port53 */
836 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
837 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
838 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
839
840 /* Port54 */
841 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
842 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
843 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
844
845 /* Port55 */
846 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
847 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
848 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
849 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
850
851 /* Port56 */
852 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
853 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
854 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
855 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
856 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
857
858 /* Port57 */
859 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
860 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
861 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
862 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
863 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
864
865 /* Port58 */
Laurent Pinchartb7983902013-04-19 11:52:59 +0200[diff] [blame]866 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]867 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
868 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
869 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
870 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
871
872 /* Port59 */
873 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
874 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
875 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
876
877 /* Port60 */
878 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
879 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
880 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
881
882 /* Port61 */
883 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
884 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
885
886 /* Port62 */
887 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
888 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
889 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
890 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
891
892 /* Port63 */
893 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
894 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
895 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
896
897 /* Port64 */
898 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
899 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
900 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
901 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
902
903 /* Port65 */
904 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
905 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
906 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
907
908 /* Port66 */
909 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
910 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
911 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
912 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
913
914 /* Port67 - Port73 Function1 */
915 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
916 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
917 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
918 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
919 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
920 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
921 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
922
923 /* Port67 - Port73 Function2 */
924 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
925 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
926 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
927 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
928 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
929 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
930 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
931
932 /* Port67 - Port73 Function4 */
933 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
934 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
935 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
936 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
937 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
938 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
939 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
940
941 /* Port67 - Port73 Function6 */
942 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
943 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
944 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
945 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
946 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
947 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
948 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
949
950 /* Port67 - Port71 IRQ */
951 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
952 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
953 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
954 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
955 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
956
957 /* Port74 */
958 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
959 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
960 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
961 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
962 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
963
964 /* Port75 */
965 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
966 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
967 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
968 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
969 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
970
971 /* Port76 - Port80 Function */
972 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
973 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
974 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
975 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
976 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
977
978 /* Port81 */
979 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
980 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
981
982 /* Port82 - Port88 Function */
983 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
984 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
985 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
986 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
987 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
988 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
989 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
990
991 /* Port89 */
992 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
993 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
994 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
995
996 /* Port90 */
997 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
998 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
999 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1000 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1001
1002 /* Port91 */
1003 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1004 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1005 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1006 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1007
1008 /* Port92 */
1009 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1010 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1011 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1012 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1013 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1014
1015 /* Port93 */
1016 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1017 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1018 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1019 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1020 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1021
1022 /* Port94 */
1023 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1024 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1025 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1026 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1027 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1028
1029 /* Port95 */
1030 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1031 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1032
1033 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1034 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1035 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1036 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1037
1038 /* Port96 */
1039 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1040 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1041
1042 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1043 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1044 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1045 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1046
1047 /* Port97 */
1048 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1049 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1050 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1051 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1052 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1053
1054 /* Port98 */
1055 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1056 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1057 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1058 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1059
1060 /* Port99 */
1061 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1062 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1063 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1064 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1065 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1066
1067 /* Port100 */
1068 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1069 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1070 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1071 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1072
1073 /* Port101 */
1074 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1075
1076 /* Port102 */
1077 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1078 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1079
1080 /* Port103 */
1081 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1082 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1083 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1084
1085 /* Port104 */
1086 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1087 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1088 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1089
1090 /* Port105 */
1091 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1092 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1093
1094 /* Port106 */
1095 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1096 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1097
1098 /* Port107 - Port115 Function */
1099 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1100 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1101 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1102 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1103 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1104 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1105 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1106 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1107 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1108
1109 /* Port116 */
1110 PINMUX_DATA(A25_MARK, PORT116_FN1),
1111 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1112 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1113 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1114 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1115
1116 /* Port117 */
1117 PINMUX_DATA(A24_MARK, PORT117_FN1),
1118 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1119 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1120 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1121 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1122
1123 /* Port118 */
1124 PINMUX_DATA(A23_MARK, PORT118_FN1),
1125 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1126 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1127 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1128 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1129
1130 /* Port119 */
1131 PINMUX_DATA(A22_MARK, PORT119_FN1),
1132 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1133 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1134 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1135 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1136
1137 /* Port120 */
1138 PINMUX_DATA(A21_MARK, PORT120_FN1),
1139 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1140 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1141 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1142
1143 /* Port121 */
1144 PINMUX_DATA(A20_MARK, PORT121_FN1),
1145 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1146 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1147 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1148
1149 /* Port122 */
1150 PINMUX_DATA(A19_MARK, PORT122_FN1),
1151 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1152
1153 /* Port123 */
1154 PINMUX_DATA(A18_MARK, PORT123_FN1),
1155 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1156
1157 /* Port124 */
1158 PINMUX_DATA(A17_MARK, PORT124_FN1),
1159 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1160
1161 /* Port125 - Port141 Function */
1162 PINMUX_DATA(A16_MARK, PORT125_FN1),
1163 PINMUX_DATA(A15_MARK, PORT126_FN1),
1164 PINMUX_DATA(A14_MARK, PORT127_FN1),
1165 PINMUX_DATA(A13_MARK, PORT128_FN1),
1166 PINMUX_DATA(A12_MARK, PORT129_FN1),
1167 PINMUX_DATA(A11_MARK, PORT130_FN1),
1168 PINMUX_DATA(A10_MARK, PORT131_FN1),
1169 PINMUX_DATA(A9_MARK, PORT132_FN1),
1170 PINMUX_DATA(A8_MARK, PORT133_FN1),
1171 PINMUX_DATA(A7_MARK, PORT134_FN1),
1172 PINMUX_DATA(A6_MARK, PORT135_FN1),
1173 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1174 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1175 PINMUX_DATA(A3_MARK, PORT138_FN1),
1176 PINMUX_DATA(A2_MARK, PORT139_FN1),
1177 PINMUX_DATA(A1_MARK, PORT140_FN1),
1178 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1179
1180 /* Port142 - Port157 Function1 */
1181 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1182 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1183 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1184 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1185 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1186 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1187 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1188 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1189 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1190 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1191 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1192 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1193 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1194 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1195 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1196 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1197
1198 /* Port142 - Port149 Function3 */
1199 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1200 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1201 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1202 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1204 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1205 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1206 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1207
1208 /* Port158 */
1209 PINMUX_DATA(D31_MARK, PORT158_FN1),
1210 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1211 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1212 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1213 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1214 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1215
1216 /* Port159 */
1217 PINMUX_DATA(D30_MARK, PORT159_FN1),
1218 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1219 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1220 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1221 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1222
1223 /* Port160 */
1224 PINMUX_DATA(D29_MARK, PORT160_FN1),
1225 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1226 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1227 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1228 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1229
1230 /* Port161 */
1231 PINMUX_DATA(D28_MARK, PORT161_FN1),
1232 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1233 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1234 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1235 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1236 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1237
1238 /* Port162 */
1239 PINMUX_DATA(D27_MARK, PORT162_FN1),
1240 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1241 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1242 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1243 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1244
1245 /* Port163 */
1246 PINMUX_DATA(D26_MARK, PORT163_FN1),
1247 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1248 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1249 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1250 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1251 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1252
1253 /* Port164 */
1254 PINMUX_DATA(D25_MARK, PORT164_FN1),
1255 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1256 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1257 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1258 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1259
1260 /* Port165 */
1261 PINMUX_DATA(D24_MARK, PORT165_FN1),
1262 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1263 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1264 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1265
1266 /* Port166 - Port171 Function1 */
1267 PINMUX_DATA(D21_MARK, PORT166_FN1),
1268 PINMUX_DATA(D20_MARK, PORT167_FN1),
1269 PINMUX_DATA(D19_MARK, PORT168_FN1),
1270 PINMUX_DATA(D18_MARK, PORT169_FN1),
1271 PINMUX_DATA(D17_MARK, PORT170_FN1),
1272 PINMUX_DATA(D16_MARK, PORT171_FN1),
1273
1274 /* Port166 - Port171 Function3 */
1275 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1276 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1277 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1278 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1279 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1280 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1281
1282 /* Port166 - Port171 Function6 */
1283 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1284 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1285 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1286 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1287 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1288 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1289
1290 /* Port167 - Port171 IRQ */
1291 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1292 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1293 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1294 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1295 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1296
1297 /* Port172 */
1298 PINMUX_DATA(D23_MARK, PORT172_FN1),
1299 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1300 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1301 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1302 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1303
1304 /* Port173 */
1305 PINMUX_DATA(D22_MARK, PORT173_FN1),
1306 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1307 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1308 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1309 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1310
1311 /* Port174 */
1312 PINMUX_DATA(A26_MARK, PORT174_FN1),
1313 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1314 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1315 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1316
1317 /* Port175 */
1318 PINMUX_DATA(A0_MARK, PORT175_FN1),
1319 PINMUX_DATA(BS_MARK, PORT175_FN2),
1320 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1321 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1322
1323 /* Port176 */
1324 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1325
1326 /* Port177 */
1327 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1328 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1329 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1330 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1331
1332 /* Port178 */
1333 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1334 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1335 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1336
1337 /* Port179 */
1338 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1339 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1340 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1341
1342 /* Port180 */
1343 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1344 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1345 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1346 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1347 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1348
1349 /* Port181 */
1350 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1351 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1352 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1353
1354 /* Port182 */
1355 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1356 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1357 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1358
1359 /* Port183 */
1360 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1361 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1362 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1363
1364 /* Port184 */
1365 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1366 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1367 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1368
1369 /* Port185 - Port192 Function1 */
1370 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1371 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1372 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1373 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1374 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1375 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1376 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1377
1378 /* Port185 - Port192 Function3 */
1379 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1380 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1381 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1382 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1383 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1384 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1385 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1386 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1387
1388 /* Port185 - Port192 Function6 */
1389 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1390 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1391 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1392 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1393 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1394 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1395 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1396 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1397
1398 /* Port193 */
1399 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1400 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1401 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1402 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1403
1404 /* Port194 */
1405 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1406 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1407 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1408 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1409
1410 /* Port195 */
1411 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1412 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1413 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1414 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1415
1416 /* Port196 */
1417 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1418 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1419 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1420 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1421
1422 /* Port197 */
1423 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1424 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1425 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1426 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1427
1428 /* Port198 */
1429 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1430 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1431 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1432 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1433
1434 /* Port199 */
1435 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1436 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1437 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1438 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1439 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1440 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1441
1442 /* Port200 */
1443 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1444 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1445 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1446 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1447 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1448
1449 /* Port201 */
1450 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1451 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1452
1453 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1454 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1455 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1456 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1457
1458 /* Port202 */
1459 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1460 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1461
1462 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1463 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1464 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1465 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1466 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1467 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1468
1469 /* Port203 - Port208 Function1 */
1470 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1471 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1472 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1473 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1474 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1475 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1476
1477 /* Port203 - Port208 Function3 */
1478 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1479 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1480 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1481 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1482 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1483 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1484
1485 /* Port203 - Port208 Function6 */
1486 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1487 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1488 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1489 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1490 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1491 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1492
1493 /* Port203 - Port208 Function7 */
1494 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1495 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1496 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1497 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1498 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1499 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1500
1501 /* Port209 */
1502 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1503 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1504
1505 /* Port210 */
1506 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1507 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1508
1509 /* Port211 */
1510 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1511 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1512
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1513 /* SDENC */
1514 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1515 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1516
1517 /* SYSC */
1518 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1519 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1520
1521 /* DEBUG */
1522 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1523 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1524
1525 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1526 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1527 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1528};
1529
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]1530#define __I (SH_PFC_PIN_CFG_INPUT)
1531#define __O (SH_PFC_PIN_CFG_OUTPUT)
1532#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1533#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1534#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1535#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1536
Laurent Pinchartdf020272013-07-15 17:42:48 +0200[diff] [blame]1537#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
1538#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
1539#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
1540#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
1541#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
1542#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
1543#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1544#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1545#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]1546
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1547static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]1548 /* Table 56-1 (I/O and Pull U/D) */
1549 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1550 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1551 R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1552 R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1553 R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1554 R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1555 R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1556 R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1557 R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1558 R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1559 R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1560 R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1561 R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1562 R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1563 R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1564 R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1565 R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1566 R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1567 R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1568 R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1569 R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1570 R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1571 R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1572 R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1573 R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1574 R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1575 R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1576 R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1577 R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1578 R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1579 R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1580 R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1581 R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1582 R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1583 R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1584 R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1585 R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1586 R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1587 R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1588 R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1589 R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1590 R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1591 R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1592 R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1593 R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1594 R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1595 R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1596 R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1597 R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1598 R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1599 R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1600 R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1601 R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1602 R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1603 R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1604 R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1605 R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1606 R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1607 R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1608 R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1609 R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1610 R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1611 R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1612 R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1613 R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1614 R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1615 R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1616 R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1617 R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1618 R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1619 R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1620 R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1621 R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1622 R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1623 R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1624 R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1625 R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1626 R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1627 R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1628 R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1629 R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1630 R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1631 R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1632 R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1633 R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1634 R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1635 R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1636 R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1637 R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1638 R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1639 R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1640 R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1641 R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1642 R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1643 R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1644 R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1645 R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1646 R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1647 R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1648 R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1649 R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1650 R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1651 R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1652 R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1653 R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1654 R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1655};
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1656
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]1657/* - BSC -------------------------------------------------------------------- */
1658static const unsigned int bsc_data8_pins[] = {
1659 /* D[0:7] */
1660 157, 156, 155, 154, 153, 152, 151, 150,
1661};
1662static const unsigned int bsc_data8_mux[] = {
1663 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1664 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1665};
1666static const unsigned int bsc_data16_pins[] = {
1667 /* D[0:15] */
1668 157, 156, 155, 154, 153, 152, 151, 150,
1669 149, 148, 147, 146, 145, 144, 143, 142,
1670};
1671static const unsigned int bsc_data16_mux[] = {
1672 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1673 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1674 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1675 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1676};
1677static const unsigned int bsc_data32_pins[] = {
1678 /* D[0:31] */
1679 157, 156, 155, 154, 153, 152, 151, 150,
1680 149, 148, 147, 146, 145, 144, 143, 142,
1681 171, 170, 169, 168, 167, 166, 173, 172,
1682 165, 164, 163, 162, 161, 160, 159, 158,
1683};
1684static const unsigned int bsc_data32_mux[] = {
1685 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1686 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1687 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1688 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1689 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1690 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1691 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1692 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1693};
1694static const unsigned int bsc_cs0_pins[] = {
1695 /* CS */
1696 109,
1697};
1698static const unsigned int bsc_cs0_mux[] = {
1699 CS0_MARK,
1700};
1701static const unsigned int bsc_cs2_pins[] = {
1702 /* CS */
1703 110,
1704};
1705static const unsigned int bsc_cs2_mux[] = {
1706 CS2_MARK,
1707};
1708static const unsigned int bsc_cs4_pins[] = {
1709 /* CS */
1710 111,
1711};
1712static const unsigned int bsc_cs4_mux[] = {
1713 CS4_MARK,
1714};
1715static const unsigned int bsc_cs5a_0_pins[] = {
1716 /* CS */
1717 105,
1718};
1719static const unsigned int bsc_cs5a_0_mux[] = {
1720 CS5A_PORT105_MARK,
1721};
1722static const unsigned int bsc_cs5a_1_pins[] = {
1723 /* CS */
1724 19,
1725};
1726static const unsigned int bsc_cs5a_1_mux[] = {
1727 CS5A_PORT19_MARK,
1728};
1729static const unsigned int bsc_cs5b_pins[] = {
1730 /* CS */
1731 103,
1732};
1733static const unsigned int bsc_cs5b_mux[] = {
1734 CS5B_MARK,
1735};
1736static const unsigned int bsc_cs6a_pins[] = {
1737 /* CS */
1738 104,
1739};
1740static const unsigned int bsc_cs6a_mux[] = {
1741 CS6A_MARK,
1742};
1743static const unsigned int bsc_rd_we8_pins[] = {
1744 /* RD, WE[0] */
1745 115, 113,
1746};
1747static const unsigned int bsc_rd_we8_mux[] = {
1748 RD_FSC_MARK, WE0_FWE_MARK,
1749};
1750static const unsigned int bsc_rd_we16_pins[] = {
1751 /* RD, WE[0:1] */
1752 115, 113, 112,
1753};
1754static const unsigned int bsc_rd_we16_mux[] = {
1755 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1756};
1757static const unsigned int bsc_rd_we32_pins[] = {
1758 /* RD, WE[0:3] */
1759 115, 113, 112, 108, 107,
1760};
1761static const unsigned int bsc_rd_we32_mux[] = {
1762 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1763};
1764static const unsigned int bsc_bs_pins[] = {
1765 /* BS */
1766 175,
1767};
1768static const unsigned int bsc_bs_mux[] = {
1769 BS_MARK,
1770};
1771static const unsigned int bsc_rdwr_pins[] = {
1772 /* RDWR */
1773 114,
1774};
1775static const unsigned int bsc_rdwr_mux[] = {
1776 RDWR_MARK,
1777};
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]1778/* - CEU0 ------------------------------------------------------------------- */
1779static const unsigned int ceu0_data_0_7_pins[] = {
1780 /* D[0:7] */
1781 34, 33, 32, 31, 30, 29, 28, 27,
1782};
1783static const unsigned int ceu0_data_0_7_mux[] = {
1784 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1785 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1786};
1787static const unsigned int ceu0_data_8_15_0_pins[] = {
1788 /* D[8:15] */
1789 182, 181, 180, 179, 178, 26, 25, 24,
1790};
1791static const unsigned int ceu0_data_8_15_0_mux[] = {
1792 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1793 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1794 VIO0_D15_PORT24_MARK,
1795};
1796static const unsigned int ceu0_data_8_15_1_pins[] = {
1797 /* D[8:15] */
1798 182, 181, 180, 179, 178, 22, 95, 96,
1799};
1800static const unsigned int ceu0_data_8_15_1_mux[] = {
1801 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1802 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1803 VIO0_D15_PORT96_MARK,
1804};
1805static const unsigned int ceu0_clk_0_pins[] = {
1806 /* CKO */
1807 36,
1808};
1809static const unsigned int ceu0_clk_0_mux[] = {
1810 VIO_CKO_MARK,
1811};
1812static const unsigned int ceu0_clk_1_pins[] = {
1813 /* CKO */
1814 14,
1815};
1816static const unsigned int ceu0_clk_1_mux[] = {
1817 VIO_CKO1_MARK,
1818};
1819static const unsigned int ceu0_clk_2_pins[] = {
1820 /* CKO */
1821 15,
1822};
1823static const unsigned int ceu0_clk_2_mux[] = {
1824 VIO_CKO2_MARK,
1825};
1826static const unsigned int ceu0_sync_pins[] = {
1827 /* CLK, VD, HD */
1828 35, 39, 37,
1829};
1830static const unsigned int ceu0_sync_mux[] = {
1831 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1832};
1833static const unsigned int ceu0_field_pins[] = {
1834 /* FIELD */
1835 38,
1836};
1837static const unsigned int ceu0_field_mux[] = {
1838 VIO0_FIELD_MARK,
1839};
1840/* - CEU1 ------------------------------------------------------------------- */
1841static const unsigned int ceu1_data_pins[] = {
1842 /* D[0:7] */
1843 182, 181, 180, 179, 178, 26, 25, 24,
1844};
1845static const unsigned int ceu1_data_mux[] = {
1846 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1847 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1848};
1849static const unsigned int ceu1_clk_pins[] = {
1850 /* CKO */
1851 23,
1852};
1853static const unsigned int ceu1_clk_mux[] = {
1854 VIO_CKO_1_MARK,
1855};
1856static const unsigned int ceu1_sync_pins[] = {
1857 /* CLK, VD, HD */
1858 197, 198, 160,
1859};
1860static const unsigned int ceu1_sync_mux[] = {
1861 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1862};
1863static const unsigned int ceu1_field_pins[] = {
1864 /* FIELD */
1865 21,
1866};
1867static const unsigned int ceu1_field_mux[] = {
1868 VIO1_FIELD_MARK,
1869};
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]1870/* - FSIA ------------------------------------------------------------------- */
1871static const unsigned int fsia_mclk_in_pins[] = {
1872 /* CK */
1873 11,
1874};
1875static const unsigned int fsia_mclk_in_mux[] = {
1876 FSIACK_MARK,
1877};
1878static const unsigned int fsia_mclk_out_pins[] = {
1879 /* OMC */
1880 10,
1881};
1882static const unsigned int fsia_mclk_out_mux[] = {
1883 FSIAOMC_MARK,
1884};
1885static const unsigned int fsia_sclk_in_pins[] = {
1886 /* ILR, IBT */
1887 12, 13,
1888};
1889static const unsigned int fsia_sclk_in_mux[] = {
1890 FSIAILR_MARK, FSIAIBT_MARK,
1891};
1892static const unsigned int fsia_sclk_out_pins[] = {
1893 /* OLR, OBT */
1894 7, 8,
1895};
1896static const unsigned int fsia_sclk_out_mux[] = {
1897 FSIAOLR_MARK, FSIAOBT_MARK,
1898};
1899static const unsigned int fsia_data_in_0_pins[] = {
1900 /* ISLD */
1901 0,
1902};
1903static const unsigned int fsia_data_in_0_mux[] = {
1904 FSIAISLD_PORT0_MARK,
1905};
1906static const unsigned int fsia_data_in_1_pins[] = {
1907 /* ISLD */
1908 5,
1909};
1910static const unsigned int fsia_data_in_1_mux[] = {
1911 FSIAISLD_PORT5_MARK,
1912};
1913static const unsigned int fsia_data_out_0_pins[] = {
1914 /* OSLD */
1915 9,
1916};
1917static const unsigned int fsia_data_out_0_mux[] = {
1918 FSIAOSLD_MARK,
1919};
1920static const unsigned int fsia_data_out_1_pins[] = {
1921 /* OSLD */
1922 0,
1923};
1924static const unsigned int fsia_data_out_1_mux[] = {
1925 FSIAOSLD1_MARK,
1926};
1927static const unsigned int fsia_data_out_2_pins[] = {
1928 /* OSLD */
1929 1,
1930};
1931static const unsigned int fsia_data_out_2_mux[] = {
1932 FSIAOSLD2_MARK,
1933};
1934static const unsigned int fsia_spdif_0_pins[] = {
1935 /* SPDIF */
1936 9,
1937};
1938static const unsigned int fsia_spdif_0_mux[] = {
1939 FSIASPDIF_PORT9_MARK,
1940};
1941static const unsigned int fsia_spdif_1_pins[] = {
1942 /* SPDIF */
1943 18,
1944};
1945static const unsigned int fsia_spdif_1_mux[] = {
1946 FSIASPDIF_PORT18_MARK,
1947};
1948/* - FSIB ------------------------------------------------------------------- */
1949static const unsigned int fsib_mclk_in_pins[] = {
1950 /* CK */
1951 11,
1952};
1953static const unsigned int fsib_mclk_in_mux[] = {
1954 FSIBCK_MARK,
1955};
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]1956/* - GETHER ----------------------------------------------------------------- */
1957static const unsigned int gether_rmii_pins[] = {
1958 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1959 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1960};
1961static const unsigned int gether_rmii_mux[] = {
1962 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1963 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1964 RMII_MDC_MARK, RMII_MDIO_MARK,
1965};
1966static const unsigned int gether_mii_pins[] = {
1967 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1968 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1969 * CRS, COL, MDC, MDIO,
1970 */
1971 185, 186, 187, 188, 174, 161, 204,
1972 171, 170, 169, 168, 184, 183, 203,
1973 205, 163, 206, 207,
1974};
1975static const unsigned int gether_mii_mux[] = {
1976 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1977 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1978 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1979 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1980 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1981};
1982static const unsigned int gether_gmii_pins[] = {
1983 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
1984 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1985 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1986 */
1987 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1988 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1989 205, 163, 206, 207,
1990};
1991static const unsigned int gether_gmii_mux[] = {
1992 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1993 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
1994 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1995 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1996 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
1997 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1998 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1999 RMII_REF125CK_MARK,
2000};
2001static const unsigned int gether_int_pins[] = {
2002 /* PHY_INT */
2003 164,
2004};
2005static const unsigned int gether_int_mux[] = {
2006 ET_PHY_INT_MARK,
2007};
2008static const unsigned int gether_link_pins[] = {
2009 /* LINK */
2010 177,
2011};
2012static const unsigned int gether_link_mux[] = {
2013 ET_LINK_MARK,
2014};
2015static const unsigned int gether_wol_pins[] = {
2016 /* WOL */
2017 175,
2018};
2019static const unsigned int gether_wol_mux[] = {
2020 ET_WOL_MARK,
2021};
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2022/* - HDMI ------------------------------------------------------------------- */
2023static const unsigned int hdmi_pins[] = {
2024 /* HPD, CEC */
2025 210, 211,
2026};
2027static const unsigned int hdmi_mux[] = {
2028 HDMI_HPD_MARK, HDMI_CEC_MARK,
2029};
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2030/* - INTC ------------------------------------------------------------------- */
2031IRQC_PINS_MUX(0, 0, 2);
2032IRQC_PINS_MUX(0, 1, 13);
2033IRQC_PIN_MUX(1, 20);
2034IRQC_PINS_MUX(2, 0, 11);
2035IRQC_PINS_MUX(2, 1, 12);
2036IRQC_PINS_MUX(3, 0, 10);
2037IRQC_PINS_MUX(3, 1, 14);
2038IRQC_PINS_MUX(4, 0, 15);
2039IRQC_PINS_MUX(4, 1, 172);
2040IRQC_PINS_MUX(5, 0, 0);
2041IRQC_PINS_MUX(5, 1, 1);
2042IRQC_PINS_MUX(6, 0, 121);
2043IRQC_PINS_MUX(6, 1, 173);
2044IRQC_PINS_MUX(7, 0, 120);
2045IRQC_PINS_MUX(7, 1, 209);
2046IRQC_PIN_MUX(8, 119);
2047IRQC_PINS_MUX(9, 0, 118);
2048IRQC_PINS_MUX(9, 1, 210);
2049IRQC_PIN_MUX(10, 19);
2050IRQC_PIN_MUX(11, 104);
2051IRQC_PINS_MUX(12, 0, 42);
2052IRQC_PINS_MUX(12, 1, 97);
2053IRQC_PINS_MUX(13, 0, 64);
2054IRQC_PINS_MUX(13, 1, 98);
2055IRQC_PINS_MUX(14, 0, 63);
2056IRQC_PINS_MUX(14, 1, 99);
2057IRQC_PINS_MUX(15, 0, 62);
2058IRQC_PINS_MUX(15, 1, 100);
2059IRQC_PINS_MUX(16, 0, 68);
2060IRQC_PINS_MUX(16, 1, 211);
2061IRQC_PIN_MUX(17, 69);
2062IRQC_PIN_MUX(18, 70);
2063IRQC_PIN_MUX(19, 71);
2064IRQC_PIN_MUX(20, 67);
2065IRQC_PIN_MUX(21, 202);
2066IRQC_PIN_MUX(22, 95);
2067IRQC_PIN_MUX(23, 96);
2068IRQC_PIN_MUX(24, 180);
2069IRQC_PIN_MUX(25, 38);
2070IRQC_PINS_MUX(26, 0, 58);
2071IRQC_PINS_MUX(26, 1, 81);
2072IRQC_PINS_MUX(27, 0, 57);
2073IRQC_PINS_MUX(27, 1, 168);
2074IRQC_PINS_MUX(28, 0, 56);
2075IRQC_PINS_MUX(28, 1, 169);
2076IRQC_PINS_MUX(29, 0, 50);
2077IRQC_PINS_MUX(29, 1, 170);
2078IRQC_PINS_MUX(30, 0, 49);
2079IRQC_PINS_MUX(30, 1, 171);
2080IRQC_PINS_MUX(31, 0, 41);
2081IRQC_PINS_MUX(31, 1, 167);
2082
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2083/* - LCD0 ------------------------------------------------------------------- */
2084static const unsigned int lcd0_data8_pins[] = {
2085 /* D[0:7] */
2086 58, 57, 56, 55, 54, 53, 52, 51,
2087};
2088static const unsigned int lcd0_data8_mux[] = {
2089 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2090 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2091};
2092static const unsigned int lcd0_data9_pins[] = {
2093 /* D[0:8] */
2094 58, 57, 56, 55, 54, 53, 52, 51,
2095 50,
2096};
2097static const unsigned int lcd0_data9_mux[] = {
2098 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2099 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2100 LCD0_D8_MARK,
2101};
2102static const unsigned int lcd0_data12_pins[] = {
2103 /* D[0:11] */
2104 58, 57, 56, 55, 54, 53, 52, 51,
2105 50, 49, 48, 47,
2106};
2107static const unsigned int lcd0_data12_mux[] = {
2108 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2109 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2110 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2111};
2112static const unsigned int lcd0_data16_pins[] = {
2113 /* D[0:15] */
2114 58, 57, 56, 55, 54, 53, 52, 51,
2115 50, 49, 48, 47, 46, 45, 44, 43,
2116};
2117static const unsigned int lcd0_data16_mux[] = {
2118 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2119 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2120 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2121 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2122};
2123static const unsigned int lcd0_data18_pins[] = {
2124 /* D[0:17] */
2125 58, 57, 56, 55, 54, 53, 52, 51,
2126 50, 49, 48, 47, 46, 45, 44, 43,
2127 42, 41,
2128};
2129static const unsigned int lcd0_data18_mux[] = {
2130 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2131 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2132 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2133 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2134 LCD0_D16_MARK, LCD0_D17_MARK,
2135};
2136static const unsigned int lcd0_data24_0_pins[] = {
2137 /* D[0:23] */
2138 58, 57, 56, 55, 54, 53, 52, 51,
2139 50, 49, 48, 47, 46, 45, 44, 43,
2140 42, 41, 40, 4, 3, 2, 0, 1,
2141};
2142static const unsigned int lcd0_data24_0_mux[] = {
2143 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2144 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2145 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2146 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2147 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2148 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2149 LCD0_D23_PORT1_MARK,
2150};
2151static const unsigned int lcd0_data24_1_pins[] = {
2152 /* D[0:23] */
2153 58, 57, 56, 55, 54, 53, 52, 51,
2154 50, 49, 48, 47, 46, 45, 44, 43,
2155 42, 41, 163, 162, 161, 158, 160, 159,
2156};
2157static const unsigned int lcd0_data24_1_mux[] = {
2158 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2159 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2160 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2161 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2162 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2163 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2164};
2165static const unsigned int lcd0_display_pins[] = {
2166 /* DON, VCPWC, VEPWC */
2167 61, 59, 60,
2168};
2169static const unsigned int lcd0_display_mux[] = {
2170 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2171};
2172static const unsigned int lcd0_lclk_0_pins[] = {
2173 /* LCLK */
2174 102,
2175};
2176static const unsigned int lcd0_lclk_0_mux[] = {
2177 LCD0_LCLK_PORT102_MARK,
2178};
2179static const unsigned int lcd0_lclk_1_pins[] = {
2180 /* LCLK */
2181 165,
2182};
2183static const unsigned int lcd0_lclk_1_mux[] = {
2184 LCD0_LCLK_PORT165_MARK,
2185};
2186static const unsigned int lcd0_sync_pins[] = {
2187 /* VSYN, HSYN, DCK, DISP */
2188 63, 64, 62, 65,
2189};
2190static const unsigned int lcd0_sync_mux[] = {
2191 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2192};
2193static const unsigned int lcd0_sys_pins[] = {
2194 /* CS, WR, RD, RS */
2195 64, 62, 164, 65,
2196};
2197static const unsigned int lcd0_sys_mux[] = {
2198 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2199};
2200/* - LCD1 ------------------------------------------------------------------- */
2201static const unsigned int lcd1_data8_pins[] = {
2202 /* D[0:7] */
2203 4, 3, 2, 1, 0, 91, 92, 23,
2204};
2205static const unsigned int lcd1_data8_mux[] = {
2206 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2207 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2208};
2209static const unsigned int lcd1_data9_pins[] = {
2210 /* D[0:8] */
2211 4, 3, 2, 1, 0, 91, 92, 23,
2212 93,
2213};
2214static const unsigned int lcd1_data9_mux[] = {
2215 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2216 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2217 LCD1_D8_MARK,
2218};
2219static const unsigned int lcd1_data12_pins[] = {
2220 /* D[0:12] */
2221 4, 3, 2, 1, 0, 91, 92, 23,
2222 93, 94, 21, 201,
2223};
2224static const unsigned int lcd1_data12_mux[] = {
2225 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2226 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2227 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2228};
2229static const unsigned int lcd1_data16_pins[] = {
2230 /* D[0:15] */
2231 4, 3, 2, 1, 0, 91, 92, 23,
2232 93, 94, 21, 201, 200, 199, 196, 195,
2233};
2234static const unsigned int lcd1_data16_mux[] = {
2235 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2236 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2237 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2238 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2239};
2240static const unsigned int lcd1_data18_pins[] = {
2241 /* D[0:17] */
2242 4, 3, 2, 1, 0, 91, 92, 23,
2243 93, 94, 21, 201, 200, 199, 196, 195,
2244 194, 193,
2245};
2246static const unsigned int lcd1_data18_mux[] = {
2247 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2248 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2249 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2250 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2251 LCD1_D16_MARK, LCD1_D17_MARK,
2252};
2253static const unsigned int lcd1_data24_pins[] = {
2254 /* D[0:23] */
2255 4, 3, 2, 1, 0, 91, 92, 23,
2256 93, 94, 21, 201, 200, 199, 196, 195,
2257 194, 193, 198, 197, 75, 74, 15, 14,
2258};
2259static const unsigned int lcd1_data24_mux[] = {
2260 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2261 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2262 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2263 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2264 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2265 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2266};
2267static const unsigned int lcd1_display_pins[] = {
2268 /* DON, VCPWC, VEPWC */
2269 100, 5, 6,
2270};
2271static const unsigned int lcd1_display_mux[] = {
2272 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2273};
2274static const unsigned int lcd1_lclk_pins[] = {
2275 /* LCLK */
2276 40,
2277};
2278static const unsigned int lcd1_lclk_mux[] = {
2279 LCD1_LCLK_MARK,
2280};
2281static const unsigned int lcd1_sync_pins[] = {
2282 /* VSYN, HSYN, DCK, DISP */
2283 98, 97, 99, 12,
2284};
2285static const unsigned int lcd1_sync_mux[] = {
2286 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2287};
2288static const unsigned int lcd1_sys_pins[] = {
2289 /* CS, WR, RD, RS */
2290 97, 99, 13, 12,
2291};
2292static const unsigned int lcd1_sys_mux[] = {
2293 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2294};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2295/* - MMCIF ------------------------------------------------------------------ */
2296static const unsigned int mmc0_data1_0_pins[] = {
2297 /* D[0] */
2298 68,
2299};
2300static const unsigned int mmc0_data1_0_mux[] = {
2301 MMC0_D0_PORT68_MARK,
2302};
2303static const unsigned int mmc0_data4_0_pins[] = {
2304 /* D[0:3] */
2305 68, 69, 70, 71,
2306};
2307static const unsigned int mmc0_data4_0_mux[] = {
2308 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2309};
2310static const unsigned int mmc0_data8_0_pins[] = {
2311 /* D[0:7] */
2312 68, 69, 70, 71, 72, 73, 74, 75,
2313};
2314static const unsigned int mmc0_data8_0_mux[] = {
2315 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2316 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2317};
2318static const unsigned int mmc0_ctrl_0_pins[] = {
2319 /* CMD, CLK */
2320 67, 66,
2321};
2322static const unsigned int mmc0_ctrl_0_mux[] = {
2323 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2324};
2325
2326static const unsigned int mmc0_data1_1_pins[] = {
2327 /* D[0] */
2328 149,
2329};
2330static const unsigned int mmc0_data1_1_mux[] = {
2331 MMC1_D0_PORT149_MARK,
2332};
2333static const unsigned int mmc0_data4_1_pins[] = {
2334 /* D[0:3] */
2335 149, 148, 147, 146,
2336};
2337static const unsigned int mmc0_data4_1_mux[] = {
2338 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2339};
2340static const unsigned int mmc0_data8_1_pins[] = {
2341 /* D[0:7] */
2342 149, 148, 147, 146, 145, 144, 143, 142,
2343};
2344static const unsigned int mmc0_data8_1_mux[] = {
2345 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2346 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2347};
2348static const unsigned int mmc0_ctrl_1_pins[] = {
2349 /* CMD, CLK */
2350 104, 103,
2351};
2352static const unsigned int mmc0_ctrl_1_mux[] = {
2353 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2354};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2355/* - SCIFA0 ----------------------------------------------------------------- */
2356static const unsigned int scifa0_data_pins[] = {
2357 /* RXD, TXD */
2358 197, 198,
2359};
2360static const unsigned int scifa0_data_mux[] = {
2361 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2362};
2363static const unsigned int scifa0_clk_pins[] = {
2364 /* SCK */
2365 188,
2366};
2367static const unsigned int scifa0_clk_mux[] = {
2368 SCIFA0_SCK_MARK,
2369};
2370static const unsigned int scifa0_ctrl_pins[] = {
2371 /* RTS, CTS */
2372 194, 193,
2373};
2374static const unsigned int scifa0_ctrl_mux[] = {
2375 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2376};
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2377/* - SCIFA1 ----------------------------------------------------------------- */
2378static const unsigned int scifa1_data_pins[] = {
2379 /* RXD, TXD */
2380 195, 196,
2381};
2382static const unsigned int scifa1_data_mux[] = {
2383 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2384};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2385static const unsigned int scifa1_clk_pins[] = {
2386 /* SCK */
2387 185,
2388};
2389static const unsigned int scifa1_clk_mux[] = {
2390 SCIFA1_SCK_MARK,
2391};
2392static const unsigned int scifa1_ctrl_pins[] = {
2393 /* RTS, CTS */
2394 23, 21,
2395};
2396static const unsigned int scifa1_ctrl_mux[] = {
2397 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2398};
2399/* - SCIFA2 ----------------------------------------------------------------- */
2400static const unsigned int scifa2_data_pins[] = {
2401 /* RXD, TXD */
2402 200, 201,
2403};
2404static const unsigned int scifa2_data_mux[] = {
2405 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2406};
2407static const unsigned int scifa2_clk_0_pins[] = {
2408 /* SCK */
2409 22,
2410};
2411static const unsigned int scifa2_clk_0_mux[] = {
2412 SCIFA2_SCK_PORT22_MARK,
2413};
2414static const unsigned int scifa2_clk_1_pins[] = {
2415 /* SCK */
2416 199,
2417};
2418static const unsigned int scifa2_clk_1_mux[] = {
2419 SCIFA2_SCK_PORT199_MARK,
2420};
2421static const unsigned int scifa2_ctrl_pins[] = {
2422 /* RTS, CTS */
2423 96, 95,
2424};
2425static const unsigned int scifa2_ctrl_mux[] = {
2426 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2427};
2428/* - SCIFA3 ----------------------------------------------------------------- */
2429static const unsigned int scifa3_data_0_pins[] = {
2430 /* RXD, TXD */
2431 174, 175,
2432};
2433static const unsigned int scifa3_data_0_mux[] = {
2434 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2435};
2436static const unsigned int scifa3_clk_0_pins[] = {
2437 /* SCK */
2438 116,
2439};
2440static const unsigned int scifa3_clk_0_mux[] = {
2441 SCIFA3_SCK_PORT116_MARK,
2442};
2443static const unsigned int scifa3_ctrl_0_pins[] = {
2444 /* RTS, CTS */
2445 105, 117,
2446};
2447static const unsigned int scifa3_ctrl_0_mux[] = {
2448 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2449};
2450static const unsigned int scifa3_data_1_pins[] = {
2451 /* RXD, TXD */
2452 159, 160,
2453};
2454static const unsigned int scifa3_data_1_mux[] = {
2455 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2456};
2457static const unsigned int scifa3_clk_1_pins[] = {
2458 /* SCK */
2459 158,
2460};
2461static const unsigned int scifa3_clk_1_mux[] = {
2462 SCIFA3_SCK_PORT158_MARK,
2463};
2464static const unsigned int scifa3_ctrl_1_pins[] = {
2465 /* RTS, CTS */
2466 161, 162,
2467};
2468static const unsigned int scifa3_ctrl_1_mux[] = {
2469 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2470};
2471/* - SCIFA4 ----------------------------------------------------------------- */
2472static const unsigned int scifa4_data_0_pins[] = {
2473 /* RXD, TXD */
2474 12, 13,
2475};
2476static const unsigned int scifa4_data_0_mux[] = {
2477 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2478};
2479static const unsigned int scifa4_data_1_pins[] = {
2480 /* RXD, TXD */
2481 204, 203,
2482};
2483static const unsigned int scifa4_data_1_mux[] = {
2484 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2485};
2486static const unsigned int scifa4_data_2_pins[] = {
2487 /* RXD, TXD */
2488 94, 93,
2489};
2490static const unsigned int scifa4_data_2_mux[] = {
2491 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2492};
2493static const unsigned int scifa4_clk_0_pins[] = {
2494 /* SCK */
2495 21,
2496};
2497static const unsigned int scifa4_clk_0_mux[] = {
2498 SCIFA4_SCK_PORT21_MARK,
2499};
2500static const unsigned int scifa4_clk_1_pins[] = {
2501 /* SCK */
2502 205,
2503};
2504static const unsigned int scifa4_clk_1_mux[] = {
2505 SCIFA4_SCK_PORT205_MARK,
2506};
2507/* - SCIFA5 ----------------------------------------------------------------- */
2508static const unsigned int scifa5_data_0_pins[] = {
2509 /* RXD, TXD */
2510 10, 20,
2511};
2512static const unsigned int scifa5_data_0_mux[] = {
2513 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2514};
2515static const unsigned int scifa5_data_1_pins[] = {
2516 /* RXD, TXD */
2517 207, 208,
2518};
2519static const unsigned int scifa5_data_1_mux[] = {
2520 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2521};
2522static const unsigned int scifa5_data_2_pins[] = {
2523 /* RXD, TXD */
2524 92, 91,
2525};
2526static const unsigned int scifa5_data_2_mux[] = {
2527 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2528};
2529static const unsigned int scifa5_clk_0_pins[] = {
2530 /* SCK */
2531 23,
2532};
2533static const unsigned int scifa5_clk_0_mux[] = {
2534 SCIFA5_SCK_PORT23_MARK,
2535};
2536static const unsigned int scifa5_clk_1_pins[] = {
2537 /* SCK */
2538 206,
2539};
2540static const unsigned int scifa5_clk_1_mux[] = {
2541 SCIFA5_SCK_PORT206_MARK,
2542};
2543/* - SCIFA6 ----------------------------------------------------------------- */
2544static const unsigned int scifa6_data_pins[] = {
2545 /* RXD, TXD */
2546 25, 26,
2547};
2548static const unsigned int scifa6_data_mux[] = {
2549 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2550};
2551static const unsigned int scifa6_clk_pins[] = {
2552 /* SCK */
2553 24,
2554};
2555static const unsigned int scifa6_clk_mux[] = {
2556 SCIFA6_SCK_MARK,
2557};
2558/* - SCIFA7 ----------------------------------------------------------------- */
2559static const unsigned int scifa7_data_pins[] = {
2560 /* RXD, TXD */
2561 0, 1,
2562};
2563static const unsigned int scifa7_data_mux[] = {
2564 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2565};
2566/* - SCIFB ------------------------------------------------------------------ */
2567static const unsigned int scifb_data_0_pins[] = {
2568 /* RXD, TXD */
2569 191, 192,
2570};
2571static const unsigned int scifb_data_0_mux[] = {
2572 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2573};
2574static const unsigned int scifb_clk_0_pins[] = {
2575 /* SCK */
2576 190,
2577};
2578static const unsigned int scifb_clk_0_mux[] = {
2579 SCIFB_SCK_PORT190_MARK,
2580};
2581static const unsigned int scifb_ctrl_0_pins[] = {
2582 /* RTS, CTS */
2583 186, 187,
2584};
2585static const unsigned int scifb_ctrl_0_mux[] = {
2586 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2587};
2588static const unsigned int scifb_data_1_pins[] = {
2589 /* RXD, TXD */
2590 3, 4,
2591};
2592static const unsigned int scifb_data_1_mux[] = {
2593 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2594};
2595static const unsigned int scifb_clk_1_pins[] = {
2596 /* SCK */
2597 2,
2598};
2599static const unsigned int scifb_clk_1_mux[] = {
2600 SCIFB_SCK_PORT2_MARK,
2601};
2602static const unsigned int scifb_ctrl_1_pins[] = {
2603 /* RTS, CTS */
2604 172, 173,
2605};
2606static const unsigned int scifb_ctrl_1_mux[] = {
2607 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2608};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2609/* - SDHI0 ------------------------------------------------------------------ */
2610static const unsigned int sdhi0_data1_pins[] = {
2611 /* D0 */
2612 77,
2613};
2614static const unsigned int sdhi0_data1_mux[] = {
2615 SDHI0_D0_MARK,
2616};
2617static const unsigned int sdhi0_data4_pins[] = {
2618 /* D[0:3] */
2619 77, 78, 79, 80,
2620};
2621static const unsigned int sdhi0_data4_mux[] = {
2622 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2623};
2624static const unsigned int sdhi0_ctrl_pins[] = {
2625 /* CMD, CLK */
2626 76, 82,
2627};
2628static const unsigned int sdhi0_ctrl_mux[] = {
2629 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2630};
2631static const unsigned int sdhi0_cd_pins[] = {
2632 /* CD */
2633 81,
2634};
2635static const unsigned int sdhi0_cd_mux[] = {
2636 SDHI0_CD_MARK,
2637};
2638static const unsigned int sdhi0_wp_pins[] = {
2639 /* WP */
2640 83,
2641};
2642static const unsigned int sdhi0_wp_mux[] = {
2643 SDHI0_WP_MARK,
2644};
2645/* - SDHI1 ------------------------------------------------------------------ */
2646static const unsigned int sdhi1_data1_pins[] = {
2647 /* D0 */
2648 68,
2649};
2650static const unsigned int sdhi1_data1_mux[] = {
2651 SDHI1_D0_MARK,
2652};
2653static const unsigned int sdhi1_data4_pins[] = {
2654 /* D[0:3] */
2655 68, 69, 70, 71,
2656};
2657static const unsigned int sdhi1_data4_mux[] = {
2658 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2659};
2660static const unsigned int sdhi1_ctrl_pins[] = {
2661 /* CMD, CLK */
2662 67, 66,
2663};
2664static const unsigned int sdhi1_ctrl_mux[] = {
2665 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2666};
2667static const unsigned int sdhi1_cd_pins[] = {
2668 /* CD */
2669 72,
2670};
2671static const unsigned int sdhi1_cd_mux[] = {
2672 SDHI1_CD_MARK,
2673};
2674static const unsigned int sdhi1_wp_pins[] = {
2675 /* WP */
2676 73,
2677};
2678static const unsigned int sdhi1_wp_mux[] = {
2679 SDHI1_WP_MARK,
2680};
2681/* - SDHI2 ------------------------------------------------------------------ */
2682static const unsigned int sdhi2_data1_pins[] = {
2683 /* D0 */
2684 205,
2685};
2686static const unsigned int sdhi2_data1_mux[] = {
2687 SDHI2_D0_MARK,
2688};
2689static const unsigned int sdhi2_data4_pins[] = {
2690 /* D[0:3] */
2691 205, 206, 207, 208,
2692};
2693static const unsigned int sdhi2_data4_mux[] = {
2694 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2695};
2696static const unsigned int sdhi2_ctrl_pins[] = {
2697 /* CMD, CLK */
2698 204, 203,
2699};
2700static const unsigned int sdhi2_ctrl_mux[] = {
2701 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2702};
2703static const unsigned int sdhi2_cd_0_pins[] = {
2704 /* CD */
2705 202,
2706};
2707static const unsigned int sdhi2_cd_0_mux[] = {
2708 SDHI2_CD_PORT202_MARK,
2709};
2710static const unsigned int sdhi2_wp_0_pins[] = {
2711 /* WP */
2712 177,
2713};
2714static const unsigned int sdhi2_wp_0_mux[] = {
2715 SDHI2_WP_PORT177_MARK,
2716};
2717static const unsigned int sdhi2_cd_1_pins[] = {
2718 /* CD */
2719 24,
2720};
2721static const unsigned int sdhi2_cd_1_mux[] = {
2722 SDHI2_CD_PORT24_MARK,
2723};
2724static const unsigned int sdhi2_wp_1_pins[] = {
2725 /* WP */
2726 25,
2727};
2728static const unsigned int sdhi2_wp_1_mux[] = {
2729 SDHI2_WP_PORT25_MARK,
2730};
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]2731/* - TPU0 ------------------------------------------------------------------- */
2732static const unsigned int tpu0_to0_pins[] = {
2733 /* TO */
2734 23,
2735};
2736static const unsigned int tpu0_to0_mux[] = {
2737 TPU0TO0_MARK,
2738};
2739static const unsigned int tpu0_to1_pins[] = {
2740 /* TO */
2741 21,
2742};
2743static const unsigned int tpu0_to1_mux[] = {
2744 TPU0TO1_MARK,
2745};
2746static const unsigned int tpu0_to2_0_pins[] = {
2747 /* TO */
2748 66,
2749};
2750static const unsigned int tpu0_to2_0_mux[] = {
2751 TPU0TO2_PORT66_MARK,
2752};
2753static const unsigned int tpu0_to2_1_pins[] = {
2754 /* TO */
2755 202,
2756};
2757static const unsigned int tpu0_to2_1_mux[] = {
2758 TPU0TO2_PORT202_MARK,
2759};
2760static const unsigned int tpu0_to3_pins[] = {
2761 /* TO */
2762 180,
2763};
2764static const unsigned int tpu0_to3_mux[] = {
2765 TPU0TO3_MARK,
2766};
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2767
2768static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]2769 SH_PFC_PIN_GROUP(bsc_data8),
2770 SH_PFC_PIN_GROUP(bsc_data16),
2771 SH_PFC_PIN_GROUP(bsc_data32),
2772 SH_PFC_PIN_GROUP(bsc_cs0),
2773 SH_PFC_PIN_GROUP(bsc_cs2),
2774 SH_PFC_PIN_GROUP(bsc_cs4),
2775 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2776 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2777 SH_PFC_PIN_GROUP(bsc_cs5b),
2778 SH_PFC_PIN_GROUP(bsc_cs6a),
2779 SH_PFC_PIN_GROUP(bsc_rd_we8),
2780 SH_PFC_PIN_GROUP(bsc_rd_we16),
2781 SH_PFC_PIN_GROUP(bsc_rd_we32),
2782 SH_PFC_PIN_GROUP(bsc_bs),
2783 SH_PFC_PIN_GROUP(bsc_rdwr),
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]2784 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2785 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2786 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2787 SH_PFC_PIN_GROUP(ceu0_clk_0),
2788 SH_PFC_PIN_GROUP(ceu0_clk_1),
2789 SH_PFC_PIN_GROUP(ceu0_clk_2),
2790 SH_PFC_PIN_GROUP(ceu0_sync),
2791 SH_PFC_PIN_GROUP(ceu0_field),
2792 SH_PFC_PIN_GROUP(ceu1_data),
2793 SH_PFC_PIN_GROUP(ceu1_clk),
2794 SH_PFC_PIN_GROUP(ceu1_sync),
2795 SH_PFC_PIN_GROUP(ceu1_field),
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]2796 SH_PFC_PIN_GROUP(fsia_mclk_in),
2797 SH_PFC_PIN_GROUP(fsia_mclk_out),
2798 SH_PFC_PIN_GROUP(fsia_sclk_in),
2799 SH_PFC_PIN_GROUP(fsia_sclk_out),
2800 SH_PFC_PIN_GROUP(fsia_data_in_0),
2801 SH_PFC_PIN_GROUP(fsia_data_in_1),
2802 SH_PFC_PIN_GROUP(fsia_data_out_0),
2803 SH_PFC_PIN_GROUP(fsia_data_out_1),
2804 SH_PFC_PIN_GROUP(fsia_data_out_2),
2805 SH_PFC_PIN_GROUP(fsia_spdif_0),
2806 SH_PFC_PIN_GROUP(fsia_spdif_1),
2807 SH_PFC_PIN_GROUP(fsib_mclk_in),
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]2808 SH_PFC_PIN_GROUP(gether_rmii),
2809 SH_PFC_PIN_GROUP(gether_mii),
2810 SH_PFC_PIN_GROUP(gether_gmii),
2811 SH_PFC_PIN_GROUP(gether_int),
2812 SH_PFC_PIN_GROUP(gether_link),
2813 SH_PFC_PIN_GROUP(gether_wol),
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2814 SH_PFC_PIN_GROUP(hdmi),
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2815 SH_PFC_PIN_GROUP(intc_irq0_0),
2816 SH_PFC_PIN_GROUP(intc_irq0_1),
2817 SH_PFC_PIN_GROUP(intc_irq1),
2818 SH_PFC_PIN_GROUP(intc_irq2_0),
2819 SH_PFC_PIN_GROUP(intc_irq2_1),
2820 SH_PFC_PIN_GROUP(intc_irq3_0),
2821 SH_PFC_PIN_GROUP(intc_irq3_1),
2822 SH_PFC_PIN_GROUP(intc_irq4_0),
2823 SH_PFC_PIN_GROUP(intc_irq4_1),
2824 SH_PFC_PIN_GROUP(intc_irq5_0),
2825 SH_PFC_PIN_GROUP(intc_irq5_1),
2826 SH_PFC_PIN_GROUP(intc_irq6_0),
2827 SH_PFC_PIN_GROUP(intc_irq6_1),
2828 SH_PFC_PIN_GROUP(intc_irq7_0),
2829 SH_PFC_PIN_GROUP(intc_irq7_1),
2830 SH_PFC_PIN_GROUP(intc_irq8),
2831 SH_PFC_PIN_GROUP(intc_irq9_0),
2832 SH_PFC_PIN_GROUP(intc_irq9_1),
2833 SH_PFC_PIN_GROUP(intc_irq10),
2834 SH_PFC_PIN_GROUP(intc_irq11),
2835 SH_PFC_PIN_GROUP(intc_irq12_0),
2836 SH_PFC_PIN_GROUP(intc_irq12_1),
2837 SH_PFC_PIN_GROUP(intc_irq13_0),
2838 SH_PFC_PIN_GROUP(intc_irq13_1),
2839 SH_PFC_PIN_GROUP(intc_irq14_0),
2840 SH_PFC_PIN_GROUP(intc_irq14_1),
2841 SH_PFC_PIN_GROUP(intc_irq15_0),
2842 SH_PFC_PIN_GROUP(intc_irq15_1),
2843 SH_PFC_PIN_GROUP(intc_irq16_0),
2844 SH_PFC_PIN_GROUP(intc_irq16_1),
2845 SH_PFC_PIN_GROUP(intc_irq17),
2846 SH_PFC_PIN_GROUP(intc_irq18),
2847 SH_PFC_PIN_GROUP(intc_irq19),
2848 SH_PFC_PIN_GROUP(intc_irq20),
2849 SH_PFC_PIN_GROUP(intc_irq21),
2850 SH_PFC_PIN_GROUP(intc_irq22),
2851 SH_PFC_PIN_GROUP(intc_irq23),
2852 SH_PFC_PIN_GROUP(intc_irq24),
2853 SH_PFC_PIN_GROUP(intc_irq25),
2854 SH_PFC_PIN_GROUP(intc_irq26_0),
2855 SH_PFC_PIN_GROUP(intc_irq26_1),
2856 SH_PFC_PIN_GROUP(intc_irq27_0),
2857 SH_PFC_PIN_GROUP(intc_irq27_1),
2858 SH_PFC_PIN_GROUP(intc_irq28_0),
2859 SH_PFC_PIN_GROUP(intc_irq28_1),
2860 SH_PFC_PIN_GROUP(intc_irq29_0),
2861 SH_PFC_PIN_GROUP(intc_irq29_1),
2862 SH_PFC_PIN_GROUP(intc_irq30_0),
2863 SH_PFC_PIN_GROUP(intc_irq30_1),
2864 SH_PFC_PIN_GROUP(intc_irq31_0),
2865 SH_PFC_PIN_GROUP(intc_irq31_1),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2866 SH_PFC_PIN_GROUP(lcd0_data8),
2867 SH_PFC_PIN_GROUP(lcd0_data9),
2868 SH_PFC_PIN_GROUP(lcd0_data12),
2869 SH_PFC_PIN_GROUP(lcd0_data16),
2870 SH_PFC_PIN_GROUP(lcd0_data18),
2871 SH_PFC_PIN_GROUP(lcd0_data24_0),
2872 SH_PFC_PIN_GROUP(lcd0_data24_1),
2873 SH_PFC_PIN_GROUP(lcd0_display),
2874 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2875 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2876 SH_PFC_PIN_GROUP(lcd0_sync),
2877 SH_PFC_PIN_GROUP(lcd0_sys),
2878 SH_PFC_PIN_GROUP(lcd1_data8),
2879 SH_PFC_PIN_GROUP(lcd1_data9),
2880 SH_PFC_PIN_GROUP(lcd1_data12),
2881 SH_PFC_PIN_GROUP(lcd1_data16),
2882 SH_PFC_PIN_GROUP(lcd1_data18),
2883 SH_PFC_PIN_GROUP(lcd1_data24),
2884 SH_PFC_PIN_GROUP(lcd1_display),
2885 SH_PFC_PIN_GROUP(lcd1_lclk),
2886 SH_PFC_PIN_GROUP(lcd1_sync),
2887 SH_PFC_PIN_GROUP(lcd1_sys),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2888 SH_PFC_PIN_GROUP(mmc0_data1_0),
2889 SH_PFC_PIN_GROUP(mmc0_data4_0),
2890 SH_PFC_PIN_GROUP(mmc0_data8_0),
2891 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2892 SH_PFC_PIN_GROUP(mmc0_data1_1),
2893 SH_PFC_PIN_GROUP(mmc0_data4_1),
2894 SH_PFC_PIN_GROUP(mmc0_data8_1),
2895 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2896 SH_PFC_PIN_GROUP(scifa0_data),
2897 SH_PFC_PIN_GROUP(scifa0_clk),
2898 SH_PFC_PIN_GROUP(scifa0_ctrl),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2899 SH_PFC_PIN_GROUP(scifa1_data),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2900 SH_PFC_PIN_GROUP(scifa1_clk),
2901 SH_PFC_PIN_GROUP(scifa1_ctrl),
2902 SH_PFC_PIN_GROUP(scifa2_data),
2903 SH_PFC_PIN_GROUP(scifa2_clk_0),
2904 SH_PFC_PIN_GROUP(scifa2_clk_1),
2905 SH_PFC_PIN_GROUP(scifa2_ctrl),
2906 SH_PFC_PIN_GROUP(scifa3_data_0),
2907 SH_PFC_PIN_GROUP(scifa3_clk_0),
2908 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2909 SH_PFC_PIN_GROUP(scifa3_data_1),
2910 SH_PFC_PIN_GROUP(scifa3_clk_1),
2911 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2912 SH_PFC_PIN_GROUP(scifa4_data_0),
2913 SH_PFC_PIN_GROUP(scifa4_data_1),
2914 SH_PFC_PIN_GROUP(scifa4_data_2),
2915 SH_PFC_PIN_GROUP(scifa4_clk_0),
2916 SH_PFC_PIN_GROUP(scifa4_clk_1),
2917 SH_PFC_PIN_GROUP(scifa5_data_0),
2918 SH_PFC_PIN_GROUP(scifa5_data_1),
2919 SH_PFC_PIN_GROUP(scifa5_data_2),
2920 SH_PFC_PIN_GROUP(scifa5_clk_0),
2921 SH_PFC_PIN_GROUP(scifa5_clk_1),
2922 SH_PFC_PIN_GROUP(scifa6_data),
2923 SH_PFC_PIN_GROUP(scifa6_clk),
2924 SH_PFC_PIN_GROUP(scifa7_data),
2925 SH_PFC_PIN_GROUP(scifb_data_0),
2926 SH_PFC_PIN_GROUP(scifb_clk_0),
2927 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2928 SH_PFC_PIN_GROUP(scifb_data_1),
2929 SH_PFC_PIN_GROUP(scifb_clk_1),
2930 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2931 SH_PFC_PIN_GROUP(sdhi0_data1),
2932 SH_PFC_PIN_GROUP(sdhi0_data4),
2933 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2934 SH_PFC_PIN_GROUP(sdhi0_cd),
2935 SH_PFC_PIN_GROUP(sdhi0_wp),
2936 SH_PFC_PIN_GROUP(sdhi1_data1),
2937 SH_PFC_PIN_GROUP(sdhi1_data4),
2938 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2939 SH_PFC_PIN_GROUP(sdhi1_cd),
2940 SH_PFC_PIN_GROUP(sdhi1_wp),
2941 SH_PFC_PIN_GROUP(sdhi2_data1),
2942 SH_PFC_PIN_GROUP(sdhi2_data4),
2943 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2944 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2945 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2946 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2947 SH_PFC_PIN_GROUP(sdhi2_wp_1),
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]2948 SH_PFC_PIN_GROUP(tpu0_to0),
2949 SH_PFC_PIN_GROUP(tpu0_to1),
2950 SH_PFC_PIN_GROUP(tpu0_to2_0),
2951 SH_PFC_PIN_GROUP(tpu0_to2_1),
2952 SH_PFC_PIN_GROUP(tpu0_to3),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2953};
2954
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]2955static const char * const bsc_groups[] = {
2956 "bsc_data8",
2957 "bsc_data16",
2958 "bsc_data32",
2959 "bsc_cs0",
2960 "bsc_cs2",
2961 "bsc_cs4",
2962 "bsc_cs5a_0",
2963 "bsc_cs5a_1",
2964 "bsc_cs5b",
2965 "bsc_cs6a",
2966 "bsc_rd_we8",
2967 "bsc_rd_we16",
2968 "bsc_rd_we32",
2969 "bsc_bs",
2970 "bsc_rdwr",
2971};
2972
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]2973static const char * const ceu0_groups[] = {
2974 "ceu0_data_0_7",
2975 "ceu0_data_8_15_0",
2976 "ceu0_data_8_15_1",
2977 "ceu0_clk_0",
2978 "ceu0_clk_1",
2979 "ceu0_clk_2",
2980 "ceu0_sync",
2981 "ceu0_field",
2982};
2983
2984static const char * const ceu1_groups[] = {
2985 "ceu1_data",
2986 "ceu1_clk",
2987 "ceu1_sync",
2988 "ceu1_field",
2989};
2990
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]2991static const char * const fsia_groups[] = {
2992 "fsia_mclk_in",
2993 "fsia_mclk_out",
2994 "fsia_sclk_in",
2995 "fsia_sclk_out",
2996 "fsia_data_in_0",
2997 "fsia_data_in_1",
2998 "fsia_data_out_0",
2999 "fsia_data_out_1",
3000 "fsia_data_out_2",
3001 "fsia_spdif_0",
3002 "fsia_spdif_1",
3003};
3004
3005static const char * const fsib_groups[] = {
3006 "fsib_mclk_in",
3007};
3008
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]3009static const char * const gether_groups[] = {
3010 "gether_rmii",
3011 "gether_mii",
3012 "gether_gmii",
3013 "gether_int",
3014 "gether_link",
3015 "gether_wol",
3016};
3017
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]3018static const char * const hdmi_groups[] = {
3019 "hdmi",
3020};
3021
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]3022static const char * const intc_groups[] = {
3023 "intc_irq0_0",
3024 "intc_irq0_1",
3025 "intc_irq1",
3026 "intc_irq2_0",
3027 "intc_irq2_1",
3028 "intc_irq3_0",
3029 "intc_irq3_1",
3030 "intc_irq4_0",
3031 "intc_irq4_1",
3032 "intc_irq5_0",
3033 "intc_irq5_1",
3034 "intc_irq6_0",
3035 "intc_irq6_1",
3036 "intc_irq7_0",
3037 "intc_irq7_1",
3038 "intc_irq8",
3039 "intc_irq9_0",
3040 "intc_irq9_1",
3041 "intc_irq10",
3042 "intc_irq11",
3043 "intc_irq12_0",
3044 "intc_irq12_1",
3045 "intc_irq13_0",
3046 "intc_irq13_1",
3047 "intc_irq14_0",
3048 "intc_irq14_1",
3049 "intc_irq15_0",
3050 "intc_irq15_1",
3051 "intc_irq16_0",
3052 "intc_irq16_1",
3053 "intc_irq17",
3054 "intc_irq18",
3055 "intc_irq19",
3056 "intc_irq20",
3057 "intc_irq21",
3058 "intc_irq22",
3059 "intc_irq23",
3060 "intc_irq24",
3061 "intc_irq25",
3062 "intc_irq26_0",
3063 "intc_irq26_1",
3064 "intc_irq27_0",
3065 "intc_irq27_1",
3066 "intc_irq28_0",
3067 "intc_irq28_1",
3068 "intc_irq29_0",
3069 "intc_irq29_1",
3070 "intc_irq30_0",
3071 "intc_irq30_1",
3072 "intc_irq31_0",
3073 "intc_irq31_1",
3074};
3075
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3076static const char * const lcd0_groups[] = {
3077 "lcd0_data8",
3078 "lcd0_data9",
3079 "lcd0_data12",
3080 "lcd0_data16",
3081 "lcd0_data18",
3082 "lcd0_data24_0",
3083 "lcd0_data24_1",
3084 "lcd0_display",
3085 "lcd0_lclk_0",
3086 "lcd0_lclk_1",
3087 "lcd0_sync",
3088 "lcd0_sys",
3089};
3090
3091static const char * const lcd1_groups[] = {
3092 "lcd1_data8",
3093 "lcd1_data9",
3094 "lcd1_data12",
3095 "lcd1_data16",
3096 "lcd1_data18",
3097 "lcd1_data24",
3098 "lcd1_display",
3099 "lcd1_lclk",
3100 "lcd1_sync",
3101 "lcd1_sys",
3102};
3103
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3104static const char * const mmc0_groups[] = {
3105 "mmc0_data1_0",
3106 "mmc0_data4_0",
3107 "mmc0_data8_0",
3108 "mmc0_ctrl_0",
3109 "mmc0_data1_1",
3110 "mmc0_data4_1",
3111 "mmc0_data8_1",
3112 "mmc0_ctrl_1",
3113};
3114
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3115static const char * const scifa0_groups[] = {
3116 "scifa0_data",
3117 "scifa0_clk",
3118 "scifa0_ctrl",
3119};
3120
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3121static const char * const scifa1_groups[] = {
3122 "scifa1_data",
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3123 "scifa1_clk",
3124 "scifa1_ctrl",
3125};
3126
3127static const char * const scifa2_groups[] = {
3128 "scifa2_data",
3129 "scifa2_clk_0",
3130 "scifa2_clk_1",
3131 "scifa2_ctrl",
3132};
3133
3134static const char * const scifa3_groups[] = {
3135 "scifa3_data_0",
3136 "scifa3_clk_0",
3137 "scifa3_ctrl_0",
3138 "scifa3_data_1",
3139 "scifa3_clk_1",
3140 "scifa3_ctrl_1",
3141};
3142
3143static const char * const scifa4_groups[] = {
3144 "scifa4_data_0",
3145 "scifa4_data_1",
3146 "scifa4_data_2",
3147 "scifa4_clk_0",
3148 "scifa4_clk_1",
3149};
3150
3151static const char * const scifa5_groups[] = {
3152 "scifa5_data_0",
3153 "scifa5_data_1",
3154 "scifa5_data_2",
3155 "scifa5_clk_0",
3156 "scifa5_clk_1",
3157};
3158
3159static const char * const scifa6_groups[] = {
3160 "scifa6_data",
3161 "scifa6_clk",
3162};
3163
3164static const char * const scifa7_groups[] = {
3165 "scifa7_data",
3166};
3167
3168static const char * const scifb_groups[] = {
3169 "scifb_data_0",
3170 "scifb_clk_0",
3171 "scifb_ctrl_0",
3172 "scifb_data_1",
3173 "scifb_clk_1",
3174 "scifb_ctrl_1",
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3175};
3176
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3177static const char * const sdhi0_groups[] = {
3178 "sdhi0_data1",
3179 "sdhi0_data4",
3180 "sdhi0_ctrl",
3181 "sdhi0_cd",
3182 "sdhi0_wp",
3183};
3184
3185static const char * const sdhi1_groups[] = {
3186 "sdhi1_data1",
3187 "sdhi1_data4",
3188 "sdhi1_ctrl",
3189 "sdhi1_cd",
3190 "sdhi1_wp",
3191};
3192
3193static const char * const sdhi2_groups[] = {
3194 "sdhi2_data1",
3195 "sdhi2_data4",
3196 "sdhi2_ctrl",
3197 "sdhi2_cd_0",
3198 "sdhi2_wp_0",
3199 "sdhi2_cd_1",
3200 "sdhi2_wp_1",
3201};
3202
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]3203static const char * const tpu0_groups[] = {
3204 "tpu0_to0",
3205 "tpu0_to1",
3206 "tpu0_to2_0",
3207 "tpu0_to2_1",
3208 "tpu0_to3",
3209};
3210
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3211static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]3212 SH_PFC_FUNCTION(bsc),
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]3213 SH_PFC_FUNCTION(ceu0),
3214 SH_PFC_FUNCTION(ceu1),
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]3215 SH_PFC_FUNCTION(fsia),
3216 SH_PFC_FUNCTION(fsib),
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]3217 SH_PFC_FUNCTION(gether),
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]3218 SH_PFC_FUNCTION(hdmi),
Laurent Pinchartd0316962013-04-18 10:54:18 +0200[diff] [blame]3219 SH_PFC_FUNCTION(intc),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3220 SH_PFC_FUNCTION(lcd0),
3221 SH_PFC_FUNCTION(lcd1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3222 SH_PFC_FUNCTION(mmc0),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3223 SH_PFC_FUNCTION(scifa0),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3224 SH_PFC_FUNCTION(scifa1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3225 SH_PFC_FUNCTION(scifa2),
3226 SH_PFC_FUNCTION(scifa3),
3227 SH_PFC_FUNCTION(scifa4),
3228 SH_PFC_FUNCTION(scifa5),
3229 SH_PFC_FUNCTION(scifa6),
3230 SH_PFC_FUNCTION(scifa7),
3231 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3232 SH_PFC_FUNCTION(sdhi0),
3233 SH_PFC_FUNCTION(sdhi1),
3234 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]3235 SH_PFC_FUNCTION(tpu0),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3236};
3237
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]3238#undef PORTCR
3239#define PORTCR(nr, reg) \
3240 { \
3241 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3242 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3243 PORT##nr##_FN0, PORT##nr##_FN1, \
3244 PORT##nr##_FN2, PORT##nr##_FN3, \
3245 PORT##nr##_FN4, PORT##nr##_FN5, \
3246 PORT##nr##_FN6, PORT##nr##_FN7 } \
3247 }
3248
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3249static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3250 PORTCR(0, 0xe6050000), /* PORT0CR */
3251 PORTCR(1, 0xe6050001), /* PORT1CR */
3252 PORTCR(2, 0xe6050002), /* PORT2CR */
3253 PORTCR(3, 0xe6050003), /* PORT3CR */
3254 PORTCR(4, 0xe6050004), /* PORT4CR */
3255 PORTCR(5, 0xe6050005), /* PORT5CR */
3256 PORTCR(6, 0xe6050006), /* PORT6CR */
3257 PORTCR(7, 0xe6050007), /* PORT7CR */
3258 PORTCR(8, 0xe6050008), /* PORT8CR */
3259 PORTCR(9, 0xe6050009), /* PORT9CR */
3260 PORTCR(10, 0xe605000a), /* PORT10CR */
3261 PORTCR(11, 0xe605000b), /* PORT11CR */
3262 PORTCR(12, 0xe605000c), /* PORT12CR */
3263 PORTCR(13, 0xe605000d), /* PORT13CR */
3264 PORTCR(14, 0xe605000e), /* PORT14CR */
3265 PORTCR(15, 0xe605000f), /* PORT15CR */
3266 PORTCR(16, 0xe6050010), /* PORT16CR */
3267 PORTCR(17, 0xe6050011), /* PORT17CR */
3268 PORTCR(18, 0xe6050012), /* PORT18CR */
3269 PORTCR(19, 0xe6050013), /* PORT19CR */
3270 PORTCR(20, 0xe6050014), /* PORT20CR */
3271 PORTCR(21, 0xe6050015), /* PORT21CR */
3272 PORTCR(22, 0xe6050016), /* PORT22CR */
3273 PORTCR(23, 0xe6050017), /* PORT23CR */
3274 PORTCR(24, 0xe6050018), /* PORT24CR */
3275 PORTCR(25, 0xe6050019), /* PORT25CR */
3276 PORTCR(26, 0xe605001a), /* PORT26CR */
3277 PORTCR(27, 0xe605001b), /* PORT27CR */
3278 PORTCR(28, 0xe605001c), /* PORT28CR */
3279 PORTCR(29, 0xe605001d), /* PORT29CR */
3280 PORTCR(30, 0xe605001e), /* PORT30CR */
3281 PORTCR(31, 0xe605001f), /* PORT31CR */
3282 PORTCR(32, 0xe6050020), /* PORT32CR */
3283 PORTCR(33, 0xe6050021), /* PORT33CR */
3284 PORTCR(34, 0xe6050022), /* PORT34CR */
3285 PORTCR(35, 0xe6050023), /* PORT35CR */
3286 PORTCR(36, 0xe6050024), /* PORT36CR */
3287 PORTCR(37, 0xe6050025), /* PORT37CR */
3288 PORTCR(38, 0xe6050026), /* PORT38CR */
3289 PORTCR(39, 0xe6050027), /* PORT39CR */
3290 PORTCR(40, 0xe6050028), /* PORT40CR */
3291 PORTCR(41, 0xe6050029), /* PORT41CR */
3292 PORTCR(42, 0xe605002a), /* PORT42CR */
3293 PORTCR(43, 0xe605002b), /* PORT43CR */
3294 PORTCR(44, 0xe605002c), /* PORT44CR */
3295 PORTCR(45, 0xe605002d), /* PORT45CR */
3296 PORTCR(46, 0xe605002e), /* PORT46CR */
3297 PORTCR(47, 0xe605002f), /* PORT47CR */
3298 PORTCR(48, 0xe6050030), /* PORT48CR */
3299 PORTCR(49, 0xe6050031), /* PORT49CR */
3300 PORTCR(50, 0xe6050032), /* PORT50CR */
3301 PORTCR(51, 0xe6050033), /* PORT51CR */
3302 PORTCR(52, 0xe6050034), /* PORT52CR */
3303 PORTCR(53, 0xe6050035), /* PORT53CR */
3304 PORTCR(54, 0xe6050036), /* PORT54CR */
3305 PORTCR(55, 0xe6050037), /* PORT55CR */
3306 PORTCR(56, 0xe6050038), /* PORT56CR */
3307 PORTCR(57, 0xe6050039), /* PORT57CR */
3308 PORTCR(58, 0xe605003a), /* PORT58CR */
3309 PORTCR(59, 0xe605003b), /* PORT59CR */
3310 PORTCR(60, 0xe605003c), /* PORT60CR */
3311 PORTCR(61, 0xe605003d), /* PORT61CR */
3312 PORTCR(62, 0xe605003e), /* PORT62CR */
3313 PORTCR(63, 0xe605003f), /* PORT63CR */
3314 PORTCR(64, 0xe6050040), /* PORT64CR */
3315 PORTCR(65, 0xe6050041), /* PORT65CR */
3316 PORTCR(66, 0xe6050042), /* PORT66CR */
3317 PORTCR(67, 0xe6050043), /* PORT67CR */
3318 PORTCR(68, 0xe6050044), /* PORT68CR */
3319 PORTCR(69, 0xe6050045), /* PORT69CR */
3320 PORTCR(70, 0xe6050046), /* PORT70CR */
3321 PORTCR(71, 0xe6050047), /* PORT71CR */
3322 PORTCR(72, 0xe6050048), /* PORT72CR */
3323 PORTCR(73, 0xe6050049), /* PORT73CR */
3324 PORTCR(74, 0xe605004a), /* PORT74CR */
3325 PORTCR(75, 0xe605004b), /* PORT75CR */
3326 PORTCR(76, 0xe605004c), /* PORT76CR */
3327 PORTCR(77, 0xe605004d), /* PORT77CR */
3328 PORTCR(78, 0xe605004e), /* PORT78CR */
3329 PORTCR(79, 0xe605004f), /* PORT79CR */
3330 PORTCR(80, 0xe6050050), /* PORT80CR */
3331 PORTCR(81, 0xe6050051), /* PORT81CR */
3332 PORTCR(82, 0xe6050052), /* PORT82CR */
3333 PORTCR(83, 0xe6050053), /* PORT83CR */
3334
3335 PORTCR(84, 0xe6051054), /* PORT84CR */
3336 PORTCR(85, 0xe6051055), /* PORT85CR */
3337 PORTCR(86, 0xe6051056), /* PORT86CR */
3338 PORTCR(87, 0xe6051057), /* PORT87CR */
3339 PORTCR(88, 0xe6051058), /* PORT88CR */
3340 PORTCR(89, 0xe6051059), /* PORT89CR */
3341 PORTCR(90, 0xe605105a), /* PORT90CR */
3342 PORTCR(91, 0xe605105b), /* PORT91CR */
3343 PORTCR(92, 0xe605105c), /* PORT92CR */
3344 PORTCR(93, 0xe605105d), /* PORT93CR */
3345 PORTCR(94, 0xe605105e), /* PORT94CR */
3346 PORTCR(95, 0xe605105f), /* PORT95CR */
3347 PORTCR(96, 0xe6051060), /* PORT96CR */
3348 PORTCR(97, 0xe6051061), /* PORT97CR */
3349 PORTCR(98, 0xe6051062), /* PORT98CR */
3350 PORTCR(99, 0xe6051063), /* PORT99CR */
3351 PORTCR(100, 0xe6051064), /* PORT100CR */
3352 PORTCR(101, 0xe6051065), /* PORT101CR */
3353 PORTCR(102, 0xe6051066), /* PORT102CR */
3354 PORTCR(103, 0xe6051067), /* PORT103CR */
3355 PORTCR(104, 0xe6051068), /* PORT104CR */
3356 PORTCR(105, 0xe6051069), /* PORT105CR */
3357 PORTCR(106, 0xe605106a), /* PORT106CR */
3358 PORTCR(107, 0xe605106b), /* PORT107CR */
3359 PORTCR(108, 0xe605106c), /* PORT108CR */
3360 PORTCR(109, 0xe605106d), /* PORT109CR */
3361 PORTCR(110, 0xe605106e), /* PORT110CR */
3362 PORTCR(111, 0xe605106f), /* PORT111CR */
3363 PORTCR(112, 0xe6051070), /* PORT112CR */
3364 PORTCR(113, 0xe6051071), /* PORT113CR */
3365 PORTCR(114, 0xe6051072), /* PORT114CR */
3366
3367 PORTCR(115, 0xe6052073), /* PORT115CR */
3368 PORTCR(116, 0xe6052074), /* PORT116CR */
3369 PORTCR(117, 0xe6052075), /* PORT117CR */
3370 PORTCR(118, 0xe6052076), /* PORT118CR */
3371 PORTCR(119, 0xe6052077), /* PORT119CR */
3372 PORTCR(120, 0xe6052078), /* PORT120CR */
3373 PORTCR(121, 0xe6052079), /* PORT121CR */
3374 PORTCR(122, 0xe605207a), /* PORT122CR */
3375 PORTCR(123, 0xe605207b), /* PORT123CR */
3376 PORTCR(124, 0xe605207c), /* PORT124CR */
3377 PORTCR(125, 0xe605207d), /* PORT125CR */
3378 PORTCR(126, 0xe605207e), /* PORT126CR */
3379 PORTCR(127, 0xe605207f), /* PORT127CR */
3380 PORTCR(128, 0xe6052080), /* PORT128CR */
3381 PORTCR(129, 0xe6052081), /* PORT129CR */
3382 PORTCR(130, 0xe6052082), /* PORT130CR */
3383 PORTCR(131, 0xe6052083), /* PORT131CR */
3384 PORTCR(132, 0xe6052084), /* PORT132CR */
3385 PORTCR(133, 0xe6052085), /* PORT133CR */
3386 PORTCR(134, 0xe6052086), /* PORT134CR */
3387 PORTCR(135, 0xe6052087), /* PORT135CR */
3388 PORTCR(136, 0xe6052088), /* PORT136CR */
3389 PORTCR(137, 0xe6052089), /* PORT137CR */
3390 PORTCR(138, 0xe605208a), /* PORT138CR */
3391 PORTCR(139, 0xe605208b), /* PORT139CR */
3392 PORTCR(140, 0xe605208c), /* PORT140CR */
3393 PORTCR(141, 0xe605208d), /* PORT141CR */
3394 PORTCR(142, 0xe605208e), /* PORT142CR */
3395 PORTCR(143, 0xe605208f), /* PORT143CR */
3396 PORTCR(144, 0xe6052090), /* PORT144CR */
3397 PORTCR(145, 0xe6052091), /* PORT145CR */
3398 PORTCR(146, 0xe6052092), /* PORT146CR */
3399 PORTCR(147, 0xe6052093), /* PORT147CR */
3400 PORTCR(148, 0xe6052094), /* PORT148CR */
3401 PORTCR(149, 0xe6052095), /* PORT149CR */
3402 PORTCR(150, 0xe6052096), /* PORT150CR */
3403 PORTCR(151, 0xe6052097), /* PORT151CR */
3404 PORTCR(152, 0xe6052098), /* PORT152CR */
3405 PORTCR(153, 0xe6052099), /* PORT153CR */
3406 PORTCR(154, 0xe605209a), /* PORT154CR */
3407 PORTCR(155, 0xe605209b), /* PORT155CR */
3408 PORTCR(156, 0xe605209c), /* PORT156CR */
3409 PORTCR(157, 0xe605209d), /* PORT157CR */
3410 PORTCR(158, 0xe605209e), /* PORT158CR */
3411 PORTCR(159, 0xe605209f), /* PORT159CR */
3412 PORTCR(160, 0xe60520a0), /* PORT160CR */
3413 PORTCR(161, 0xe60520a1), /* PORT161CR */
3414 PORTCR(162, 0xe60520a2), /* PORT162CR */
3415 PORTCR(163, 0xe60520a3), /* PORT163CR */
3416 PORTCR(164, 0xe60520a4), /* PORT164CR */
3417 PORTCR(165, 0xe60520a5), /* PORT165CR */
3418 PORTCR(166, 0xe60520a6), /* PORT166CR */
3419 PORTCR(167, 0xe60520a7), /* PORT167CR */
3420 PORTCR(168, 0xe60520a8), /* PORT168CR */
3421 PORTCR(169, 0xe60520a9), /* PORT169CR */
3422 PORTCR(170, 0xe60520aa), /* PORT170CR */
3423 PORTCR(171, 0xe60520ab), /* PORT171CR */
3424 PORTCR(172, 0xe60520ac), /* PORT172CR */
3425 PORTCR(173, 0xe60520ad), /* PORT173CR */
3426 PORTCR(174, 0xe60520ae), /* PORT174CR */
3427 PORTCR(175, 0xe60520af), /* PORT175CR */
3428 PORTCR(176, 0xe60520b0), /* PORT176CR */
3429 PORTCR(177, 0xe60520b1), /* PORT177CR */
3430 PORTCR(178, 0xe60520b2), /* PORT178CR */
3431 PORTCR(179, 0xe60520b3), /* PORT179CR */
3432 PORTCR(180, 0xe60520b4), /* PORT180CR */
3433 PORTCR(181, 0xe60520b5), /* PORT181CR */
3434 PORTCR(182, 0xe60520b6), /* PORT182CR */
3435 PORTCR(183, 0xe60520b7), /* PORT183CR */
3436 PORTCR(184, 0xe60520b8), /* PORT184CR */
3437 PORTCR(185, 0xe60520b9), /* PORT185CR */
3438 PORTCR(186, 0xe60520ba), /* PORT186CR */
3439 PORTCR(187, 0xe60520bb), /* PORT187CR */
3440 PORTCR(188, 0xe60520bc), /* PORT188CR */
3441 PORTCR(189, 0xe60520bd), /* PORT189CR */
3442 PORTCR(190, 0xe60520be), /* PORT190CR */
3443 PORTCR(191, 0xe60520bf), /* PORT191CR */
3444 PORTCR(192, 0xe60520c0), /* PORT192CR */
3445 PORTCR(193, 0xe60520c1), /* PORT193CR */
3446 PORTCR(194, 0xe60520c2), /* PORT194CR */
3447 PORTCR(195, 0xe60520c3), /* PORT195CR */
3448 PORTCR(196, 0xe60520c4), /* PORT196CR */
3449 PORTCR(197, 0xe60520c5), /* PORT197CR */
3450 PORTCR(198, 0xe60520c6), /* PORT198CR */
3451 PORTCR(199, 0xe60520c7), /* PORT199CR */
3452 PORTCR(200, 0xe60520c8), /* PORT200CR */
3453 PORTCR(201, 0xe60520c9), /* PORT201CR */
3454 PORTCR(202, 0xe60520ca), /* PORT202CR */
3455 PORTCR(203, 0xe60520cb), /* PORT203CR */
3456 PORTCR(204, 0xe60520cc), /* PORT204CR */
3457 PORTCR(205, 0xe60520cd), /* PORT205CR */
3458 PORTCR(206, 0xe60520ce), /* PORT206CR */
3459 PORTCR(207, 0xe60520cf), /* PORT207CR */
3460 PORTCR(208, 0xe60520d0), /* PORT208CR */
3461 PORTCR(209, 0xe60520d1), /* PORT209CR */
3462
3463 PORTCR(210, 0xe60530d2), /* PORT210CR */
3464 PORTCR(211, 0xe60530d3), /* PORT211CR */
3465
3466 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3467 MSEL1CR_31_0, MSEL1CR_31_1,
3468 MSEL1CR_30_0, MSEL1CR_30_1,
3469 MSEL1CR_29_0, MSEL1CR_29_1,
3470 MSEL1CR_28_0, MSEL1CR_28_1,
3471 MSEL1CR_27_0, MSEL1CR_27_1,
3472 MSEL1CR_26_0, MSEL1CR_26_1,
3473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3474 0, 0, 0, 0, 0, 0, 0, 0,
3475 MSEL1CR_16_0, MSEL1CR_16_1,
3476 MSEL1CR_15_0, MSEL1CR_15_1,
3477 MSEL1CR_14_0, MSEL1CR_14_1,
3478 MSEL1CR_13_0, MSEL1CR_13_1,
3479 MSEL1CR_12_0, MSEL1CR_12_1,
3480 0, 0, 0, 0,
3481 MSEL1CR_9_0, MSEL1CR_9_1,
3482 0, 0,
3483 MSEL1CR_7_0, MSEL1CR_7_1,
3484 MSEL1CR_6_0, MSEL1CR_6_1,
3485 MSEL1CR_5_0, MSEL1CR_5_1,
3486 MSEL1CR_4_0, MSEL1CR_4_1,
3487 MSEL1CR_3_0, MSEL1CR_3_1,
3488 MSEL1CR_2_0, MSEL1CR_2_1,
3489 0, 0,
3490 MSEL1CR_0_0, MSEL1CR_0_1,
3491 }
3492 },
3493 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3494 0, 0, 0, 0, 0, 0, 0, 0,
3495 0, 0, 0, 0, 0, 0, 0, 0,
3496 0, 0, 0, 0, 0, 0, 0, 0,
3497 0, 0, 0, 0, 0, 0, 0, 0,
3498 MSEL3CR_15_0, MSEL3CR_15_1,
3499 0, 0, 0, 0, 0, 0, 0, 0,
3500 0, 0, 0, 0, 0, 0, 0, 0,
3501 MSEL3CR_6_0, MSEL3CR_6_1,
3502 0, 0, 0, 0, 0, 0, 0, 0,
3503 0, 0, 0, 0,
3504 }
3505 },
3506 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3507 0, 0, 0, 0, 0, 0, 0, 0,
3508 0, 0, 0, 0, 0, 0, 0, 0,
3509 0, 0, 0, 0, 0, 0, 0, 0,
3510 MSEL4CR_19_0, MSEL4CR_19_1,
3511 MSEL4CR_18_0, MSEL4CR_18_1,
3512 0, 0, 0, 0,
3513 MSEL4CR_15_0, MSEL4CR_15_1,
3514 0, 0, 0, 0, 0, 0, 0, 0,
3515 MSEL4CR_10_0, MSEL4CR_10_1,
3516 0, 0, 0, 0, 0, 0,
3517 MSEL4CR_6_0, MSEL4CR_6_1,
3518 0, 0,
3519 MSEL4CR_4_0, MSEL4CR_4_1,
3520 0, 0, 0, 0,
3521 MSEL4CR_1_0, MSEL4CR_1_1,
3522 0, 0,
3523 }
3524 },
3525 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3526 MSEL5CR_31_0, MSEL5CR_31_1,
3527 MSEL5CR_30_0, MSEL5CR_30_1,
3528 MSEL5CR_29_0, MSEL5CR_29_1,
3529 0, 0,
3530 MSEL5CR_27_0, MSEL5CR_27_1,
3531 0, 0,
3532 MSEL5CR_25_0, MSEL5CR_25_1,
3533 0, 0,
3534 MSEL5CR_23_0, MSEL5CR_23_1,
3535 0, 0,
3536 MSEL5CR_21_0, MSEL5CR_21_1,
3537 0, 0,
3538 MSEL5CR_19_0, MSEL5CR_19_1,
3539 0, 0,
3540 MSEL5CR_17_0, MSEL5CR_17_1,
3541 0, 0,
3542 MSEL5CR_15_0, MSEL5CR_15_1,
3543 MSEL5CR_14_0, MSEL5CR_14_1,
3544 MSEL5CR_13_0, MSEL5CR_13_1,
3545 MSEL5CR_12_0, MSEL5CR_12_1,
3546 MSEL5CR_11_0, MSEL5CR_11_1,
3547 MSEL5CR_10_0, MSEL5CR_10_1,
3548 0, 0,
3549 MSEL5CR_8_0, MSEL5CR_8_1,
3550 MSEL5CR_7_0, MSEL5CR_7_1,
3551 MSEL5CR_6_0, MSEL5CR_6_1,
3552 MSEL5CR_5_0, MSEL5CR_5_1,
3553 MSEL5CR_4_0, MSEL5CR_4_1,
3554 MSEL5CR_3_0, MSEL5CR_3_1,
3555 MSEL5CR_2_0, MSEL5CR_2_1,
3556 0, 0,
3557 MSEL5CR_0_0, MSEL5CR_0_1,
3558 }
3559 },
3560 { },
3561};
3562
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3563static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3564 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3565 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3566 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3567 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3568 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3569 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3570 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3571 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3572 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3573 },
3574 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3575 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3576 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3577 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3578 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3579 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3580 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3581 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3582 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3583 },
3584 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3585 0, 0, 0, 0,
3586 0, 0, 0, 0,
3587 0, 0, 0, 0,
3588 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3589 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3590 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3591 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3592 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3593 },
3594 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3595 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3596 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3597 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3598 0, 0, 0, 0,
3599 0, 0, 0, 0,
3600 0, 0, 0, 0,
3601 0, 0, 0, 0,
3602 0, 0, 0, 0 }
3603 },
3604 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3605 0, 0, 0, 0,
3606 0, 0, 0, 0,
3607 0, 0, 0, 0,
3608 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3609 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3610 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3611 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3612 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3613 },
3614 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3615 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3616 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3617 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3618 PORT115_DATA, 0, 0, 0,
3619 0, 0, 0, 0,
3620 0, 0, 0, 0,
3621 0, 0, 0, 0,
3622 0, 0, 0, 0 }
3623 },
3624 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3625 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3626 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3627 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3628 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3629 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3630 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3631 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3632 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3633 },
3634 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3635 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3636 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3637 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3638 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3639 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3640 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3641 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3642 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3643 },
3644 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3645 0, 0, 0, 0,
3646 0, 0, 0, 0,
3647 0, 0, 0, 0,
3648 0, 0, PORT209_DATA, PORT208_DATA,
3649 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3650 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3651 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3652 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3653 },
3654 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3655 0, 0, 0, 0,
3656 0, 0, 0, 0,
3657 0, 0, 0, 0,
3658 PORT211_DATA, PORT210_DATA, 0, 0,
3659 0, 0, 0, 0,
3660 0, 0, 0, 0,
3661 0, 0, 0, 0,
3662 0, 0, 0, 0 }
3663 },
3664 { },
3665};
3666
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3667static const struct pinmux_irq pinmux_irqs[] = {
Laurent Pinchart7d568452013-04-23 00:36:40 +0200[diff] [blame]3668 PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */
3669 PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */
3670 PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */
3671 PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */
3672 PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */
3673 PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */
3674 PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */
3675 PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */
3676 PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */
3677 PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */
3678 PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */
3679 PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */
3680 PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */
3681 PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */
3682 PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */
3683 PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */
3684 PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */
3685 PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */
3686 PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */
3687 PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */
3688 PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */
3689 PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */
3690 PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */
3691 PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */
3692 PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */
3693 PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */
3694 PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */
3695 PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */
3696 PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */
3697 PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */
3698 PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */
3699 PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3700};
3701
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]3702#define PORTnCR_PULMD_OFF (0 << 6)
3703#define PORTnCR_PULMD_DOWN (2 << 6)
3704#define PORTnCR_PULMD_UP (3 << 6)
3705#define PORTnCR_PULMD_MASK (3 << 6)
3706
3707struct r8a7740_portcr_group {
3708 unsigned int end_pin;
3709 unsigned int offset;
3710};
3711
3712static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3713 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3714};
3715
3716static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3717{
3718 unsigned int i;
3719
3720 for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3721 const struct r8a7740_portcr_group *group =
3722 &r8a7740_portcr_offsets[i];
3723
3724 if (i <= group->end_pin)
3725 return pfc->window->virt + group->offset + pin;
3726 }
3727
3728 return NULL;
3729}
3730
3731static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3732{
3733 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3734 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3735
3736 switch (value) {
3737 case PORTnCR_PULMD_UP:
3738 return PIN_CONFIG_BIAS_PULL_UP;
3739 case PORTnCR_PULMD_DOWN:
3740 return PIN_CONFIG_BIAS_PULL_DOWN;
3741 case PORTnCR_PULMD_OFF:
3742 default:
3743 return PIN_CONFIG_BIAS_DISABLE;
3744 }
3745}
3746
3747static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3748 unsigned int bias)
3749{
3750 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3751 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3752
3753 switch (bias) {
3754 case PIN_CONFIG_BIAS_PULL_UP:
3755 value |= PORTnCR_PULMD_UP;
3756 break;
3757 case PIN_CONFIG_BIAS_PULL_DOWN:
3758 value |= PORTnCR_PULMD_DOWN;
3759 break;
3760 }
3761
3762 iowrite8(value, addr);
3763}
3764
3765static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
3766 .get_bias = r8a7740_pinmux_get_bias,
3767 .set_bias = r8a7740_pinmux_set_bias,
3768};
3769
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3770const struct sh_pfc_soc_info r8a7740_pinmux_info = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3771 .name = "r8a7740_pfc",
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]3772 .ops = &r8a7740_pinmux_ops,
3773
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3774 .input = { PINMUX_INPUT_BEGIN,
3775 PINMUX_INPUT_END },
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3776 .output = { PINMUX_OUTPUT_BEGIN,
3777 PINMUX_OUTPUT_END },
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3778 .function = { PINMUX_FUNCTION_BEGIN,
3779 PINMUX_FUNCTION_END },
3780
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3781 .pins = pinmux_pins,
3782 .nr_pins = ARRAY_SIZE(pinmux_pins),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3783 .groups = pinmux_groups,
3784 .nr_groups = ARRAY_SIZE(pinmux_groups),
3785 .functions = pinmux_functions,
3786 .nr_functions = ARRAY_SIZE(pinmux_functions),
3787
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3788 .cfg_regs = pinmux_config_regs,
3789 .data_regs = pinmux_data_regs,
3790
3791 .gpio_data = pinmux_data,
3792 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3793
3794 .gpio_irq = pinmux_irqs,
3795 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3796};