blob: 1cd3123a7495bf055d36b0ad431f18777130c90a [file] [log] [blame]
Dhaval Patel14d46ce2017-01-17 16:28:12 -08001/*
2 * Copyright (C) 2014-2017 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07005 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -08006 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07009 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -080010 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070017 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040018
19#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
20
Clarence Ip4ce59322016-06-26 22:27:51 -040021#include <linux/debugfs.h>
Alan Kwong4dd64c82017-02-04 18:41:51 -080022#include <linux/dma-buf.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040023#include <uapi/drm/sde_drm.h>
Benet Clarkd009b1d2016-06-27 14:45:59 -070024#include <uapi/drm/msm_drm_pp.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040025
26#include "msm_prop.h"
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080027#include "msm_drv.h"
Clarence Ipaa0faf42016-05-30 12:07:48 -040028
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070029#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040030#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040031#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040032#include "sde_hw_sspp.h"
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080033#include "sde_hw_catalog_format.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040034#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070035#include "sde_crtc.h"
Lloyd Atkinson8772e202016-09-26 17:52:16 -040036#include "sde_vbif.h"
Alan Kwong83285fb2016-10-21 20:51:17 -040037#include "sde_plane.h"
Benet Clarkd009b1d2016-06-27 14:45:59 -070038#include "sde_color_processing.h"
Alan Kwong4dd64c82017-02-04 18:41:51 -080039#include "sde_hw_rot.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040040
Clarence Ip56902792017-03-17 15:22:07 -040041static bool suspend_blank = true;
42module_param(suspend_blank, bool, 0400);
43MODULE_PARM_DESC(suspend_blank,
44 "If set, active planes will force their outputs to black,\n"
45 "by temporarily enabling the color fill, when recovering\n"
46 "from a system resume instead of attempting to display the\n"
47 "last provided frame buffer.");
48
Clarence Ip13a8cf42016-09-29 17:27:47 -040049#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
50 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
51
52#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
53 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
54
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040055#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
56#define PHASE_STEP_SHIFT 21
57#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
58#define PHASE_RESIDUAL 15
59
Clarence Ipe78efb72016-06-24 18:35:21 -040060#define SHARP_STRENGTH_DEFAULT 32
61#define SHARP_EDGE_THR_DEFAULT 112
62#define SHARP_SMOOTH_THR_DEFAULT 8
63#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040064
Clarence Ip5e2a9222016-06-26 22:38:24 -040065#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070066
Clarence Ipcae1bb62016-07-07 12:07:13 -040067#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
68
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080069/* multirect rect index */
70enum {
71 R0,
72 R1,
73 R_MAX
74};
75
76#define TX_MODE_BUFFER_LINE_THRES 2
77
Clarence Ip282dad62016-09-27 17:07:35 -040078/* dirty bits for update function */
79#define SDE_PLANE_DIRTY_RECTS 0x1
80#define SDE_PLANE_DIRTY_FORMAT 0x2
81#define SDE_PLANE_DIRTY_SHARPEN 0x4
82#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
83
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -070084#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
85#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
86
Alan Kwong4dd64c82017-02-04 18:41:51 -080087#define DEFAULT_REFRESH_RATE 60
88
Alan Kwong1a00e4d2016-07-18 09:42:30 -040089/**
90 * enum sde_plane_qos - Different qos configurations for each pipe
91 *
92 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
93 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
94 * this configuration is mutually exclusive from VBLANK_CTRL.
95 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
96 */
97enum sde_plane_qos {
98 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
99 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
100 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
101};
102
Clarence Ip5fc00c52016-09-23 15:03:34 -0400103/*
104 * struct sde_plane - local sde plane structure
105 * @csc_cfg: Decoded user configuration for csc
106 * @csc_usr_ptr: Points to csc_cfg if valid user config available
107 * @csc_ptr: Points to sde_csc_cfg structure to use for current
Alan Kwong4dd64c82017-02-04 18:41:51 -0800108 * @catalog: Points to sde catalog structure
109 * @sbuf_mode: force stream buffer mode if set
110 * @sbuf_writeback: fource stream buffer writeback if set
111 * @blob_rot_caps: Pointer to rotator capability blob
Clarence Ip5fc00c52016-09-23 15:03:34 -0400112 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700113struct sde_plane {
114 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400115
116 int mmu_id;
117
Clarence Ip730e7192016-06-26 22:45:09 -0400118 struct mutex lock;
119
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400120 enum sde_sspp pipe;
121 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700122 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400123 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400124
125 struct sde_hw_pipe *pipe_hw;
126 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -0400127 struct sde_hw_sharp_cfg sharp_cfg;
abeykun48f407a2016-08-25 12:06:44 -0400128 struct sde_hw_scaler3_cfg *scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400129 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400130 uint32_t color_fill;
131 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400132 bool is_rt_pipe;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800133 bool is_virtual;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800134 struct sde_mdss_cfg *catalog;
135 u32 sbuf_mode;
136 u32 sbuf_writeback;
Clarence Ip4ce59322016-06-26 22:27:51 -0400137
Clarence Ipb43d4592016-09-08 14:21:35 -0400138 struct sde_hw_pixel_ext pixel_ext;
139 bool pixel_ext_usr;
140
Clarence Ip373f8592016-05-26 00:58:42 -0400141 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400142 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -0400143 struct sde_csc_cfg *csc_ptr;
144
Clarence Ip4c1d9772016-06-26 09:35:38 -0400145 const struct sde_sspp_sub_blks *pipe_sblk;
146
Clarence Ip5e2a9222016-06-26 22:38:24 -0400147 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400148
Clarence Ipaa0faf42016-05-30 12:07:48 -0400149 struct msm_property_info property_info;
150 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700151 struct drm_property_blob *blob_info;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800152 struct drm_property_blob *blob_rot_caps;
Clarence Ip730e7192016-06-26 22:45:09 -0400153
Clarence Ip4ce59322016-06-26 22:27:51 -0400154 /* debugfs related stuff */
155 struct dentry *debugfs_root;
156 struct sde_debugfs_regset32 debugfs_src;
157 struct sde_debugfs_regset32 debugfs_scaler;
158 struct sde_debugfs_regset32 debugfs_csc;
Clarence Ip716ab662017-03-20 06:51:24 -0700159 bool debugfs_default_scale;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700160};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700161
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700162#define to_sde_plane(x) container_of(x, struct sde_plane, base)
163
Alan Kwong4dd64c82017-02-04 18:41:51 -0800164static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
165{
166 struct msm_drm_private *priv;
167
168 if (!plane || !plane->dev)
169 return NULL;
170 priv = plane->dev->dev_private;
171 if (!priv)
172 return NULL;
173 return to_sde_kms(priv->kms);
174}
175
Alan Kwong4aacd532017-02-04 18:51:33 -0800176/**
177 * _sde_plane_get_crtc_state - obtain crtc state attached to given plane state
178 * @pstate: Pointer to drm plane state
179 * return: Pointer to crtc state if success; pointer error, otherwise
180 */
181static struct drm_crtc_state *_sde_plane_get_crtc_state(
182 struct drm_plane_state *pstate)
183{
184 struct drm_crtc_state *cstate;
185
186 if (!pstate || !pstate->crtc)
187 return NULL;
188
189 if (pstate->state)
190 cstate = drm_atomic_get_crtc_state(pstate->state, pstate->crtc);
191 else
192 cstate = pstate->crtc->state;
193
194 return cstate;
195}
196
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400197static bool sde_plane_enabled(struct drm_plane_state *state)
198{
Clarence Ipdbde9832016-06-26 09:48:36 -0400199 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400200}
201
Alan Kwong4dd64c82017-02-04 18:41:51 -0800202static bool sde_plane_sspp_enabled(struct drm_plane_state *state)
203{
204 return state && to_sde_plane_state(state)->rot.out_fb && state->crtc;
205}
206
207/**
208 * sde_plane_crtc_enabled - determine if crtc of given plane state is enabled
209 * @state: Pointer to drm plane state
210 * return: true if plane and the associated crtc are both enabled
211 */
212static bool sde_plane_crtc_enabled(struct drm_plane_state *state)
213{
214 return sde_plane_enabled(state) && state->crtc->state &&
215 state->crtc->state->active &&
216 state->crtc->state->enable;
217}
218
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400219/**
220 * _sde_plane_calc_fill_level - calculate fill level of the given source format
221 * @plane: Pointer to drm plane
222 * @fmt: Pointer to source buffer format
223 * @src_wdith: width of source buffer
224 * Return: fill level corresponding to the source buffer/format or 0 if error
225 */
226static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
227 const struct sde_format *fmt, u32 src_width)
228{
229 struct sde_plane *psde;
230 u32 fixed_buff_size;
231 u32 total_fl;
232
233 if (!plane || !fmt) {
234 SDE_ERROR("invalid arguments\n");
235 return 0;
236 }
237
238 psde = to_sde_plane(plane);
239 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
240
241 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
242 if (fmt->chroma_sample == SDE_CHROMA_420) {
243 /* NV12 */
244 total_fl = (fixed_buff_size / 2) /
245 ((src_width + 32) * fmt->bpp);
246 } else {
247 /* non NV12 */
248 total_fl = (fixed_buff_size) /
249 ((src_width + 32) * fmt->bpp);
250 }
251 } else {
252 total_fl = (fixed_buff_size * 2) /
253 ((src_width + 32) * fmt->bpp);
254 }
255
256 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
257 plane->base.id, psde->pipe - SSPP_VIG0,
258 fmt->base.pixel_format, src_width, total_fl);
259
260 return total_fl;
261}
262
263/**
264 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
265 * @total_fl: fill level
266 * Return: LUT setting corresponding to the fill level
267 */
268static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
269{
270 u32 qos_lut;
271
272 if (total_fl <= 4)
273 qos_lut = 0x1B;
274 else if (total_fl <= 5)
275 qos_lut = 0x5B;
276 else if (total_fl <= 6)
277 qos_lut = 0x15B;
278 else if (total_fl <= 7)
279 qos_lut = 0x55B;
280 else if (total_fl <= 8)
281 qos_lut = 0x155B;
282 else if (total_fl <= 9)
283 qos_lut = 0x555B;
284 else if (total_fl <= 10)
285 qos_lut = 0x1555B;
286 else if (total_fl <= 11)
287 qos_lut = 0x5555B;
288 else if (total_fl <= 12)
289 qos_lut = 0x15555B;
290 else
291 qos_lut = 0x55555B;
292
293 return qos_lut;
294}
295
296/**
297 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
298 * @total_fl: fill level
299 * Return: LUT setting corresponding to the fill level
300 */
301static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
302{
303 u32 qos_lut;
304
305 if (total_fl <= 10)
306 qos_lut = 0x1AAff;
307 else if (total_fl <= 11)
308 qos_lut = 0x5AAFF;
309 else if (total_fl <= 12)
310 qos_lut = 0x15AAFF;
311 else
312 qos_lut = 0x55AAFF;
313
314 return qos_lut;
315}
316
317/**
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400318 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
319 * @plane: Pointer to drm plane
320 * @fb: Pointer to framebuffer associated with the given plane
321 */
322static void _sde_plane_set_qos_lut(struct drm_plane *plane,
323 struct drm_framebuffer *fb)
324{
325 struct sde_plane *psde;
326 const struct sde_format *fmt = NULL;
327 u32 qos_lut;
328 u32 total_fl = 0;
329
330 if (!plane || !fb) {
331 SDE_ERROR("invalid arguments plane %d fb %d\n",
332 plane != 0, fb != 0);
333 return;
334 }
335
336 psde = to_sde_plane(plane);
337
338 if (!psde->pipe_hw || !psde->pipe_sblk) {
339 SDE_ERROR("invalid arguments\n");
340 return;
341 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
342 return;
343 }
344
345 if (!psde->is_rt_pipe) {
346 qos_lut = psde->pipe_sblk->creq_lut_nrt;
347 } else {
348 fmt = sde_get_sde_format_ext(
349 fb->pixel_format,
350 fb->modifier,
351 drm_format_num_planes(fb->pixel_format));
352 total_fl = _sde_plane_calc_fill_level(plane, fmt,
353 psde->pipe_cfg.src_rect.w);
354
355 if (SDE_FORMAT_IS_LINEAR(fmt))
356 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
357 else
358 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
359 }
360
361 psde->pipe_qos_cfg.creq_lut = qos_lut;
362
363 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
364 (fmt) ? fmt->base.pixel_format : 0,
365 psde->is_rt_pipe, total_fl, qos_lut,
366 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
367
368 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
369 plane->base.id,
370 psde->pipe - SSPP_VIG0,
371 (fmt) ? fmt->base.pixel_format : 0,
372 psde->is_rt_pipe, total_fl, qos_lut);
373
374 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
375}
376
377/**
378 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
379 * @plane: Pointer to drm plane
380 * @fb: Pointer to framebuffer associated with the given plane
381 */
382static void _sde_plane_set_danger_lut(struct drm_plane *plane,
383 struct drm_framebuffer *fb)
384{
385 struct sde_plane *psde;
386 const struct sde_format *fmt = NULL;
387 u32 danger_lut, safe_lut;
388
389 if (!plane || !fb) {
390 SDE_ERROR("invalid arguments\n");
391 return;
392 }
393
394 psde = to_sde_plane(plane);
395
396 if (!psde->pipe_hw || !psde->pipe_sblk) {
397 SDE_ERROR("invalid arguments\n");
398 return;
399 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
400 return;
401 }
402
403 if (!psde->is_rt_pipe) {
404 danger_lut = psde->pipe_sblk->danger_lut_nrt;
405 safe_lut = psde->pipe_sblk->safe_lut_nrt;
406 } else {
407 fmt = sde_get_sde_format_ext(
408 fb->pixel_format,
409 fb->modifier,
410 drm_format_num_planes(fb->pixel_format));
411
412 if (SDE_FORMAT_IS_LINEAR(fmt)) {
413 danger_lut = psde->pipe_sblk->danger_lut_linear;
414 safe_lut = psde->pipe_sblk->safe_lut_linear;
415 } else {
416 danger_lut = psde->pipe_sblk->danger_lut_tile;
417 safe_lut = psde->pipe_sblk->safe_lut_tile;
418 }
419 }
420
421 psde->pipe_qos_cfg.danger_lut = danger_lut;
422 psde->pipe_qos_cfg.safe_lut = safe_lut;
423
424 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
425 (fmt) ? fmt->base.pixel_format : 0,
426 (fmt) ? fmt->fetch_mode : 0,
427 psde->pipe_qos_cfg.danger_lut,
428 psde->pipe_qos_cfg.safe_lut);
429
430 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
431 plane->base.id,
432 psde->pipe - SSPP_VIG0,
433 fmt ? fmt->base.pixel_format : 0,
434 fmt ? fmt->fetch_mode : -1,
435 psde->pipe_qos_cfg.danger_lut,
436 psde->pipe_qos_cfg.safe_lut);
437
438 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
439 &psde->pipe_qos_cfg);
440}
441
442/**
443 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
444 * @plane: Pointer to drm plane
445 * @enable: true to enable QoS control
446 * @flags: QoS control mode (enum sde_plane_qos)
447 */
448static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
449 bool enable, u32 flags)
450{
451 struct sde_plane *psde;
452
453 if (!plane) {
454 SDE_ERROR("invalid arguments\n");
455 return;
456 }
457
458 psde = to_sde_plane(plane);
459
460 if (!psde->pipe_hw || !psde->pipe_sblk) {
461 SDE_ERROR("invalid arguments\n");
462 return;
463 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
464 return;
465 }
466
467 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
468 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
469 psde->pipe_qos_cfg.danger_vblank =
470 psde->pipe_sblk->danger_vblank;
471 psde->pipe_qos_cfg.vblank_en = enable;
472 }
473
474 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
475 /* this feature overrules previous VBLANK_CTRL */
476 psde->pipe_qos_cfg.vblank_en = false;
477 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
478 }
479
480 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
481 psde->pipe_qos_cfg.danger_safe_en = enable;
482
483 if (!psde->is_rt_pipe) {
484 psde->pipe_qos_cfg.vblank_en = false;
485 psde->pipe_qos_cfg.danger_safe_en = false;
486 }
487
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400488 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400489 plane->base.id,
490 psde->pipe - SSPP_VIG0,
491 psde->pipe_qos_cfg.danger_safe_en,
492 psde->pipe_qos_cfg.vblank_en,
493 psde->pipe_qos_cfg.creq_vblank,
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400494 psde->pipe_qos_cfg.danger_vblank,
495 psde->is_rt_pipe);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400496
497 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
498 &psde->pipe_qos_cfg);
499}
500
Alan Kwongf0fd8512016-10-24 21:39:26 -0400501int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
502{
503 struct sde_plane *psde;
504 struct msm_drm_private *priv;
505 struct sde_kms *sde_kms;
506
507 if (!plane || !plane->dev) {
508 SDE_ERROR("invalid arguments\n");
509 return -EINVAL;
510 }
511
512 priv = plane->dev->dev_private;
513 if (!priv || !priv->kms) {
514 SDE_ERROR("invalid KMS reference\n");
515 return -EINVAL;
516 }
517
518 sde_kms = to_sde_kms(priv->kms);
519 psde = to_sde_plane(plane);
520
521 if (!psde->is_rt_pipe)
522 goto end;
523
524 sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
525
526 _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
527
528 sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
529
530end:
531 return 0;
532}
533
Alan Kwong5d324e42016-07-28 22:56:18 -0400534/**
535 * _sde_plane_set_ot_limit - set OT limit for the given plane
536 * @plane: Pointer to drm plane
537 * @crtc: Pointer to drm crtc
538 */
539static void _sde_plane_set_ot_limit(struct drm_plane *plane,
540 struct drm_crtc *crtc)
541{
542 struct sde_plane *psde;
543 struct sde_vbif_set_ot_params ot_params;
544 struct msm_drm_private *priv;
545 struct sde_kms *sde_kms;
546
547 if (!plane || !plane->dev || !crtc) {
548 SDE_ERROR("invalid arguments plane %d crtc %d\n",
549 plane != 0, crtc != 0);
550 return;
551 }
552
553 priv = plane->dev->dev_private;
554 if (!priv || !priv->kms) {
555 SDE_ERROR("invalid KMS reference\n");
556 return;
557 }
558
559 sde_kms = to_sde_kms(priv->kms);
560 psde = to_sde_plane(plane);
561 if (!psde->pipe_hw) {
562 SDE_ERROR("invalid pipe reference\n");
563 return;
564 }
565
566 memset(&ot_params, 0, sizeof(ot_params));
567 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
568 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
569 ot_params.width = psde->pipe_cfg.src_rect.w;
570 ot_params.height = psde->pipe_cfg.src_rect.h;
571 ot_params.is_wfd = !psde->is_rt_pipe;
572 ot_params.frame_rate = crtc->mode.vrefresh;
573 ot_params.vbif_idx = VBIF_RT;
574 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
575 ot_params.rd = true;
576
577 sde_vbif_set_ot_limit(sde_kms, &ot_params);
578}
579
Clarence Ipcae1bb62016-07-07 12:07:13 -0400580/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400581static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400582 struct sde_plane_state *pstate, uint64_t fd)
583{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400584 if (!psde || !pstate) {
585 SDE_ERROR("invalid arg(s), plane %d state %d\n",
586 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400587 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400588 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400589
590 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400591 if (pstate->input_fence)
592 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400593
594 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400595 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400596
Clarence Ip13a8cf42016-09-29 17:27:47 -0400597 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400598}
599
Clarence Ipcae1bb62016-07-07 12:07:13 -0400600int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400601{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400602 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400603 struct sde_plane_state *pstate;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400604 uint32_t prefix;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400605 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400606 int ret = -EINVAL;
Dhaval Patel39323d42017-03-01 23:48:24 -0800607 signed long rc;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400608
609 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700610 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400611 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400612 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400613 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400614 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400615 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400616 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400617
Clarence Ipcae1bb62016-07-07 12:07:13 -0400618 if (input_fence) {
Dhaval Patel39323d42017-03-01 23:48:24 -0800619 psde->is_error = false;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400620 prefix = sde_sync_get_name_prefix(input_fence);
Dhaval Patel39323d42017-03-01 23:48:24 -0800621 rc = sde_sync_wait(input_fence, wait_ms);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400622
Lloyd Atkinson5d40d312016-09-06 08:34:13 -0400623 SDE_EVT32(DRMID(plane), -ret, prefix);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400624
Dhaval Patel39323d42017-03-01 23:48:24 -0800625 switch (rc) {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400626 case 0:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400627 SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
628 wait_ms, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400629 psde->is_error = true;
Dhaval Patel39323d42017-03-01 23:48:24 -0800630 ret = -ETIMEDOUT;
631 break;
632 case -ERESTARTSYS:
633 SDE_ERROR_PLANE(psde,
634 "%ums wait interrupted on %08X\n",
635 wait_ms, prefix);
636 psde->is_error = true;
637 ret = -ERESTARTSYS;
638 break;
639 case -EINVAL:
640 SDE_ERROR_PLANE(psde,
641 "invalid fence param for %08X\n",
642 prefix);
643 psde->is_error = true;
644 ret = -EINVAL;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400645 break;
646 default:
Dhaval Patel39323d42017-03-01 23:48:24 -0800647 SDE_DEBUG_PLANE(psde, "signaled\n");
648 ret = 0;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400649 break;
650 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400651 } else {
652 ret = 0;
653 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400654 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400655 return ret;
656}
657
Clarence Ip282dad62016-09-27 17:07:35 -0400658static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400659 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400660 struct sde_hw_pipe_cfg *pipe_cfg,
661 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400662{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400663 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400664 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400665
Clarence Ip13a8cf42016-09-29 17:27:47 -0400666 if (!plane || !pstate || !pipe_cfg || !fb) {
667 SDE_ERROR(
668 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
669 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400670 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400671 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400672
673 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400674 if (!psde->pipe_hw) {
675 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400676 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400677 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400678
Clarence Ipb6eb2362016-09-08 16:18:13 -0400679 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
680 if (ret == -EAGAIN)
681 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
682 else if (ret)
683 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
684 else if (psde->pipe_hw->ops.setup_sourceaddress)
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800685 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
686 pstate->multirect_index);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400687}
688
abeykun48f407a2016-08-25 12:06:44 -0400689static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
690 struct sde_plane_state *pstate)
691{
Clarence Ip3bf8d872017-02-16 15:25:38 -0500692 struct sde_hw_scaler3_cfg *cfg;
abeykun48f407a2016-08-25 12:06:44 -0400693 int ret = 0;
694
Clarence Ip3bf8d872017-02-16 15:25:38 -0500695 if (!psde || !psde->scaler3_cfg) {
696 SDE_ERROR("invalid args\n");
697 return -EINVAL;
698 } else if (!pstate) {
699 /* pstate is expected to be null on forced color fill */
700 SDE_DEBUG("null pstate\n");
701 return -EINVAL;
702 }
703
704 cfg = psde->scaler3_cfg;
705
abeykun48f407a2016-08-25 12:06:44 -0400706 cfg->dir_lut = msm_property_get_blob(
707 &psde->property_info,
708 pstate->property_blobs, &cfg->dir_len,
709 PLANE_PROP_SCALER_LUT_ED);
710 cfg->cir_lut = msm_property_get_blob(
711 &psde->property_info,
712 pstate->property_blobs, &cfg->cir_len,
713 PLANE_PROP_SCALER_LUT_CIR);
714 cfg->sep_lut = msm_property_get_blob(
715 &psde->property_info,
716 pstate->property_blobs, &cfg->sep_len,
717 PLANE_PROP_SCALER_LUT_SEP);
718 if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
719 ret = -ENODATA;
720 return ret;
721}
722
Clarence Ipcb410d42016-06-26 22:52:33 -0400723static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400724 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
725 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400726 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400727 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
728{
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -0700729 uint32_t decimated, i;
730
731 if (!psde || !scale_cfg || !fmt || !chroma_subsmpl_h ||
732 !chroma_subsmpl_v) {
733 SDE_ERROR("psde %pK scale_cfg %pK fmt %pK smp_h %d smp_v %d\n"
734 , psde, scale_cfg, fmt, chroma_subsmpl_h,
735 chroma_subsmpl_v);
736 return;
737 }
738
739 memset(scale_cfg, 0, sizeof(*scale_cfg));
Clarence Ip716ab662017-03-20 06:51:24 -0700740 memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -0700741
742 decimated = DECIMATED_DIMENSION(src_w,
743 psde->pipe_cfg.horz_decimation);
744 scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
745 mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
746 decimated = DECIMATED_DIMENSION(src_h,
747 psde->pipe_cfg.vert_decimation);
748 scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
749 mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
750
751
752 scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
753 scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
754 scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
755 scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
756
757 scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
758 scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
759 scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
760 scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
761
762 scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
763 scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
764 scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
765 scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
766
767 for (i = 0; i < SDE_MAX_PLANES; i++) {
768 scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
769 psde->pipe_cfg.horz_decimation);
770 scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h,
771 psde->pipe_cfg.vert_decimation);
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -0700772 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
773 scale_cfg->src_width[i] /= chroma_subsmpl_h;
774 scale_cfg->src_height[i] /= chroma_subsmpl_v;
775 }
776 scale_cfg->preload_x[i] = SDE_QSEED3_DEFAULT_PRELOAD_H;
777 scale_cfg->preload_y[i] = SDE_QSEED3_DEFAULT_PRELOAD_V;
778 psde->pixel_ext.num_ext_pxls_top[i] =
779 scale_cfg->src_height[i];
780 psde->pixel_ext.num_ext_pxls_left[i] =
781 scale_cfg->src_width[i];
782 }
783 if (!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
784 && (src_w == dst_w))
785 return;
786
787 scale_cfg->dst_width = dst_w;
788 scale_cfg->dst_height = dst_h;
789 scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
790 scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
791 scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
792 scale_cfg->lut_flag = 0;
793 scale_cfg->blend_cfg = 1;
794 scale_cfg->enable = 1;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400795}
796
Clarence Ipcb410d42016-06-26 22:52:33 -0400797/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400798 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400799 * @psde: Pointer to SDE plane object
800 * @src: Source size
801 * @dst: Destination size
802 * @phase_steps: Pointer to output array for phase steps
803 * @filter: Pointer to output array for filter type
804 * @fmt: Pointer to format definition
805 * @chroma_subsampling: Subsampling amount for chroma channel
806 *
807 * Returns: 0 on success
808 */
809static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400810 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400811 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400812 uint32_t chroma_subsampling)
813{
Clarence Ipcb410d42016-06-26 22:52:33 -0400814 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400815 SDE_ERROR(
816 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
817 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400818 return -EINVAL;
819 }
820
Clarence Ip4c1d9772016-06-26 09:35:38 -0400821 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400822 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400823 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400824 phase_steps[SDE_SSPP_COMP_1_2] =
825 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
826 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
827 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400828
829 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400830 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400831 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400832 (src <= dst) ? SDE_SCALE_FILTER_BIL :
833 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400834
Clarence Ipdbde9832016-06-26 09:48:36 -0400835 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400836 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400837 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
838 } else {
839 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
840 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400841 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400842 }
843 } else {
844 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400845 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
846 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
847 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400848 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400849 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400850}
851
Clarence Ipcb410d42016-06-26 22:52:33 -0400852/**
853 * _sde_plane_setup_pixel_ext - determine default pixel extension values
854 * @psde: Pointer to SDE plane object
855 * @src: Source size
856 * @dst: Destination size
857 * @decimated_src: Source size after decimation, if any
858 * @phase_steps: Pointer to output array for phase steps
859 * @out_src: Output array for pixel extension values
860 * @out_edge1: Output array for pixel extension first edge
861 * @out_edge2: Output array for pixel extension second edge
862 * @filter: Pointer to array for filter type
863 * @fmt: Pointer to format definition
864 * @chroma_subsampling: Subsampling amount for chroma channel
865 * @post_compare: Whether to chroma subsampled source size for comparisions
866 */
867static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400868 uint32_t src, uint32_t dst, uint32_t decimated_src,
869 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400870 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400871 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400872 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400873{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400874 int64_t edge1, edge2, caf;
875 uint32_t src_work;
876 int i, tmp;
877
Clarence Ipcb410d42016-06-26 22:52:33 -0400878 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400879 out_edge2 && filter && fmt) {
880 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400881 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400882 caf = PHASE_STEP_UNIT_SCALE;
883 else
884 caf = 0;
885
886 for (i = 0; i < SDE_MAX_PLANES; i++) {
887 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400888 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400889 src_work /= chroma_subsampling;
890 if (post_compare)
891 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400892 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400893 /* unity */
894 edge1 = 0;
895 edge2 = 0;
896 } else if (dst >= src) {
897 /* upscale */
898 edge1 = (1 << PHASE_RESIDUAL);
899 edge1 -= caf;
900 edge2 = (1 << PHASE_RESIDUAL);
901 edge2 += (dst - 1) * *(phase_steps + i);
902 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
903 edge2 += caf;
904 edge2 = -(edge2);
905 } else {
906 /* downscale */
907 edge1 = 0;
908 edge2 = (dst - 1) * *(phase_steps + i);
909 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
910 edge2 += *(phase_steps + i);
911 edge2 = -(edge2);
912 }
913
914 /* only enable CAF for luma plane */
915 caf = 0;
916
917 /* populate output arrays */
918 *(out_src + i) = src_work;
919
920 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400921 if (edge1 >= 0) {
922 tmp = (uint32_t)edge1;
923 tmp >>= PHASE_STEP_SHIFT;
924 *(out_edge1 + i) = -tmp;
925 } else {
926 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400927 *(out_edge1 + i) =
928 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
929 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400930 }
931 if (edge2 >= 0) {
932 tmp = (uint32_t)edge2;
933 tmp >>= PHASE_STEP_SHIFT;
934 *(out_edge2 + i) = -tmp;
935 } else {
936 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400937 *(out_edge2 + i) =
938 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
939 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400940 }
941 }
942 }
943}
944
Clarence Ip5fc00c52016-09-23 15:03:34 -0400945static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400946{
947 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
948 {
Clarence Ip373f8592016-05-26 00:58:42 -0400949 /* S15.16 format */
950 0x00012A00, 0x00000000, 0x00019880,
951 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
952 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400953 },
Clarence Ip373f8592016-05-26 00:58:42 -0400954 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400955 { 0xfff0, 0xff80, 0xff80,},
956 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400957 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400958 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400959 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400960 };
abeykun1c312f62016-08-26 09:47:12 -0400961 static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
962 {
963 /* S15.16 format */
964 0x00012A00, 0x00000000, 0x00019880,
965 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
966 0x00012A00, 0x00020480, 0x00000000,
967 },
968 /* signed bias */
969 { 0xffc0, 0xfe00, 0xfe00,},
970 { 0x0, 0x0, 0x0,},
971 /* unsigned clamp */
972 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
973 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
974 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400975
Clarence Ip5fc00c52016-09-23 15:03:34 -0400976 if (!psde) {
977 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400978 return;
979 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400980
Clarence Ipcae1bb62016-07-07 12:07:13 -0400981 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400982 if (psde->csc_usr_ptr)
983 psde->csc_ptr = psde->csc_usr_ptr;
abeykun1c312f62016-08-26 09:47:12 -0400984 else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
985 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400986 else
Clarence Ip373f8592016-05-26 00:58:42 -0400987 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400988
Clarence Ip13a8cf42016-09-29 17:27:47 -0400989 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400990 psde->csc_ptr->csc_mv[0],
991 psde->csc_ptr->csc_mv[1],
992 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400993}
994
Benet Clarkeb1b4462016-06-27 14:43:06 -0700995static void sde_color_process_plane_setup(struct drm_plane *plane)
996{
997 struct sde_plane *psde;
998 struct sde_plane_state *pstate;
999 uint32_t hue, saturation, value, contrast;
Benet Clarkd009b1d2016-06-27 14:45:59 -07001000 struct drm_msm_memcol *memcol = NULL;
1001 size_t memcol_sz = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -07001002
1003 psde = to_sde_plane(plane);
1004 pstate = to_sde_plane_state(plane->state);
1005
1006 hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
1007 if (psde->pipe_hw->ops.setup_pa_hue)
1008 psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
1009 saturation = (uint32_t) sde_plane_get_property(pstate,
1010 PLANE_PROP_SATURATION_ADJUST);
1011 if (psde->pipe_hw->ops.setup_pa_sat)
1012 psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
1013 value = (uint32_t) sde_plane_get_property(pstate,
1014 PLANE_PROP_VALUE_ADJUST);
1015 if (psde->pipe_hw->ops.setup_pa_val)
1016 psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
1017 contrast = (uint32_t) sde_plane_get_property(pstate,
1018 PLANE_PROP_CONTRAST_ADJUST);
1019 if (psde->pipe_hw->ops.setup_pa_cont)
1020 psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
Benet Clarkeb1b4462016-06-27 14:43:06 -07001021
Benet Clarkd009b1d2016-06-27 14:45:59 -07001022 if (psde->pipe_hw->ops.setup_pa_memcolor) {
1023 /* Skin memory color setup */
1024 memcol = msm_property_get_blob(&psde->property_info,
1025 pstate->property_blobs,
1026 &memcol_sz,
1027 PLANE_PROP_SKIN_COLOR);
1028 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
1029 MEMCOLOR_SKIN, memcol);
1030
1031 /* Sky memory color setup */
1032 memcol = msm_property_get_blob(&psde->property_info,
1033 pstate->property_blobs,
1034 &memcol_sz,
1035 PLANE_PROP_SKY_COLOR);
1036 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
1037 MEMCOLOR_SKY, memcol);
1038
1039 /* Foliage memory color setup */
1040 memcol = msm_property_get_blob(&psde->property_info,
1041 pstate->property_blobs,
1042 &memcol_sz,
1043 PLANE_PROP_FOLIAGE_COLOR);
1044 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
1045 MEMCOLOR_FOLIAGE, memcol);
1046 }
1047}
Benet Clarkeb1b4462016-06-27 14:43:06 -07001048
Clarence Ipcb410d42016-06-26 22:52:33 -04001049static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001050 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -04001051 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001052{
Clarence Ipb43d4592016-09-08 14:21:35 -04001053 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -04001054 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001055
Clarence Ipb43d4592016-09-08 14:21:35 -04001056 if (!psde || !fmt) {
1057 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
1058 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -04001059 return;
Clarence Ipb43d4592016-09-08 14:21:35 -04001060 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001061
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001062 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001063
Clarence Ipdedbba92016-09-27 17:43:10 -04001064 psde->pipe_cfg.horz_decimation =
1065 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1066 psde->pipe_cfg.vert_decimation =
1067 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -04001068
1069 /* don't chroma subsample if decimating */
1070 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001071 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -04001072 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001073 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -04001074
Clarence Ip5e2a9222016-06-26 22:38:24 -04001075 /* update scaler */
1076 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
abeykun48f407a2016-08-25 12:06:44 -04001077 int error;
1078
1079 error = _sde_plane_setup_scaler3_lut(psde, pstate);
Clarence Ip716ab662017-03-20 06:51:24 -07001080 if (error || !psde->pixel_ext_usr ||
1081 psde->debugfs_default_scale) {
Clarence Ipb43d4592016-09-08 14:21:35 -04001082 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -04001083 _sde_plane_setup_scaler3(psde,
1084 psde->pipe_cfg.src_rect.w,
1085 psde->pipe_cfg.src_rect.h,
1086 psde->pipe_cfg.dst_rect.w,
1087 psde->pipe_cfg.dst_rect.h,
abeykun48f407a2016-08-25 12:06:44 -04001088 psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001089 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001090 }
Clarence Ip716ab662017-03-20 06:51:24 -07001091 } else if (!psde->pixel_ext_usr || !pstate ||
1092 psde->debugfs_default_scale) {
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001093 uint32_t deci_dim, i;
1094
Clarence Ipb43d4592016-09-08 14:21:35 -04001095 /* calculate default configuration for QSEED2 */
1096 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001097
Clarence Ip13a8cf42016-09-29 17:27:47 -04001098 SDE_DEBUG_PLANE(psde, "default config\n");
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001099 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
1100 psde->pipe_cfg.horz_decimation);
Clarence Ipb43d4592016-09-08 14:21:35 -04001101 _sde_plane_setup_scaler2(psde,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001102 deci_dim,
Clarence Ipb43d4592016-09-08 14:21:35 -04001103 psde->pipe_cfg.dst_rect.w,
1104 pe->phase_step_x,
1105 pe->horz_filter, fmt, chroma_subsmpl_h);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001106
Clarence Ipdbde9832016-06-26 09:48:36 -04001107 if (SDE_FORMAT_IS_YUV(fmt))
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001108 deci_dim &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -04001109 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001110 psde->pipe_cfg.dst_rect.w, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001111 pe->phase_step_x,
1112 pe->roi_w,
1113 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -04001114 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001115 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001116
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001117 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001118 psde->pipe_cfg.vert_decimation);
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001119 _sde_plane_setup_scaler2(psde,
1120 deci_dim,
1121 psde->pipe_cfg.dst_rect.h,
1122 pe->phase_step_y,
1123 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ipcb410d42016-06-26 22:52:33 -04001124 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001125 psde->pipe_cfg.dst_rect.h, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001126 pe->phase_step_y,
1127 pe->roi_h,
1128 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -04001129 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001130 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001131
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001132 for (i = 0; i < SDE_MAX_PLANES; i++) {
1133 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001134 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001135 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001136 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001137
1138 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001139 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001140 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001141 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001142
1143 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001144 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001145 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001146 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001147
1148 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001149 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001150 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001151 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001152 }
1153 }
Clarence Ipcb410d42016-06-26 22:52:33 -04001154}
1155
Clarence Ipcae1bb62016-07-07 12:07:13 -04001156/**
1157 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -04001158 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -04001159 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
1160 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
1161 * Returns: 0 on success
1162 */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001163static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -04001164 uint32_t color, uint32_t alpha)
1165{
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001166 const struct sde_format *fmt;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001167 const struct drm_plane *plane;
1168 const struct sde_plane_state *pstate;
Clarence Ipcb410d42016-06-26 22:52:33 -04001169
Clarence Ip13a8cf42016-09-29 17:27:47 -04001170 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001171 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001172 return -EINVAL;
1173 }
1174
Clarence Ipcb410d42016-06-26 22:52:33 -04001175 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001176 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001177 return -EINVAL;
1178 }
1179
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001180 plane = &psde->base;
1181 pstate = to_sde_plane_state(plane->state);
1182
Clarence Ip13a8cf42016-09-29 17:27:47 -04001183 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001184
Clarence Ipcb410d42016-06-26 22:52:33 -04001185 /*
1186 * select fill format to match user property expectation,
1187 * h/w only supports RGB variants
1188 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001189 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -04001190
1191 /* update sspp */
1192 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
1193 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001194 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
1195 pstate->multirect_index);
Clarence Ipcb410d42016-06-26 22:52:33 -04001196
1197 /* override scaler/decimation if solid fill */
1198 psde->pipe_cfg.src_rect.x = 0;
1199 psde->pipe_cfg.src_rect.y = 0;
1200 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
1201 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
Dhaval Patele4b6bb22017-03-27 17:22:21 -07001202 _sde_plane_setup_scaler(psde, fmt, 0);
Clarence Ipcb410d42016-06-26 22:52:33 -04001203
Clarence Ipcb410d42016-06-26 22:52:33 -04001204 if (psde->pipe_hw->ops.setup_format)
1205 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001206 fmt, SDE_SSPP_SOLID_FILL,
1207 pstate->multirect_index);
Clarence Ipcb410d42016-06-26 22:52:33 -04001208
1209 if (psde->pipe_hw->ops.setup_rects)
1210 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08001211 &psde->pipe_cfg,
1212 pstate->multirect_index);
1213
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08001214 if (psde->pipe_hw->ops.setup_pe)
1215 psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
1216 &psde->pixel_ext);
Clarence Ipcb410d42016-06-26 22:52:33 -04001217 }
1218
1219 return 0;
1220}
1221
Alan Kwong4dd64c82017-02-04 18:41:51 -08001222/**
Alan Kwongcdb2f282017-03-18 13:42:06 -07001223 * _sde_plane_fb_get/put - framebuffer callback for crtc res ops
1224 */
1225static void *_sde_plane_fb_get(void *fb, u32 type, u64 tag)
1226{
1227 drm_framebuffer_reference(fb);
1228 return fb;
1229}
1230static void _sde_plane_fb_put(void *fb)
1231{
1232 drm_framebuffer_unreference(fb);
1233}
1234static struct sde_crtc_res_ops fb_res_ops = {
1235 .put = _sde_plane_fb_put,
1236 .get = _sde_plane_fb_get,
1237};
1238
1239/**
1240 * _sde_plane_fbo_get/put - framebuffer object callback for crtc res ops
1241 */
1242static void *_sde_plane_fbo_get(void *fbo, u32 type, u64 tag)
1243{
1244 sde_kms_fbo_reference(fbo);
1245 return fbo;
1246}
1247static void _sde_plane_fbo_put(void *fbo)
1248{
1249 sde_kms_fbo_unreference(fbo);
1250}
1251static struct sde_crtc_res_ops fbo_res_ops = {
1252 .put = _sde_plane_fbo_put,
1253 .get = _sde_plane_fbo_get,
1254};
1255
1256/**
Alan Kwong4aacd532017-02-04 18:51:33 -08001257 * sde_plane_rot_calc_prefill - calculate rotator start prefill
Alan Kwong4dd64c82017-02-04 18:41:51 -08001258 * @plane: Pointer to drm plane
1259 * return: prefill time in line
1260 */
1261static u32 sde_plane_rot_calc_prefill(struct drm_plane *plane)
1262{
1263 struct drm_plane_state *state;
1264 struct drm_crtc_state *cstate;
1265 struct sde_plane_state *pstate;
1266 struct sde_plane_rot_state *rstate;
1267 struct sde_kms *sde_kms;
1268 u32 blocksize = 128;
1269 u32 prefill_line = 0;
1270
1271 if (!plane || !plane->state || !plane->state->fb ||
1272 !plane->state->crtc || !plane->state->crtc->state) {
1273 SDE_ERROR("invalid parameters\n");
1274 return 0;
1275 }
1276
1277 sde_kms = _sde_plane_get_kms(plane);
1278 state = plane->state;
1279 cstate = state->crtc->state;
1280 pstate = to_sde_plane_state(state);
1281 rstate = &pstate->rot;
1282
1283 if (!rstate->rot_hw || !rstate->rot_hw->caps || !rstate->out_src_h ||
1284 !sde_kms || !sde_kms->catalog) {
1285 SDE_ERROR("invalid parameters\n");
1286 return 0;
1287 }
1288
Alan Kwong4aacd532017-02-04 18:51:33 -08001289 sde_format_get_block_size(rstate->out_fb_format, &blocksize,
1290 &blocksize);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001291 prefill_line = blocksize + sde_kms->catalog->sbuf_headroom;
1292
1293 SDE_DEBUG("plane%d prefill:%u\n", plane->base.id, prefill_line);
1294
1295 return prefill_line;
1296}
1297
1298/**
1299 * sde_plane_is_sbuf_mode - check if sspp of given plane is in streaming
1300 * buffer mode
1301 * @plane: Pointer to drm plane
1302 * @prefill: Pointer to prefill line count
1303 * return: true if sspp is in stream buffer mode
1304 */
1305bool sde_plane_is_sbuf_mode(struct drm_plane *plane, u32 *prefill)
1306{
1307 struct sde_plane_state *pstate = plane && plane->state ?
1308 to_sde_plane_state(plane->state) : NULL;
1309 struct sde_plane_rot_state *rstate = pstate ? &pstate->rot : NULL;
1310 bool sbuf_mode = rstate ? rstate->out_sbuf : false;
1311
1312 if (prefill && sbuf_mode)
1313 *prefill = sde_plane_rot_calc_prefill(plane);
1314
1315 return sbuf_mode;
1316}
1317
1318/**
1319 * sde_plane_rot_calc_cfg - calculate rotator/sspp configuration by
1320 * enumerating over all planes attached to the same rotator
1321 * @plane: Pointer to drm plane
1322 * @state: Pointer to drm state to be updated
1323 * return: none
1324 */
1325static void sde_plane_rot_calc_cfg(struct drm_plane *plane,
1326 struct drm_plane_state *state)
1327{
1328 struct sde_plane_state *pstate;
1329 struct sde_plane_rot_state *rstate;
1330 struct sde_hw_blk *hw_blk;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001331 struct drm_crtc_state *cstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001332 struct drm_rect *in_rot, *out_rot;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001333 struct drm_plane *attached_plane;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001334 u32 dst_x, dst_y, dst_w, dst_h;
1335 int found = 0;
1336 int xpos = 0;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001337 int ret;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001338
1339 if (!plane || !state || !state->state) {
1340 SDE_ERROR("invalid parameters\n");
1341 return;
1342 }
1343
Alan Kwongcdb2f282017-03-18 13:42:06 -07001344 cstate = _sde_plane_get_crtc_state(state);
1345 if (IS_ERR_OR_NULL(cstate)) {
1346 ret = PTR_ERR(cstate);
1347 SDE_ERROR("invalid crtc state %d\n", ret);
1348 return;
1349 }
1350
Alan Kwong4dd64c82017-02-04 18:41:51 -08001351 pstate = to_sde_plane_state(state);
1352 rstate = &pstate->rot;
1353
1354 if (!rstate->rot_hw) {
1355 SDE_ERROR("invalid rotator hw\n");
1356 return;
1357 }
1358
1359 in_rot = &rstate->in_rot_rect;
1360 in_rot->x1 = state->src_x;
1361 in_rot->y1 = state->src_y;
1362 in_rot->x2 = state->src_x + state->src_w;
1363 in_rot->y2 = state->src_y + state->src_h;
1364
1365 out_rot = &rstate->out_rot_rect;
1366 dst_x = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_X);
1367 dst_y = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_Y);
1368 dst_w = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_W);
1369 dst_h = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_H);
1370
1371 if (!dst_w && !dst_h) {
1372 rstate->out_rot_rect = rstate->in_rot_rect;
1373 drm_rect_rotate(&rstate->out_rot_rect, state->fb->width << 16,
1374 state->fb->height << 16, rstate->in_rotation);
1375 } else {
1376 out_rot->x1 = dst_x;
1377 out_rot->y1 = dst_y;
1378 out_rot->x2 = dst_x + dst_w;
1379 out_rot->y2 = dst_y + dst_h;
1380 }
1381
1382 rstate->out_src_rect = rstate->out_rot_rect;
1383
1384 hw_blk = &rstate->rot_hw->base;
1385
1386 /* enumerating over all planes attached to the same rotator */
Alan Kwongcdb2f282017-03-18 13:42:06 -07001387 drm_atomic_crtc_state_for_each_plane(attached_plane, cstate) {
Alan Kwong4dd64c82017-02-04 18:41:51 -08001388 struct drm_plane_state *attached_state;
1389 struct sde_plane_state *attached_pstate;
1390 struct sde_plane_rot_state *attached_rstate;
1391 struct drm_rect attached_out_rect;
1392
Alan Kwong4dd64c82017-02-04 18:41:51 -08001393 attached_state = drm_atomic_get_existing_plane_state(
1394 state->state, attached_plane);
1395
1396 if (!attached_state)
1397 continue;
1398
1399 attached_pstate = to_sde_plane_state(attached_state);
1400 attached_rstate = &attached_pstate->rot;
1401
Alan Kwongcdb2f282017-03-18 13:42:06 -07001402 if (attached_rstate->rot_hw != rstate->rot_hw)
1403 continue;
1404
1405 found++;
1406
1407 /* skip itself */
1408 if (attached_plane == plane)
1409 continue;
1410
Alan Kwong4dd64c82017-02-04 18:41:51 -08001411 /* find bounding rotator source roi */
1412 if (attached_state->src_x < in_rot->x1)
1413 in_rot->x1 = attached_state->src_x;
1414
1415 if (attached_state->src_y < in_rot->y1)
1416 in_rot->y1 = attached_state->src_y;
1417
1418 if (attached_state->src_x + attached_state->src_w > in_rot->x2)
1419 in_rot->x2 = attached_state->src_x +
1420 attached_state->src_w;
1421
1422 if (attached_state->src_y + attached_state->src_h > in_rot->y2)
1423 in_rot->y2 = attached_state->src_y +
1424 attached_state->src_h;
1425
1426 /* find bounding rotator destination roi */
1427 dst_x = sde_plane_get_property(attached_pstate,
1428 PLANE_PROP_ROT_DST_X);
1429 dst_y = sde_plane_get_property(attached_pstate,
1430 PLANE_PROP_ROT_DST_Y);
1431 dst_w = sde_plane_get_property(attached_pstate,
1432 PLANE_PROP_ROT_DST_W);
1433 dst_h = sde_plane_get_property(attached_pstate,
1434 PLANE_PROP_ROT_DST_H);
1435 if (!dst_w && !dst_h) {
1436 attached_out_rect.x1 = attached_state->src_x;
1437 attached_out_rect.y1 = attached_state->src_y;
1438 attached_out_rect.x2 = attached_out_rect.x1 +
1439 attached_state->src_w;
1440 attached_out_rect.y2 = attached_out_rect.y1 +
1441 attached_state->src_h;
1442 drm_rect_rotate(&attached_out_rect,
1443 state->fb->width << 16,
1444 state->fb->height << 16,
1445 rstate->in_rotation);
1446 } else {
1447 attached_out_rect.x1 = dst_x;
1448 attached_out_rect.y1 = dst_y;
1449 attached_out_rect.x2 = dst_x + dst_w;
1450 attached_out_rect.y2 = dst_y + dst_h;
1451 }
1452
1453 /* find relative sspp position */
1454 if (attached_out_rect.x1 < rstate->out_src_rect.x1)
1455 xpos++;
1456
1457 if (attached_out_rect.x1 < out_rot->x1)
1458 out_rot->x1 = attached_out_rect.x1;
1459
1460 if (attached_out_rect.y1 < out_rot->y1)
1461 out_rot->y1 = attached_out_rect.y1;
1462
1463 if (attached_out_rect.x2 > out_rot->x2)
1464 out_rot->x2 = attached_out_rect.x2;
1465
1466 if (attached_out_rect.y2 > out_rot->y2)
1467 out_rot->y2 = attached_out_rect.y2;
1468
1469 SDE_DEBUG("plane%d.%u src_x:%d sspp:%dx%d+%d+%d/%dx%d+%d+%d\n",
1470 attached_plane->base.id,
1471 attached_rstate->sequence_id,
1472 attached_rstate->out_src_rect.x1 >> 16,
1473 attached_state->src_w >> 16,
1474 attached_state->src_h >> 16,
1475 attached_state->src_x >> 16,
1476 attached_state->src_y >> 16,
1477 drm_rect_width(&attached_rstate->out_src_rect) >> 16,
1478 drm_rect_height(&attached_rstate->out_src_rect) >> 16,
1479 attached_rstate->out_src_rect.x1 >> 16,
1480 attached_rstate->out_src_rect.y1 >> 16);
1481 }
1482
1483 rstate->out_xpos = xpos;
1484 rstate->nplane = found;
1485
1486 SDE_DEBUG("plane%d.%u xpos:%d/%d rot:%dx%d+%d+%d/%dx%d+%d+%d\n",
1487 plane->base.id, rstate->sequence_id,
1488 rstate->out_xpos, rstate->nplane,
1489 drm_rect_width(in_rot) >> 16,
1490 drm_rect_height(in_rot) >> 16,
1491 in_rot->x1 >> 16, in_rot->y1 >> 16,
1492 drm_rect_width(&rstate->out_rot_rect) >> 16,
1493 drm_rect_height(&rstate->out_rot_rect) >> 16,
1494 rstate->out_rot_rect.x1 >> 16,
1495 rstate->out_rot_rect.y1 >> 16);
1496}
1497
1498/**
1499 * sde_plane_rot_submit_command - commit given state for the rotator stage
1500 * @plane: Pointer to drm plane
1501 * @state: Pointer to the state to be committed
1502 * @hw_cmd: rotator command type
1503 * return: 0 if success; error code otherwise
1504 */
1505static int sde_plane_rot_submit_command(struct drm_plane *plane,
1506 struct drm_plane_state *state, enum sde_hw_rot_cmd_type hw_cmd)
1507{
1508 struct sde_plane *psde = to_sde_plane(plane);
1509 struct sde_plane_state *pstate = to_sde_plane_state(state);
1510 struct sde_plane_rot_state *rstate = &pstate->rot;
1511 struct sde_hw_rot_cmd *rot_cmd;
Alan Kwong4aacd532017-02-04 18:51:33 -08001512 struct drm_crtc_state *cstate;
1513 struct sde_crtc_state *sde_cstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001514 int ret, i;
1515
1516 if (!plane || !state || !state->fb || !rstate->rot_hw) {
1517 SDE_ERROR("invalid parameters\n");
1518 return -EINVAL;
1519 }
1520
Alan Kwong4aacd532017-02-04 18:51:33 -08001521 cstate = _sde_plane_get_crtc_state(state);
1522 if (IS_ERR_OR_NULL(cstate)) {
1523 SDE_ERROR("invalid crtc state %ld\n", PTR_ERR(cstate));
1524 return -EINVAL;
1525 }
1526 sde_cstate = to_sde_crtc_state(cstate);
1527
Alan Kwong4dd64c82017-02-04 18:41:51 -08001528 rot_cmd = &rstate->rot_cmd;
1529
1530 rot_cmd->master = (rstate->out_xpos == 0);
1531 rot_cmd->sequence_id = rstate->sequence_id;
1532 rot_cmd->fps = pstate->base.crtc && pstate->base.crtc->state ?
1533 drm_mode_vrefresh(&pstate->base.crtc->state->adjusted_mode) :
1534 DEFAULT_REFRESH_RATE;
1535 rot_cmd->rot90 = rstate->rot90;
1536 rot_cmd->hflip = rstate->hflip;
1537 rot_cmd->vflip = rstate->vflip;
1538 rot_cmd->secure = state->fb->flags & DRM_MODE_FB_SECURE ? true : false;
Alan Kwong4aacd532017-02-04 18:51:33 -08001539 rot_cmd->prefill_bw = sde_crtc_get_property(sde_cstate,
1540 CRTC_PROP_ROT_PREFILL_BW);
Alan Kwong8c176bf2017-02-09 19:34:32 -08001541 rot_cmd->clkrate = sde_crtc_get_property(sde_cstate,
1542 CRTC_PROP_ROT_CLK);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001543 rot_cmd->dst_writeback = psde->sbuf_writeback;
1544
1545 if (sde_crtc_get_intf_mode(state->crtc) == INTF_MODE_VIDEO)
1546 rot_cmd->video_mode = true;
1547 else
1548 rot_cmd->video_mode = false;
1549
1550 rot_cmd->src_pixel_format = state->fb->pixel_format;
1551 rot_cmd->src_modifier = state->fb->modifier[0];
1552 rot_cmd->src_stride = state->fb->pitches[0];
1553
1554 rot_cmd->src_format = to_sde_format(msm_framebuffer_format(state->fb));
1555 if (!rot_cmd->src_format) {
1556 SDE_ERROR("failed to get src format\n");
1557 return -EINVAL;
1558 }
1559
1560 rot_cmd->src_width = state->fb->width;
1561 rot_cmd->src_height = state->fb->height;
1562 rot_cmd->src_rect_x = rstate->in_rot_rect.x1 >> 16;
1563 rot_cmd->src_rect_y = rstate->in_rot_rect.y1 >> 16;
1564 rot_cmd->src_rect_w = drm_rect_width(&rstate->in_rot_rect) >> 16;
1565 rot_cmd->src_rect_h = drm_rect_height(&rstate->in_rot_rect) >> 16;
1566 rot_cmd->dst_rect_x = rstate->out_rot_rect.x1 >> 16;
1567 rot_cmd->dst_rect_y = rstate->out_rot_rect.y1 >> 16;
1568 rot_cmd->dst_rect_w = drm_rect_width(&rstate->out_rot_rect) >> 16;
1569 rot_cmd->dst_rect_h = drm_rect_height(&rstate->out_rot_rect) >> 16;
1570
1571 if (hw_cmd == SDE_HW_ROT_CMD_COMMIT) {
1572 struct sde_hw_fmt_layout layout;
1573
1574 memset(&layout, 0, sizeof(struct sde_hw_fmt_layout));
1575 sde_format_populate_layout(rstate->mmu_id, state->fb,
1576 &layout);
1577 for (i = 0; i < ARRAY_SIZE(rot_cmd->src_iova); i++) {
1578 rot_cmd->src_iova[i] = layout.plane_addr[i];
1579 rot_cmd->src_len[i] = layout.plane_size[i];
1580 }
1581 rot_cmd->src_planes = layout.num_planes;
1582
1583 memset(&layout, 0, sizeof(struct sde_hw_fmt_layout));
1584 sde_format_populate_layout(rstate->mmu_id, rstate->out_fb,
1585 &layout);
1586 for (i = 0; i < ARRAY_SIZE(rot_cmd->dst_iova); i++) {
1587 rot_cmd->dst_iova[i] = layout.plane_addr[i];
1588 rot_cmd->dst_len[i] = layout.plane_size[i];
1589 }
1590 rot_cmd->dst_planes = layout.num_planes;
1591 }
1592
1593 ret = rstate->rot_hw->ops.commit(rstate->rot_hw, rot_cmd, hw_cmd);
1594 if (ret) {
1595 SDE_ERROR("failed to commit rotator %d\n", ret);
1596 return ret;
1597 }
1598
1599 rstate->out_rotation = rstate->in_rotation;
1600 rstate->out_fb_flags = rot_cmd->dst_modifier ?
1601 DRM_MODE_FB_MODIFIERS : 0;
1602 rstate->out_fb_flags |= rot_cmd->secure ? DRM_MODE_FB_SECURE : 0;
1603 rstate->out_fb_format = rot_cmd->dst_format;
1604 rstate->out_fb_pixel_format = rot_cmd->dst_pixel_format;
1605
1606 for (i = 0; i < ARRAY_SIZE(rstate->out_fb_modifier); i++)
1607 rstate->out_fb_modifier[i] = rot_cmd->dst_modifier;
1608
1609 rstate->out_fb_width = drm_rect_width(&rstate->out_rot_rect) >> 16;
1610 rstate->out_fb_height = drm_rect_height(&rstate->out_rot_rect) >> 16;
1611 rstate->out_src_x = rstate->out_src_rect.x1 - rstate->out_rot_rect.x1;
1612 rstate->out_src_y = rstate->out_src_rect.y1 - rstate->out_rot_rect.y1;
1613 rstate->out_src_w = drm_rect_width(&rstate->out_src_rect);
1614 rstate->out_src_h = drm_rect_height(&rstate->out_src_rect);
1615
1616 if (rot_cmd->rot90)
1617 rstate->out_rotation &= ~DRM_ROTATE_90;
1618
1619 if (rot_cmd->hflip)
1620 rstate->out_rotation &= ~DRM_REFLECT_X;
1621
1622 if (rot_cmd->vflip)
1623 rstate->out_rotation &= ~DRM_REFLECT_Y;
1624
1625 SDE_DEBUG(
1626 "plane%d.%d rot:%d/%c%c%c%c/%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d\n",
1627 plane->base.id, rstate->sequence_id, hw_cmd,
1628 rot_cmd->rot90 ? 'r' : '_',
1629 rot_cmd->hflip ? 'h' : '_',
1630 rot_cmd->vflip ? 'v' : '_',
1631 rot_cmd->video_mode ? 'V' : 'C',
1632 state->fb->width, state->fb->height,
1633 state->fb->pixel_format >> 0,
1634 state->fb->pixel_format >> 8,
1635 state->fb->pixel_format >> 16,
1636 state->fb->pixel_format >> 24,
1637 state->fb->modifier[0],
1638 drm_rect_width(&rstate->in_rot_rect) >> 16,
1639 drm_rect_height(&rstate->in_rot_rect) >> 16,
1640 rstate->in_rot_rect.x1 >> 16,
1641 rstate->in_rot_rect.y1 >> 16);
1642
1643 SDE_DEBUG("plane%d.%d sspp:%d/%x/%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d\n",
1644 plane->base.id, rstate->sequence_id, hw_cmd,
1645 rstate->out_rotation,
1646 rstate->out_fb_width, rstate->out_fb_height,
1647 rstate->out_fb_pixel_format >> 0,
1648 rstate->out_fb_pixel_format >> 8,
1649 rstate->out_fb_pixel_format >> 16,
1650 rstate->out_fb_pixel_format >> 24,
1651 rstate->out_fb_modifier[0],
1652 rstate->out_src_w >> 16, rstate->out_src_h >> 16,
1653 rstate->out_src_x >> 16, rstate->out_src_y >> 16);
1654
1655 return ret;
1656}
1657
1658/**
1659 * sde_plane_rot_prepare_fb - prepare framebuffer of the new state
1660 * for rotator (pre-sspp) stage
1661 * @plane: Pointer to drm plane
1662 * @new_state: Pointer to new drm plane state
1663 * return: 0 if success; error code otherwise
1664 */
1665static int sde_plane_rot_prepare_fb(struct drm_plane *plane,
1666 struct drm_plane_state *new_state)
1667{
1668 struct drm_framebuffer *fb = new_state->fb;
1669 struct sde_plane_state *new_pstate = to_sde_plane_state(new_state);
1670 struct sde_plane_rot_state *new_rstate = &new_pstate->rot;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001671 struct drm_crtc_state *cstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001672 int ret;
1673
1674 SDE_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n",
1675 plane->base.id,
1676 new_rstate->sequence_id, fb ? fb->base.id : 0,
1677 !!new_rstate->out_sbuf, !!new_rstate->rot_hw,
1678 sde_plane_crtc_enabled(new_state));
1679
1680 if (!new_rstate->out_sbuf || !new_rstate->rot_hw)
1681 return 0;
1682
Alan Kwongcdb2f282017-03-18 13:42:06 -07001683 cstate = _sde_plane_get_crtc_state(new_state);
1684 if (IS_ERR(cstate)) {
1685 ret = PTR_ERR(cstate);
1686 SDE_ERROR("invalid crtc state %d\n", ret);
1687 return ret;
1688 }
1689
Alan Kwong4dd64c82017-02-04 18:41:51 -08001690 /* need to re-calc based on all newly validated plane states */
1691 sde_plane_rot_calc_cfg(plane, new_state);
1692
1693 /* check if stream buffer is already attached to rotator */
1694 if (sde_plane_enabled(new_state)) {
1695 struct sde_kms_fbo *fbo;
1696 struct drm_framebuffer *fb;
1697
Alan Kwongcdb2f282017-03-18 13:42:06 -07001698 fbo = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
1699 (u64) &new_rstate->rot_hw->base);
1700 fb = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FB,
1701 (u64) &new_rstate->rot_hw->base);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001702 if (fb && fbo) {
1703 SDE_DEBUG("plane%d.%d get fb/fbo\n", plane->base.id,
1704 new_rstate->sequence_id);
Alan Kwongcdb2f282017-03-18 13:42:06 -07001705 } else if (fbo) {
1706 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
1707 (u64) &new_rstate->rot_hw->base);
1708 fbo = NULL;
1709 } else if (fb) {
1710 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
1711 (u64) &new_rstate->rot_hw->base);
1712 fb = NULL;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001713 }
Alan Kwongcdb2f282017-03-18 13:42:06 -07001714
1715 new_rstate->out_fbo = fbo;
1716 new_rstate->out_fb = fb;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001717 }
1718
1719 /* release buffer if output format configuration changes */
1720 if (new_rstate->out_fb &&
1721 ((new_rstate->out_fb_height != new_rstate->out_fb->height) ||
1722 (new_rstate->out_fb_width != new_rstate->out_fb->width) ||
1723 (new_rstate->out_fb_pixel_format !=
1724 new_rstate->out_fb->pixel_format) ||
1725 (new_rstate->out_fb_modifier[0] !=
1726 new_rstate->out_fb->modifier[0]) ||
1727 (new_rstate->out_fb_flags != new_rstate->out_fb->flags))) {
1728
1729 SDE_DEBUG("plane%d.%d release fb/fbo\n", plane->base.id,
1730 new_rstate->sequence_id);
1731
Alan Kwongcdb2f282017-03-18 13:42:06 -07001732 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
1733 (u64) &new_rstate->rot_hw->base);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001734 new_rstate->out_fb = NULL;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001735 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
1736 (u64) &new_rstate->rot_hw->base);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001737 new_rstate->out_fbo = NULL;
1738 }
1739
1740 /* create new stream buffer if it is not available */
1741 if (sde_plane_enabled(new_state) && !new_rstate->out_fb) {
1742 u32 fb_w = drm_rect_width(&new_rstate->out_rot_rect) >> 16;
1743 u32 fb_h = drm_rect_height(&new_rstate->out_rot_rect) >> 16;
1744
1745 SDE_DEBUG("plane%d.%d allocate fb/fbo\n", plane->base.id,
1746 new_rstate->sequence_id);
1747
1748 if (new_state->fb->flags & DRM_MODE_FB_SECURE)
1749 new_rstate->mmu_id = MSM_SMMU_DOMAIN_SECURE;
1750 else
1751 new_rstate->mmu_id = MSM_SMMU_DOMAIN_UNSECURE;
1752
1753 /* check if out_fb is already attached to rotator */
1754 new_rstate->out_fbo = sde_kms_fbo_alloc(plane->dev, fb_w, fb_h,
1755 new_rstate->out_fb_pixel_format,
1756 new_rstate->out_fb_modifier,
1757 new_rstate->out_fb_flags);
1758 if (!new_rstate->out_fbo) {
1759 SDE_ERROR("failed to allocate inline buffer object\n");
1760 ret = -EINVAL;
1761 goto error_create_fbo;
1762 }
1763
Alan Kwongcdb2f282017-03-18 13:42:06 -07001764 ret = sde_crtc_res_add(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
1765 (u64) &new_rstate->rot_hw->base,
1766 new_rstate->out_fbo, &fbo_res_ops);
1767 if (ret) {
1768 SDE_ERROR("failed to add crtc resource\n");
1769 goto error_create_fbo_res;
1770 }
Alan Kwong4dd64c82017-02-04 18:41:51 -08001771
1772 new_rstate->out_fb = sde_kms_fbo_create_fb(plane->dev,
1773 new_rstate->out_fbo);
1774 if (!new_rstate->out_fb) {
1775 SDE_ERROR("failed to create inline framebuffer\n");
1776 ret = -EINVAL;
1777 goto error_create_fb;
1778 }
1779
Alan Kwongcdb2f282017-03-18 13:42:06 -07001780 ret = sde_crtc_res_add(cstate, SDE_CRTC_RES_ROT_OUT_FB,
1781 (u64) &new_rstate->rot_hw->base,
1782 new_rstate->out_fb, &fb_res_ops);
1783 if (ret) {
1784 SDE_ERROR("failed to add crtc resource %d\n", ret);
1785 goto error_create_fb_res;
1786 }
Alan Kwong4dd64c82017-02-04 18:41:51 -08001787 }
1788
1789 /* prepare rotator input buffer */
1790 ret = msm_framebuffer_prepare(new_state->fb, new_rstate->mmu_id);
1791 if (ret) {
1792 SDE_ERROR("failed to prepare input framebuffer\n");
1793 goto error_prepare_input_buffer;
1794 }
1795
1796 /* prepare rotator output buffer */
1797 if (sde_plane_enabled(new_state) && new_rstate->out_fb) {
1798 SDE_DEBUG("plane%d.%d prepare fb/fbo\n", plane->base.id,
1799 new_rstate->sequence_id);
1800
1801 ret = msm_framebuffer_prepare(new_rstate->out_fb,
1802 new_rstate->mmu_id);
1803 if (ret) {
1804 SDE_ERROR("failed to prepare inline framebuffer\n");
1805 goto error_prepare_output_buffer;
1806 }
1807 }
1808
1809 return 0;
1810
1811error_prepare_output_buffer:
1812 msm_framebuffer_cleanup(new_state->fb, new_rstate->mmu_id);
1813error_prepare_input_buffer:
Alan Kwongcdb2f282017-03-18 13:42:06 -07001814 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
1815 (u64) &new_rstate->rot_hw->base);
1816error_create_fb_res:
Alan Kwong4dd64c82017-02-04 18:41:51 -08001817 new_rstate->out_fb = NULL;
1818error_create_fb:
Alan Kwongcdb2f282017-03-18 13:42:06 -07001819 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
1820 (u64) &new_rstate->rot_hw->base);
1821error_create_fbo_res:
Alan Kwong4dd64c82017-02-04 18:41:51 -08001822 new_rstate->out_fbo = NULL;
1823error_create_fbo:
1824 return ret;
1825}
1826
1827/**
1828 * sde_plane_rot_cleanup_fb - cleanup framebuffer of previous state for the
1829 * rotator (pre-sspp) stage
1830 * @plane: Pointer to drm plane
1831 * @old_state: Pointer to previous drm plane state
1832 * return: none
1833 */
1834static void sde_plane_rot_cleanup_fb(struct drm_plane *plane,
1835 struct drm_plane_state *old_state)
1836{
1837 struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
1838 struct sde_plane_rot_state *old_rstate = &old_pstate->rot;
1839 struct sde_hw_rot_cmd *cmd = &old_rstate->rot_cmd;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001840 struct drm_crtc_state *cstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001841 int ret;
1842
1843 SDE_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n", plane->base.id,
1844 old_rstate->sequence_id, old_state->fb->base.id,
1845 !!old_rstate->out_sbuf, !!old_rstate->rot_hw,
1846 sde_plane_crtc_enabled(old_state));
1847
1848 if (!old_rstate->out_sbuf || !old_rstate->rot_hw)
1849 return;
1850
Alan Kwongcdb2f282017-03-18 13:42:06 -07001851 cstate = _sde_plane_get_crtc_state(old_state);
1852 if (IS_ERR(cstate)) {
1853 ret = PTR_ERR(cstate);
1854 SDE_ERROR("invalid crtc state %d\n", ret);
1855 return;
1856 }
1857
Alan Kwong4dd64c82017-02-04 18:41:51 -08001858 if (sde_plane_crtc_enabled(old_state)) {
1859 ret = old_rstate->rot_hw->ops.commit(old_rstate->rot_hw, cmd,
1860 SDE_HW_ROT_CMD_CLEANUP);
1861 if (ret)
1862 SDE_ERROR("failed to cleanup rotator buffers\n");
1863 }
1864
1865 if (sde_plane_enabled(old_state)) {
1866 if (old_rstate->out_fb) {
1867 msm_framebuffer_cleanup(old_rstate->out_fb,
1868 old_rstate->mmu_id);
Alan Kwongcdb2f282017-03-18 13:42:06 -07001869 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
1870 (u64) &old_rstate->rot_hw->base);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001871 old_rstate->out_fb = NULL;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001872 sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
1873 (u64) &old_rstate->rot_hw->base);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001874 old_rstate->out_fbo = NULL;
1875 }
1876
1877 msm_framebuffer_cleanup(old_state->fb, old_rstate->mmu_id);
1878 }
1879}
1880
1881/**
1882 * sde_plane_rot_atomic_check - verify rotator update of the given state
1883 * @plane: Pointer to drm plane
1884 * @state: Pointer to drm plane state to be validated
1885 * return: 0 if success; error code otherwise
1886 */
1887static int sde_plane_rot_atomic_check(struct drm_plane *plane,
1888 struct drm_plane_state *state)
1889{
1890 struct sde_plane *psde;
1891 struct sde_plane_state *pstate, *old_pstate;
1892 struct sde_plane_rot_state *rstate, *old_rstate;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001893 struct drm_crtc_state *cstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001894 struct sde_hw_blk *hw_blk;
1895 int i, ret = 0;
1896
1897 if (!plane || !state) {
1898 SDE_ERROR("invalid plane/state\n");
1899 return -EINVAL;
1900 }
1901
1902 psde = to_sde_plane(plane);
1903 pstate = to_sde_plane_state(state);
1904 old_pstate = to_sde_plane_state(plane->state);
1905 rstate = &pstate->rot;
1906 old_rstate = &old_pstate->rot;
1907
Alan Kwongcdb2f282017-03-18 13:42:06 -07001908 /* cstate will be null if crtc is disconnected from plane */
1909 cstate = _sde_plane_get_crtc_state(state);
1910 if (IS_ERR(cstate)) {
1911 ret = PTR_ERR(cstate);
1912 SDE_ERROR("invalid crtc state %d\n", ret);
1913 return ret;
1914 }
1915
Alan Kwong4dd64c82017-02-04 18:41:51 -08001916 SDE_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n", plane->base.id,
1917 rstate->sequence_id, state->fb ? state->fb->base.id : 0,
1918 !!rstate->out_sbuf, !!rstate->rot_hw,
1919 sde_plane_crtc_enabled(state));
1920
1921 rstate->in_rotation = drm_rotation_simplify(
1922 sde_plane_get_property(pstate, PLANE_PROP_ROTATION),
1923 DRM_ROTATE_90 | DRM_REFLECT_X | DRM_REFLECT_Y);
1924 rstate->rot90 = rstate->in_rotation & DRM_ROTATE_90 ? true : false;
1925 rstate->hflip = rstate->in_rotation & DRM_REFLECT_X ? true : false;
1926 rstate->vflip = rstate->in_rotation & DRM_REFLECT_Y ? true : false;
1927 rstate->out_sbuf = psde->sbuf_mode || rstate->rot90;
1928
Alan Kwongcdb2f282017-03-18 13:42:06 -07001929 if (sde_plane_enabled(state) && rstate->out_sbuf) {
1930 SDE_DEBUG("plane%d.%d acquire rotator\n",
Alan Kwong4dd64c82017-02-04 18:41:51 -08001931 plane->base.id, rstate->sequence_id);
1932
Alan Kwongcdb2f282017-03-18 13:42:06 -07001933 hw_blk = sde_crtc_res_get(cstate, SDE_HW_BLK_ROT,
1934 (u64) state->fb);
1935 if (!hw_blk) {
Alan Kwong4dd64c82017-02-04 18:41:51 -08001936 SDE_ERROR("plane%d no available rotator\n",
1937 plane->base.id);
1938 return -EINVAL;
1939 }
1940
Alan Kwongcdb2f282017-03-18 13:42:06 -07001941 rstate->rot_hw = to_sde_hw_rot(hw_blk);
1942
Alan Kwong4dd64c82017-02-04 18:41:51 -08001943 if (!rstate->rot_hw->ops.commit) {
1944 SDE_ERROR("plane%d invalid rotator ops\n",
1945 plane->base.id);
Alan Kwongcdb2f282017-03-18 13:42:06 -07001946 sde_crtc_res_put(cstate,
1947 SDE_HW_BLK_ROT, (u64) state->fb);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001948 rstate->rot_hw = NULL;
1949 return -EINVAL;
1950 }
1951
1952 rstate->in_fb = state->fb;
Alan Kwongcdb2f282017-03-18 13:42:06 -07001953 } else {
1954 rstate->in_fb = NULL;
1955 rstate->rot_hw = NULL;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001956 }
1957
1958 if (sde_plane_enabled(state) && rstate->out_sbuf && rstate->rot_hw) {
1959
1960 SDE_DEBUG("plane%d.%d use rotator\n",
1961 plane->base.id, rstate->sequence_id);
1962
1963 sde_plane_rot_calc_cfg(plane, state);
1964
1965 ret = sde_plane_rot_submit_command(plane, state,
1966 SDE_HW_ROT_CMD_VALIDATE);
1967
1968 } else if (sde_plane_enabled(state)) {
1969
1970 SDE_DEBUG("plane%d.%d bypass rotator\n", plane->base.id,
1971 rstate->sequence_id);
1972
1973 /* bypass rotator - initialize output setting as input */
1974 rstate->out_rotation = rstate->in_rotation;
1975 rstate->out_fb_pixel_format = state->fb->pixel_format;
1976
1977 for (i = 0.; i < ARRAY_SIZE(rstate->out_fb_modifier); i++)
1978 rstate->out_fb_modifier[i] = state->fb->modifier[i];
1979
1980 rstate->out_fb_flags = state->fb->flags;
1981 rstate->out_fb_width = state->fb->width;
1982 rstate->out_fb_height = state->fb->height;
1983 rstate->out_src_x = state->src_x;
1984 rstate->out_src_y = state->src_y;
1985 rstate->out_src_w = state->src_w;
1986 rstate->out_src_h = state->src_h;
1987
1988 rstate->out_fb_format = NULL;
1989 rstate->out_sbuf = false;
1990 rstate->out_fb = state->fb;
1991 }
1992
1993 return ret;
1994}
1995
1996/**
1997 * sde_plane_rot_atomic_update - perform atomic update for rotator stage
1998 * @plane: Pointer to drm plane
1999 * @old_state: Pointer to previous state
2000 * return: none
2001 */
2002static void sde_plane_rot_atomic_update(struct drm_plane *plane,
2003 struct drm_plane_state *old_state)
2004{
2005 struct drm_plane_state *state;
2006 struct sde_plane_state *pstate;
2007 struct sde_plane_rot_state *rstate;
2008
2009 if (!plane || !plane->state) {
2010 SDE_ERROR("invalid plane/state\n");
2011 return;
2012 }
2013
2014 state = plane->state;
2015 pstate = to_sde_plane_state(state);
2016 rstate = &pstate->rot;
2017
2018 SDE_DEBUG("plane%d.%d sbuf:%d rot:%d crtc:%d\n", plane->base.id,
2019 rstate->sequence_id,
2020 !!rstate->out_sbuf, !!rstate->rot_hw,
2021 sde_plane_crtc_enabled(plane->state));
2022
2023 if (!sde_plane_crtc_enabled(state))
2024 return;
2025
2026 if (!rstate->out_sbuf || !rstate->rot_hw)
2027 return;
2028
2029 sde_plane_rot_submit_command(plane, state, SDE_HW_ROT_CMD_COMMIT);
2030}
2031
2032/**
2033 * sde_plane_rot_destroy_state - destroy state for rotator stage
2034 * @plane: Pointer to drm plane
2035 * @state: Pointer to state to be destroyed
2036 * return: none
2037 */
2038static void sde_plane_rot_destroy_state(struct drm_plane *plane,
2039 struct drm_plane_state *state)
2040{
2041 struct sde_plane_state *pstate = to_sde_plane_state(state);
2042 struct sde_plane_rot_state *rstate = &pstate->rot;
2043
2044 SDE_DEBUG("plane%d.%d sbuf:%d rot:%d crtc:%d\n", plane->base.id,
2045 rstate->sequence_id,
2046 !!rstate->out_sbuf, !!rstate->rot_hw,
2047 sde_plane_crtc_enabled(state));
Alan Kwong4dd64c82017-02-04 18:41:51 -08002048}
2049
2050/**
2051 * sde_plane_rot_duplicate_state - duplicate state for rotator stage
2052 * @plane: Pointer to drm plane
2053 * @new_state: Pointer to duplicated state
2054 * return: 0 if success; error code otherwise
2055 */
2056static int sde_plane_rot_duplicate_state(struct drm_plane *plane,
2057 struct drm_plane_state *new_state)
2058{
2059 struct sde_plane_state *pstate = to_sde_plane_state(new_state);
2060 struct sde_plane_rot_state *rstate = &pstate->rot;
Alan Kwongcdb2f282017-03-18 13:42:06 -07002061 struct drm_crtc_state *cstate;
2062 int ret;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002063
2064 rstate->sequence_id++;
2065
2066 SDE_DEBUG("plane%d.%d sbuf:%d rot:%d\n", plane->base.id,
2067 rstate->sequence_id,
2068 !!rstate->out_sbuf, !!rstate->rot_hw);
2069
Alan Kwongcdb2f282017-03-18 13:42:06 -07002070 cstate = _sde_plane_get_crtc_state(new_state);
2071 if (IS_ERR(cstate)) {
2072 ret = PTR_ERR(cstate);
2073 SDE_ERROR("invalid crtc state %d\n", ret);
2074 return -EINVAL;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002075 }
2076
Alan Kwongcdb2f282017-03-18 13:42:06 -07002077 if (rstate->rot_hw && cstate)
2078 sde_crtc_res_get(cstate, SDE_HW_BLK_ROT, (u64) rstate->in_fb);
2079 else if (rstate->rot_hw && !cstate)
2080 SDE_ERROR("plane%d.%d zombie rotator hw\n",
2081 plane->base.id, rstate->sequence_id);
2082
Alan Kwong4dd64c82017-02-04 18:41:51 -08002083 rstate->out_fb = NULL;
2084 rstate->out_fbo = NULL;
2085
2086 return 0;
2087}
2088
2089/**
2090 * sde_plane_rot_install_caps - install plane rotator capabilities
2091 * @plane: Pointer to drm plane
2092 * return: none
2093 */
2094static void sde_plane_rot_install_caps(struct drm_plane *plane)
2095{
2096 struct sde_plane *psde = to_sde_plane(plane);
2097 const struct sde_format_extended *format_list;
2098 struct sde_kms_info *info;
2099 struct sde_hw_rot *rot_hw;
2100 const char *downscale_caps;
2101
2102 if (!psde->catalog || !(psde->features & BIT(SDE_SSPP_SBUF)) ||
2103 !psde->catalog->rot_count)
2104 return;
2105
2106 if (psde->blob_rot_caps)
2107 return;
2108
2109 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
2110 if (!info)
2111 return;
2112
2113 rot_hw = sde_hw_rot_get(NULL);
2114 if (!rot_hw || !rot_hw->ops.get_format_caps ||
2115 !rot_hw->ops.get_downscale_caps) {
2116 SDE_ERROR("invalid rotator hw\n");
2117 goto error_rot;
2118 }
2119
2120 sde_kms_info_reset(info);
2121
2122 format_list = rot_hw->ops.get_format_caps(rot_hw);
2123 if (format_list) {
2124 sde_kms_info_start(info, "pixel_formats");
2125 while (format_list->fourcc_format) {
2126 sde_kms_info_append_format(info,
2127 format_list->fourcc_format,
2128 format_list->modifier);
2129 ++format_list;
2130 }
2131 sde_kms_info_stop(info);
2132 }
2133
2134 downscale_caps = rot_hw->ops.get_downscale_caps(rot_hw);
2135 if (downscale_caps) {
2136 sde_kms_info_start(info, "downscale_ratios");
2137 sde_kms_info_append(info, downscale_caps);
2138 sde_kms_info_stop(info);
2139 }
2140
2141 if (rot_hw->ops.get_cache_size)
2142 sde_kms_info_add_keyint(info, "cache_size",
2143 rot_hw->ops.get_cache_size(rot_hw));
2144
2145 msm_property_set_blob(&psde->property_info, &psde->blob_rot_caps,
2146 info->data, info->len, PLANE_PROP_ROT_CAPS_V1);
2147
2148 sde_hw_rot_put(rot_hw);
2149error_rot:
2150 kfree(info);
2151}
2152
2153/**
2154 * sde_plane_rot_install_properties - install plane rotator properties
2155 * @plane: Pointer to drm plane
2156 * @catalog: Pointer to mdss configuration
2157 * return: none
2158 */
2159static void sde_plane_rot_install_properties(struct drm_plane *plane,
2160 struct sde_mdss_cfg *catalog)
2161{
2162 struct sde_plane *psde = to_sde_plane(plane);
2163 unsigned long supported_rotations = DRM_REFLECT_X | DRM_REFLECT_Y;
2164
2165 if (!plane || !psde) {
2166 SDE_ERROR("invalid plane\n");
2167 return;
2168 } else if (!catalog) {
2169 SDE_ERROR("invalid catalog\n");
2170 return;
2171 }
2172
2173 if ((psde->features & BIT(SDE_SSPP_SBUF)) && catalog->rot_count)
2174 supported_rotations |= DRM_ROTATE_0 | DRM_ROTATE_90 |
2175 DRM_ROTATE_180 | DRM_ROTATE_270;
2176
2177 msm_property_install_rotation(&psde->property_info,
2178 supported_rotations, PLANE_PROP_ROTATION);
2179
2180 if (!(psde->features & BIT(SDE_SSPP_SBUF)) || !catalog->rot_count)
2181 return;
2182
2183 msm_property_install_range(&psde->property_info, "rot_dst_x",
2184 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_X);
2185 msm_property_install_range(&psde->property_info, "rot_dst_y",
2186 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_Y);
2187 msm_property_install_range(&psde->property_info, "rot_dst_w",
2188 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_W);
2189 msm_property_install_range(&psde->property_info, "rot_dst_h",
2190 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_H);
2191 msm_property_install_blob(&psde->property_info, "rot_caps_v1",
2192 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_ROT_CAPS_V1);
2193}
2194
2195static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -07002196 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -04002197{
Clarence Ipc47a0692016-10-11 10:54:17 -04002198 uint32_t nplanes, src_flags;
Clarence Ipcb410d42016-06-26 22:52:33 -04002199 struct sde_plane *psde;
2200 struct sde_plane_state *pstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002201 struct sde_plane_rot_state *rstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04002202 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002203 struct drm_crtc *crtc;
2204 struct drm_framebuffer *fb;
2205 struct sde_rect src, dst;
2206 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -04002207 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -04002208
Clarence Ip13a8cf42016-09-29 17:27:47 -04002209 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -04002210 SDE_ERROR("invalid plane\n");
2211 return -EINVAL;
2212 } else if (!plane->state) {
2213 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04002214 return -EINVAL;
2215 }
2216
2217 psde = to_sde_plane(plane);
2218 pstate = to_sde_plane_state(plane->state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002219 rstate = &pstate->rot;
Clarence Ipcb410d42016-06-26 22:52:33 -04002220
Dhaval Patel47302cf2016-08-18 15:04:28 -07002221 crtc = state->crtc;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002222 fb = rstate->out_fb;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002223 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002224 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
2225 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -07002226 return -EINVAL;
2227 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -04002228 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002229 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -04002230
Alan Kwong4dd64c82017-02-04 18:41:51 -08002231 SDE_DEBUG(
2232 "plane%d.%d sspp:%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
2233 plane->base.id, rstate->sequence_id,
2234 rstate->out_fb_width, rstate->out_fb_height,
2235 rstate->out_fb_pixel_format >> 0,
2236 rstate->out_fb_pixel_format >> 8,
2237 rstate->out_fb_pixel_format >> 16,
2238 rstate->out_fb_pixel_format >> 24,
2239 rstate->out_fb_modifier[0],
2240 rstate->out_src_w >> 16, rstate->out_src_h >> 16,
2241 rstate->out_src_x >> 16, rstate->out_src_y >> 16,
2242 rstate->out_rotation,
2243 state->crtc_w, state->crtc_h,
2244 state->crtc_x, state->crtc_y);
2245
Clarence Ip282dad62016-09-27 17:07:35 -04002246 /* determine what needs to be refreshed */
2247 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
2248 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -04002249 case PLANE_PROP_SCALER_V1:
abeykun48f407a2016-08-25 12:06:44 -04002250 case PLANE_PROP_SCALER_V2:
Clarence Ipdedbba92016-09-27 17:43:10 -04002251 case PLANE_PROP_H_DECIMATE:
2252 case PLANE_PROP_V_DECIMATE:
2253 case PLANE_PROP_SRC_CONFIG:
2254 case PLANE_PROP_ZPOS:
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002255 case PLANE_PROP_EXCL_RECT_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04002256 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
2257 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04002258 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04002259 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
2260 break;
2261 case PLANE_PROP_COLOR_FILL:
2262 /* potentially need to refresh everything */
2263 pstate->dirty = SDE_PLANE_DIRTY_ALL;
2264 break;
2265 case PLANE_PROP_ROTATION:
2266 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
2267 break;
Clarence Ip282dad62016-09-27 17:07:35 -04002268 case PLANE_PROP_INFO:
2269 case PLANE_PROP_ALPHA:
2270 case PLANE_PROP_INPUT_FENCE:
2271 case PLANE_PROP_BLEND_OP:
2272 /* no special action required */
2273 break;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002274 case PLANE_PROP_ROT_DST_X:
2275 case PLANE_PROP_ROT_DST_Y:
2276 case PLANE_PROP_ROT_DST_W:
2277 case PLANE_PROP_ROT_DST_H:
2278 /* handled by rotator atomic update */
2279 break;
Clarence Ip282dad62016-09-27 17:07:35 -04002280 default:
2281 /* unknown property, refresh everything */
2282 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
2283 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
2284 break;
2285 }
Clarence Ipcb410d42016-06-26 22:52:33 -04002286 }
2287
Clarence Ip282dad62016-09-27 17:07:35 -04002288 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
2289 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -04002290
2291 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
2292
Clarence Ip282dad62016-09-27 17:07:35 -04002293 /* early out if nothing dirty */
2294 if (!pstate->dirty)
2295 return 0;
2296 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002297
Dhaval Patel4d424602017-02-18 19:40:14 -08002298 psde->is_rt_pipe = (sde_crtc_get_client_type(crtc) != NRT_CLIENT);
Clarence Ip282dad62016-09-27 17:07:35 -04002299 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
2300
2301 /* update roi config */
2302 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
Alan Kwong4dd64c82017-02-04 18:41:51 -08002303 POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
2304 rstate->out_src_w, rstate->out_src_h, q16_data);
Clarence Ip282dad62016-09-27 17:07:35 -04002305 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
2306 state->crtc_w, state->crtc_h, !q16_data);
2307
Clarence Ip13a8cf42016-09-29 17:27:47 -04002308 SDE_DEBUG_PLANE(psde,
Alan Kwong4dd64c82017-02-04 18:41:51 -08002309 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %c%c%c%c ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04002310 fb->base.id, src.x, src.y, src.w, src.h,
2311 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
Alan Kwong4dd64c82017-02-04 18:41:51 -08002312 fmt->base.pixel_format >> 0,
2313 fmt->base.pixel_format >> 8,
2314 fmt->base.pixel_format >> 16,
2315 fmt->base.pixel_format >> 24,
Clarence Ip282dad62016-09-27 17:07:35 -04002316 SDE_FORMAT_IS_UBWC(fmt));
2317
2318 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
2319 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002320 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002321 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
2322 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
2323 src.h /= 2;
2324 src.y = DIV_ROUND_UP(src.y, 2);
2325 src.y &= ~0x1;
2326 }
2327
2328 psde->pipe_cfg.src_rect = src;
2329 psde->pipe_cfg.dst_rect = dst;
2330
Dhaval Patele4b6bb22017-03-27 17:22:21 -07002331 _sde_plane_setup_scaler(psde, fmt, pstate);
2332
Clarence Ip282dad62016-09-27 17:07:35 -04002333 /* check for color fill */
2334 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
2335 PLANE_PROP_COLOR_FILL);
2336 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
2337 /* skip remaining processing on color fill */
2338 pstate->dirty = 0x0;
2339 } else if (psde->pipe_hw->ops.setup_rects) {
Clarence Ip282dad62016-09-27 17:07:35 -04002340 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08002341 &psde->pipe_cfg,
2342 pstate->multirect_index);
Clarence Ip282dad62016-09-27 17:07:35 -04002343 }
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002344
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08002345 if (psde->pipe_hw->ops.setup_pe)
2346 psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
2347 &psde->pixel_ext);
2348
2349 if (psde->pipe_hw->ops.setup_scaler)
2350 psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
2351 &psde->pipe_cfg, &psde->pixel_ext,
2352 psde->scaler3_cfg);
2353
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002354 /* update excl rect */
2355 if (psde->pipe_hw->ops.setup_excl_rect)
2356 psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002357 &pstate->excl_rect,
2358 pstate->multirect_index);
2359
2360 if (psde->pipe_hw->ops.setup_multirect)
2361 psde->pipe_hw->ops.setup_multirect(
2362 psde->pipe_hw,
2363 pstate->multirect_index,
2364 pstate->multirect_mode);
Dhaval Patel48c76022016-09-01 17:51:23 -07002365 }
2366
Clarence Ip282dad62016-09-27 17:07:35 -04002367 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
2368 psde->pipe_hw->ops.setup_format) {
2369 src_flags = 0x0;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002370 SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", rstate->out_rotation);
2371 if (rstate->out_rotation & DRM_REFLECT_X)
Clarence Ip282dad62016-09-27 17:07:35 -04002372 src_flags |= SDE_SSPP_FLIP_LR;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002373 if (rstate->out_rotation & DRM_REFLECT_Y)
Clarence Ip282dad62016-09-27 17:07:35 -04002374 src_flags |= SDE_SSPP_FLIP_UD;
2375
2376 /* update format */
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002377 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags,
2378 pstate->multirect_index);
Clarence Ip282dad62016-09-27 17:07:35 -04002379
Alan Kwong4dd64c82017-02-04 18:41:51 -08002380 if (psde->pipe_hw->ops.setup_sys_cache) {
2381 if (rstate->out_sbuf) {
2382 if (rstate->nplane < 2)
2383 pstate->sc_cfg.op_mode =
2384 SDE_PIPE_SC_OP_MODE_INLINE_SINGLE;
2385 else if (rstate->out_xpos == 0)
2386 pstate->sc_cfg.op_mode =
2387 SDE_PIPE_SC_OP_MODE_INLINE_LEFT;
2388 else
2389 pstate->sc_cfg.op_mode =
2390 SDE_PIPE_SC_OP_MODE_INLINE_RIGHT;
2391
2392 pstate->sc_cfg.rd_en = true;
2393 pstate->sc_cfg.rd_scid =
2394 rstate->rot_hw->caps->scid;
2395 pstate->sc_cfg.rd_noallocate = true;
2396 pstate->sc_cfg.rd_op_type =
2397 SDE_PIPE_SC_RD_OP_TYPE_CACHEABLE;
2398 } else {
2399 pstate->sc_cfg.op_mode =
2400 SDE_PIPE_SC_OP_MODE_OFFLINE;
2401 pstate->sc_cfg.rd_en = false;
2402 pstate->sc_cfg.rd_scid = 0;
2403 pstate->sc_cfg.rd_noallocate = false;
2404 pstate->sc_cfg.rd_op_type =
2405 SDE_PIPE_SC_RD_OP_TYPE_CACHEABLE;
2406 }
2407
2408 psde->pipe_hw->ops.setup_sys_cache(
2409 psde->pipe_hw, &pstate->sc_cfg);
2410 }
2411
Clarence Ip282dad62016-09-27 17:07:35 -04002412 /* update csc */
2413 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04002414 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04002415 else
2416 psde->csc_ptr = 0;
2417 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002418
Benet Clarkeb1b4462016-06-27 14:43:06 -07002419 sde_color_process_plane_setup(plane);
2420
Clarence Ipe78efb72016-06-24 18:35:21 -04002421 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04002422 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
2423 psde->pipe_hw->ops.setup_sharpening) {
2424 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
2425 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
2426 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
2427 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04002428
Clarence Ipe78efb72016-06-24 18:35:21 -04002429 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04002430 &psde->sharp_cfg);
2431 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002432
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002433 _sde_plane_set_qos_lut(plane, fb);
2434 _sde_plane_set_danger_lut(plane, fb);
2435
Alan Kwong5d324e42016-07-28 22:56:18 -04002436 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002437 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04002438 _sde_plane_set_ot_limit(plane, crtc);
2439 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002440
Clarence Ip282dad62016-09-27 17:07:35 -04002441 /* clear dirty */
2442 pstate->dirty = 0x0;
2443
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002444 /* clear multirect mode*/
2445 pstate->multirect_index = SDE_SSPP_RECT_SOLO;
2446 pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
2447 return 0;
2448}
2449
2450int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
2451{
2452 struct sde_plane_state *pstate[R_MAX];
2453 const struct drm_plane_state *drm_state[R_MAX];
2454 struct sde_rect src[R_MAX], dst[R_MAX];
2455 struct sde_plane *sde_plane[R_MAX];
2456 const struct sde_format *fmt[R_MAX];
2457 bool q16_data = true;
2458 int i, max_sspp_linewidth;
2459 int buffer_lines = TX_MODE_BUFFER_LINE_THRES;
2460
2461 for (i = 0; i < R_MAX; i++) {
2462 const struct msm_format *msm_fmt;
2463
2464 drm_state[i] = i ? plane->r1 : plane->r0;
2465 pstate[i] = to_sde_plane_state(drm_state[i]);
2466 sde_plane[i] = to_sde_plane(drm_state[i]->plane);
2467
2468 if (pstate[i] == NULL) {
2469 SDE_ERROR("SDE plane state of plane id %d is NULL\n",
2470 drm_state[i]->plane->base.id);
2471 return -EINVAL;
2472 }
2473
2474 POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
2475 drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
2476 POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
2477 drm_state[i]->crtc_y, drm_state[i]->crtc_w,
2478 drm_state[i]->crtc_h, !q16_data);
2479
2480 if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
2481 SDE_ERROR_PLANE(sde_plane[i],
2482 "scaling is not supported in multirect mode\n");
2483 return -EINVAL;
2484 }
2485
2486 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
2487 fmt[i] = to_sde_format(msm_fmt);
2488 if (SDE_FORMAT_IS_YUV(fmt[i])) {
2489 SDE_ERROR_PLANE(sde_plane[i],
2490 "Unsupported format for multirect mode\n");
2491 return -EINVAL;
2492 }
2493 }
2494
2495 max_sspp_linewidth = sde_plane[R0]->pipe_sblk->maxlinewidth;
2496
2497 /* Validate RECT's and set the mode */
2498
2499 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
2500 if (src[R0].w <= max_sspp_linewidth/2 &&
2501 src[R1].w <= max_sspp_linewidth/2) {
2502 if (dst[R0].x <= dst[R1].x) {
2503 pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
2504 pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
2505 } else {
2506 pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
2507 pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
2508 }
2509
2510 pstate[R0]->multirect_mode = SDE_SSPP_MULTIRECT_PARALLEL;
2511 pstate[R1]->multirect_mode = SDE_SSPP_MULTIRECT_PARALLEL;
2512 goto done;
2513 }
2514
2515 /* TIME_MX Mode */
2516 if (SDE_FORMAT_IS_UBWC(fmt[R0]))
2517 buffer_lines = 2 * fmt[R0]->tile_height;
2518
2519 if (dst[R1].y >= dst[R0].y + dst[R0].h + buffer_lines) {
2520 pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
2521 pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
2522 } else if (dst[R0].y >= dst[R1].y + dst[R1].h + buffer_lines) {
2523 pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
2524 pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
2525 } else {
2526 SDE_ERROR(
2527 "No multirect mode possible for the planes (%d - %d)\n",
2528 drm_state[R0]->plane->base.id,
2529 drm_state[R1]->plane->base.id);
2530 return -EINVAL;
2531 }
2532
2533 pstate[R0]->multirect_mode = SDE_SSPP_MULTIRECT_TIME_MX;
2534 pstate[R1]->multirect_mode = SDE_SSPP_MULTIRECT_TIME_MX;
2535done:
Clarence Ip5e2a9222016-06-26 22:38:24 -04002536 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002537}
2538
Alan Kwong4dd64c82017-02-04 18:41:51 -08002539/**
2540 * sde_plane_get_ctl_flush - get control flush for the given plane
2541 * @plane: Pointer to drm plane structure
2542 * @ctl: Pointer to hardware control driver
2543 * @flush: Pointer to flush control word
2544 */
2545void sde_plane_get_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
2546 u32 *flush)
2547{
2548 struct sde_plane_state *pstate;
2549 struct sde_plane_rot_state *rstate;
2550 u32 bitmask;
2551
2552 if (!plane || !flush) {
2553 SDE_ERROR("invalid parameters\n");
2554 return;
2555 }
2556
2557 pstate = to_sde_plane_state(plane->state);
2558 rstate = &pstate->rot;
2559
2560 bitmask = ctl->ops.get_bitmask_sspp(ctl, sde_plane_pipe(plane));
2561
2562 if (sde_plane_is_sbuf_mode(plane, NULL) && rstate->rot_hw &&
2563 ctl->ops.get_bitmask_rot)
2564 ctl->ops.get_bitmask_rot(ctl, &bitmask, rstate->rot_hw->idx);
2565
2566 *flush = bitmask;
2567}
2568
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002569static int sde_plane_prepare_fb(struct drm_plane *plane,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07002570 struct drm_plane_state *new_state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002571{
2572 struct drm_framebuffer *fb = new_state->fb;
2573 struct sde_plane *psde = to_sde_plane(plane);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002574 struct sde_plane_rot_state *new_rstate;
2575 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002576
2577 if (!new_state->fb)
2578 return 0;
2579
Clarence Ip13a8cf42016-09-29 17:27:47 -04002580 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002581
2582 ret = sde_plane_rot_prepare_fb(plane, new_state);
2583 if (ret) {
2584 SDE_ERROR("failed to prepare rot framebuffer\n");
2585 return ret;
2586 }
2587
2588 new_rstate = &to_sde_plane_state(new_state)->rot;
2589
2590 ret = msm_framebuffer_prepare(new_rstate->out_fb, new_rstate->mmu_id);
2591 if (ret) {
2592 SDE_ERROR("failed to prepare framebuffer\n");
2593 return ret;
2594 }
2595
2596 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002597}
2598
2599static void sde_plane_cleanup_fb(struct drm_plane *plane,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07002600 struct drm_plane_state *old_state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002601{
Alan Kwong4dd64c82017-02-04 18:41:51 -08002602 struct sde_plane *psde = to_sde_plane(plane);
2603 struct sde_plane_rot_state *old_rstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002604
Alan Kwong4dd64c82017-02-04 18:41:51 -08002605 if (!old_state->fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002606 return;
2607
Alan Kwong4dd64c82017-02-04 18:41:51 -08002608 SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
2609
2610 old_rstate = &to_sde_plane_state(old_state)->rot;
2611
2612 msm_framebuffer_cleanup(old_rstate->out_fb, old_rstate->mmu_id);
2613
2614 sde_plane_rot_cleanup_fb(plane, old_state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002615}
2616
Alan Kwong4dd64c82017-02-04 18:41:51 -08002617static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002618 struct drm_plane_state *state,
2619 struct drm_plane_state *old_state)
2620{
2621 struct sde_plane_state *pstate = to_sde_plane_state(state);
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002622 struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002623 struct sde_plane_rot_state *rstate = &pstate->rot;
2624 struct sde_plane_rot_state *old_rstate = &old_pstate->rot;
2625 struct drm_framebuffer *fb, *old_fb;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002626
Dhaval Patel47302cf2016-08-18 15:04:28 -07002627 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04002628 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07002629 return;
2630
Clarence Ip282dad62016-09-27 17:07:35 -04002631 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
2632 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002633 SDE_DEBUG_PLANE(psde,
2634 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002635 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002636 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002637 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002638 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002639 } else if (rstate->out_src_w != old_rstate->out_src_w ||
2640 rstate->out_src_h != old_rstate->out_src_h ||
2641 rstate->out_src_x != old_rstate->out_src_x ||
2642 rstate->out_src_y != old_rstate->out_src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002643 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002644 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002645 } else if (state->crtc_w != old_state->crtc_w ||
2646 state->crtc_h != old_state->crtc_h ||
2647 state->crtc_x != old_state->crtc_x ||
2648 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002649 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002650 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002651 } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
2652 pstate->excl_rect.h != old_pstate->excl_rect.h ||
2653 pstate->excl_rect.x != old_pstate->excl_rect.x ||
2654 pstate->excl_rect.y != old_pstate->excl_rect.y) {
2655 SDE_DEBUG_PLANE(psde, "excl rect updated\n");
2656 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002657 } else if (pstate->multirect_index != old_pstate->multirect_index ||
2658 pstate->multirect_mode != old_pstate->multirect_mode) {
2659 SDE_DEBUG_PLANE(psde, "multirect config updated\n");
2660 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Clarence Ip282dad62016-09-27 17:07:35 -04002661 }
2662
Alan Kwong4dd64c82017-02-04 18:41:51 -08002663 fb = rstate->out_fb;
2664 old_fb = old_rstate->out_fb;
2665
2666 if (!fb || !old_fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002667 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Alan Kwong4dd64c82017-02-04 18:41:51 -08002668 } else if (fb->pixel_format != old_fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002669 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002670 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002671 } else {
Alan Kwong4dd64c82017-02-04 18:41:51 -08002672 uint64_t *new_mods = fb->modifier;
2673 uint64_t *old_mods = old_fb->modifier;
2674 uint32_t *new_pitches = fb->pitches;
2675 uint32_t *old_pitches = old_fb->pitches;
2676 uint32_t *new_offset = fb->offsets;
2677 uint32_t *old_offset = old_fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002678 int i;
2679
Alan Kwong4dd64c82017-02-04 18:41:51 -08002680 for (i = 0; i < ARRAY_SIZE(fb->modifier); i++) {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002681 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002682 SDE_DEBUG_PLANE(psde,
2683 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07002684 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04002685 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04002686 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
2687 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002688 break;
2689 }
2690 }
Alan Kwong4dd64c82017-02-04 18:41:51 -08002691 for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04002692 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002693 SDE_DEBUG_PLANE(psde,
2694 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07002695 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04002696 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04002697 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04002698 break;
2699 }
2700 }
Alan Kwong4dd64c82017-02-04 18:41:51 -08002701 for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002702 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002703 SDE_DEBUG_PLANE(psde,
2704 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07002705 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04002706 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04002707 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
2708 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002709 break;
2710 }
2711 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04002712 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002713}
2714
Alan Kwong4dd64c82017-02-04 18:41:51 -08002715static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002716 struct drm_plane_state *state)
2717{
Clarence Ipdedbba92016-09-27 17:43:10 -04002718 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04002719 struct sde_plane *psde;
2720 struct sde_plane_state *pstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002721 struct sde_plane_rot_state *rstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04002722 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002723 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04002724 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002725 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
2726 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04002727
2728 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002729 SDE_ERROR("invalid arg(s), plane %d state %d\n",
2730 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04002731 ret = -EINVAL;
2732 goto exit;
2733 }
2734
2735 psde = to_sde_plane(plane);
2736 pstate = to_sde_plane_state(state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002737 rstate = &pstate->rot;
Clarence Ipdbde9832016-06-26 09:48:36 -04002738
2739 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002740 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04002741 ret = -EINVAL;
2742 goto exit;
2743 }
2744
Clarence Ipdedbba92016-09-27 17:43:10 -04002745 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
2746 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04002747
2748 /* src values are in Q16 fixed point, convert to integer */
Alan Kwong4dd64c82017-02-04 18:41:51 -08002749 POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
2750 rstate->out_src_w, rstate->out_src_h, q16_data);
Dhaval Patel47302cf2016-08-18 15:04:28 -07002751 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
2752 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04002753
Dhaval Patel47302cf2016-08-18 15:04:28 -07002754 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
2755 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04002756
Dhaval Patel47302cf2016-08-18 15:04:28 -07002757 max_upscale = psde->pipe_sblk->maxupscale;
2758 max_downscale = psde->pipe_sblk->maxdwnscale;
2759 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04002760
Clarence Ip13a8cf42016-09-29 17:27:47 -04002761 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002762 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002763
Dhaval Patel47302cf2016-08-18 15:04:28 -07002764 if (!sde_plane_enabled(state))
2765 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04002766
Alan Kwong4dd64c82017-02-04 18:41:51 -08002767 SDE_DEBUG(
2768 "plane%d.%u sspp:%x/%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d crtc:%dx%d+%d+%d\n",
2769 plane->base.id, rstate->sequence_id,
2770 rstate->out_rotation,
2771 rstate->out_fb_width, rstate->out_fb_height,
2772 rstate->out_fb_pixel_format >> 0,
2773 rstate->out_fb_pixel_format >> 8,
2774 rstate->out_fb_pixel_format >> 16,
2775 rstate->out_fb_pixel_format >> 24,
2776 rstate->out_fb_modifier[0],
2777 rstate->out_src_w >> 16, rstate->out_src_h >> 16,
2778 rstate->out_src_x >> 16, rstate->out_src_y >> 16,
2779 state->crtc_w, state->crtc_h,
2780 state->crtc_x, state->crtc_y);
2781
Dhaval Patel47302cf2016-08-18 15:04:28 -07002782 fmt = to_sde_format(msm_framebuffer_format(state->fb));
2783
2784 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
2785
2786 if (SDE_FORMAT_IS_YUV(fmt) &&
2787 (!(psde->features & SDE_SSPP_SCALER) ||
abeykun1c312f62016-08-26 09:47:12 -04002788 !(psde->features & (BIT(SDE_SSPP_CSC)
2789 | BIT(SDE_SSPP_CSC_10BIT))))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002790 SDE_ERROR_PLANE(psde,
2791 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07002792 ret = -EINVAL;
2793
2794 /* check src bounds */
Alan Kwong4dd64c82017-02-04 18:41:51 -08002795 } else if (rstate->out_fb_width > MAX_IMG_WIDTH ||
2796 rstate->out_fb_height > MAX_IMG_HEIGHT ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07002797 src.w < min_src_size || src.h < min_src_size ||
Alan Kwong4dd64c82017-02-04 18:41:51 -08002798 CHECK_LAYER_BOUNDS(src.x, src.w, rstate->out_fb_width) ||
2799 CHECK_LAYER_BOUNDS(src.y, src.h, rstate->out_fb_height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002800 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002801 src.x, src.y, src.w, src.h);
2802 ret = -E2BIG;
2803
2804 /* valid yuv image */
2805 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
2806 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002807 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002808 src.x, src.y, src.w, src.h);
2809 ret = -EINVAL;
2810
2811 /* min dst support */
2812 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002813 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002814 dst.x, dst.y, dst.w, dst.h);
2815 ret = -EINVAL;
2816
2817 /* decimation validation */
2818 } else if (deci_w || deci_h) {
2819 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
2820 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002821 SDE_ERROR_PLANE(psde,
2822 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04002823 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002824 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002825 SDE_ERROR_PLANE(psde,
2826 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04002827 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002828 }
2829
Dhaval Patel47302cf2016-08-18 15:04:28 -07002830 } else if (!(psde->features & SDE_SSPP_SCALER) &&
2831 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002832 SDE_ERROR_PLANE(psde,
2833 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002834 src.w, src.h, dst.w, dst.h);
2835 ret = -EINVAL;
2836
2837 /* check decimated source width */
2838 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002839 SDE_ERROR_PLANE(psde,
2840 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002841 src.w, src_deci_w, max_linewidth);
2842 ret = -E2BIG;
2843
2844 /* check max scaler capability */
2845 } else if (((src_deci_w * max_upscale) < dst.w) ||
2846 ((src_deci_h * max_upscale) < dst.h) ||
2847 ((dst.w * max_downscale) < src_deci_w) ||
2848 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002849 SDE_ERROR_PLANE(psde,
2850 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002851 src_deci_w, src_deci_h, dst.w, dst.h);
2852 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002853 }
2854
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002855 /* check excl rect configs */
2856 if (pstate->excl_rect.w && pstate->excl_rect.h) {
2857 struct sde_rect intersect;
2858
2859 /*
2860 * Check exclusion rect against src rect.
2861 * Cropping is not required as hardware will consider only the
2862 * intersecting region with the src rect.
2863 */
2864 sde_kms_rect_intersect(&intersect, &src, &pstate->excl_rect);
2865 if (!intersect.w || !intersect.h || SDE_FORMAT_IS_YUV(fmt)) {
2866 SDE_ERROR_PLANE(psde,
2867 "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt:%s\n",
2868 pstate->excl_rect.x, pstate->excl_rect.y,
2869 pstate->excl_rect.w, pstate->excl_rect.h,
2870 src.x, src.y, src.w, src.h,
2871 drm_get_format_name(fmt->base.pixel_format));
2872 ret = -EINVAL;
2873 }
2874 }
2875
Dhaval Patel47302cf2016-08-18 15:04:28 -07002876modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002877 if (!ret)
Alan Kwong4dd64c82017-02-04 18:41:51 -08002878 _sde_plane_sspp_atomic_check_mode_changed(psde,
2879 state, plane->state);
2880exit:
2881 return ret;
2882}
2883
2884static int sde_plane_atomic_check(struct drm_plane *plane,
2885 struct drm_plane_state *state)
2886{
2887 int ret = 0;
2888 struct sde_plane *psde;
2889 struct sde_plane_state *pstate;
2890
2891 if (!plane || !state) {
2892 SDE_ERROR("invalid arg(s), plane %d state %d\n",
2893 plane != 0, state != 0);
2894 ret = -EINVAL;
2895 goto exit;
2896 }
2897
2898 psde = to_sde_plane(plane);
2899 pstate = to_sde_plane_state(state);
2900
2901 SDE_DEBUG_PLANE(psde, "\n");
2902
2903 ret = sde_plane_rot_atomic_check(plane, state);
2904 if (ret)
2905 goto exit;
2906
2907 ret = sde_plane_sspp_atomic_check(plane, state);
2908
Clarence Ipdbde9832016-06-26 09:48:36 -04002909exit:
2910 return ret;
2911}
2912
Clarence Ipcae1bb62016-07-07 12:07:13 -04002913/**
2914 * sde_plane_flush - final plane operations before commit flush
2915 * @plane: Pointer to drm plane structure
2916 */
2917void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04002918{
Clarence Ipcae1bb62016-07-07 12:07:13 -04002919 struct sde_plane *psde;
2920
Clarence Ip13a8cf42016-09-29 17:27:47 -04002921 if (!plane) {
2922 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04002923 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04002924 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04002925
2926 psde = to_sde_plane(plane);
2927
2928 /*
2929 * These updates have to be done immediately before the plane flush
2930 * timing, and may not be moved to the atomic_update/mode_set functions.
2931 */
2932 if (psde->is_error)
Clarence Ip3bf8d872017-02-16 15:25:38 -05002933 /* force white frame with 100% alpha pipe output on error */
2934 _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04002935 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
2936 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04002937 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04002938 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
2939 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
2940
Clarence Ip56902792017-03-17 15:22:07 -04002941 /* force black color fill during suspend */
2942 if (msm_is_suspend_state(plane->dev) && suspend_blank)
2943 _sde_plane_color_fill(psde, 0x0, 0x0);
2944
Clarence Ipcae1bb62016-07-07 12:07:13 -04002945 /* flag h/w flush complete */
2946 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04002947 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002948}
2949
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002950static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04002951 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002952{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002953 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04002954 struct drm_plane_state *state;
2955 struct sde_plane_state *pstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002956 struct sde_plane_state *old_pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002957
Clarence Ip13a8cf42016-09-29 17:27:47 -04002958 if (!plane) {
2959 SDE_ERROR("invalid plane\n");
2960 return;
2961 } else if (!plane->state) {
2962 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04002963 return;
2964 }
2965
Clarence Ip13a8cf42016-09-29 17:27:47 -04002966 psde = to_sde_plane(plane);
2967 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04002968 state = plane->state;
2969 pstate = to_sde_plane_state(state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002970 old_pstate = to_sde_plane_state(old_state);
Clarence Ip5e2a9222016-06-26 22:38:24 -04002971
Clarence Ip13a8cf42016-09-29 17:27:47 -04002972 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04002973
Alan Kwong4dd64c82017-02-04 18:41:51 -08002974 sde_plane_rot_atomic_update(plane, old_state);
2975
2976 if (!sde_plane_sspp_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04002977 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04002978 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002979 int ret;
2980
Alan Kwong4dd64c82017-02-04 18:41:51 -08002981 ret = sde_plane_sspp_atomic_update(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002982 /* atomic_check should have ensured that this doesn't fail */
2983 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002984 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002985}
2986
Dhaval Patel47302cf2016-08-18 15:04:28 -07002987
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002988/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07002989static void _sde_plane_install_properties(struct drm_plane *plane,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002990 struct sde_mdss_cfg *catalog, u32 master_plane_id)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002991{
Clarence Ip5e2a9222016-06-26 22:38:24 -04002992 static const struct drm_prop_enum_list e_blend_op[] = {
2993 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
2994 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
2995 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
2996 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
2997 };
2998 static const struct drm_prop_enum_list e_src_config[] = {
2999 {SDE_DRM_DEINTERLACE, "deinterlace"}
3000 };
Clarence Ipea3d6262016-07-15 16:20:11 -04003001 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07003002 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04003003 struct sde_plane *psde = to_sde_plane(plane);
Clarence Ipc47a0692016-10-11 10:54:17 -04003004 int zpos_max = 255;
3005 int zpos_def = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -07003006 char feature_name[256];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003007
Clarence Ip13a8cf42016-09-29 17:27:47 -04003008 if (!plane || !psde) {
3009 SDE_ERROR("invalid plane\n");
3010 return;
3011 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
3012 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
3013 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003014 return;
Clarence Ipc47a0692016-10-11 10:54:17 -04003015 } else if (!catalog) {
3016 SDE_ERROR("invalid catalog\n");
3017 return;
Clarence Ip5e2a9222016-06-26 22:38:24 -04003018 }
3019
Alan Kwong4dd64c82017-02-04 18:41:51 -08003020 psde->catalog = catalog;
3021
Clarence Ipc47a0692016-10-11 10:54:17 -04003022 if (sde_is_custom_client()) {
Clarence Ip649989a2016-10-21 14:28:34 -04003023 if (catalog->mixer_count && catalog->mixer &&
3024 catalog->mixer[0].sblk->maxblendstages) {
3025 zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
3026 if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
3027 zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
3028 }
Clarence Ipc47a0692016-10-11 10:54:17 -04003029 } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
3030 /* reserve zpos == 0 for primary planes */
3031 zpos_def = drm_plane_index(plane) + 1;
3032 }
3033
3034 msm_property_install_range(&psde->property_info, "zpos",
3035 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003036
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04003037 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07003038 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003039
Dhaval Patel47302cf2016-08-18 15:04:28 -07003040 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04003041 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07003042 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003043
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003044 if (!master_plane_id) {
3045 if (psde->pipe_sblk->maxhdeciexp) {
3046 msm_property_install_range(&psde->property_info,
3047 "h_decimate", 0x0, 0,
3048 psde->pipe_sblk->maxhdeciexp, 0,
3049 PLANE_PROP_H_DECIMATE);
3050 }
Clarence Ipdedbba92016-09-27 17:43:10 -04003051
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003052 if (psde->pipe_sblk->maxvdeciexp) {
3053 msm_property_install_range(&psde->property_info,
3054 "v_decimate", 0x0, 0,
3055 psde->pipe_sblk->maxvdeciexp, 0,
3056 PLANE_PROP_V_DECIMATE);
3057 }
Clarence Ipdedbba92016-09-27 17:43:10 -04003058
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003059 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
3060 msm_property_install_volatile_range(
3061 &psde->property_info, "scaler_v2",
3062 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
3063 msm_property_install_blob(&psde->property_info,
3064 "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
3065 msm_property_install_blob(&psde->property_info,
3066 "lut_cir", 0,
3067 PLANE_PROP_SCALER_LUT_CIR);
3068 msm_property_install_blob(&psde->property_info,
3069 "lut_sep", 0,
3070 PLANE_PROP_SCALER_LUT_SEP);
3071 } else if (psde->features & SDE_SSPP_SCALER) {
3072 msm_property_install_volatile_range(
3073 &psde->property_info, "scaler_v1", 0x0,
3074 0, ~0, 0, PLANE_PROP_SCALER_V1);
3075 }
Clarence Ipb43d4592016-09-08 14:21:35 -04003076
Dhaval Patel0aee0972017-02-08 19:00:58 -08003077 if (psde->features & BIT(SDE_SSPP_CSC) ||
3078 psde->features & BIT(SDE_SSPP_CSC_10BIT))
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003079 msm_property_install_volatile_range(
3080 &psde->property_info, "csc_v1", 0x0,
3081 0, ~0, 0, PLANE_PROP_CSC_V1);
Clarence Ip5fc00c52016-09-23 15:03:34 -04003082
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003083 if (psde->features & BIT(SDE_SSPP_HSIC)) {
3084 snprintf(feature_name, sizeof(feature_name), "%s%d",
3085 "SDE_SSPP_HUE_V",
3086 psde->pipe_sblk->hsic_blk.version >> 16);
3087 msm_property_install_range(&psde->property_info,
3088 feature_name, 0, 0, 0xFFFFFFFF, 0,
3089 PLANE_PROP_HUE_ADJUST);
3090 snprintf(feature_name, sizeof(feature_name), "%s%d",
3091 "SDE_SSPP_SATURATION_V",
3092 psde->pipe_sblk->hsic_blk.version >> 16);
3093 msm_property_install_range(&psde->property_info,
3094 feature_name, 0, 0, 0xFFFFFFFF, 0,
3095 PLANE_PROP_SATURATION_ADJUST);
3096 snprintf(feature_name, sizeof(feature_name), "%s%d",
3097 "SDE_SSPP_VALUE_V",
3098 psde->pipe_sblk->hsic_blk.version >> 16);
3099 msm_property_install_range(&psde->property_info,
3100 feature_name, 0, 0, 0xFFFFFFFF, 0,
3101 PLANE_PROP_VALUE_ADJUST);
3102 snprintf(feature_name, sizeof(feature_name), "%s%d",
3103 "SDE_SSPP_CONTRAST_V",
3104 psde->pipe_sblk->hsic_blk.version >> 16);
3105 msm_property_install_range(&psde->property_info,
3106 feature_name, 0, 0, 0xFFFFFFFF, 0,
3107 PLANE_PROP_CONTRAST_ADJUST);
3108 }
Benet Clarkeb1b4462016-06-27 14:43:06 -07003109 }
3110
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08003111 if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
3112 msm_property_install_volatile_range(&psde->property_info,
3113 "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
3114
Alan Kwong4dd64c82017-02-04 18:41:51 -08003115 sde_plane_rot_install_properties(plane, catalog);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003116
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04003117 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07003118 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003119
Dhaval Patel47302cf2016-08-18 15:04:28 -07003120 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
3121 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
3122
3123 if (psde->pipe_hw->ops.setup_solidfill)
3124 msm_property_install_range(&psde->property_info, "color_fill",
3125 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
3126
Dhaval Patel4e574842016-08-23 15:11:37 -07003127 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003128 if (!info) {
3129 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07003130 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003131 }
Dhaval Patel4e574842016-08-23 15:11:37 -07003132
3133 msm_property_install_blob(&psde->property_info, "capabilities",
3134 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
3135 sde_kms_info_reset(info);
3136
Clarence Ipea3d6262016-07-15 16:20:11 -04003137 format_list = psde->pipe_sblk->format_list;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003138
3139 if (master_plane_id) {
3140 sde_kms_info_add_keyint(info, "primary_smart_plane_id",
3141 master_plane_id);
3142 format_list = plane_formats;
3143 }
3144
Clarence Ipea3d6262016-07-15 16:20:11 -04003145 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04003146 sde_kms_info_start(info, "pixel_formats");
3147 while (format_list->fourcc_format) {
3148 sde_kms_info_append_format(info,
3149 format_list->fourcc_format,
3150 format_list->modifier);
3151 ++format_list;
3152 }
3153 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04003154 }
Dhaval Patel4e574842016-08-23 15:11:37 -07003155
3156 sde_kms_info_add_keyint(info, "max_linewidth",
3157 psde->pipe_sblk->maxlinewidth);
3158 sde_kms_info_add_keyint(info, "max_upscale",
3159 psde->pipe_sblk->maxupscale);
3160 sde_kms_info_add_keyint(info, "max_downscale",
3161 psde->pipe_sblk->maxdwnscale);
3162 sde_kms_info_add_keyint(info, "max_horizontal_deci",
3163 psde->pipe_sblk->maxhdeciexp);
3164 sde_kms_info_add_keyint(info, "max_vertical_deci",
3165 psde->pipe_sblk->maxvdeciexp);
3166 msm_property_set_blob(&psde->property_info, &psde->blob_info,
3167 info->data, info->len, PLANE_PROP_INFO);
3168
3169 kfree(info);
Benet Clarkd009b1d2016-06-27 14:45:59 -07003170
3171 if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
3172 snprintf(feature_name, sizeof(feature_name), "%s%d",
3173 "SDE_SSPP_SKIN_COLOR_V",
3174 psde->pipe_sblk->memcolor_blk.version >> 16);
3175 msm_property_install_blob(&psde->property_info, feature_name, 0,
3176 PLANE_PROP_SKIN_COLOR);
3177 snprintf(feature_name, sizeof(feature_name), "%s%d",
3178 "SDE_SSPP_SKY_COLOR_V",
3179 psde->pipe_sblk->memcolor_blk.version >> 16);
3180 msm_property_install_blob(&psde->property_info, feature_name, 0,
3181 PLANE_PROP_SKY_COLOR);
3182 snprintf(feature_name, sizeof(feature_name), "%s%d",
3183 "SDE_SSPP_FOLIAGE_COLOR_V",
3184 psde->pipe_sblk->memcolor_blk.version >> 16);
3185 msm_property_install_blob(&psde->property_info, feature_name, 0,
3186 PLANE_PROP_FOLIAGE_COLOR);
3187 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003188}
3189
Clarence Ip5fc00c52016-09-23 15:03:34 -04003190static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
3191{
3192 struct sde_drm_csc_v1 csc_v1;
3193 int i;
3194
3195 if (!psde) {
3196 SDE_ERROR("invalid plane\n");
3197 return;
3198 }
3199
3200 psde->csc_usr_ptr = NULL;
3201 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003202 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04003203 return;
3204 }
3205
3206 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003207 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04003208 return;
3209 }
3210
Clarence Ipb43d4592016-09-08 14:21:35 -04003211 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04003212 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
3213 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
3214 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
3215 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
3216 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
3217 }
3218 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
3219 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
3220 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
3221 }
3222 psde->csc_usr_ptr = &psde->csc_cfg;
3223}
3224
Clarence Ipb43d4592016-09-08 14:21:35 -04003225static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
3226{
3227 struct sde_drm_scaler_v1 scale_v1;
3228 struct sde_hw_pixel_ext *pe;
3229 int i;
3230
3231 if (!psde) {
3232 SDE_ERROR("invalid plane\n");
3233 return;
3234 }
3235
3236 psde->pixel_ext_usr = false;
3237 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003238 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04003239 return;
3240 }
3241
3242 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003243 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04003244 return;
3245 }
3246
3247 /* populate from user space */
3248 pe = &(psde->pixel_ext);
3249 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
3250 for (i = 0; i < SDE_MAX_PLANES; i++) {
3251 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
3252 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
3253 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
3254 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
3255
3256 pe->horz_filter[i] = scale_v1.horz_filter[i];
3257 pe->vert_filter[i] = scale_v1.vert_filter[i];
3258 }
3259 for (i = 0; i < SDE_MAX_PLANES; i++) {
abeykun41060122016-11-28 13:02:01 -05003260 pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
3261 pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
3262 pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
3263 pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
3264 pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
Clarence Ipb43d4592016-09-08 14:21:35 -04003265
abeykun41060122016-11-28 13:02:01 -05003266 pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
3267 pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
3268 pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
3269 pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
3270 pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
Clarence Ipb43d4592016-09-08 14:21:35 -04003271 }
abeykun41060122016-11-28 13:02:01 -05003272
Clarence Ipb43d4592016-09-08 14:21:35 -04003273 psde->pixel_ext_usr = true;
3274
Clarence Ip13a8cf42016-09-29 17:27:47 -04003275 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04003276}
3277
abeykun48f407a2016-08-25 12:06:44 -04003278static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
3279 struct sde_plane_state *pstate, void *usr)
3280{
3281 struct sde_drm_scaler_v2 scale_v2;
3282 struct sde_hw_pixel_ext *pe;
3283 int i;
3284 struct sde_hw_scaler3_cfg *cfg;
3285
3286 if (!psde) {
3287 SDE_ERROR("invalid plane\n");
3288 return;
3289 }
3290
3291 cfg = psde->scaler3_cfg;
3292 psde->pixel_ext_usr = false;
3293 if (!usr) {
3294 SDE_DEBUG_PLANE(psde, "scale data removed\n");
3295 return;
3296 }
3297
3298 if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
3299 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
3300 return;
3301 }
3302
3303 /* populate from user space */
3304 pe = &(psde->pixel_ext);
3305 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
3306 cfg->enable = scale_v2.enable;
3307 cfg->dir_en = scale_v2.dir_en;
3308 for (i = 0; i < SDE_MAX_PLANES; i++) {
3309 cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
3310 cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
3311 cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
3312 cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
3313
3314 cfg->preload_x[i] = scale_v2.preload_x[i];
3315 cfg->preload_y[i] = scale_v2.preload_y[i];
3316 cfg->src_width[i] = scale_v2.src_width[i];
3317 cfg->src_height[i] = scale_v2.src_height[i];
3318 }
3319 cfg->dst_width = scale_v2.dst_width;
3320 cfg->dst_height = scale_v2.dst_height;
3321
3322 cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
3323 cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
3324 cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
3325 cfg->blend_cfg = scale_v2.blend_cfg;
3326
3327 cfg->lut_flag = scale_v2.lut_flag;
3328 cfg->dir_lut_idx = scale_v2.dir_lut_idx;
3329 cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
3330 cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
3331 cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
3332 cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
3333
3334 cfg->de.enable = scale_v2.de.enable;
3335 cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
3336 cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
3337 cfg->de.clip = scale_v2.de.clip;
3338 cfg->de.limit = scale_v2.de.limit;
3339 cfg->de.thr_quiet = scale_v2.de.thr_quiet;
3340 cfg->de.thr_dieout = scale_v2.de.thr_dieout;
3341 cfg->de.thr_low = scale_v2.de.thr_low;
3342 cfg->de.thr_high = scale_v2.de.thr_high;
3343 cfg->de.prec_shift = scale_v2.de.prec_shift;
3344 for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
3345 cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
3346 cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
3347 cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
3348 }
3349 for (i = 0; i < SDE_MAX_PLANES; i++) {
abeykun41060122016-11-28 13:02:01 -05003350 pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
3351 pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
3352 pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
3353 pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
3354 pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
abeykun48f407a2016-08-25 12:06:44 -04003355
abeykun41060122016-11-28 13:02:01 -05003356 pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
3357 pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
3358 pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
3359 pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
3360 pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
abeykun48f407a2016-08-25 12:06:44 -04003361 }
3362 psde->pixel_ext_usr = true;
3363
3364 SDE_DEBUG_PLANE(psde, "user property data copied\n");
3365}
3366
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08003367static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
3368 struct sde_plane_state *pstate, void *usr_ptr)
3369{
3370 struct drm_clip_rect excl_rect_v1;
3371
3372 if (!psde) {
3373 SDE_ERROR("invalid plane\n");
3374 return;
3375 }
3376
3377 if (!usr_ptr) {
3378 SDE_DEBUG_PLANE(psde, "excl rect data removed\n");
3379 return;
3380 }
3381
3382 if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
3383 SDE_ERROR_PLANE(psde, "failed to copy excl rect data\n");
3384 return;
3385 }
3386
3387 /* populate from user space */
3388 pstate->excl_rect.x = excl_rect_v1.x1;
3389 pstate->excl_rect.y = excl_rect_v1.y1;
3390 pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1 + 1;
3391 pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1 + 1;
3392}
3393
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003394static int sde_plane_atomic_set_property(struct drm_plane *plane,
3395 struct drm_plane_state *state, struct drm_property *property,
3396 uint64_t val)
3397{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003398 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003399 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04003400 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003401
Clarence Ip13a8cf42016-09-29 17:27:47 -04003402 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003403
3404 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003405 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003406 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003407 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003408 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04003409 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003410 ret = msm_property_atomic_set(&psde->property_info,
3411 pstate->property_values, pstate->property_blobs,
3412 property, val);
3413 if (!ret) {
3414 idx = msm_property_index(&psde->property_info,
3415 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04003416 switch (idx) {
3417 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04003418 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04003419 break;
3420 case PLANE_PROP_CSC_V1:
3421 _sde_plane_set_csc_v1(psde, (void *)val);
3422 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04003423 case PLANE_PROP_SCALER_V1:
3424 _sde_plane_set_scaler_v1(psde, (void *)val);
3425 break;
abeykun48f407a2016-08-25 12:06:44 -04003426 case PLANE_PROP_SCALER_V2:
3427 _sde_plane_set_scaler_v2(psde, pstate,
3428 (void *)val);
3429 break;
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08003430 case PLANE_PROP_EXCL_RECT_V1:
3431 _sde_plane_set_excl_rect_v1(psde, pstate,
3432 (void *)val);
3433 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04003434 default:
3435 /* nothing to do */
3436 break;
3437 }
Clarence Ipe78efb72016-06-24 18:35:21 -04003438 }
3439 }
3440
Alan Kwong4dd64c82017-02-04 18:41:51 -08003441 SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
3442 property->name, property->base.id, val, ret);
3443
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003444 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003445}
3446
3447static int sde_plane_set_property(struct drm_plane *plane,
3448 struct drm_property *property, uint64_t val)
3449{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003450 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04003451
Clarence Ipae4e60c2016-06-26 22:44:04 -04003452 return sde_plane_atomic_set_property(plane,
3453 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003454}
3455
3456static int sde_plane_atomic_get_property(struct drm_plane *plane,
3457 const struct drm_plane_state *state,
3458 struct drm_property *property, uint64_t *val)
3459{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003460 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003461 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04003462 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003463
Clarence Ipaa0faf42016-05-30 12:07:48 -04003464 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003465 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003466 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003467 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003468 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003469 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04003470 pstate = to_sde_plane_state(state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08003471 sde_plane_rot_install_caps(plane);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003472 ret = msm_property_atomic_get(&psde->property_info,
3473 pstate->property_values, pstate->property_blobs,
3474 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04003475 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003476
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003477 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003478}
3479
3480static void sde_plane_destroy(struct drm_plane *plane)
3481{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003482 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003483
Clarence Ip13a8cf42016-09-29 17:27:47 -04003484 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003485
Clarence Ip13a8cf42016-09-29 17:27:47 -04003486 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04003487 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
3488
Dhaval Patel4e574842016-08-23 15:11:37 -07003489 if (psde->blob_info)
3490 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003491 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04003492 mutex_destroy(&psde->lock);
3493
Clarence Ip4ce59322016-06-26 22:27:51 -04003494 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003495
Clarence Ip4ce59322016-06-26 22:27:51 -04003496 /* this will destroy the states as well */
3497 drm_plane_cleanup(plane);
3498
Clarence Ip4c1d9772016-06-26 09:35:38 -04003499 if (psde->pipe_hw)
3500 sde_hw_sspp_destroy(psde->pipe_hw);
3501
Clarence Ip4ce59322016-06-26 22:27:51 -04003502 kfree(psde);
3503 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003504}
3505
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003506static void sde_plane_destroy_state(struct drm_plane *plane,
3507 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003508{
Clarence Ipaa0faf42016-05-30 12:07:48 -04003509 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04003510 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04003511
Clarence Ipae4e60c2016-06-26 22:44:04 -04003512 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003513 SDE_ERROR("invalid arg(s), plane %d state %d\n",
3514 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04003515 return;
3516 }
3517
Clarence Ipaa0faf42016-05-30 12:07:48 -04003518 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04003519 pstate = to_sde_plane_state(state);
3520
Clarence Ip13a8cf42016-09-29 17:27:47 -04003521 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003522
Alan Kwong4dd64c82017-02-04 18:41:51 -08003523 sde_plane_rot_destroy_state(plane, &pstate->base);
3524
Clarence Ipe78efb72016-06-24 18:35:21 -04003525 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003526 if (state->fb)
3527 drm_framebuffer_unreference(state->fb);
3528
Clarence Ipae4e60c2016-06-26 22:44:04 -04003529 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04003530 if (pstate->input_fence)
3531 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04003532
Clarence Ipaa0faf42016-05-30 12:07:48 -04003533 /* destroy value helper */
3534 msm_property_destroy_state(&psde->property_info, pstate,
3535 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003536}
3537
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003538static struct drm_plane_state *
3539sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003540{
Clarence Ipaa0faf42016-05-30 12:07:48 -04003541 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003542 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04003543 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04003544 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003545
Clarence Ip13a8cf42016-09-29 17:27:47 -04003546 if (!plane) {
3547 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003548 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003549 } else if (!plane->state) {
3550 SDE_ERROR("invalid plane state\n");
3551 return NULL;
3552 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003553
Clarence Ip730e7192016-06-26 22:45:09 -04003554 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003555 psde = to_sde_plane(plane);
3556 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003557 if (!pstate) {
3558 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003559 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003560 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003561
Clarence Ip13a8cf42016-09-29 17:27:47 -04003562 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003563
3564 /* duplicate value helper */
3565 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
3566 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04003567
Clarence Ip17e908b2016-09-29 15:58:00 -04003568 /* clear out any input fence */
3569 pstate->input_fence = 0;
3570 input_fence_default = msm_property_get_default(
3571 &psde->property_info, PLANE_PROP_INPUT_FENCE);
3572 msm_property_set_property(&psde->property_info, pstate->property_values,
3573 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003574
Clarence Ip282dad62016-09-27 17:07:35 -04003575 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04003576 pstate->pending = false;
3577
Alan Kwongcdb2f282017-03-18 13:42:06 -07003578 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
3579
Alan Kwong4dd64c82017-02-04 18:41:51 -08003580 sde_plane_rot_duplicate_state(plane, &pstate->base);
3581
Clarence Ip730e7192016-06-26 22:45:09 -04003582 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003583}
3584
3585static void sde_plane_reset(struct drm_plane *plane)
3586{
Clarence Ipae4e60c2016-06-26 22:44:04 -04003587 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003588 struct sde_plane_state *pstate;
3589
Clarence Ipae4e60c2016-06-26 22:44:04 -04003590 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003591 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04003592 return;
3593 }
3594
Clarence Ip730e7192016-06-26 22:45:09 -04003595 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003596 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003597
Clarence Ipae4e60c2016-06-26 22:44:04 -04003598 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04003599 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04003600 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003601 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04003602 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003603
Clarence Ipaa0faf42016-05-30 12:07:48 -04003604 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003605 if (!pstate) {
3606 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003607 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003608 }
Clarence Ip730e7192016-06-26 22:45:09 -04003609
Clarence Ipaa0faf42016-05-30 12:07:48 -04003610 /* reset value helper */
3611 msm_property_reset_state(&psde->property_info, pstate,
3612 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003613
3614 pstate->base.plane = plane;
3615
3616 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003617}
3618
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003619#ifdef CONFIG_DEBUG_FS
Alan Kwongf0fd8512016-10-24 21:39:26 -04003620static ssize_t _sde_plane_danger_read(struct file *file,
3621 char __user *buff, size_t count, loff_t *ppos)
3622{
3623 struct sde_kms *kms = file->private_data;
3624 struct sde_mdss_cfg *cfg = kms->catalog;
3625 int len = 0;
3626 char buf[40] = {'\0'};
3627
3628 if (!cfg)
3629 return -ENODEV;
3630
3631 if (*ppos)
3632 return 0; /* the end */
3633
3634 len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
3635 if (len < 0 || len >= sizeof(buf))
3636 return 0;
3637
3638 if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
3639 return -EFAULT;
3640
3641 *ppos += len; /* increase offset */
3642
3643 return len;
3644}
3645
3646static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
3647{
3648 struct drm_plane *plane;
3649
3650 drm_for_each_plane(plane, kms->dev) {
3651 if (plane->fb && plane->state) {
3652 sde_plane_danger_signal_ctrl(plane, enable);
3653 SDE_DEBUG("plane:%d img:%dx%d ",
3654 plane->base.id, plane->fb->width,
3655 plane->fb->height);
3656 SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
3657 plane->state->src_x >> 16,
3658 plane->state->src_y >> 16,
3659 plane->state->src_w >> 16,
3660 plane->state->src_h >> 16,
3661 plane->state->crtc_x, plane->state->crtc_y,
3662 plane->state->crtc_w, plane->state->crtc_h);
3663 } else {
3664 SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
3665 }
3666 }
3667}
3668
3669static ssize_t _sde_plane_danger_write(struct file *file,
3670 const char __user *user_buf, size_t count, loff_t *ppos)
3671{
3672 struct sde_kms *kms = file->private_data;
3673 struct sde_mdss_cfg *cfg = kms->catalog;
3674 int disable_panic;
3675 char buf[10];
3676
3677 if (!cfg)
3678 return -EFAULT;
3679
3680 if (count >= sizeof(buf))
3681 return -EFAULT;
3682
3683 if (copy_from_user(buf, user_buf, count))
3684 return -EFAULT;
3685
3686 buf[count] = 0; /* end of string */
3687
3688 if (kstrtoint(buf, 0, &disable_panic))
3689 return -EFAULT;
3690
3691 if (disable_panic) {
3692 /* Disable panic signal for all active pipes */
3693 SDE_DEBUG("Disabling danger:\n");
3694 _sde_plane_set_danger_state(kms, false);
3695 kms->has_danger_ctrl = false;
3696 } else {
3697 /* Enable panic signal for all active pipes */
3698 SDE_DEBUG("Enabling danger:\n");
3699 kms->has_danger_ctrl = true;
3700 _sde_plane_set_danger_state(kms, true);
3701 }
3702
3703 return count;
3704}
3705
3706static const struct file_operations sde_plane_danger_enable = {
3707 .open = simple_open,
3708 .read = _sde_plane_danger_read,
3709 .write = _sde_plane_danger_write,
3710};
3711
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003712static int _sde_plane_init_debugfs(struct drm_plane *plane)
Clarence Ip4ce59322016-06-26 22:27:51 -04003713{
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003714 struct sde_plane *psde;
3715 struct sde_kms *kms;
3716 struct msm_drm_private *priv;
Clarence Ip4ce59322016-06-26 22:27:51 -04003717 const struct sde_sspp_sub_blks *sblk = 0;
3718 const struct sde_sspp_cfg *cfg = 0;
3719
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003720 if (!plane || !plane->dev) {
3721 SDE_ERROR("invalid arguments\n");
3722 return -EINVAL;
3723 }
3724
3725 priv = plane->dev->dev_private;
3726 if (!priv || !priv->kms) {
3727 SDE_ERROR("invalid KMS reference\n");
3728 return -EINVAL;
3729 }
3730
3731 kms = to_sde_kms(priv->kms);
3732 psde = to_sde_plane(plane);
3733
Clarence Ip4ce59322016-06-26 22:27:51 -04003734 if (psde && psde->pipe_hw)
3735 cfg = psde->pipe_hw->cap;
3736 if (cfg)
3737 sblk = cfg->sblk;
3738
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003739 if (!sblk)
3740 return 0;
Clarence Ip4ce59322016-06-26 22:27:51 -04003741
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003742 /* create overall sub-directory for the pipe */
3743 psde->debugfs_root =
3744 debugfs_create_dir(psde->pipe_name,
3745 sde_debugfs_get_root(kms));
Clarence Ip4ce59322016-06-26 22:27:51 -04003746
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003747 if (!psde->debugfs_root)
3748 return -ENOMEM;
Clarence Ip4ce59322016-06-26 22:27:51 -04003749
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003750 /* don't error check these */
3751 debugfs_create_x32("features", 0644,
3752 psde->debugfs_root, &psde->features);
Alan Kwongf0fd8512016-10-24 21:39:26 -04003753
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003754 /* add register dump support */
3755 sde_debugfs_setup_regset32(&psde->debugfs_src,
3756 sblk->src_blk.base + cfg->base,
3757 sblk->src_blk.len,
3758 kms);
3759 sde_debugfs_create_regset32("src_blk", 0444,
3760 psde->debugfs_root, &psde->debugfs_src);
Alan Kwongf0fd8512016-10-24 21:39:26 -04003761
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003762 if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
3763 cfg->features & BIT(SDE_SSPP_SCALER_QSEED2)) {
3764 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
3765 sblk->scaler_blk.base + cfg->base,
3766 sblk->scaler_blk.len,
3767 kms);
3768 sde_debugfs_create_regset32("scaler_blk", 0444,
3769 psde->debugfs_root,
3770 &psde->debugfs_scaler);
Clarence Ip716ab662017-03-20 06:51:24 -07003771 debugfs_create_bool("default_scaling",
3772 0644,
3773 psde->debugfs_root,
3774 &psde->debugfs_default_scale);
Clarence Ip4ce59322016-06-26 22:27:51 -04003775 }
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003776
3777 if (cfg->features & BIT(SDE_SSPP_CSC) ||
3778 cfg->features & BIT(SDE_SSPP_CSC_10BIT)) {
3779 sde_debugfs_setup_regset32(&psde->debugfs_csc,
3780 sblk->csc_blk.base + cfg->base,
3781 sblk->csc_blk.len,
3782 kms);
3783 sde_debugfs_create_regset32("csc_blk", 0444,
3784 psde->debugfs_root, &psde->debugfs_csc);
3785 }
3786
3787 debugfs_create_u32("xin_id",
3788 0444,
3789 psde->debugfs_root,
3790 (u32 *) &cfg->xin_id);
3791 debugfs_create_u32("clk_ctrl",
3792 0444,
3793 psde->debugfs_root,
3794 (u32 *) &cfg->clk_ctrl);
3795 debugfs_create_x32("creq_vblank",
3796 0644,
3797 psde->debugfs_root,
3798 (u32 *) &sblk->creq_vblank);
3799 debugfs_create_x32("danger_vblank",
3800 0644,
3801 psde->debugfs_root,
3802 (u32 *) &sblk->danger_vblank);
3803
3804 debugfs_create_file("disable_danger",
3805 0644,
3806 psde->debugfs_root,
3807 kms, &sde_plane_danger_enable);
Alan Kwong4dd64c82017-02-04 18:41:51 -08003808 debugfs_create_u32("sbuf_mode",
3809 0644,
3810 psde->debugfs_root, &psde->sbuf_mode);
3811 debugfs_create_u32("sbuf_writeback",
3812 0644,
3813 psde->debugfs_root,
3814 &psde->sbuf_writeback);
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003815
3816 return 0;
3817}
3818
3819static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
3820{
3821 struct sde_plane *psde;
3822
3823 if (!plane)
3824 return;
3825 psde = to_sde_plane(plane);
3826
3827 debugfs_remove_recursive(psde->debugfs_root);
3828}
3829#else
3830static int _sde_plane_init_debugfs(struct drm_plane *plane)
3831{
3832 return 0;
3833}
3834static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
3835{
3836}
3837#endif
3838
3839static int sde_plane_late_register(struct drm_plane *plane)
3840{
3841 return _sde_plane_init_debugfs(plane);
3842}
3843
3844static void sde_plane_early_unregister(struct drm_plane *plane)
3845{
3846 _sde_plane_destroy_debugfs(plane);
3847}
3848
3849static const struct drm_plane_funcs sde_plane_funcs = {
3850 .update_plane = drm_atomic_helper_update_plane,
3851 .disable_plane = drm_atomic_helper_disable_plane,
3852 .destroy = sde_plane_destroy,
3853 .set_property = sde_plane_set_property,
3854 .atomic_set_property = sde_plane_atomic_set_property,
3855 .atomic_get_property = sde_plane_atomic_get_property,
3856 .reset = sde_plane_reset,
3857 .atomic_duplicate_state = sde_plane_duplicate_state,
3858 .atomic_destroy_state = sde_plane_destroy_state,
3859 .late_register = sde_plane_late_register,
3860 .early_unregister = sde_plane_early_unregister,
3861};
3862
3863static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
3864 .prepare_fb = sde_plane_prepare_fb,
3865 .cleanup_fb = sde_plane_cleanup_fb,
3866 .atomic_check = sde_plane_atomic_check,
3867 .atomic_update = sde_plane_atomic_update,
3868};
3869
3870enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
3871{
3872 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
3873}
3874
3875bool is_sde_plane_virtual(struct drm_plane *plane)
3876{
3877 return plane ? to_sde_plane(plane)->is_virtual : false;
Clarence Ip4ce59322016-06-26 22:27:51 -04003878}
3879
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003880/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04003881struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip2bbf7b32016-09-23 15:07:16 -04003882 uint32_t pipe, bool primary_plane,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003883 unsigned long possible_crtcs, u32 master_plane_id)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003884{
3885 struct drm_plane *plane = NULL;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003886 const struct sde_format_extended *format_list;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003887 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003888 struct msm_drm_private *priv;
3889 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003890 enum drm_plane_type type;
Clarence Ipc47a0692016-10-11 10:54:17 -04003891 int ret = -EINVAL;
Clarence Ip4c1d9772016-06-26 09:35:38 -04003892
3893 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003894 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003895 goto exit;
3896 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003897
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003898 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04003899 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003900 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04003901 goto exit;
3902 }
3903
3904 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003905 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04003906 goto exit;
3907 }
3908 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003909
Clarence Ip4c1d9772016-06-26 09:35:38 -04003910 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003911 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003912 goto exit;
3913 }
3914
Clarence Ip4ce59322016-06-26 22:27:51 -04003915 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003916 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
3917 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003918 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003919 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04003920 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003921 }
3922
Clarence Ip4c1d9772016-06-26 09:35:38 -04003923 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003924 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003925 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04003926 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003927 psde->is_virtual = (master_plane_id != 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003928
Clarence Ip4c1d9772016-06-26 09:35:38 -04003929 /* initialize underlying h/w driver */
3930 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
3931 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003932 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003933 ret = PTR_ERR(psde->pipe_hw);
3934 goto clean_plane;
3935 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003936 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003937 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003938 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04003939
3940 /* cache features mask for later */
3941 psde->features = psde->pipe_hw->cap->features;
3942 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04003943 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003944 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04003945 goto clean_sspp;
3946 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04003947
abeykun48f407a2016-08-25 12:06:44 -04003948 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
3949 psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
3950 GFP_KERNEL);
3951 if (!psde->scaler3_cfg) {
3952 SDE_ERROR("[%u]failed to allocate scale struct\n",
3953 pipe);
3954 ret = -ENOMEM;
3955 goto clean_sspp;
3956 }
3957 }
3958
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003959 format_list = psde->pipe_sblk->format_list;
3960
3961 if (master_plane_id)
3962 format_list = plane_formats;
3963
3964 psde->nformats = sde_populate_formats(plane_formats,
3965 psde->formats,
3966 0,
3967 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003968
Clarence Ip4c1d9772016-06-26 09:35:38 -04003969 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003970 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003971 goto clean_sspp;
3972 }
3973
3974 if (psde->features & BIT(SDE_SSPP_CURSOR))
3975 type = DRM_PLANE_TYPE_CURSOR;
3976 else if (primary_plane)
3977 type = DRM_PLANE_TYPE_PRIMARY;
3978 else
3979 type = DRM_PLANE_TYPE_OVERLAY;
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07003980 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
3981 psde->formats, psde->nformats,
3982 type, NULL);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003983 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04003984 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003985
Clarence Ip4c1d9772016-06-26 09:35:38 -04003986 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003987 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003988
Clarence Ipaa0faf42016-05-30 12:07:48 -04003989 msm_property_init(&psde->property_info, &plane->base, dev,
3990 priv->plane_property, psde->property_data,
3991 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
3992 sizeof(struct sde_plane_state));
3993
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003994 _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003995
Clarence Ip4ce59322016-06-26 22:27:51 -04003996 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04003997 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04003998
Clarence Ip730e7192016-06-26 22:45:09 -04003999 mutex_init(&psde->lock);
4000
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08004001 SDE_DEBUG("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07004002 return plane;
4003
Clarence Ip4c1d9772016-06-26 09:35:38 -04004004clean_sspp:
4005 if (psde && psde->pipe_hw)
4006 sde_hw_sspp_destroy(psde->pipe_hw);
abeykun48f407a2016-08-25 12:06:44 -04004007
4008 if (psde && psde->scaler3_cfg)
4009 kfree(psde->scaler3_cfg);
Clarence Ip4c1d9772016-06-26 09:35:38 -04004010clean_plane:
4011 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04004012exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07004013 return ERR_PTR(ret);
4014}