blob: 46508c7bc512c552e6e0e49383ead1fe1e41996f [file] [log] [blame]
Dhaval Patel14d46ce2017-01-17 16:28:12 -08001/*
2 * Copyright (C) 2014-2017 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07005 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -08006 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07009 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -080010 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070017 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040018
19#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
20
Clarence Ip4ce59322016-06-26 22:27:51 -040021#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040022#include <uapi/drm/sde_drm.h>
Benet Clarkd009b1d2016-06-27 14:45:59 -070023#include <uapi/drm/msm_drm_pp.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040024
25#include "msm_prop.h"
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080026#include "msm_drv.h"
Clarence Ipaa0faf42016-05-30 12:07:48 -040027
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070028#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040029#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040030#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040031#include "sde_hw_sspp.h"
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080032#include "sde_hw_catalog_format.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040033#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070034#include "sde_crtc.h"
Lloyd Atkinson8772e202016-09-26 17:52:16 -040035#include "sde_vbif.h"
Alan Kwong83285fb2016-10-21 20:51:17 -040036#include "sde_plane.h"
Benet Clarkd009b1d2016-06-27 14:45:59 -070037#include "sde_color_processing.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040038
Clarence Ip13a8cf42016-09-29 17:27:47 -040039#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
40 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
41
42#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
43 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
44
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040045#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
46#define PHASE_STEP_SHIFT 21
47#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
48#define PHASE_RESIDUAL 15
49
Clarence Ipe78efb72016-06-24 18:35:21 -040050#define SHARP_STRENGTH_DEFAULT 32
51#define SHARP_EDGE_THR_DEFAULT 112
52#define SHARP_SMOOTH_THR_DEFAULT 8
53#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040054
Clarence Ip5e2a9222016-06-26 22:38:24 -040055#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070056
Clarence Ipcae1bb62016-07-07 12:07:13 -040057#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
58
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080059/* multirect rect index */
60enum {
61 R0,
62 R1,
63 R_MAX
64};
65
66#define TX_MODE_BUFFER_LINE_THRES 2
67
Clarence Ip282dad62016-09-27 17:07:35 -040068/* dirty bits for update function */
69#define SDE_PLANE_DIRTY_RECTS 0x1
70#define SDE_PLANE_DIRTY_FORMAT 0x2
71#define SDE_PLANE_DIRTY_SHARPEN 0x4
72#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
73
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -070074#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
75#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
76
Alan Kwong1a00e4d2016-07-18 09:42:30 -040077/**
78 * enum sde_plane_qos - Different qos configurations for each pipe
79 *
80 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
81 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
82 * this configuration is mutually exclusive from VBLANK_CTRL.
83 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
84 */
85enum sde_plane_qos {
86 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
87 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
88 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
89};
90
Clarence Ip5fc00c52016-09-23 15:03:34 -040091/*
92 * struct sde_plane - local sde plane structure
93 * @csc_cfg: Decoded user configuration for csc
94 * @csc_usr_ptr: Points to csc_cfg if valid user config available
95 * @csc_ptr: Points to sde_csc_cfg structure to use for current
96 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070097struct sde_plane {
98 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040099
100 int mmu_id;
101
Clarence Ip730e7192016-06-26 22:45:09 -0400102 struct mutex lock;
103
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400104 enum sde_sspp pipe;
105 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700106 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400107 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400108
109 struct sde_hw_pipe *pipe_hw;
110 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -0400111 struct sde_hw_sharp_cfg sharp_cfg;
abeykun48f407a2016-08-25 12:06:44 -0400112 struct sde_hw_scaler3_cfg *scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400113 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400114 uint32_t color_fill;
115 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400116 bool is_rt_pipe;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800117 bool is_virtual;
Clarence Ip4ce59322016-06-26 22:27:51 -0400118
Clarence Ipb43d4592016-09-08 14:21:35 -0400119 struct sde_hw_pixel_ext pixel_ext;
120 bool pixel_ext_usr;
121
Clarence Ip373f8592016-05-26 00:58:42 -0400122 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400123 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -0400124 struct sde_csc_cfg *csc_ptr;
125
Clarence Ip4c1d9772016-06-26 09:35:38 -0400126 const struct sde_sspp_sub_blks *pipe_sblk;
127
Clarence Ip5e2a9222016-06-26 22:38:24 -0400128 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400129
Clarence Ipaa0faf42016-05-30 12:07:48 -0400130 struct msm_property_info property_info;
131 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700132 struct drm_property_blob *blob_info;
Clarence Ip730e7192016-06-26 22:45:09 -0400133
Clarence Ip4ce59322016-06-26 22:27:51 -0400134 /* debugfs related stuff */
135 struct dentry *debugfs_root;
136 struct sde_debugfs_regset32 debugfs_src;
137 struct sde_debugfs_regset32 debugfs_scaler;
138 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700139};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700140
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700141#define to_sde_plane(x) container_of(x, struct sde_plane, base)
142
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400143static bool sde_plane_enabled(struct drm_plane_state *state)
144{
Clarence Ipdbde9832016-06-26 09:48:36 -0400145 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400146}
147
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400148/**
149 * _sde_plane_calc_fill_level - calculate fill level of the given source format
150 * @plane: Pointer to drm plane
151 * @fmt: Pointer to source buffer format
152 * @src_wdith: width of source buffer
153 * Return: fill level corresponding to the source buffer/format or 0 if error
154 */
155static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
156 const struct sde_format *fmt, u32 src_width)
157{
158 struct sde_plane *psde;
159 u32 fixed_buff_size;
160 u32 total_fl;
161
162 if (!plane || !fmt) {
163 SDE_ERROR("invalid arguments\n");
164 return 0;
165 }
166
167 psde = to_sde_plane(plane);
168 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
169
170 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
171 if (fmt->chroma_sample == SDE_CHROMA_420) {
172 /* NV12 */
173 total_fl = (fixed_buff_size / 2) /
174 ((src_width + 32) * fmt->bpp);
175 } else {
176 /* non NV12 */
177 total_fl = (fixed_buff_size) /
178 ((src_width + 32) * fmt->bpp);
179 }
180 } else {
181 total_fl = (fixed_buff_size * 2) /
182 ((src_width + 32) * fmt->bpp);
183 }
184
185 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
186 plane->base.id, psde->pipe - SSPP_VIG0,
187 fmt->base.pixel_format, src_width, total_fl);
188
189 return total_fl;
190}
191
192/**
193 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
194 * @total_fl: fill level
195 * Return: LUT setting corresponding to the fill level
196 */
197static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
198{
199 u32 qos_lut;
200
201 if (total_fl <= 4)
202 qos_lut = 0x1B;
203 else if (total_fl <= 5)
204 qos_lut = 0x5B;
205 else if (total_fl <= 6)
206 qos_lut = 0x15B;
207 else if (total_fl <= 7)
208 qos_lut = 0x55B;
209 else if (total_fl <= 8)
210 qos_lut = 0x155B;
211 else if (total_fl <= 9)
212 qos_lut = 0x555B;
213 else if (total_fl <= 10)
214 qos_lut = 0x1555B;
215 else if (total_fl <= 11)
216 qos_lut = 0x5555B;
217 else if (total_fl <= 12)
218 qos_lut = 0x15555B;
219 else
220 qos_lut = 0x55555B;
221
222 return qos_lut;
223}
224
225/**
226 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
227 * @total_fl: fill level
228 * Return: LUT setting corresponding to the fill level
229 */
230static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
231{
232 u32 qos_lut;
233
234 if (total_fl <= 10)
235 qos_lut = 0x1AAff;
236 else if (total_fl <= 11)
237 qos_lut = 0x5AAFF;
238 else if (total_fl <= 12)
239 qos_lut = 0x15AAFF;
240 else
241 qos_lut = 0x55AAFF;
242
243 return qos_lut;
244}
245
246/**
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400247 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
248 * @plane: Pointer to drm plane
249 * @fb: Pointer to framebuffer associated with the given plane
250 */
251static void _sde_plane_set_qos_lut(struct drm_plane *plane,
252 struct drm_framebuffer *fb)
253{
254 struct sde_plane *psde;
255 const struct sde_format *fmt = NULL;
256 u32 qos_lut;
257 u32 total_fl = 0;
258
259 if (!plane || !fb) {
260 SDE_ERROR("invalid arguments plane %d fb %d\n",
261 plane != 0, fb != 0);
262 return;
263 }
264
265 psde = to_sde_plane(plane);
266
267 if (!psde->pipe_hw || !psde->pipe_sblk) {
268 SDE_ERROR("invalid arguments\n");
269 return;
270 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
271 return;
272 }
273
274 if (!psde->is_rt_pipe) {
275 qos_lut = psde->pipe_sblk->creq_lut_nrt;
276 } else {
277 fmt = sde_get_sde_format_ext(
278 fb->pixel_format,
279 fb->modifier,
280 drm_format_num_planes(fb->pixel_format));
281 total_fl = _sde_plane_calc_fill_level(plane, fmt,
282 psde->pipe_cfg.src_rect.w);
283
284 if (SDE_FORMAT_IS_LINEAR(fmt))
285 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
286 else
287 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
288 }
289
290 psde->pipe_qos_cfg.creq_lut = qos_lut;
291
292 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
293 (fmt) ? fmt->base.pixel_format : 0,
294 psde->is_rt_pipe, total_fl, qos_lut,
295 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
296
297 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
298 plane->base.id,
299 psde->pipe - SSPP_VIG0,
300 (fmt) ? fmt->base.pixel_format : 0,
301 psde->is_rt_pipe, total_fl, qos_lut);
302
303 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
304}
305
306/**
307 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
308 * @plane: Pointer to drm plane
309 * @fb: Pointer to framebuffer associated with the given plane
310 */
311static void _sde_plane_set_danger_lut(struct drm_plane *plane,
312 struct drm_framebuffer *fb)
313{
314 struct sde_plane *psde;
315 const struct sde_format *fmt = NULL;
316 u32 danger_lut, safe_lut;
317
318 if (!plane || !fb) {
319 SDE_ERROR("invalid arguments\n");
320 return;
321 }
322
323 psde = to_sde_plane(plane);
324
325 if (!psde->pipe_hw || !psde->pipe_sblk) {
326 SDE_ERROR("invalid arguments\n");
327 return;
328 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
329 return;
330 }
331
332 if (!psde->is_rt_pipe) {
333 danger_lut = psde->pipe_sblk->danger_lut_nrt;
334 safe_lut = psde->pipe_sblk->safe_lut_nrt;
335 } else {
336 fmt = sde_get_sde_format_ext(
337 fb->pixel_format,
338 fb->modifier,
339 drm_format_num_planes(fb->pixel_format));
340
341 if (SDE_FORMAT_IS_LINEAR(fmt)) {
342 danger_lut = psde->pipe_sblk->danger_lut_linear;
343 safe_lut = psde->pipe_sblk->safe_lut_linear;
344 } else {
345 danger_lut = psde->pipe_sblk->danger_lut_tile;
346 safe_lut = psde->pipe_sblk->safe_lut_tile;
347 }
348 }
349
350 psde->pipe_qos_cfg.danger_lut = danger_lut;
351 psde->pipe_qos_cfg.safe_lut = safe_lut;
352
353 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
354 (fmt) ? fmt->base.pixel_format : 0,
355 (fmt) ? fmt->fetch_mode : 0,
356 psde->pipe_qos_cfg.danger_lut,
357 psde->pipe_qos_cfg.safe_lut);
358
359 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
360 plane->base.id,
361 psde->pipe - SSPP_VIG0,
362 fmt ? fmt->base.pixel_format : 0,
363 fmt ? fmt->fetch_mode : -1,
364 psde->pipe_qos_cfg.danger_lut,
365 psde->pipe_qos_cfg.safe_lut);
366
367 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
368 &psde->pipe_qos_cfg);
369}
370
371/**
372 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
373 * @plane: Pointer to drm plane
374 * @enable: true to enable QoS control
375 * @flags: QoS control mode (enum sde_plane_qos)
376 */
377static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
378 bool enable, u32 flags)
379{
380 struct sde_plane *psde;
381
382 if (!plane) {
383 SDE_ERROR("invalid arguments\n");
384 return;
385 }
386
387 psde = to_sde_plane(plane);
388
389 if (!psde->pipe_hw || !psde->pipe_sblk) {
390 SDE_ERROR("invalid arguments\n");
391 return;
392 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
393 return;
394 }
395
396 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
397 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
398 psde->pipe_qos_cfg.danger_vblank =
399 psde->pipe_sblk->danger_vblank;
400 psde->pipe_qos_cfg.vblank_en = enable;
401 }
402
403 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
404 /* this feature overrules previous VBLANK_CTRL */
405 psde->pipe_qos_cfg.vblank_en = false;
406 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
407 }
408
409 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
410 psde->pipe_qos_cfg.danger_safe_en = enable;
411
412 if (!psde->is_rt_pipe) {
413 psde->pipe_qos_cfg.vblank_en = false;
414 psde->pipe_qos_cfg.danger_safe_en = false;
415 }
416
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400417 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400418 plane->base.id,
419 psde->pipe - SSPP_VIG0,
420 psde->pipe_qos_cfg.danger_safe_en,
421 psde->pipe_qos_cfg.vblank_en,
422 psde->pipe_qos_cfg.creq_vblank,
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400423 psde->pipe_qos_cfg.danger_vblank,
424 psde->is_rt_pipe);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400425
426 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
427 &psde->pipe_qos_cfg);
428}
429
Alan Kwongf0fd8512016-10-24 21:39:26 -0400430int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
431{
432 struct sde_plane *psde;
433 struct msm_drm_private *priv;
434 struct sde_kms *sde_kms;
435
436 if (!plane || !plane->dev) {
437 SDE_ERROR("invalid arguments\n");
438 return -EINVAL;
439 }
440
441 priv = plane->dev->dev_private;
442 if (!priv || !priv->kms) {
443 SDE_ERROR("invalid KMS reference\n");
444 return -EINVAL;
445 }
446
447 sde_kms = to_sde_kms(priv->kms);
448 psde = to_sde_plane(plane);
449
450 if (!psde->is_rt_pipe)
451 goto end;
452
453 sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
454
455 _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
456
457 sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
458
459end:
460 return 0;
461}
462
Alan Kwong5d324e42016-07-28 22:56:18 -0400463/**
464 * _sde_plane_set_ot_limit - set OT limit for the given plane
465 * @plane: Pointer to drm plane
466 * @crtc: Pointer to drm crtc
467 */
468static void _sde_plane_set_ot_limit(struct drm_plane *plane,
469 struct drm_crtc *crtc)
470{
471 struct sde_plane *psde;
472 struct sde_vbif_set_ot_params ot_params;
473 struct msm_drm_private *priv;
474 struct sde_kms *sde_kms;
475
476 if (!plane || !plane->dev || !crtc) {
477 SDE_ERROR("invalid arguments plane %d crtc %d\n",
478 plane != 0, crtc != 0);
479 return;
480 }
481
482 priv = plane->dev->dev_private;
483 if (!priv || !priv->kms) {
484 SDE_ERROR("invalid KMS reference\n");
485 return;
486 }
487
488 sde_kms = to_sde_kms(priv->kms);
489 psde = to_sde_plane(plane);
490 if (!psde->pipe_hw) {
491 SDE_ERROR("invalid pipe reference\n");
492 return;
493 }
494
495 memset(&ot_params, 0, sizeof(ot_params));
496 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
497 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
498 ot_params.width = psde->pipe_cfg.src_rect.w;
499 ot_params.height = psde->pipe_cfg.src_rect.h;
500 ot_params.is_wfd = !psde->is_rt_pipe;
501 ot_params.frame_rate = crtc->mode.vrefresh;
502 ot_params.vbif_idx = VBIF_RT;
503 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
504 ot_params.rd = true;
505
506 sde_vbif_set_ot_limit(sde_kms, &ot_params);
507}
508
Clarence Ipcae1bb62016-07-07 12:07:13 -0400509/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400510static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400511 struct sde_plane_state *pstate, uint64_t fd)
512{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400513 if (!psde || !pstate) {
514 SDE_ERROR("invalid arg(s), plane %d state %d\n",
515 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400516 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400517 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400518
519 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400520 if (pstate->input_fence)
521 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400522
523 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400524 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400525
Clarence Ip13a8cf42016-09-29 17:27:47 -0400526 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400527}
528
Clarence Ipcae1bb62016-07-07 12:07:13 -0400529int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400530{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400531 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400532 struct sde_plane_state *pstate;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400533 uint32_t prefix;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400534 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400535 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400536
537 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700538 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400539 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400540 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400541 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400542 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400543 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400544 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400545
Clarence Ipcae1bb62016-07-07 12:07:13 -0400546 if (input_fence) {
Clarence Ip78a04ed2016-10-04 15:57:45 -0400547 prefix = sde_sync_get_name_prefix(input_fence);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400548 ret = sde_sync_wait(input_fence, wait_ms);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400549
Lloyd Atkinson5d40d312016-09-06 08:34:13 -0400550 SDE_EVT32(DRMID(plane), -ret, prefix);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400551
Clarence Ipcae1bb62016-07-07 12:07:13 -0400552 switch (ret) {
553 case 0:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400554 SDE_DEBUG_PLANE(psde, "signaled\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400555 break;
556 case -ETIME:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400557 SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
558 wait_ms, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400559 psde->is_error = true;
560 break;
561 default:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400562 SDE_ERROR_PLANE(psde, "error %d on %08X\n",
563 ret, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400564 psde->is_error = true;
565 break;
566 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400567 } else {
568 ret = 0;
569 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400570 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400571 return ret;
572}
573
Clarence Ip282dad62016-09-27 17:07:35 -0400574static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400575 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400576 struct sde_hw_pipe_cfg *pipe_cfg,
577 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400578{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400579 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400580 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400581
Clarence Ip13a8cf42016-09-29 17:27:47 -0400582 if (!plane || !pstate || !pipe_cfg || !fb) {
583 SDE_ERROR(
584 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
585 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400586 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400587 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400588
589 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400590 if (!psde->pipe_hw) {
591 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400592 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400593 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400594
Clarence Ipb6eb2362016-09-08 16:18:13 -0400595 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
596 if (ret == -EAGAIN)
597 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
598 else if (ret)
599 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
600 else if (psde->pipe_hw->ops.setup_sourceaddress)
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800601 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
602 pstate->multirect_index);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400603}
604
abeykun48f407a2016-08-25 12:06:44 -0400605static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
606 struct sde_plane_state *pstate)
607{
608 struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg;
609 int ret = 0;
610
611 cfg->dir_lut = msm_property_get_blob(
612 &psde->property_info,
613 pstate->property_blobs, &cfg->dir_len,
614 PLANE_PROP_SCALER_LUT_ED);
615 cfg->cir_lut = msm_property_get_blob(
616 &psde->property_info,
617 pstate->property_blobs, &cfg->cir_len,
618 PLANE_PROP_SCALER_LUT_CIR);
619 cfg->sep_lut = msm_property_get_blob(
620 &psde->property_info,
621 pstate->property_blobs, &cfg->sep_len,
622 PLANE_PROP_SCALER_LUT_SEP);
623 if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
624 ret = -ENODATA;
625 return ret;
626}
627
Clarence Ipcb410d42016-06-26 22:52:33 -0400628static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400629 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
630 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400631 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400632 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
633{
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -0700634 uint32_t decimated, i;
635
636 if (!psde || !scale_cfg || !fmt || !chroma_subsmpl_h ||
637 !chroma_subsmpl_v) {
638 SDE_ERROR("psde %pK scale_cfg %pK fmt %pK smp_h %d smp_v %d\n"
639 , psde, scale_cfg, fmt, chroma_subsmpl_h,
640 chroma_subsmpl_v);
641 return;
642 }
643
644 memset(scale_cfg, 0, sizeof(*scale_cfg));
645
646 decimated = DECIMATED_DIMENSION(src_w,
647 psde->pipe_cfg.horz_decimation);
648 scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
649 mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
650 decimated = DECIMATED_DIMENSION(src_h,
651 psde->pipe_cfg.vert_decimation);
652 scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
653 mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
654
655
656 scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
657 scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
658 scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
659 scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
660
661 scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
662 scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
663 scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
664 scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
665
666 scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
667 scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
668 scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
669 scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
670
671 for (i = 0; i < SDE_MAX_PLANES; i++) {
672 scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
673 psde->pipe_cfg.horz_decimation);
674 scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h,
675 psde->pipe_cfg.vert_decimation);
676 if (SDE_FORMAT_IS_YUV(fmt))
677 scale_cfg->src_width[i] &= ~0x1;
678 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
679 scale_cfg->src_width[i] /= chroma_subsmpl_h;
680 scale_cfg->src_height[i] /= chroma_subsmpl_v;
681 }
682 scale_cfg->preload_x[i] = SDE_QSEED3_DEFAULT_PRELOAD_H;
683 scale_cfg->preload_y[i] = SDE_QSEED3_DEFAULT_PRELOAD_V;
684 psde->pixel_ext.num_ext_pxls_top[i] =
685 scale_cfg->src_height[i];
686 psde->pixel_ext.num_ext_pxls_left[i] =
687 scale_cfg->src_width[i];
688 }
689 if (!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
690 && (src_w == dst_w))
691 return;
692
693 scale_cfg->dst_width = dst_w;
694 scale_cfg->dst_height = dst_h;
695 scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
696 scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
697 scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
698 scale_cfg->lut_flag = 0;
699 scale_cfg->blend_cfg = 1;
700 scale_cfg->enable = 1;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400701}
702
Clarence Ipcb410d42016-06-26 22:52:33 -0400703/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400704 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400705 * @psde: Pointer to SDE plane object
706 * @src: Source size
707 * @dst: Destination size
708 * @phase_steps: Pointer to output array for phase steps
709 * @filter: Pointer to output array for filter type
710 * @fmt: Pointer to format definition
711 * @chroma_subsampling: Subsampling amount for chroma channel
712 *
713 * Returns: 0 on success
714 */
715static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400716 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400717 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400718 uint32_t chroma_subsampling)
719{
Clarence Ipcb410d42016-06-26 22:52:33 -0400720 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400721 SDE_ERROR(
722 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
723 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400724 return -EINVAL;
725 }
726
Clarence Ip4c1d9772016-06-26 09:35:38 -0400727 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400728 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400729 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400730 phase_steps[SDE_SSPP_COMP_1_2] =
731 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
732 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
733 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400734
735 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400736 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400737 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400738 (src <= dst) ? SDE_SCALE_FILTER_BIL :
739 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400740
Clarence Ipdbde9832016-06-26 09:48:36 -0400741 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400742 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400743 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
744 } else {
745 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
746 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400747 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400748 }
749 } else {
750 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400751 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
752 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
753 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400754 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400755 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400756}
757
Clarence Ipcb410d42016-06-26 22:52:33 -0400758/**
759 * _sde_plane_setup_pixel_ext - determine default pixel extension values
760 * @psde: Pointer to SDE plane object
761 * @src: Source size
762 * @dst: Destination size
763 * @decimated_src: Source size after decimation, if any
764 * @phase_steps: Pointer to output array for phase steps
765 * @out_src: Output array for pixel extension values
766 * @out_edge1: Output array for pixel extension first edge
767 * @out_edge2: Output array for pixel extension second edge
768 * @filter: Pointer to array for filter type
769 * @fmt: Pointer to format definition
770 * @chroma_subsampling: Subsampling amount for chroma channel
771 * @post_compare: Whether to chroma subsampled source size for comparisions
772 */
773static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400774 uint32_t src, uint32_t dst, uint32_t decimated_src,
775 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400776 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400777 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400778 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400779{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400780 int64_t edge1, edge2, caf;
781 uint32_t src_work;
782 int i, tmp;
783
Clarence Ipcb410d42016-06-26 22:52:33 -0400784 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400785 out_edge2 && filter && fmt) {
786 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400787 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400788 caf = PHASE_STEP_UNIT_SCALE;
789 else
790 caf = 0;
791
792 for (i = 0; i < SDE_MAX_PLANES; i++) {
793 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400794 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400795 src_work /= chroma_subsampling;
796 if (post_compare)
797 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400798 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400799 /* unity */
800 edge1 = 0;
801 edge2 = 0;
802 } else if (dst >= src) {
803 /* upscale */
804 edge1 = (1 << PHASE_RESIDUAL);
805 edge1 -= caf;
806 edge2 = (1 << PHASE_RESIDUAL);
807 edge2 += (dst - 1) * *(phase_steps + i);
808 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
809 edge2 += caf;
810 edge2 = -(edge2);
811 } else {
812 /* downscale */
813 edge1 = 0;
814 edge2 = (dst - 1) * *(phase_steps + i);
815 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
816 edge2 += *(phase_steps + i);
817 edge2 = -(edge2);
818 }
819
820 /* only enable CAF for luma plane */
821 caf = 0;
822
823 /* populate output arrays */
824 *(out_src + i) = src_work;
825
826 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400827 if (edge1 >= 0) {
828 tmp = (uint32_t)edge1;
829 tmp >>= PHASE_STEP_SHIFT;
830 *(out_edge1 + i) = -tmp;
831 } else {
832 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400833 *(out_edge1 + i) =
834 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
835 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400836 }
837 if (edge2 >= 0) {
838 tmp = (uint32_t)edge2;
839 tmp >>= PHASE_STEP_SHIFT;
840 *(out_edge2 + i) = -tmp;
841 } else {
842 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400843 *(out_edge2 + i) =
844 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
845 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400846 }
847 }
848 }
849}
850
Clarence Ip5fc00c52016-09-23 15:03:34 -0400851static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400852{
853 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
854 {
Clarence Ip373f8592016-05-26 00:58:42 -0400855 /* S15.16 format */
856 0x00012A00, 0x00000000, 0x00019880,
857 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
858 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400859 },
Clarence Ip373f8592016-05-26 00:58:42 -0400860 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400861 { 0xfff0, 0xff80, 0xff80,},
862 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400863 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400864 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400865 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400866 };
abeykun1c312f62016-08-26 09:47:12 -0400867 static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
868 {
869 /* S15.16 format */
870 0x00012A00, 0x00000000, 0x00019880,
871 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
872 0x00012A00, 0x00020480, 0x00000000,
873 },
874 /* signed bias */
875 { 0xffc0, 0xfe00, 0xfe00,},
876 { 0x0, 0x0, 0x0,},
877 /* unsigned clamp */
878 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
879 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
880 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400881
Clarence Ip5fc00c52016-09-23 15:03:34 -0400882 if (!psde) {
883 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400884 return;
885 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400886
Clarence Ipcae1bb62016-07-07 12:07:13 -0400887 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400888 if (psde->csc_usr_ptr)
889 psde->csc_ptr = psde->csc_usr_ptr;
abeykun1c312f62016-08-26 09:47:12 -0400890 else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
891 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400892 else
Clarence Ip373f8592016-05-26 00:58:42 -0400893 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400894
Clarence Ip13a8cf42016-09-29 17:27:47 -0400895 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400896 psde->csc_ptr->csc_mv[0],
897 psde->csc_ptr->csc_mv[1],
898 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400899}
900
Benet Clarkeb1b4462016-06-27 14:43:06 -0700901static void sde_color_process_plane_setup(struct drm_plane *plane)
902{
903 struct sde_plane *psde;
904 struct sde_plane_state *pstate;
905 uint32_t hue, saturation, value, contrast;
Benet Clarkd009b1d2016-06-27 14:45:59 -0700906 struct drm_msm_memcol *memcol = NULL;
907 size_t memcol_sz = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -0700908
909 psde = to_sde_plane(plane);
910 pstate = to_sde_plane_state(plane->state);
911
912 hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
913 if (psde->pipe_hw->ops.setup_pa_hue)
914 psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
915 saturation = (uint32_t) sde_plane_get_property(pstate,
916 PLANE_PROP_SATURATION_ADJUST);
917 if (psde->pipe_hw->ops.setup_pa_sat)
918 psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
919 value = (uint32_t) sde_plane_get_property(pstate,
920 PLANE_PROP_VALUE_ADJUST);
921 if (psde->pipe_hw->ops.setup_pa_val)
922 psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
923 contrast = (uint32_t) sde_plane_get_property(pstate,
924 PLANE_PROP_CONTRAST_ADJUST);
925 if (psde->pipe_hw->ops.setup_pa_cont)
926 psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
Benet Clarkeb1b4462016-06-27 14:43:06 -0700927
Benet Clarkd009b1d2016-06-27 14:45:59 -0700928 if (psde->pipe_hw->ops.setup_pa_memcolor) {
929 /* Skin memory color setup */
930 memcol = msm_property_get_blob(&psde->property_info,
931 pstate->property_blobs,
932 &memcol_sz,
933 PLANE_PROP_SKIN_COLOR);
934 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
935 MEMCOLOR_SKIN, memcol);
936
937 /* Sky memory color setup */
938 memcol = msm_property_get_blob(&psde->property_info,
939 pstate->property_blobs,
940 &memcol_sz,
941 PLANE_PROP_SKY_COLOR);
942 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
943 MEMCOLOR_SKY, memcol);
944
945 /* Foliage memory color setup */
946 memcol = msm_property_get_blob(&psde->property_info,
947 pstate->property_blobs,
948 &memcol_sz,
949 PLANE_PROP_FOLIAGE_COLOR);
950 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
951 MEMCOLOR_FOLIAGE, memcol);
952 }
953}
Benet Clarkeb1b4462016-06-27 14:43:06 -0700954
Clarence Ipcb410d42016-06-26 22:52:33 -0400955static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400956 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400957 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700958{
Clarence Ipb43d4592016-09-08 14:21:35 -0400959 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -0400960 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400961
Clarence Ipb43d4592016-09-08 14:21:35 -0400962 if (!psde || !fmt) {
963 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
964 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400965 return;
Clarence Ipb43d4592016-09-08 14:21:35 -0400966 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400967
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400968 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400969
Clarence Ipdedbba92016-09-27 17:43:10 -0400970 psde->pipe_cfg.horz_decimation =
971 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
972 psde->pipe_cfg.vert_decimation =
973 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400974
975 /* don't chroma subsample if decimating */
976 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400977 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400978 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400979 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400980
Clarence Ip5e2a9222016-06-26 22:38:24 -0400981 /* update scaler */
982 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
abeykun48f407a2016-08-25 12:06:44 -0400983 int error;
984
985 error = _sde_plane_setup_scaler3_lut(psde, pstate);
986 if (error || !psde->pixel_ext_usr) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400987 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -0400988 _sde_plane_setup_scaler3(psde,
989 psde->pipe_cfg.src_rect.w,
990 psde->pipe_cfg.src_rect.h,
991 psde->pipe_cfg.dst_rect.w,
992 psde->pipe_cfg.dst_rect.h,
abeykun48f407a2016-08-25 12:06:44 -0400993 psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400994 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400995 }
Clarence Ipb43d4592016-09-08 14:21:35 -0400996 } else if (!psde->pixel_ext_usr) {
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -0500997 uint32_t deci_dim, i;
998
Clarence Ipb43d4592016-09-08 14:21:35 -0400999 /* calculate default configuration for QSEED2 */
1000 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001001
Clarence Ip13a8cf42016-09-29 17:27:47 -04001002 SDE_DEBUG_PLANE(psde, "default config\n");
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001003 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
1004 psde->pipe_cfg.horz_decimation);
Clarence Ipb43d4592016-09-08 14:21:35 -04001005 _sde_plane_setup_scaler2(psde,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001006 deci_dim,
Clarence Ipb43d4592016-09-08 14:21:35 -04001007 psde->pipe_cfg.dst_rect.w,
1008 pe->phase_step_x,
1009 pe->horz_filter, fmt, chroma_subsmpl_h);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001010
Clarence Ipdbde9832016-06-26 09:48:36 -04001011 if (SDE_FORMAT_IS_YUV(fmt))
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001012 deci_dim &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -04001013 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001014 psde->pipe_cfg.dst_rect.w, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001015 pe->phase_step_x,
1016 pe->roi_w,
1017 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -04001018 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001019 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001020
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001021 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001022 psde->pipe_cfg.vert_decimation);
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001023 _sde_plane_setup_scaler2(psde,
1024 deci_dim,
1025 psde->pipe_cfg.dst_rect.h,
1026 pe->phase_step_y,
1027 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ipcb410d42016-06-26 22:52:33 -04001028 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001029 psde->pipe_cfg.dst_rect.h, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001030 pe->phase_step_y,
1031 pe->roi_h,
1032 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -04001033 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001034 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001035
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001036 for (i = 0; i < SDE_MAX_PLANES; i++) {
1037 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001038 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001039 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001040 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001041
1042 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001043 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001044 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001045 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001046
1047 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001048 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001049 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001050 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001051
1052 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001053 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001054 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001055 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001056 }
1057 }
Clarence Ipcb410d42016-06-26 22:52:33 -04001058}
1059
Clarence Ipcae1bb62016-07-07 12:07:13 -04001060/**
1061 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -04001062 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -04001063 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
1064 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
1065 * Returns: 0 on success
1066 */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001067static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -04001068 uint32_t color, uint32_t alpha)
1069{
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001070 const struct sde_format *fmt;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001071 const struct drm_plane *plane;
1072 const struct sde_plane_state *pstate;
Clarence Ipcb410d42016-06-26 22:52:33 -04001073
Clarence Ip13a8cf42016-09-29 17:27:47 -04001074 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001075 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001076 return -EINVAL;
1077 }
1078
Clarence Ipcb410d42016-06-26 22:52:33 -04001079 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001080 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001081 return -EINVAL;
1082 }
1083
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001084 plane = &psde->base;
1085 pstate = to_sde_plane_state(plane->state);
1086
Clarence Ip13a8cf42016-09-29 17:27:47 -04001087 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001088
Clarence Ipcb410d42016-06-26 22:52:33 -04001089 /*
1090 * select fill format to match user property expectation,
1091 * h/w only supports RGB variants
1092 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001093 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -04001094
1095 /* update sspp */
1096 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
1097 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001098 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
1099 pstate->multirect_index);
Clarence Ipcb410d42016-06-26 22:52:33 -04001100
1101 /* override scaler/decimation if solid fill */
1102 psde->pipe_cfg.src_rect.x = 0;
1103 psde->pipe_cfg.src_rect.y = 0;
1104 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
1105 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
1106
Clarence Ipcb410d42016-06-26 22:52:33 -04001107 if (psde->pipe_hw->ops.setup_format)
1108 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001109 fmt, SDE_SSPP_SOLID_FILL,
1110 pstate->multirect_index);
Clarence Ipcb410d42016-06-26 22:52:33 -04001111
1112 if (psde->pipe_hw->ops.setup_rects)
1113 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08001114 &psde->pipe_cfg,
1115 pstate->multirect_index);
1116
1117 _sde_plane_setup_scaler(psde, fmt, 0);
1118 if (psde->pipe_hw->ops.setup_pe)
1119 psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
1120 &psde->pixel_ext);
Clarence Ipcb410d42016-06-26 22:52:33 -04001121 }
1122
1123 return 0;
1124}
1125
1126static int _sde_plane_mode_set(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001127 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -04001128{
Clarence Ipc47a0692016-10-11 10:54:17 -04001129 uint32_t nplanes, src_flags;
Clarence Ipcb410d42016-06-26 22:52:33 -04001130 struct sde_plane *psde;
1131 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001132 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001133 struct drm_crtc *crtc;
1134 struct drm_framebuffer *fb;
1135 struct sde_rect src, dst;
1136 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001137 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -04001138
Clarence Ip13a8cf42016-09-29 17:27:47 -04001139 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -04001140 SDE_ERROR("invalid plane\n");
1141 return -EINVAL;
1142 } else if (!plane->state) {
1143 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001144 return -EINVAL;
1145 }
1146
1147 psde = to_sde_plane(plane);
1148 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -04001149
Dhaval Patel47302cf2016-08-18 15:04:28 -07001150 crtc = state->crtc;
1151 fb = state->fb;
1152 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001153 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
1154 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -07001155 return -EINVAL;
1156 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001157 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001158 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -04001159
Clarence Ip282dad62016-09-27 17:07:35 -04001160 /* determine what needs to be refreshed */
1161 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
1162 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -04001163 case PLANE_PROP_SCALER_V1:
abeykun48f407a2016-08-25 12:06:44 -04001164 case PLANE_PROP_SCALER_V2:
Clarence Ipdedbba92016-09-27 17:43:10 -04001165 case PLANE_PROP_H_DECIMATE:
1166 case PLANE_PROP_V_DECIMATE:
1167 case PLANE_PROP_SRC_CONFIG:
1168 case PLANE_PROP_ZPOS:
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001169 case PLANE_PROP_EXCL_RECT_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04001170 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1171 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001172 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04001173 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
1174 break;
1175 case PLANE_PROP_COLOR_FILL:
1176 /* potentially need to refresh everything */
1177 pstate->dirty = SDE_PLANE_DIRTY_ALL;
1178 break;
1179 case PLANE_PROP_ROTATION:
1180 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
1181 break;
Clarence Ip282dad62016-09-27 17:07:35 -04001182 case PLANE_PROP_INFO:
1183 case PLANE_PROP_ALPHA:
1184 case PLANE_PROP_INPUT_FENCE:
1185 case PLANE_PROP_BLEND_OP:
1186 /* no special action required */
1187 break;
1188 default:
1189 /* unknown property, refresh everything */
1190 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
1191 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
1192 break;
1193 }
Clarence Ipcb410d42016-06-26 22:52:33 -04001194 }
1195
Clarence Ip282dad62016-09-27 17:07:35 -04001196 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
1197 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -04001198
1199 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
1200
Clarence Ip282dad62016-09-27 17:07:35 -04001201 /* early out if nothing dirty */
1202 if (!pstate->dirty)
1203 return 0;
1204 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001205
Dhaval Patel4d424602017-02-18 19:40:14 -08001206 psde->is_rt_pipe = (sde_crtc_get_client_type(crtc) != NRT_CLIENT);
Clarence Ip282dad62016-09-27 17:07:35 -04001207 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1208
1209 /* update roi config */
1210 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
1211 POPULATE_RECT(&src, state->src_x, state->src_y,
1212 state->src_w, state->src_h, q16_data);
1213 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
1214 state->crtc_w, state->crtc_h, !q16_data);
1215
Clarence Ip13a8cf42016-09-29 17:27:47 -04001216 SDE_DEBUG_PLANE(psde,
1217 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001218 fb->base.id, src.x, src.y, src.w, src.h,
1219 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
1220 drm_get_format_name(fmt->base.pixel_format),
1221 SDE_FORMAT_IS_UBWC(fmt));
1222
1223 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
1224 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001225 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001226 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
1227 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
1228 src.h /= 2;
1229 src.y = DIV_ROUND_UP(src.y, 2);
1230 src.y &= ~0x1;
1231 }
1232
1233 psde->pipe_cfg.src_rect = src;
1234 psde->pipe_cfg.dst_rect = dst;
1235
1236 /* check for color fill */
1237 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
1238 PLANE_PROP_COLOR_FILL);
1239 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
1240 /* skip remaining processing on color fill */
1241 pstate->dirty = 0x0;
1242 } else if (psde->pipe_hw->ops.setup_rects) {
Clarence Ip282dad62016-09-27 17:07:35 -04001243 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08001244 &psde->pipe_cfg,
1245 pstate->multirect_index);
Clarence Ip282dad62016-09-27 17:07:35 -04001246 }
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001247
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08001248 _sde_plane_setup_scaler(psde, fmt, pstate);
1249 if (psde->pipe_hw->ops.setup_pe)
1250 psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
1251 &psde->pixel_ext);
1252
1253 if (psde->pipe_hw->ops.setup_scaler)
1254 psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
1255 &psde->pipe_cfg, &psde->pixel_ext,
1256 psde->scaler3_cfg);
1257
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001258 /* update excl rect */
1259 if (psde->pipe_hw->ops.setup_excl_rect)
1260 psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001261 &pstate->excl_rect,
1262 pstate->multirect_index);
1263
1264 if (psde->pipe_hw->ops.setup_multirect)
1265 psde->pipe_hw->ops.setup_multirect(
1266 psde->pipe_hw,
1267 pstate->multirect_index,
1268 pstate->multirect_mode);
Dhaval Patel48c76022016-09-01 17:51:23 -07001269 }
1270
Clarence Ip282dad62016-09-27 17:07:35 -04001271 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
1272 psde->pipe_hw->ops.setup_format) {
1273 src_flags = 0x0;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001274 SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001275 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
1276 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1277 BIT(DRM_REFLECT_X))
1278 src_flags |= SDE_SSPP_FLIP_LR;
1279 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1280 BIT(DRM_REFLECT_Y))
1281 src_flags |= SDE_SSPP_FLIP_UD;
1282
1283 /* update format */
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001284 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags,
1285 pstate->multirect_index);
Clarence Ip282dad62016-09-27 17:07:35 -04001286
1287 /* update csc */
1288 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04001289 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04001290 else
1291 psde->csc_ptr = 0;
1292 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001293
Benet Clarkeb1b4462016-06-27 14:43:06 -07001294 sde_color_process_plane_setup(plane);
1295
Clarence Ipe78efb72016-06-24 18:35:21 -04001296 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04001297 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
1298 psde->pipe_hw->ops.setup_sharpening) {
1299 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
1300 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
1301 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
1302 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04001303
Clarence Ipe78efb72016-06-24 18:35:21 -04001304 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04001305 &psde->sharp_cfg);
1306 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001307
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001308 _sde_plane_set_qos_lut(plane, fb);
1309 _sde_plane_set_danger_lut(plane, fb);
1310
Alan Kwong5d324e42016-07-28 22:56:18 -04001311 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001312 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04001313 _sde_plane_set_ot_limit(plane, crtc);
1314 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001315
Clarence Ip282dad62016-09-27 17:07:35 -04001316 /* clear dirty */
1317 pstate->dirty = 0x0;
1318
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001319 /* clear multirect mode*/
1320 pstate->multirect_index = SDE_SSPP_RECT_SOLO;
1321 pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
1322 return 0;
1323}
1324
1325int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
1326{
1327 struct sde_plane_state *pstate[R_MAX];
1328 const struct drm_plane_state *drm_state[R_MAX];
1329 struct sde_rect src[R_MAX], dst[R_MAX];
1330 struct sde_plane *sde_plane[R_MAX];
1331 const struct sde_format *fmt[R_MAX];
1332 bool q16_data = true;
1333 int i, max_sspp_linewidth;
1334 int buffer_lines = TX_MODE_BUFFER_LINE_THRES;
1335
1336 for (i = 0; i < R_MAX; i++) {
1337 const struct msm_format *msm_fmt;
1338
1339 drm_state[i] = i ? plane->r1 : plane->r0;
1340 pstate[i] = to_sde_plane_state(drm_state[i]);
1341 sde_plane[i] = to_sde_plane(drm_state[i]->plane);
1342
1343 if (pstate[i] == NULL) {
1344 SDE_ERROR("SDE plane state of plane id %d is NULL\n",
1345 drm_state[i]->plane->base.id);
1346 return -EINVAL;
1347 }
1348
1349 POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
1350 drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
1351 POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
1352 drm_state[i]->crtc_y, drm_state[i]->crtc_w,
1353 drm_state[i]->crtc_h, !q16_data);
1354
1355 if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
1356 SDE_ERROR_PLANE(sde_plane[i],
1357 "scaling is not supported in multirect mode\n");
1358 return -EINVAL;
1359 }
1360
1361 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
1362 fmt[i] = to_sde_format(msm_fmt);
1363 if (SDE_FORMAT_IS_YUV(fmt[i])) {
1364 SDE_ERROR_PLANE(sde_plane[i],
1365 "Unsupported format for multirect mode\n");
1366 return -EINVAL;
1367 }
1368 }
1369
1370 max_sspp_linewidth = sde_plane[R0]->pipe_sblk->maxlinewidth;
1371
1372 /* Validate RECT's and set the mode */
1373
1374 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
1375 if (src[R0].w <= max_sspp_linewidth/2 &&
1376 src[R1].w <= max_sspp_linewidth/2) {
1377 if (dst[R0].x <= dst[R1].x) {
1378 pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
1379 pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
1380 } else {
1381 pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
1382 pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
1383 }
1384
1385 pstate[R0]->multirect_mode = SDE_SSPP_MULTIRECT_PARALLEL;
1386 pstate[R1]->multirect_mode = SDE_SSPP_MULTIRECT_PARALLEL;
1387 goto done;
1388 }
1389
1390 /* TIME_MX Mode */
1391 if (SDE_FORMAT_IS_UBWC(fmt[R0]))
1392 buffer_lines = 2 * fmt[R0]->tile_height;
1393
1394 if (dst[R1].y >= dst[R0].y + dst[R0].h + buffer_lines) {
1395 pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
1396 pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
1397 } else if (dst[R0].y >= dst[R1].y + dst[R1].h + buffer_lines) {
1398 pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
1399 pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
1400 } else {
1401 SDE_ERROR(
1402 "No multirect mode possible for the planes (%d - %d)\n",
1403 drm_state[R0]->plane->base.id,
1404 drm_state[R1]->plane->base.id);
1405 return -EINVAL;
1406 }
1407
1408 pstate[R0]->multirect_mode = SDE_SSPP_MULTIRECT_TIME_MX;
1409 pstate[R1]->multirect_mode = SDE_SSPP_MULTIRECT_TIME_MX;
1410done:
Clarence Ip5e2a9222016-06-26 22:38:24 -04001411 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001412}
1413
1414static int sde_plane_prepare_fb(struct drm_plane *plane,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001415 struct drm_plane_state *new_state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001416{
1417 struct drm_framebuffer *fb = new_state->fb;
1418 struct sde_plane *psde = to_sde_plane(plane);
1419
1420 if (!new_state->fb)
1421 return 0;
1422
Clarence Ip13a8cf42016-09-29 17:27:47 -04001423 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001424 return msm_framebuffer_prepare(fb, psde->mmu_id);
1425}
1426
1427static void sde_plane_cleanup_fb(struct drm_plane *plane,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001428 struct drm_plane_state *old_state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001429{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001430 struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
1431 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001432
1433 if (!fb)
1434 return;
1435
Clarence Ip13a8cf42016-09-29 17:27:47 -04001436 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001437 msm_framebuffer_cleanup(fb, psde->mmu_id);
1438}
1439
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001440static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
1441 struct drm_plane_state *state,
1442 struct drm_plane_state *old_state)
1443{
1444 struct sde_plane_state *pstate = to_sde_plane_state(state);
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001445 struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001446
Dhaval Patel47302cf2016-08-18 15:04:28 -07001447 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04001448 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001449 return;
1450
Clarence Ip282dad62016-09-27 17:07:35 -04001451 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
1452 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001453 SDE_DEBUG_PLANE(psde,
1454 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001455 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001456 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001457 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001458 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001459 } else if (state->src_w != old_state->src_w ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07001460 state->src_h != old_state->src_h ||
1461 state->src_x != old_state->src_x ||
1462 state->src_y != old_state->src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001463 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001464 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001465 } else if (state->crtc_w != old_state->crtc_w ||
1466 state->crtc_h != old_state->crtc_h ||
1467 state->crtc_x != old_state->crtc_x ||
1468 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001469 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001470 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001471 } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
1472 pstate->excl_rect.h != old_pstate->excl_rect.h ||
1473 pstate->excl_rect.x != old_pstate->excl_rect.x ||
1474 pstate->excl_rect.y != old_pstate->excl_rect.y) {
1475 SDE_DEBUG_PLANE(psde, "excl rect updated\n");
1476 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001477 } else if (pstate->multirect_index != old_pstate->multirect_index ||
1478 pstate->multirect_mode != old_pstate->multirect_mode) {
1479 SDE_DEBUG_PLANE(psde, "multirect config updated\n");
1480 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Clarence Ip282dad62016-09-27 17:07:35 -04001481 }
1482
1483 if (!state->fb || !old_state->fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001484 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001485 } else if (state->fb->pixel_format != old_state->fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001486 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001487 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001488 } else {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001489 uint64_t *new_mods = state->fb->modifier;
1490 uint64_t *old_mods = old_state->fb->modifier;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001491 uint32_t *new_pitches = state->fb->pitches;
1492 uint32_t *old_pitches = old_state->fb->pitches;
1493 uint32_t *new_offset = state->fb->offsets;
1494 uint32_t *old_offset = old_state->fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001495 int i;
1496
1497 for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
1498 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001499 SDE_DEBUG_PLANE(psde,
1500 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001501 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001502 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001503 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1504 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001505 break;
1506 }
1507 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001508 for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
1509 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001510 SDE_DEBUG_PLANE(psde,
1511 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001512 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001513 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001514 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001515 break;
1516 }
1517 }
Dhaval Patel47302cf2016-08-18 15:04:28 -07001518 for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
1519 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001520 SDE_DEBUG_PLANE(psde,
1521 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001522 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001523 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001524 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1525 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001526 break;
1527 }
1528 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001529 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001530}
1531
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001532static int sde_plane_atomic_check(struct drm_plane *plane,
1533 struct drm_plane_state *state)
1534{
Clarence Ipdedbba92016-09-27 17:43:10 -04001535 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04001536 struct sde_plane *psde;
1537 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001538 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001539 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04001540 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001541 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
1542 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04001543
1544 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001545 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1546 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04001547 ret = -EINVAL;
1548 goto exit;
1549 }
1550
1551 psde = to_sde_plane(plane);
1552 pstate = to_sde_plane_state(state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001553
1554 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001555 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001556 ret = -EINVAL;
1557 goto exit;
1558 }
1559
Clarence Ipdedbba92016-09-27 17:43:10 -04001560 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1561 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04001562
1563 /* src values are in Q16 fixed point, convert to integer */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001564 POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
1565 state->src_h, q16_data);
1566 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
1567 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04001568
Dhaval Patel47302cf2016-08-18 15:04:28 -07001569 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
1570 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04001571
Dhaval Patel47302cf2016-08-18 15:04:28 -07001572 max_upscale = psde->pipe_sblk->maxupscale;
1573 max_downscale = psde->pipe_sblk->maxdwnscale;
1574 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04001575
Clarence Ip13a8cf42016-09-29 17:27:47 -04001576 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001577 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001578
Dhaval Patel47302cf2016-08-18 15:04:28 -07001579 if (!sde_plane_enabled(state))
1580 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04001581
Dhaval Patel47302cf2016-08-18 15:04:28 -07001582 fmt = to_sde_format(msm_framebuffer_format(state->fb));
1583
1584 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
1585
1586 if (SDE_FORMAT_IS_YUV(fmt) &&
1587 (!(psde->features & SDE_SSPP_SCALER) ||
abeykun1c312f62016-08-26 09:47:12 -04001588 !(psde->features & (BIT(SDE_SSPP_CSC)
1589 | BIT(SDE_SSPP_CSC_10BIT))))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001590 SDE_ERROR_PLANE(psde,
1591 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07001592 ret = -EINVAL;
1593
1594 /* check src bounds */
1595 } else if (state->fb->width > MAX_IMG_WIDTH ||
1596 state->fb->height > MAX_IMG_HEIGHT ||
1597 src.w < min_src_size || src.h < min_src_size ||
1598 CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
1599 CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001600 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001601 src.x, src.y, src.w, src.h);
1602 ret = -E2BIG;
1603
1604 /* valid yuv image */
1605 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
1606 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001607 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001608 src.x, src.y, src.w, src.h);
1609 ret = -EINVAL;
1610
1611 /* min dst support */
1612 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001613 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001614 dst.x, dst.y, dst.w, dst.h);
1615 ret = -EINVAL;
1616
1617 /* decimation validation */
1618 } else if (deci_w || deci_h) {
1619 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
1620 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001621 SDE_ERROR_PLANE(psde,
1622 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001623 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001624 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001625 SDE_ERROR_PLANE(psde,
1626 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001627 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001628 }
1629
Dhaval Patel47302cf2016-08-18 15:04:28 -07001630 } else if (!(psde->features & SDE_SSPP_SCALER) &&
1631 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001632 SDE_ERROR_PLANE(psde,
1633 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001634 src.w, src.h, dst.w, dst.h);
1635 ret = -EINVAL;
1636
1637 /* check decimated source width */
1638 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001639 SDE_ERROR_PLANE(psde,
1640 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001641 src.w, src_deci_w, max_linewidth);
1642 ret = -E2BIG;
1643
1644 /* check max scaler capability */
1645 } else if (((src_deci_w * max_upscale) < dst.w) ||
1646 ((src_deci_h * max_upscale) < dst.h) ||
1647 ((dst.w * max_downscale) < src_deci_w) ||
1648 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001649 SDE_ERROR_PLANE(psde,
1650 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001651 src_deci_w, src_deci_h, dst.w, dst.h);
1652 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001653 }
1654
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001655 /* check excl rect configs */
1656 if (pstate->excl_rect.w && pstate->excl_rect.h) {
1657 struct sde_rect intersect;
1658
1659 /*
1660 * Check exclusion rect against src rect.
1661 * Cropping is not required as hardware will consider only the
1662 * intersecting region with the src rect.
1663 */
1664 sde_kms_rect_intersect(&intersect, &src, &pstate->excl_rect);
1665 if (!intersect.w || !intersect.h || SDE_FORMAT_IS_YUV(fmt)) {
1666 SDE_ERROR_PLANE(psde,
1667 "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt:%s\n",
1668 pstate->excl_rect.x, pstate->excl_rect.y,
1669 pstate->excl_rect.w, pstate->excl_rect.h,
1670 src.x, src.y, src.w, src.h,
1671 drm_get_format_name(fmt->base.pixel_format));
1672 ret = -EINVAL;
1673 }
1674 }
1675
Dhaval Patel47302cf2016-08-18 15:04:28 -07001676modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001677 if (!ret)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001678 _sde_plane_atomic_check_mode_changed(psde, state, plane->state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001679exit:
1680 return ret;
1681}
1682
Clarence Ipcae1bb62016-07-07 12:07:13 -04001683/**
1684 * sde_plane_flush - final plane operations before commit flush
1685 * @plane: Pointer to drm plane structure
1686 */
1687void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04001688{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001689 struct sde_plane *psde;
1690
Clarence Ip13a8cf42016-09-29 17:27:47 -04001691 if (!plane) {
1692 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001693 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001694 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04001695
1696 psde = to_sde_plane(plane);
1697
1698 /*
1699 * These updates have to be done immediately before the plane flush
1700 * timing, and may not be moved to the atomic_update/mode_set functions.
1701 */
1702 if (psde->is_error)
1703 /* force white frame with 0% alpha pipe output on error */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001704 _sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001705 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
1706 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001707 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001708 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
1709 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
1710
1711 /* flag h/w flush complete */
1712 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04001713 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001714}
1715
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001716static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001717 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001718{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001719 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001720 struct drm_plane_state *state;
1721 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001722
Clarence Ip13a8cf42016-09-29 17:27:47 -04001723 if (!plane) {
1724 SDE_ERROR("invalid plane\n");
1725 return;
1726 } else if (!plane->state) {
1727 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001728 return;
1729 }
1730
Clarence Ip13a8cf42016-09-29 17:27:47 -04001731 psde = to_sde_plane(plane);
1732 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001733 state = plane->state;
1734 pstate = to_sde_plane_state(state);
1735
Clarence Ip13a8cf42016-09-29 17:27:47 -04001736 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001737
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001738 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001739 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001740 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001741 int ret;
1742
Dhaval Patel47302cf2016-08-18 15:04:28 -07001743 ret = _sde_plane_mode_set(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001744 /* atomic_check should have ensured that this doesn't fail */
1745 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001746 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001747}
1748
Dhaval Patel47302cf2016-08-18 15:04:28 -07001749
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001750/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001751static void _sde_plane_install_properties(struct drm_plane *plane,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001752 struct sde_mdss_cfg *catalog, u32 master_plane_id)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001753{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001754 static const struct drm_prop_enum_list e_blend_op[] = {
1755 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1756 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1757 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1758 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1759 };
1760 static const struct drm_prop_enum_list e_src_config[] = {
1761 {SDE_DRM_DEINTERLACE, "deinterlace"}
1762 };
Clarence Ipea3d6262016-07-15 16:20:11 -04001763 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07001764 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001765 struct sde_plane *psde = to_sde_plane(plane);
Clarence Ipc47a0692016-10-11 10:54:17 -04001766 int zpos_max = 255;
1767 int zpos_def = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -07001768 char feature_name[256];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001769
Clarence Ip13a8cf42016-09-29 17:27:47 -04001770 if (!plane || !psde) {
1771 SDE_ERROR("invalid plane\n");
1772 return;
1773 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
1774 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
1775 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001776 return;
Clarence Ipc47a0692016-10-11 10:54:17 -04001777 } else if (!catalog) {
1778 SDE_ERROR("invalid catalog\n");
1779 return;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001780 }
1781
Clarence Ipc47a0692016-10-11 10:54:17 -04001782 if (sde_is_custom_client()) {
Clarence Ip649989a2016-10-21 14:28:34 -04001783 if (catalog->mixer_count && catalog->mixer &&
1784 catalog->mixer[0].sblk->maxblendstages) {
1785 zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
1786 if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
1787 zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
1788 }
Clarence Ipc47a0692016-10-11 10:54:17 -04001789 } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
1790 /* reserve zpos == 0 for primary planes */
1791 zpos_def = drm_plane_index(plane) + 1;
1792 }
1793
1794 msm_property_install_range(&psde->property_info, "zpos",
1795 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001796
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001797 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001798 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001799
Dhaval Patel47302cf2016-08-18 15:04:28 -07001800 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001801 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07001802 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001803
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001804 if (!master_plane_id) {
1805 if (psde->pipe_sblk->maxhdeciexp) {
1806 msm_property_install_range(&psde->property_info,
1807 "h_decimate", 0x0, 0,
1808 psde->pipe_sblk->maxhdeciexp, 0,
1809 PLANE_PROP_H_DECIMATE);
1810 }
Clarence Ipdedbba92016-09-27 17:43:10 -04001811
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001812 if (psde->pipe_sblk->maxvdeciexp) {
1813 msm_property_install_range(&psde->property_info,
1814 "v_decimate", 0x0, 0,
1815 psde->pipe_sblk->maxvdeciexp, 0,
1816 PLANE_PROP_V_DECIMATE);
1817 }
Clarence Ipdedbba92016-09-27 17:43:10 -04001818
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001819 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
1820 msm_property_install_volatile_range(
1821 &psde->property_info, "scaler_v2",
1822 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
1823 msm_property_install_blob(&psde->property_info,
1824 "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
1825 msm_property_install_blob(&psde->property_info,
1826 "lut_cir", 0,
1827 PLANE_PROP_SCALER_LUT_CIR);
1828 msm_property_install_blob(&psde->property_info,
1829 "lut_sep", 0,
1830 PLANE_PROP_SCALER_LUT_SEP);
1831 } else if (psde->features & SDE_SSPP_SCALER) {
1832 msm_property_install_volatile_range(
1833 &psde->property_info, "scaler_v1", 0x0,
1834 0, ~0, 0, PLANE_PROP_SCALER_V1);
1835 }
Clarence Ipb43d4592016-09-08 14:21:35 -04001836
Dhaval Patel0aee0972017-02-08 19:00:58 -08001837 if (psde->features & BIT(SDE_SSPP_CSC) ||
1838 psde->features & BIT(SDE_SSPP_CSC_10BIT))
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001839 msm_property_install_volatile_range(
1840 &psde->property_info, "csc_v1", 0x0,
1841 0, ~0, 0, PLANE_PROP_CSC_V1);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001842
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001843 if (psde->features & BIT(SDE_SSPP_HSIC)) {
1844 snprintf(feature_name, sizeof(feature_name), "%s%d",
1845 "SDE_SSPP_HUE_V",
1846 psde->pipe_sblk->hsic_blk.version >> 16);
1847 msm_property_install_range(&psde->property_info,
1848 feature_name, 0, 0, 0xFFFFFFFF, 0,
1849 PLANE_PROP_HUE_ADJUST);
1850 snprintf(feature_name, sizeof(feature_name), "%s%d",
1851 "SDE_SSPP_SATURATION_V",
1852 psde->pipe_sblk->hsic_blk.version >> 16);
1853 msm_property_install_range(&psde->property_info,
1854 feature_name, 0, 0, 0xFFFFFFFF, 0,
1855 PLANE_PROP_SATURATION_ADJUST);
1856 snprintf(feature_name, sizeof(feature_name), "%s%d",
1857 "SDE_SSPP_VALUE_V",
1858 psde->pipe_sblk->hsic_blk.version >> 16);
1859 msm_property_install_range(&psde->property_info,
1860 feature_name, 0, 0, 0xFFFFFFFF, 0,
1861 PLANE_PROP_VALUE_ADJUST);
1862 snprintf(feature_name, sizeof(feature_name), "%s%d",
1863 "SDE_SSPP_CONTRAST_V",
1864 psde->pipe_sblk->hsic_blk.version >> 16);
1865 msm_property_install_range(&psde->property_info,
1866 feature_name, 0, 0, 0xFFFFFFFF, 0,
1867 PLANE_PROP_CONTRAST_ADJUST);
1868 }
Benet Clarkeb1b4462016-06-27 14:43:06 -07001869 }
1870
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08001871 if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
1872 msm_property_install_volatile_range(&psde->property_info,
1873 "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
1874
Clarence Ip5e2a9222016-06-26 22:38:24 -04001875 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001876 msm_property_install_rotation(&psde->property_info,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001877 (unsigned int) (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y)),
1878 PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001879
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001880 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001881 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001882
Dhaval Patel47302cf2016-08-18 15:04:28 -07001883 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
1884 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
1885
1886 if (psde->pipe_hw->ops.setup_solidfill)
1887 msm_property_install_range(&psde->property_info, "color_fill",
1888 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
1889
Dhaval Patel4e574842016-08-23 15:11:37 -07001890 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001891 if (!info) {
1892 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07001893 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001894 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001895
1896 msm_property_install_blob(&psde->property_info, "capabilities",
1897 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
1898 sde_kms_info_reset(info);
1899
Clarence Ipea3d6262016-07-15 16:20:11 -04001900 format_list = psde->pipe_sblk->format_list;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001901
1902 if (master_plane_id) {
1903 sde_kms_info_add_keyint(info, "primary_smart_plane_id",
1904 master_plane_id);
1905 format_list = plane_formats;
1906 }
1907
Clarence Ipea3d6262016-07-15 16:20:11 -04001908 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04001909 sde_kms_info_start(info, "pixel_formats");
1910 while (format_list->fourcc_format) {
1911 sde_kms_info_append_format(info,
1912 format_list->fourcc_format,
1913 format_list->modifier);
1914 ++format_list;
1915 }
1916 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04001917 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001918
1919 sde_kms_info_add_keyint(info, "max_linewidth",
1920 psde->pipe_sblk->maxlinewidth);
1921 sde_kms_info_add_keyint(info, "max_upscale",
1922 psde->pipe_sblk->maxupscale);
1923 sde_kms_info_add_keyint(info, "max_downscale",
1924 psde->pipe_sblk->maxdwnscale);
1925 sde_kms_info_add_keyint(info, "max_horizontal_deci",
1926 psde->pipe_sblk->maxhdeciexp);
1927 sde_kms_info_add_keyint(info, "max_vertical_deci",
1928 psde->pipe_sblk->maxvdeciexp);
1929 msm_property_set_blob(&psde->property_info, &psde->blob_info,
1930 info->data, info->len, PLANE_PROP_INFO);
1931
1932 kfree(info);
Benet Clarkd009b1d2016-06-27 14:45:59 -07001933
1934 if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
1935 snprintf(feature_name, sizeof(feature_name), "%s%d",
1936 "SDE_SSPP_SKIN_COLOR_V",
1937 psde->pipe_sblk->memcolor_blk.version >> 16);
1938 msm_property_install_blob(&psde->property_info, feature_name, 0,
1939 PLANE_PROP_SKIN_COLOR);
1940 snprintf(feature_name, sizeof(feature_name), "%s%d",
1941 "SDE_SSPP_SKY_COLOR_V",
1942 psde->pipe_sblk->memcolor_blk.version >> 16);
1943 msm_property_install_blob(&psde->property_info, feature_name, 0,
1944 PLANE_PROP_SKY_COLOR);
1945 snprintf(feature_name, sizeof(feature_name), "%s%d",
1946 "SDE_SSPP_FOLIAGE_COLOR_V",
1947 psde->pipe_sblk->memcolor_blk.version >> 16);
1948 msm_property_install_blob(&psde->property_info, feature_name, 0,
1949 PLANE_PROP_FOLIAGE_COLOR);
1950 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001951}
1952
Clarence Ip5fc00c52016-09-23 15:03:34 -04001953static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
1954{
1955 struct sde_drm_csc_v1 csc_v1;
1956 int i;
1957
1958 if (!psde) {
1959 SDE_ERROR("invalid plane\n");
1960 return;
1961 }
1962
1963 psde->csc_usr_ptr = NULL;
1964 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001965 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001966 return;
1967 }
1968
1969 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001970 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001971 return;
1972 }
1973
Clarence Ipb43d4592016-09-08 14:21:35 -04001974 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04001975 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
1976 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
1977 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
1978 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
1979 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
1980 }
1981 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
1982 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
1983 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
1984 }
1985 psde->csc_usr_ptr = &psde->csc_cfg;
1986}
1987
Clarence Ipb43d4592016-09-08 14:21:35 -04001988static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
1989{
1990 struct sde_drm_scaler_v1 scale_v1;
1991 struct sde_hw_pixel_ext *pe;
1992 int i;
1993
1994 if (!psde) {
1995 SDE_ERROR("invalid plane\n");
1996 return;
1997 }
1998
1999 psde->pixel_ext_usr = false;
2000 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002001 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04002002 return;
2003 }
2004
2005 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002006 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04002007 return;
2008 }
2009
2010 /* populate from user space */
2011 pe = &(psde->pixel_ext);
2012 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
2013 for (i = 0; i < SDE_MAX_PLANES; i++) {
2014 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
2015 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
2016 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
2017 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
2018
2019 pe->horz_filter[i] = scale_v1.horz_filter[i];
2020 pe->vert_filter[i] = scale_v1.vert_filter[i];
2021 }
2022 for (i = 0; i < SDE_MAX_PLANES; i++) {
abeykun41060122016-11-28 13:02:01 -05002023 pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
2024 pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
2025 pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
2026 pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
2027 pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
Clarence Ipb43d4592016-09-08 14:21:35 -04002028
abeykun41060122016-11-28 13:02:01 -05002029 pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
2030 pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
2031 pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
2032 pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
2033 pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
Clarence Ipb43d4592016-09-08 14:21:35 -04002034 }
abeykun41060122016-11-28 13:02:01 -05002035
Clarence Ipb43d4592016-09-08 14:21:35 -04002036 psde->pixel_ext_usr = true;
2037
Clarence Ip13a8cf42016-09-29 17:27:47 -04002038 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04002039}
2040
abeykun48f407a2016-08-25 12:06:44 -04002041static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
2042 struct sde_plane_state *pstate, void *usr)
2043{
2044 struct sde_drm_scaler_v2 scale_v2;
2045 struct sde_hw_pixel_ext *pe;
2046 int i;
2047 struct sde_hw_scaler3_cfg *cfg;
2048
2049 if (!psde) {
2050 SDE_ERROR("invalid plane\n");
2051 return;
2052 }
2053
2054 cfg = psde->scaler3_cfg;
2055 psde->pixel_ext_usr = false;
2056 if (!usr) {
2057 SDE_DEBUG_PLANE(psde, "scale data removed\n");
2058 return;
2059 }
2060
2061 if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
2062 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
2063 return;
2064 }
2065
2066 /* populate from user space */
2067 pe = &(psde->pixel_ext);
2068 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
2069 cfg->enable = scale_v2.enable;
2070 cfg->dir_en = scale_v2.dir_en;
2071 for (i = 0; i < SDE_MAX_PLANES; i++) {
2072 cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
2073 cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
2074 cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
2075 cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
2076
2077 cfg->preload_x[i] = scale_v2.preload_x[i];
2078 cfg->preload_y[i] = scale_v2.preload_y[i];
2079 cfg->src_width[i] = scale_v2.src_width[i];
2080 cfg->src_height[i] = scale_v2.src_height[i];
2081 }
2082 cfg->dst_width = scale_v2.dst_width;
2083 cfg->dst_height = scale_v2.dst_height;
2084
2085 cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
2086 cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
2087 cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
2088 cfg->blend_cfg = scale_v2.blend_cfg;
2089
2090 cfg->lut_flag = scale_v2.lut_flag;
2091 cfg->dir_lut_idx = scale_v2.dir_lut_idx;
2092 cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
2093 cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
2094 cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
2095 cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
2096
2097 cfg->de.enable = scale_v2.de.enable;
2098 cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
2099 cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
2100 cfg->de.clip = scale_v2.de.clip;
2101 cfg->de.limit = scale_v2.de.limit;
2102 cfg->de.thr_quiet = scale_v2.de.thr_quiet;
2103 cfg->de.thr_dieout = scale_v2.de.thr_dieout;
2104 cfg->de.thr_low = scale_v2.de.thr_low;
2105 cfg->de.thr_high = scale_v2.de.thr_high;
2106 cfg->de.prec_shift = scale_v2.de.prec_shift;
2107 for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
2108 cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
2109 cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
2110 cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
2111 }
2112 for (i = 0; i < SDE_MAX_PLANES; i++) {
abeykun41060122016-11-28 13:02:01 -05002113 pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
2114 pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
2115 pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
2116 pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
2117 pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
abeykun48f407a2016-08-25 12:06:44 -04002118
abeykun41060122016-11-28 13:02:01 -05002119 pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
2120 pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
2121 pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
2122 pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
2123 pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
abeykun48f407a2016-08-25 12:06:44 -04002124 }
2125 psde->pixel_ext_usr = true;
2126
2127 SDE_DEBUG_PLANE(psde, "user property data copied\n");
2128}
2129
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002130static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
2131 struct sde_plane_state *pstate, void *usr_ptr)
2132{
2133 struct drm_clip_rect excl_rect_v1;
2134
2135 if (!psde) {
2136 SDE_ERROR("invalid plane\n");
2137 return;
2138 }
2139
2140 if (!usr_ptr) {
2141 SDE_DEBUG_PLANE(psde, "excl rect data removed\n");
2142 return;
2143 }
2144
2145 if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
2146 SDE_ERROR_PLANE(psde, "failed to copy excl rect data\n");
2147 return;
2148 }
2149
2150 /* populate from user space */
2151 pstate->excl_rect.x = excl_rect_v1.x1;
2152 pstate->excl_rect.y = excl_rect_v1.y1;
2153 pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1 + 1;
2154 pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1 + 1;
2155}
2156
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002157static int sde_plane_atomic_set_property(struct drm_plane *plane,
2158 struct drm_plane_state *state, struct drm_property *property,
2159 uint64_t val)
2160{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002161 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002162 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04002163 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002164
Clarence Ip13a8cf42016-09-29 17:27:47 -04002165 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002166
2167 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002168 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002169 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002170 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04002171 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04002172 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04002173 ret = msm_property_atomic_set(&psde->property_info,
2174 pstate->property_values, pstate->property_blobs,
2175 property, val);
2176 if (!ret) {
2177 idx = msm_property_index(&psde->property_info,
2178 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04002179 switch (idx) {
2180 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04002181 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04002182 break;
2183 case PLANE_PROP_CSC_V1:
2184 _sde_plane_set_csc_v1(psde, (void *)val);
2185 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04002186 case PLANE_PROP_SCALER_V1:
2187 _sde_plane_set_scaler_v1(psde, (void *)val);
2188 break;
abeykun48f407a2016-08-25 12:06:44 -04002189 case PLANE_PROP_SCALER_V2:
2190 _sde_plane_set_scaler_v2(psde, pstate,
2191 (void *)val);
2192 break;
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002193 case PLANE_PROP_EXCL_RECT_V1:
2194 _sde_plane_set_excl_rect_v1(psde, pstate,
2195 (void *)val);
2196 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04002197 default:
2198 /* nothing to do */
2199 break;
2200 }
Clarence Ipe78efb72016-06-24 18:35:21 -04002201 }
2202 }
2203
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002204 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002205}
2206
2207static int sde_plane_set_property(struct drm_plane *plane,
2208 struct drm_property *property, uint64_t val)
2209{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002210 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04002211
Clarence Ipae4e60c2016-06-26 22:44:04 -04002212 return sde_plane_atomic_set_property(plane,
2213 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002214}
2215
2216static int sde_plane_atomic_get_property(struct drm_plane *plane,
2217 const struct drm_plane_state *state,
2218 struct drm_property *property, uint64_t *val)
2219{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002220 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002221 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04002222 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002223
Clarence Ipaa0faf42016-05-30 12:07:48 -04002224 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002225 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002226 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002227 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002228 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002229 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04002230 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04002231 ret = msm_property_atomic_get(&psde->property_info,
2232 pstate->property_values, pstate->property_blobs,
2233 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04002234 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002235
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002236 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002237}
2238
2239static void sde_plane_destroy(struct drm_plane *plane)
2240{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002241 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002242
Clarence Ip13a8cf42016-09-29 17:27:47 -04002243 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002244
Clarence Ip13a8cf42016-09-29 17:27:47 -04002245 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002246 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
2247
Clarence Ip4ce59322016-06-26 22:27:51 -04002248 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04002249
Dhaval Patel4e574842016-08-23 15:11:37 -07002250 if (psde->blob_info)
2251 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04002252 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04002253 mutex_destroy(&psde->lock);
2254
Clarence Ip4ce59322016-06-26 22:27:51 -04002255 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002256
Clarence Ip4ce59322016-06-26 22:27:51 -04002257 /* this will destroy the states as well */
2258 drm_plane_cleanup(plane);
2259
Clarence Ip4c1d9772016-06-26 09:35:38 -04002260 if (psde->pipe_hw)
2261 sde_hw_sspp_destroy(psde->pipe_hw);
2262
Clarence Ip4ce59322016-06-26 22:27:51 -04002263 kfree(psde);
2264 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002265}
2266
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002267static void sde_plane_destroy_state(struct drm_plane *plane,
2268 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002269{
Clarence Ipaa0faf42016-05-30 12:07:48 -04002270 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04002271 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04002272
Clarence Ipae4e60c2016-06-26 22:44:04 -04002273 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002274 SDE_ERROR("invalid arg(s), plane %d state %d\n",
2275 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04002276 return;
2277 }
2278
Clarence Ipaa0faf42016-05-30 12:07:48 -04002279 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04002280 pstate = to_sde_plane_state(state);
2281
Clarence Ip13a8cf42016-09-29 17:27:47 -04002282 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04002283
Clarence Ipe78efb72016-06-24 18:35:21 -04002284 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002285 if (state->fb)
2286 drm_framebuffer_unreference(state->fb);
2287
Clarence Ipae4e60c2016-06-26 22:44:04 -04002288 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04002289 if (pstate->input_fence)
2290 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04002291
Clarence Ipaa0faf42016-05-30 12:07:48 -04002292 /* destroy value helper */
2293 msm_property_destroy_state(&psde->property_info, pstate,
2294 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002295}
2296
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002297static struct drm_plane_state *
2298sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002299{
Clarence Ipaa0faf42016-05-30 12:07:48 -04002300 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002301 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04002302 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04002303 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002304
Clarence Ip13a8cf42016-09-29 17:27:47 -04002305 if (!plane) {
2306 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002307 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04002308 } else if (!plane->state) {
2309 SDE_ERROR("invalid plane state\n");
2310 return NULL;
2311 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002312
Clarence Ip730e7192016-06-26 22:45:09 -04002313 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04002314 psde = to_sde_plane(plane);
2315 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04002316 if (!pstate) {
2317 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04002318 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04002319 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002320
Clarence Ip13a8cf42016-09-29 17:27:47 -04002321 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002322
2323 /* duplicate value helper */
2324 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
2325 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04002326
Clarence Ip730e7192016-06-26 22:45:09 -04002327 /* add ref count for frame buffer */
2328 if (pstate->base.fb)
2329 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002330
Clarence Ip17e908b2016-09-29 15:58:00 -04002331 /* clear out any input fence */
2332 pstate->input_fence = 0;
2333 input_fence_default = msm_property_get_default(
2334 &psde->property_info, PLANE_PROP_INPUT_FENCE);
2335 msm_property_set_property(&psde->property_info, pstate->property_values,
2336 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002337
Clarence Ip282dad62016-09-27 17:07:35 -04002338 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04002339 pstate->pending = false;
2340
2341 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002342}
2343
2344static void sde_plane_reset(struct drm_plane *plane)
2345{
Clarence Ipae4e60c2016-06-26 22:44:04 -04002346 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002347 struct sde_plane_state *pstate;
2348
Clarence Ipae4e60c2016-06-26 22:44:04 -04002349 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002350 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04002351 return;
2352 }
2353
Clarence Ip730e7192016-06-26 22:45:09 -04002354 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04002355 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04002356
Clarence Ipae4e60c2016-06-26 22:44:04 -04002357 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04002358 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04002359 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04002360 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04002361 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002362
Clarence Ipaa0faf42016-05-30 12:07:48 -04002363 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04002364 if (!pstate) {
2365 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04002366 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04002367 }
Clarence Ip730e7192016-06-26 22:45:09 -04002368
Clarence Ipaa0faf42016-05-30 12:07:48 -04002369 /* reset value helper */
2370 msm_property_reset_state(&psde->property_info, pstate,
2371 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002372
2373 pstate->base.plane = plane;
2374
2375 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002376}
2377
2378static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002379 .update_plane = drm_atomic_helper_update_plane,
2380 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002381 .destroy = sde_plane_destroy,
2382 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002383 .atomic_set_property = sde_plane_atomic_set_property,
2384 .atomic_get_property = sde_plane_atomic_get_property,
2385 .reset = sde_plane_reset,
2386 .atomic_duplicate_state = sde_plane_duplicate_state,
2387 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002388};
2389
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002390static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
2391 .prepare_fb = sde_plane_prepare_fb,
2392 .cleanup_fb = sde_plane_cleanup_fb,
2393 .atomic_check = sde_plane_atomic_check,
2394 .atomic_update = sde_plane_atomic_update,
2395};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002396
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002397enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002398{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002399 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002400}
2401
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002402bool is_sde_plane_virtual(struct drm_plane *plane)
2403{
2404 return plane ? to_sde_plane(plane)->is_virtual : false;
2405}
2406
Alan Kwongf0fd8512016-10-24 21:39:26 -04002407static ssize_t _sde_plane_danger_read(struct file *file,
2408 char __user *buff, size_t count, loff_t *ppos)
2409{
2410 struct sde_kms *kms = file->private_data;
2411 struct sde_mdss_cfg *cfg = kms->catalog;
2412 int len = 0;
2413 char buf[40] = {'\0'};
2414
2415 if (!cfg)
2416 return -ENODEV;
2417
2418 if (*ppos)
2419 return 0; /* the end */
2420
2421 len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
2422 if (len < 0 || len >= sizeof(buf))
2423 return 0;
2424
2425 if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
2426 return -EFAULT;
2427
2428 *ppos += len; /* increase offset */
2429
2430 return len;
2431}
2432
2433static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
2434{
2435 struct drm_plane *plane;
2436
2437 drm_for_each_plane(plane, kms->dev) {
2438 if (plane->fb && plane->state) {
2439 sde_plane_danger_signal_ctrl(plane, enable);
2440 SDE_DEBUG("plane:%d img:%dx%d ",
2441 plane->base.id, plane->fb->width,
2442 plane->fb->height);
2443 SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
2444 plane->state->src_x >> 16,
2445 plane->state->src_y >> 16,
2446 plane->state->src_w >> 16,
2447 plane->state->src_h >> 16,
2448 plane->state->crtc_x, plane->state->crtc_y,
2449 plane->state->crtc_w, plane->state->crtc_h);
2450 } else {
2451 SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
2452 }
2453 }
2454}
2455
2456static ssize_t _sde_plane_danger_write(struct file *file,
2457 const char __user *user_buf, size_t count, loff_t *ppos)
2458{
2459 struct sde_kms *kms = file->private_data;
2460 struct sde_mdss_cfg *cfg = kms->catalog;
2461 int disable_panic;
2462 char buf[10];
2463
2464 if (!cfg)
2465 return -EFAULT;
2466
2467 if (count >= sizeof(buf))
2468 return -EFAULT;
2469
2470 if (copy_from_user(buf, user_buf, count))
2471 return -EFAULT;
2472
2473 buf[count] = 0; /* end of string */
2474
2475 if (kstrtoint(buf, 0, &disable_panic))
2476 return -EFAULT;
2477
2478 if (disable_panic) {
2479 /* Disable panic signal for all active pipes */
2480 SDE_DEBUG("Disabling danger:\n");
2481 _sde_plane_set_danger_state(kms, false);
2482 kms->has_danger_ctrl = false;
2483 } else {
2484 /* Enable panic signal for all active pipes */
2485 SDE_DEBUG("Enabling danger:\n");
2486 kms->has_danger_ctrl = true;
2487 _sde_plane_set_danger_state(kms, true);
2488 }
2489
2490 return count;
2491}
2492
2493static const struct file_operations sde_plane_danger_enable = {
2494 .open = simple_open,
2495 .read = _sde_plane_danger_read,
2496 .write = _sde_plane_danger_write,
2497};
2498
Clarence Ip4ce59322016-06-26 22:27:51 -04002499static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
2500{
2501 const struct sde_sspp_sub_blks *sblk = 0;
2502 const struct sde_sspp_cfg *cfg = 0;
2503
2504 if (psde && psde->pipe_hw)
2505 cfg = psde->pipe_hw->cap;
2506 if (cfg)
2507 sblk = cfg->sblk;
2508
2509 if (kms && sblk) {
2510 /* create overall sub-directory for the pipe */
2511 psde->debugfs_root =
2512 debugfs_create_dir(psde->pipe_name,
2513 sde_debugfs_get_root(kms));
2514 if (psde->debugfs_root) {
2515 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04002516 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04002517 psde->debugfs_root, &psde->features);
2518
2519 /* add register dump support */
2520 sde_debugfs_setup_regset32(&psde->debugfs_src,
2521 sblk->src_blk.base + cfg->base,
2522 sblk->src_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04002523 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04002524 sde_debugfs_create_regset32("src_blk", 0444,
2525 psde->debugfs_root, &psde->debugfs_src);
2526
2527 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
2528 sblk->scaler_blk.base + cfg->base,
2529 sblk->scaler_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04002530 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04002531 sde_debugfs_create_regset32("scaler_blk", 0444,
2532 psde->debugfs_root,
2533 &psde->debugfs_scaler);
2534
2535 sde_debugfs_setup_regset32(&psde->debugfs_csc,
2536 sblk->csc_blk.base + cfg->base,
2537 sblk->csc_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04002538 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04002539 sde_debugfs_create_regset32("csc_blk", 0444,
2540 psde->debugfs_root, &psde->debugfs_csc);
Alan Kwongf0fd8512016-10-24 21:39:26 -04002541
2542 debugfs_create_u32("xin_id",
2543 0444,
2544 psde->debugfs_root,
2545 (u32 *) &cfg->xin_id);
2546 debugfs_create_u32("clk_ctrl",
2547 0444,
2548 psde->debugfs_root,
2549 (u32 *) &cfg->clk_ctrl);
2550 debugfs_create_x32("creq_vblank",
2551 0644,
2552 psde->debugfs_root,
2553 (u32 *) &sblk->creq_vblank);
2554 debugfs_create_x32("danger_vblank",
2555 0644,
2556 psde->debugfs_root,
2557 (u32 *) &sblk->danger_vblank);
2558
2559 debugfs_create_file("disable_danger",
2560 0644,
2561 psde->debugfs_root,
2562 kms, &sde_plane_danger_enable);
Clarence Ip4ce59322016-06-26 22:27:51 -04002563 }
2564 }
2565}
2566
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002567/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04002568struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip2bbf7b32016-09-23 15:07:16 -04002569 uint32_t pipe, bool primary_plane,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002570 unsigned long possible_crtcs, u32 master_plane_id)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002571{
2572 struct drm_plane *plane = NULL;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002573 const struct sde_format_extended *format_list;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002574 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002575 struct msm_drm_private *priv;
2576 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002577 enum drm_plane_type type;
Clarence Ipc47a0692016-10-11 10:54:17 -04002578 int ret = -EINVAL;
Clarence Ip4c1d9772016-06-26 09:35:38 -04002579
2580 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002581 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002582 goto exit;
2583 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002584
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002585 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04002586 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002587 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04002588 goto exit;
2589 }
2590
2591 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002592 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04002593 goto exit;
2594 }
2595 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002596
Clarence Ip4c1d9772016-06-26 09:35:38 -04002597 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002598 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002599 goto exit;
2600 }
2601
Clarence Ip4ce59322016-06-26 22:27:51 -04002602 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002603 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
2604 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002605 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002606 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04002607 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002608 }
2609
Clarence Ip4c1d9772016-06-26 09:35:38 -04002610 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002611 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002612 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04002613 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002614 psde->is_virtual = (master_plane_id != 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002615
Clarence Ip4c1d9772016-06-26 09:35:38 -04002616 /* initialize underlying h/w driver */
2617 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
2618 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002619 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002620 ret = PTR_ERR(psde->pipe_hw);
2621 goto clean_plane;
2622 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002623 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002624 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002625 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04002626
2627 /* cache features mask for later */
2628 psde->features = psde->pipe_hw->cap->features;
2629 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04002630 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002631 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04002632 goto clean_sspp;
2633 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04002634
abeykun48f407a2016-08-25 12:06:44 -04002635 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
2636 psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
2637 GFP_KERNEL);
2638 if (!psde->scaler3_cfg) {
2639 SDE_ERROR("[%u]failed to allocate scale struct\n",
2640 pipe);
2641 ret = -ENOMEM;
2642 goto clean_sspp;
2643 }
2644 }
2645
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002646 format_list = psde->pipe_sblk->format_list;
2647
2648 if (master_plane_id)
2649 format_list = plane_formats;
2650
2651 psde->nformats = sde_populate_formats(plane_formats,
2652 psde->formats,
2653 0,
2654 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002655
Clarence Ip4c1d9772016-06-26 09:35:38 -04002656 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002657 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002658 goto clean_sspp;
2659 }
2660
2661 if (psde->features & BIT(SDE_SSPP_CURSOR))
2662 type = DRM_PLANE_TYPE_CURSOR;
2663 else if (primary_plane)
2664 type = DRM_PLANE_TYPE_PRIMARY;
2665 else
2666 type = DRM_PLANE_TYPE_OVERLAY;
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07002667 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
2668 psde->formats, psde->nformats,
2669 type, NULL);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002670 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04002671 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002672
Clarence Ip4c1d9772016-06-26 09:35:38 -04002673 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002674 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002675
Clarence Ipaa0faf42016-05-30 12:07:48 -04002676 msm_property_init(&psde->property_info, &plane->base, dev,
2677 priv->plane_property, psde->property_data,
2678 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
2679 sizeof(struct sde_plane_state));
2680
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002681 _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
Clarence Ip5e2a9222016-06-26 22:38:24 -04002682
Clarence Ip4ce59322016-06-26 22:27:51 -04002683 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04002684 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04002685
Clarence Ip730e7192016-06-26 22:45:09 -04002686 mutex_init(&psde->lock);
2687
Clarence Ip4ce59322016-06-26 22:27:51 -04002688 _sde_plane_init_debugfs(psde, kms);
2689
Clarence Ip13a8cf42016-09-29 17:27:47 -04002690 DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002691 return plane;
2692
Clarence Ip4c1d9772016-06-26 09:35:38 -04002693clean_sspp:
2694 if (psde && psde->pipe_hw)
2695 sde_hw_sspp_destroy(psde->pipe_hw);
abeykun48f407a2016-08-25 12:06:44 -04002696
2697 if (psde && psde->scaler3_cfg)
2698 kfree(psde->scaler3_cfg);
Clarence Ip4c1d9772016-06-26 09:35:38 -04002699clean_plane:
2700 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04002701exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002702 return ERR_PTR(ret);
2703}