Vinu Deokaran | dc3ce96 | 2014-12-01 14:56:28 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __MDSS_PLL_H |
| 14 | #define __MDSS_PLL_H |
| 15 | |
| 16 | #include <linux/mdss_io_util.h> |
| 17 | #include <linux/io.h> |
| 18 | |
| 19 | #define MDSS_PLL_REG_W(base, offset, data) \ |
| 20 | writel_relaxed((data), (base) + (offset)) |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 21 | #define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset)) |
| 22 | |
| 23 | #define PLL_CALC_DATA(addr0, addr1, data0, data1) \ |
| 24 | (((data1) << 24) | (((addr1)/4) << 16) | ((data0) << 8) | ((addr0)/4)) |
| 25 | |
| 26 | #define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \ |
| 27 | writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \ |
| 28 | (base) + (offset)) |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 29 | |
| 30 | enum { |
Kuogee Hsieh | 6c9c1d9 | 2015-01-21 15:56:53 -0800 | [diff] [blame] | 31 | MDSS_DSI_PLL_8996, |
Veera Sundaram Sankaran | bfbfa0d | 2015-04-14 18:21:49 -0700 | [diff] [blame] | 32 | MDSS_HDMI_PLL_8996, |
Casey Piper | 7173257 | 2015-05-04 16:09:01 -0700 | [diff] [blame] | 33 | MDSS_HDMI_PLL_8996_V2, |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 34 | MDSS_UNKNOWN_PLL, |
| 35 | }; |
| 36 | |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 37 | enum { |
Kuogee Hsieh | 6c9c1d9 | 2015-01-21 15:56:53 -0800 | [diff] [blame] | 38 | MDSS_PLL_TARGET_8996, |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 39 | }; |
| 40 | |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 41 | struct mdss_pll_resources { |
| 42 | |
| 43 | /* Pll specific resources like GPIO, power supply, clocks, etc*/ |
| 44 | struct dss_module_power mp; |
| 45 | |
Jeevan Shriram | 6dd6b97 | 2014-08-19 22:43:46 -0700 | [diff] [blame] | 46 | /* |
Veera Sundaram Sankaran | 23775f1 | 2014-11-13 14:28:25 -0800 | [diff] [blame] | 47 | * dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh |
Jeevan Shriram | 6dd6b97 | 2014-08-19 22:43:46 -0700 | [diff] [blame] | 48 | * register mapping |
| 49 | */ |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 50 | void __iomem *pll_base; |
| 51 | void __iomem *phy_base; |
Veera Sundaram Sankaran | 23775f1 | 2014-11-13 14:28:25 -0800 | [diff] [blame] | 52 | void __iomem *gdsc_base; |
Jeevan Shriram | 6dd6b97 | 2014-08-19 22:43:46 -0700 | [diff] [blame] | 53 | void __iomem *dyn_pll_base; |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 54 | |
Huaibin Yang | ff625c0 | 2014-12-09 12:38:51 -0800 | [diff] [blame] | 55 | bool is_init_locked; |
Huaibin Yang | c5c6ad4 | 2014-11-26 15:18:39 -0800 | [diff] [blame] | 56 | s64 vco_current_rate; |
Huaibin Yang | ff625c0 | 2014-12-09 12:38:51 -0800 | [diff] [blame] | 57 | s64 vco_locking_rate; |
Huaibin Yang | c5c6ad4 | 2014-11-26 15:18:39 -0800 | [diff] [blame] | 58 | s64 vco_ref_clk_rate; |
| 59 | |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 60 | /* |
| 61 | * Certain pll's needs to update the same vco rate after resume in |
| 62 | * suspend/resume scenario. Cached the vco rate for such plls. |
| 63 | */ |
| 64 | unsigned long vco_cached_rate; |
| 65 | |
| 66 | /* dsi/edp/hmdi pll interface type */ |
| 67 | u32 pll_interface_type; |
| 68 | |
| 69 | /* |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 70 | * Target ID. Used in pll_register API for valid target check before |
| 71 | * registering the PLL clocks. |
| 72 | */ |
| 73 | u32 target_id; |
| 74 | |
| 75 | /* HW recommended delay during configuration of vco clock rate */ |
| 76 | u32 vco_delay; |
| 77 | |
Padmanabhan Komanduru | 99fa0d7 | 2014-05-05 19:48:23 +0530 | [diff] [blame] | 78 | /* Ref-count of the PLL resources */ |
| 79 | u32 resource_ref_cnt; |
| 80 | |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 81 | /* |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 82 | * Keep track to resource status to avoid updating same status for the |
| 83 | * pll from different paths |
| 84 | */ |
| 85 | bool resource_enable; |
| 86 | |
| 87 | /* |
| 88 | * Certain plls' do not allow vco rate update if it is on. Keep track of |
| 89 | * status for them to turn on/off after set rate success. |
| 90 | */ |
| 91 | bool pll_on; |
| 92 | |
| 93 | /* |
| 94 | * handoff_status is true of pll is already enabled by bootloader with |
| 95 | * continuous splash enable case. Clock API will call the handoff API |
| 96 | * to enable the status. It is disabled if continuous splash |
| 97 | * feature is disabled. |
| 98 | */ |
| 99 | bool handoff_resources; |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 100 | |
| 101 | /* |
| 102 | * caching the pll trim codes in the case of dynamic refresh |
| 103 | */ |
Huaibin Yang | c5c6ad4 | 2014-11-26 15:18:39 -0800 | [diff] [blame] | 104 | int cache_pll_trim_codes[2]; |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 105 | |
| 106 | /* |
| 107 | * for maintaining the status of saving trim codes |
| 108 | */ |
| 109 | bool reg_upd; |
Siddhartha Agrawal | a91de84 | 2014-08-25 10:41:10 -0700 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * Notifier callback for MDSS gdsc regulator events |
| 113 | */ |
| 114 | struct notifier_block gdsc_cb; |
| 115 | |
| 116 | /* |
| 117 | * Worker function to call PLL off event |
| 118 | */ |
| 119 | struct work_struct pll_off; |
| 120 | |
Siddhartha Agrawal | 174bbb3 | 2014-09-05 10:44:54 -0700 | [diff] [blame] | 121 | /* |
| 122 | * PLL index if multiple index are available. Eg. in case of |
| 123 | * DSI we have 2 plls. |
| 124 | */ |
| 125 | uint32_t index; |
| 126 | |
Kuogee Hsieh | 1d23056 | 2015-05-29 09:38:54 -0700 | [diff] [blame^] | 127 | bool ssc_en; /* share pll with master */ |
| 128 | bool ssc_center; /* default is down spread */ |
| 129 | |
Kuogee Hsieh | df49854 | 2015-02-04 14:26:07 -0800 | [diff] [blame] | 130 | struct mdss_pll_resources *slave; |
| 131 | |
Dhaval Patel | 0d49d47 | 2015-04-27 10:37:21 -0700 | [diff] [blame] | 132 | /* |
| 133 | * target pll revision information |
| 134 | */ |
| 135 | int revision; |
| 136 | |
Kuogee Hsieh | 6c9c1d9 | 2015-01-21 15:56:53 -0800 | [diff] [blame] | 137 | void *priv; |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | struct mdss_pll_vco_calc { |
| 141 | s32 div_frac_start1; |
| 142 | s32 div_frac_start2; |
| 143 | s32 div_frac_start3; |
| 144 | s64 dec_start1; |
| 145 | s64 dec_start2; |
| 146 | s64 pll_plllock_cmp1; |
| 147 | s64 pll_plllock_cmp2; |
| 148 | s64 pll_plllock_cmp3; |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 149 | }; |
| 150 | |
Veera Sundaram Sankaran | 23775f1 | 2014-11-13 14:28:25 -0800 | [diff] [blame] | 151 | static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) |
| 152 | { |
| 153 | if (!pll_res->gdsc_base) { |
| 154 | WARN(1, "gdsc_base register is not defined\n"); |
| 155 | return true; |
| 156 | } |
| 157 | |
| 158 | return ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && |
| 159 | (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; |
| 160 | } |
| 161 | |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 162 | int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable); |
| 163 | int mdss_pll_util_resource_init(struct platform_device *pdev, |
| 164 | struct mdss_pll_resources *pll_res); |
| 165 | void mdss_pll_util_resource_deinit(struct platform_device *pdev, |
| 166 | struct mdss_pll_resources *pll_res); |
| 167 | void mdss_pll_util_resource_release(struct platform_device *pdev, |
| 168 | struct mdss_pll_resources *pll_res); |
| 169 | int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, |
| 170 | bool enable); |
| 171 | int mdss_pll_util_resource_parse(struct platform_device *pdev, |
| 172 | struct mdss_pll_resources *pll_res); |
Siddhartha Agrawal | a91de84 | 2014-08-25 10:41:10 -0700 | [diff] [blame] | 173 | struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res |
| 174 | , char *name); |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 175 | #endif |