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gerrit-public.fairphone.software / kernel / msm-4.9 / 1e9fc30e38bbedf5cbba9238393084c35e1df551 / . / drivers / gpu / drm / nouveau / core / engine / device / nv40.c
blob: 31a50d10dd1b2c815e45954ca416cc95014c0c14 [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]25#include <subdev/bios.h>
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]26#include <subdev/bus.h>
27#include <subdev/vm.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]28#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]29#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]30#include <subdev/clock.h>
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]31#include <subdev/therm.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]32#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]33#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]34#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]35#include <subdev/fb.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]36#include <subdev/instmem.h>
37#include <subdev/vm.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]38
Ben Skeggsdded35d2013-04-25 17:23:43 +1000[diff] [blame]39#include <engine/device.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]40#include <engine/dmaobj.h>
41#include <engine/fifo.h>
42#include <engine/software.h>
43#include <engine/graph.h>
44#include <engine/mpeg.h>
45#include <engine/disp.h>
46
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]47int
48nv40_identify(struct nouveau_device *device)
49{
50 switch (device->chipset) {
51 case 0x40:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]52 device->cname = "NV40";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]53 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]54 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]55 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]56 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]57 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]58 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]59 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]60 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]62 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
64 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]65 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
66 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]67 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]68 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
69 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
70 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]71 break;
72 case 0x41:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]73 device->cname = "NV41";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]74 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]75 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]76 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]77 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]78 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]79 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]80 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]81 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]82 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]83 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]84 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggs002d0c72012-09-27 08:56:24 +1000[diff] [blame]85 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
87 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]88 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]89 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
90 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
91 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]92 break;
93 case 0x42:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]94 device->cname = "NV42";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]97 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]98 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]99 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]100 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]101 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]102 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]104 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]105 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggs002d0c72012-09-27 08:56:24 +1000[diff] [blame]106 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
108 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]109 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]110 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
112 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]113 break;
114 case 0x43:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]115 device->cname = "NV43";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]116 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]117 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]118 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]119 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]120 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]121 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]122 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]123 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]125 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggs002d0c72012-09-27 08:56:24 +1000[diff] [blame]127 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]128 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
129 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]130 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]131 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
132 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
133 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]134 break;
135 case 0x45:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]136 device->cname = "NV45";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]137 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]138 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]139 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]140 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]141 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]142 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]143 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]144 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]145 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]146 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
148 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
150 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]151 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]152 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]153 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]154 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]155 break;
156 case 0x47:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]157 device->cname = "G70";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]158 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]159 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]160 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]161 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]162 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]163 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]164 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]165 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]167 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]168 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggs002d0c72012-09-27 08:56:24 +1000[diff] [blame]169 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
171 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]172 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]173 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]174 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]175 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]176 break;
177 case 0x49:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]178 device->cname = "G71";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]179 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]180 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]181 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]182 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]183 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]184 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]185 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]186 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]187 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]188 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]189 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggs002d0c72012-09-27 08:56:24 +1000[diff] [blame]190 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]191 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
192 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]193 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]194 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]195 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]196 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]197 break;
198 case 0x4b:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]199 device->cname = "G73";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]200 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]201 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]202 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]203 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]204 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]205 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]206 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]207 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]209 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggs002d0c72012-09-27 08:56:24 +1000[diff] [blame]211 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]212 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
213 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]214 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]215 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]216 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]217 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]218 break;
219 case 0x44:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]220 device->cname = "NV44";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]221 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]222 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]223 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]224 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]225 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]226 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]227 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]228 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]229 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]230 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]231 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]232 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]233 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
234 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]235 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]236 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]237 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]238 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]239 break;
240 case 0x46:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]241 device->cname = "G72";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]242 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]243 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]244 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]245 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]246 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]247 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]248 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]249 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]250 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]251 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]252 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]253 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]254 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
255 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]256 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]257 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]258 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]259 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]260 break;
261 case 0x4a:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]262 device->cname = "NV44A";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]263 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]264 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]265 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]266 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]267 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]268 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]269 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]270 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]271 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]272 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]274 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]277 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]280 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]281 break;
282 case 0x4c:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]283 device->cname = "C61";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]284 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]285 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]286 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]287 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]288 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]289 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]290 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]291 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]293 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]294 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]295 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]296 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
297 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]298 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]299 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]300 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]301 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]302 break;
303 case 0x4e:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]304 device->cname = "C51";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]305 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]306 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]307 device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]308 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]309 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]310 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]311 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]312 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]313 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]314 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]315 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]316 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]317 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
318 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]319 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]320 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]321 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]322 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]323 break;
324 case 0x63:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]325 device->cname = "C73";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]326 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]327 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]328 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]329 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]330 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]331 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]332 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]333 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]335 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]336 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]337 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]338 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
339 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]340 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]341 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]342 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]343 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]344 break;
345 case 0x67:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]346 device->cname = "C67";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]347 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]348 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]349 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]350 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]351 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]352 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]353 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]354 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]355 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]356 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]357 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]358 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]359 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
360 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]361 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]362 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]363 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]364 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]365 break;
366 case 0x68:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]367 device->cname = "C68";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]368 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]369 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]370 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]371 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]372 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]373 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]374 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]375 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]376 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame^]377 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]378 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
Ben Skeggse5f186c2012-09-27 08:55:53 +1000[diff] [blame]379 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]380 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
381 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]382 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]383 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
Ilia Mirkin5fa75432013-09-07 21:04:09 -0400[diff] [blame]384 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]385 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]386 break;
387 default:
388 nv_fatal(device, "unknown Curie chipset\n");
389 return -EINVAL;
390 }
391
392 return 0;
393}